2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct brw_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
63 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
110 uint32_t format_block_size
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_block_size
;
114 uint32_t width
, height
;
119 case ISL_TILING_LINEAR
:
135 /* XXX: Should W tile be same as Y? */
141 case ISL_TILING_Ys
: {
142 if (ISL_DEV_GEN(dev
) < 9)
145 if (!isl_is_pow2(bs
))
148 bool is_Ys
= tiling
== ISL_TILING_Ys
;
150 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
151 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
156 *tile_info
= (struct isl_tile_info
) {
160 .size
= width
* height
,
167 isl_tiling_get_extent(const struct isl_device
*dev
,
168 enum isl_tiling tiling
,
169 uint32_t format_block_size
,
170 struct isl_extent2d
*e
)
172 struct isl_tile_info tile_info
;
173 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
174 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
178 * @param[out] tiling is set only on success
181 isl_surf_choose_tiling(const struct isl_device
*dev
,
182 const struct isl_surf_init_info
*restrict info
,
183 enum isl_tiling
*tiling
)
185 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
187 if (ISL_DEV_GEN(dev
) >= 7) {
188 gen7_filter_tiling(dev
, info
, &tiling_flags
);
190 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
191 gen7_filter_tiling(dev
, info
, &tiling_flags
);
194 #define CHOOSE(__tiling) \
196 if (tiling_flags & (1u << (__tiling))) { \
197 *tiling = (__tiling); \
202 /* Of the tiling modes remaining, choose the one that offers the best
206 if (info
->dim
== ISL_SURF_DIM_1D
) {
207 /* Prefer linear for 1D surfaces because they do not benefit from
208 * tiling. To the contrary, tiling leads to wasted memory and poor
209 * memory locality due to the swizzling and alignment restrictions
210 * required in tiled surfaces.
212 CHOOSE(ISL_TILING_LINEAR
);
215 CHOOSE(ISL_TILING_Ys
);
216 CHOOSE(ISL_TILING_Yf
);
217 CHOOSE(ISL_TILING_Y0
);
218 CHOOSE(ISL_TILING_X
);
219 CHOOSE(ISL_TILING_W
);
220 CHOOSE(ISL_TILING_LINEAR
);
224 /* No tiling mode accomodates the inputs. */
229 isl_choose_msaa_layout(const struct isl_device
*dev
,
230 const struct isl_surf_init_info
*info
,
231 enum isl_tiling tiling
,
232 enum isl_msaa_layout
*msaa_layout
)
234 if (ISL_DEV_GEN(dev
) >= 8) {
235 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
236 } else if (ISL_DEV_GEN(dev
) >= 7) {
237 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
238 } else if (ISL_DEV_GEN(dev
) >= 6) {
239 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
241 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
246 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
247 uint32_t *width
, uint32_t *height
)
249 assert(isl_is_pow2(samples
));
251 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
254 * If the surface is multisampled and it is a depth or stencil surface
255 * or Multisampled Surface StorageFormat in SURFACE_STATE is
256 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
260 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
262 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
265 static enum isl_array_pitch_span
266 isl_choose_array_pitch_span(const struct isl_device
*dev
,
267 const struct isl_surf_init_info
*restrict info
,
268 enum isl_dim_layout dim_layout
,
269 const struct isl_extent4d
*phys_level0_sa
)
271 switch (dim_layout
) {
272 case ISL_DIM_LAYOUT_GEN9_1D
:
273 case ISL_DIM_LAYOUT_GEN4_2D
:
274 if (ISL_DEV_GEN(dev
) >= 8) {
275 /* QPitch becomes programmable in Broadwell. So choose the
276 * most compact QPitch possible in order to conserve memory.
278 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
279 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
281 * - Software must ensure that this field is set to a value
282 * sufficiently large such that the array slices in the surface
283 * do not overlap. Refer to the Memory Data Formats section for
284 * information on how surfaces are stored in memory.
286 * - This field specifies the distance in rows between array
287 * slices. It is used only in the following cases:
289 * - Surface Array is enabled OR
290 * - Number of Mulitsamples is not NUMSAMPLES_1 and
291 * Multisampled Surface Storage Format set to MSFMT_MSS OR
292 * - Surface Type is SURFTYPE_CUBE
294 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
295 } else if (ISL_DEV_GEN(dev
) >= 7) {
296 /* Note that Ivybridge introduces
297 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
298 * driver more control over the QPitch.
301 if (phys_level0_sa
->array_len
== 1) {
302 /* The hardware will never use the QPitch. So choose the most
303 * compact QPitch possible in order to conserve memory.
305 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
308 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
309 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
310 * Section 6.18.4.7: Surface Arrays (p112):
312 * If Surface Array Spacing is set to ARYSPC_FULL (note that
313 * the depth buffer and stencil buffer have an implied value of
316 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
319 if (info
->levels
== 1) {
320 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
323 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
326 return ISL_ARRAY_PITCH_SPAN_FULL
;
327 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
328 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
329 isl_surf_usage_is_stencil(info
->usage
)) {
330 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
331 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
333 * The separate stencil buffer does not support mip mapping, thus
334 * the storage for LODs other than LOD 0 is not needed.
336 assert(info
->levels
== 1);
337 assert(phys_level0_sa
->array_len
== 1);
338 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
340 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
341 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
342 isl_surf_usage_is_stencil(info
->usage
)) {
343 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
344 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
346 * The separate stencil buffer does not support mip mapping,
347 * thus the storage for LODs other than LOD 0 is not needed.
349 assert(info
->levels
== 1);
350 assert(phys_level0_sa
->array_len
== 1);
351 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
354 if (phys_level0_sa
->array_len
== 1) {
355 /* The hardware will never use the QPitch. So choose the most
356 * compact QPitch possible in order to conserve memory.
358 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
361 return ISL_ARRAY_PITCH_SPAN_FULL
;
364 case ISL_DIM_LAYOUT_GEN4_3D
:
365 /* The hardware will never use the QPitch. So choose the most
366 * compact QPitch possible in order to conserve memory.
368 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
371 unreachable("bad isl_dim_layout");
372 return ISL_ARRAY_PITCH_SPAN_FULL
;
376 isl_choose_image_alignment_el(const struct isl_device
*dev
,
377 const struct isl_surf_init_info
*restrict info
,
378 enum isl_tiling tiling
,
379 enum isl_msaa_layout msaa_layout
,
380 struct isl_extent3d
*image_align_el
)
382 if (ISL_DEV_GEN(dev
) >= 9) {
383 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
385 } else if (ISL_DEV_GEN(dev
) >= 8) {
386 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
388 } else if (ISL_DEV_GEN(dev
) >= 7) {
389 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
391 } else if (ISL_DEV_GEN(dev
) >= 6) {
392 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
395 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
400 static enum isl_dim_layout
401 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
402 enum isl_surf_dim logical_dim
)
404 if (ISL_DEV_GEN(dev
) >= 9) {
405 switch (logical_dim
) {
406 case ISL_SURF_DIM_1D
:
407 return ISL_DIM_LAYOUT_GEN9_1D
;
408 case ISL_SURF_DIM_2D
:
409 case ISL_SURF_DIM_3D
:
410 return ISL_DIM_LAYOUT_GEN4_2D
;
413 switch (logical_dim
) {
414 case ISL_SURF_DIM_1D
:
415 case ISL_SURF_DIM_2D
:
416 return ISL_DIM_LAYOUT_GEN4_2D
;
417 case ISL_SURF_DIM_3D
:
418 return ISL_DIM_LAYOUT_GEN4_3D
;
422 unreachable("bad isl_surf_dim");
423 return ISL_DIM_LAYOUT_GEN4_2D
;
427 * Calculate the physical extent of the surface's first level, in units of
428 * surface samples. The result is aligned to the format's compression block.
431 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
432 const struct isl_surf_init_info
*restrict info
,
433 enum isl_dim_layout dim_layout
,
434 enum isl_tiling tiling
,
435 enum isl_msaa_layout msaa_layout
,
436 struct isl_extent4d
*phys_level0_sa
)
438 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
440 if (isl_format_is_yuv(info
->format
))
441 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
444 case ISL_SURF_DIM_1D
:
445 assert(info
->height
== 1);
446 assert(info
->depth
== 1);
447 assert(info
->samples
== 1);
448 assert(!isl_format_is_compressed(info
->format
));
450 switch (dim_layout
) {
451 case ISL_DIM_LAYOUT_GEN4_3D
:
452 unreachable("bad isl_dim_layout");
454 case ISL_DIM_LAYOUT_GEN9_1D
:
455 case ISL_DIM_LAYOUT_GEN4_2D
:
456 *phys_level0_sa
= (struct isl_extent4d
) {
460 .a
= info
->array_len
,
466 case ISL_SURF_DIM_2D
:
467 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
469 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
470 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
472 switch (msaa_layout
) {
473 case ISL_MSAA_LAYOUT_NONE
:
474 assert(info
->depth
== 1);
475 assert(info
->samples
== 1);
477 *phys_level0_sa
= (struct isl_extent4d
) {
478 .w
= isl_align(info
->width
, fmtl
->bw
),
479 .h
= isl_align(info
->height
, fmtl
->bh
),
481 .a
= info
->array_len
,
485 case ISL_MSAA_LAYOUT_ARRAY
:
486 assert(info
->depth
== 1);
487 assert(info
->array_len
== 1);
488 assert(!isl_format_is_compressed(info
->format
));
490 *phys_level0_sa
= (struct isl_extent4d
) {
498 case ISL_MSAA_LAYOUT_INTERLEAVED
:
499 assert(info
->depth
== 1);
500 assert(info
->array_len
== 1);
501 assert(!isl_format_is_compressed(info
->format
));
503 *phys_level0_sa
= (struct isl_extent4d
) {
510 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
517 case ISL_SURF_DIM_3D
:
518 assert(info
->array_len
== 1);
519 assert(info
->samples
== 1);
522 isl_finishme("%s:%s: compression block with depth > 1",
526 switch (dim_layout
) {
527 case ISL_DIM_LAYOUT_GEN9_1D
:
528 unreachable("bad isl_dim_layout");
530 case ISL_DIM_LAYOUT_GEN4_2D
:
531 assert(ISL_DEV_GEN(dev
) >= 9);
533 *phys_level0_sa
= (struct isl_extent4d
) {
534 .w
= isl_align(info
->width
, fmtl
->bw
),
535 .h
= isl_align(info
->height
, fmtl
->bh
),
541 case ISL_DIM_LAYOUT_GEN4_3D
:
542 assert(ISL_DEV_GEN(dev
) < 9);
543 *phys_level0_sa
= (struct isl_extent4d
) {
544 .w
= isl_align(info
->width
, fmtl
->bw
),
545 .h
= isl_align(info
->height
, fmtl
->bh
),
556 * A variant of isl_calc_phys_slice0_extent_sa() specific to
557 * ISL_DIM_LAYOUT_GEN4_2D.
560 isl_calc_phys_slice0_extent_sa_gen4_2d(
561 const struct isl_device
*dev
,
562 const struct isl_surf_init_info
*restrict info
,
563 enum isl_msaa_layout msaa_layout
,
564 const struct isl_extent3d
*image_align_sa
,
565 const struct isl_extent4d
*phys_level0_sa
,
566 struct isl_extent2d
*phys_slice0_sa
)
568 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
570 assert(phys_level0_sa
->depth
== 1);
572 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
573 /* Do not pad the surface to the image alignment. Instead, pad it only
574 * to the pixel format's block alignment.
576 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
577 * cycles on the below mipmap layout caluclations. Reducing the
578 * alignment here is safe because we later align the row pitch and array
579 * pitch to the tile boundary. It is safe even for
580 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
581 * to accomodate the interleaved samples.
583 * For linear surfaces, reducing the alignment here permits us to later
584 * choose an arbitrary, non-aligned row pitch. If the surface backs
585 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
586 * VkBufferImageCopy::bufferRowLength.
588 *phys_slice0_sa
= (struct isl_extent2d
) {
589 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
590 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
595 uint32_t slice_top_w
= 0;
596 uint32_t slice_bottom_w
= 0;
597 uint32_t slice_left_h
= 0;
598 uint32_t slice_right_h
= 0;
600 uint32_t W0
= phys_level0_sa
->w
;
601 uint32_t H0
= phys_level0_sa
->h
;
603 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
604 uint32_t W
= isl_minify(W0
, l
);
605 uint32_t H
= isl_minify(H0
, l
);
607 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
608 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
611 * If the surface is multisampled and it is a depth or stencil
612 * surface or Multisampled Surface StorageFormat in
613 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
614 * adjusted as follows before proceeding: [...]
616 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
619 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
620 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
637 *phys_slice0_sa
= (struct isl_extent2d
) {
638 .w
= MAX(slice_top_w
, slice_bottom_w
),
639 .h
= MAX(slice_left_h
, slice_right_h
),
644 * A variant of isl_calc_phys_slice0_extent_sa() specific to
645 * ISL_DIM_LAYOUT_GEN4_3D.
648 isl_calc_phys_slice0_extent_sa_gen4_3d(
649 const struct isl_device
*dev
,
650 const struct isl_surf_init_info
*restrict info
,
651 const struct isl_extent3d
*image_align_sa
,
652 const struct isl_extent4d
*phys_level0_sa
,
653 struct isl_extent2d
*phys_slice0_sa
)
655 assert(info
->samples
== 1);
656 assert(phys_level0_sa
->array_len
== 1);
658 uint32_t slice_w
= 0;
659 uint32_t slice_h
= 0;
661 uint32_t W0
= phys_level0_sa
->w
;
662 uint32_t H0
= phys_level0_sa
->h
;
663 uint32_t D0
= phys_level0_sa
->d
;
665 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
666 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
667 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
668 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
670 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
671 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
673 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
674 slice_h
+= level_h
* max_layers_vert
;
677 *phys_slice0_sa
= (struct isl_extent2d
) {
684 * A variant of isl_calc_phys_slice0_extent_sa() specific to
685 * ISL_DIM_LAYOUT_GEN9_1D.
688 isl_calc_phys_slice0_extent_sa_gen9_1d(
689 const struct isl_device
*dev
,
690 const struct isl_surf_init_info
*restrict info
,
691 const struct isl_extent3d
*image_align_sa
,
692 const struct isl_extent4d
*phys_level0_sa
,
693 struct isl_extent2d
*phys_slice0_sa
)
695 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
697 assert(phys_level0_sa
->height
== 1);
698 assert(phys_level0_sa
->depth
== 1);
699 assert(info
->samples
== 1);
700 assert(image_align_sa
->w
>= fmtl
->bw
);
702 uint32_t slice_w
= 0;
703 const uint32_t W0
= phys_level0_sa
->w
;
705 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
706 uint32_t W
= isl_minify(W0
, l
);
707 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
712 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
716 * Calculate the physical extent of the surface's first array slice, in units
717 * of surface samples. If the surface is multi-leveled, then the result will
718 * be aligned to \a image_align_sa.
721 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
722 const struct isl_surf_init_info
*restrict info
,
723 enum isl_dim_layout dim_layout
,
724 enum isl_msaa_layout msaa_layout
,
725 const struct isl_extent3d
*image_align_sa
,
726 const struct isl_extent4d
*phys_level0_sa
,
727 struct isl_extent2d
*phys_slice0_sa
)
729 switch (dim_layout
) {
730 case ISL_DIM_LAYOUT_GEN9_1D
:
731 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
732 image_align_sa
, phys_level0_sa
,
735 case ISL_DIM_LAYOUT_GEN4_2D
:
736 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
737 image_align_sa
, phys_level0_sa
,
740 case ISL_DIM_LAYOUT_GEN4_3D
:
741 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
742 phys_level0_sa
, phys_slice0_sa
);
748 * Calculate the pitch between physical array slices, in units of rows of
752 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
753 const struct isl_surf_init_info
*restrict info
,
754 const struct isl_tile_info
*tile_info
,
755 enum isl_dim_layout dim_layout
,
756 enum isl_array_pitch_span array_pitch_span
,
757 const struct isl_extent3d
*image_align_sa
,
758 const struct isl_extent4d
*phys_level0_sa
,
759 const struct isl_extent2d
*phys_slice0_sa
)
761 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
762 uint32_t pitch_sa_rows
= 0;
764 switch (dim_layout
) {
765 case ISL_DIM_LAYOUT_GEN9_1D
:
766 /* Each row is an array slice */
769 case ISL_DIM_LAYOUT_GEN4_2D
:
770 switch (array_pitch_span
) {
771 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
772 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
774 case ISL_ARRAY_PITCH_SPAN_FULL
: {
775 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
776 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
777 * Surfaces >> Surface Arrays.
779 uint32_t H0_sa
= phys_level0_sa
->h
;
780 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
782 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
783 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
786 if (ISL_DEV_GEN(dev
) >= 7) {
787 /* The QPitch equation changed slightly in Ivybridge. */
793 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
795 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
796 (info
->height
% 4 == 1)) {
797 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
798 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
800 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
801 * the value calculated in the equation above , for every
802 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
804 * XXX(chadv): Is the errata natural corollary of the physical
805 * layout of interleaved samples?
810 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
815 case ISL_DIM_LAYOUT_GEN4_3D
:
816 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
817 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
820 unreachable("bad isl_dim_layout");
824 assert(pitch_sa_rows
% fmtl
->bh
== 0);
825 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
827 if (ISL_DEV_GEN(dev
) >= 9 &&
828 info
->dim
== ISL_SURF_DIM_3D
&&
829 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
830 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
832 * Tile Mode != Linear: This field must be set to an integer multiple
835 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->height
);
838 return pitch_el_rows
;
842 * Calculate the pitch of each surface row, in bytes.
845 isl_calc_row_pitch(const struct isl_device
*dev
,
846 const struct isl_surf_init_info
*restrict info
,
847 const struct isl_tile_info
*tile_info
,
848 const struct isl_extent3d
*image_align_sa
,
849 const struct isl_extent2d
*phys_slice0_sa
)
851 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
853 uint32_t row_pitch
= info
->min_pitch
;
855 /* First, align the surface to a cache line boundary, as the PRM explains
858 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
859 * Formats >> Surface Padding Requirements >> Render Target and Media
862 * The data port accesses data (pixels) outside of the surface if they
863 * are contained in the same cache request as pixels that are within the
864 * surface. These pixels will not be returned by the requesting message,
865 * however if these pixels lie outside of defined pages in the GTT,
866 * a GTT error will result when the cache request is processed. In order
867 * to avoid these GTT errors, “padding” at the bottom of the surface is
868 * sometimes necessary.
870 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
871 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
873 * The sampling engine accesses texels outside of the surface if they
874 * are contained in the same cache line as texels that are within the
875 * surface. These texels will not participate in any calculation
876 * performed by the sampling engine and will not affect the result of
877 * any sampling engine operation, however if these texels lie outside of
878 * defined pages in the GTT, a GTT error will result when the cache line
879 * is accessed. In order to avoid these GTT errors, “padding” at the
880 * bottom and right side of a sampling engine surface is sometimes
883 * It is possible that a cache line will straddle a page boundary if the
884 * base address or pitch is not aligned. All pages included in the cache
885 * lines that are part of the surface must map to valid GTT entries to
886 * avoid errors. To determine the necessary padding on the bottom and
887 * right side of the surface, refer to the table in Alignment Unit Size
888 * section for the i and j parameters for the surface format in use. The
889 * surface must then be extended to the next multiple of the alignment
890 * unit size in each dimension, and all texels contained in this
891 * extended surface must have valid GTT entries.
893 * For example, suppose the surface size is 15 texels by 10 texels and
894 * the alignment parameters are i=4 and j=2. In this case, the extended
895 * surface would be 16 by 10. Note that these calculations are done in
896 * texels, and must be converted to bytes based on the surface format
897 * being used to determine whether additional pages need to be defined.
899 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
900 row_pitch
= MAX(row_pitch
, fmtl
->bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
902 switch (tile_info
->tiling
) {
903 case ISL_TILING_LINEAR
:
904 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
905 * RENDER_SURFACE_STATE Surface Pitch (p349):
907 * - For linear render target surfaces and surfaces accessed with the
908 * typed data port messages, the pitch must be a multiple of the
909 * element size for non-YUV surface formats. Pitch must be
910 * a multiple of 2 * element size for YUV surface formats.
912 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
913 * ignore because isl doesn't do buffers.]
915 * - For other linear surfaces, the pitch can be any multiple of
918 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
919 if (isl_format_is_yuv(info
->format
)) {
920 row_pitch
= isl_align_npot(row_pitch
, 2 * fmtl
->bs
);
922 row_pitch
= isl_align_npot(row_pitch
, fmtl
->bs
);
927 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
928 * RENDER_SURFACE_STATE Surface Pitch (p349):
930 * - For tiled surfaces, the pitch must be a multiple of the tile
933 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
941 * Calculate the surface's total height, including padding, in units of
945 isl_calc_total_height_el(const struct isl_device
*dev
,
946 const struct isl_surf_init_info
*restrict info
,
947 const struct isl_tile_info
*tile_info
,
948 uint32_t phys_array_len
,
950 uint32_t array_pitch_el_rows
)
952 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
954 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
955 uint32_t pad_bytes
= 0;
957 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
958 * Formats >> Surface Padding Requirements >> Render Target and Media
961 * The data port accesses data (pixels) outside of the surface if they
962 * are contained in the same cache request as pixels that are within the
963 * surface. These pixels will not be returned by the requesting message,
964 * however if these pixels lie outside of defined pages in the GTT,
965 * a GTT error will result when the cache request is processed. In
966 * order to avoid these GTT errors, “padding” at the bottom of the
967 * surface is sometimes necessary.
969 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
970 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
972 * ... Lots of padding requirements, all listed separately below.
975 /* We can safely ignore the first padding requirement, quoted below,
976 * because isl doesn't do buffers.
978 * - [pre-BDW] For buffers, which have no inherent “height,” padding
979 * requirements are different. A buffer must be padded to the next
980 * multiple of 256 array elements, with an additional 16 bytes added
981 * beyond that to account for the L1 cache line.
985 * - For compressed textures [...], padding at the bottom of the surface
986 * is to an even compressed row.
988 if (isl_format_is_compressed(info
->format
))
989 total_h_el
= isl_align(total_h_el
, 2);
992 * - For cube surfaces, an additional two rows of padding are required
993 * at the bottom of the surface.
995 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
999 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1000 * additional padding is required. These surfaces require an extra row
1001 * plus 16 bytes of padding at the bottom in addition to the general
1002 * padding requirements.
1004 if (isl_format_is_yuv(info
->format
) &&
1005 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
1011 * - For linear surfaces, additional padding of 64 bytes is required at
1012 * the bottom of the surface. This is in addition to the padding
1015 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1018 /* The below text weakens, not strengthens, the padding requirements for
1019 * linear surfaces. Therefore we can safely ignore it.
1021 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1022 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1023 * padding requirement is to the next aligned 64-byte boundary beyond
1024 * the end of the surface. The rest of the padding requirements
1025 * documented above do not apply to these surfaces.
1029 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1030 * height % 4 != 0, the surface must be padded with
1031 * 4-(height % 4)*Surface Pitch # of bytes.
1033 if (ISL_DEV_GEN(dev
) >= 9 &&
1034 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1035 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1036 total_h_el
= isl_align(total_h_el
, 4);
1040 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1041 * to 4 times the Surface Pitch # of bytes
1043 if (ISL_DEV_GEN(dev
) >= 9 &&
1044 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1045 info
->dim
== ISL_SURF_DIM_1D
) {
1049 /* Be sloppy. Align any leftover padding to a row boundary. */
1050 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1056 isl_surf_init_s(const struct isl_device
*dev
,
1057 struct isl_surf
*surf
,
1058 const struct isl_surf_init_info
*restrict info
)
1060 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1062 const struct isl_extent4d logical_level0_px
= {
1066 .a
= info
->array_len
,
1069 enum isl_dim_layout dim_layout
=
1070 isl_surf_choose_dim_layout(dev
, info
->dim
);
1072 enum isl_tiling tiling
;
1073 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1076 struct isl_tile_info tile_info
;
1077 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
1080 enum isl_msaa_layout msaa_layout
;
1081 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1084 struct isl_extent3d image_align_el
;
1085 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1088 struct isl_extent3d image_align_sa
=
1089 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1091 struct isl_extent4d phys_level0_sa
;
1092 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1094 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1095 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1097 enum isl_array_pitch_span array_pitch_span
=
1098 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1100 struct isl_extent2d phys_slice0_sa
;
1101 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1102 &image_align_sa
, &phys_level0_sa
,
1104 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1105 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1107 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1111 const uint32_t array_pitch_el_rows
=
1112 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1113 array_pitch_span
, &image_align_sa
,
1114 &phys_level0_sa
, &phys_slice0_sa
);
1116 const uint32_t total_h_el
=
1117 isl_calc_total_height_el(dev
, info
, &tile_info
,
1118 phys_level0_sa
.array_len
, row_pitch
,
1119 array_pitch_el_rows
);
1121 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1122 const uint32_t size
= row_pitch
* isl_align(total_h_sa
, tile_info
.height
);
1124 /* Alignment of surface base address, in bytes */
1125 uint32_t base_alignment
= MAX(1, info
->min_alignment
);
1126 assert(isl_is_pow2(base_alignment
) && isl_is_pow2(tile_info
.size
));
1127 base_alignment
= MAX(base_alignment
, tile_info
.size
);
1129 *surf
= (struct isl_surf
) {
1131 .dim_layout
= dim_layout
,
1132 .msaa_layout
= msaa_layout
,
1134 .format
= info
->format
,
1136 .levels
= info
->levels
,
1137 .samples
= info
->samples
,
1139 .image_alignment_el
= image_align_el
,
1140 .logical_level0_px
= logical_level0_px
,
1141 .phys_level0_sa
= phys_level0_sa
,
1144 .alignment
= base_alignment
,
1145 .row_pitch
= row_pitch
,
1146 .array_pitch_el_rows
= array_pitch_el_rows
,
1147 .array_pitch_span
= array_pitch_span
,
1149 .usage
= info
->usage
,
1156 isl_surf_get_tile_info(const struct isl_device
*dev
,
1157 const struct isl_surf
*surf
,
1158 struct isl_tile_info
*tile_info
)
1160 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1161 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bs
, tile_info
);
1165 * A variant of isl_surf_get_image_offset_sa() specific to
1166 * ISL_DIM_LAYOUT_GEN4_2D.
1169 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1170 uint32_t level
, uint32_t layer
,
1171 uint32_t *x_offset_sa
,
1172 uint32_t *y_offset_sa
)
1174 assert(level
< surf
->levels
);
1175 assert(layer
< surf
->phys_level0_sa
.array_len
);
1176 assert(surf
->phys_level0_sa
.depth
== 1);
1178 const struct isl_extent3d image_align_sa
=
1179 isl_surf_get_image_alignment_sa(surf
);
1181 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1182 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1185 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1187 for (uint32_t l
= 0; l
< level
; ++l
) {
1189 uint32_t W
= isl_minify(W0
, l
);
1191 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1192 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1194 x
+= isl_align_npot(W
, image_align_sa
.w
);
1196 uint32_t H
= isl_minify(H0
, l
);
1198 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1199 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1201 y
+= isl_align_npot(H
, image_align_sa
.h
);
1210 * A variant of isl_surf_get_image_offset_sa() specific to
1211 * ISL_DIM_LAYOUT_GEN4_3D.
1214 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1215 uint32_t level
, uint32_t logical_z_offset_px
,
1216 uint32_t *x_offset_sa
,
1217 uint32_t *y_offset_sa
)
1219 assert(level
< surf
->levels
);
1220 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1221 assert(surf
->phys_level0_sa
.array_len
== 1);
1223 const struct isl_extent3d image_align_sa
=
1224 isl_surf_get_image_alignment_sa(surf
);
1226 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1227 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1228 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1233 for (uint32_t l
= 0; l
< level
; ++l
) {
1234 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1235 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1236 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1238 y
+= level_h
* max_layers_vert
;
1241 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1242 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1243 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1245 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1247 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1248 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1255 * A variant of isl_surf_get_image_offset_sa() specific to
1256 * ISL_DIM_LAYOUT_GEN9_1D.
1259 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1260 uint32_t level
, uint32_t layer
,
1261 uint32_t *x_offset_sa
,
1262 uint32_t *y_offset_sa
)
1264 assert(level
< surf
->levels
);
1265 assert(layer
< surf
->phys_level0_sa
.array_len
);
1266 assert(surf
->phys_level0_sa
.height
== 1);
1267 assert(surf
->phys_level0_sa
.depth
== 1);
1268 assert(surf
->samples
== 1);
1270 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1271 const struct isl_extent3d image_align_sa
=
1272 isl_surf_get_image_alignment_sa(surf
);
1276 for (uint32_t l
= 0; l
< level
; ++l
) {
1277 uint32_t W
= isl_minify(W0
, l
);
1278 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1284 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1288 * Calculate the offset, in units of surface samples, to a subimage in the
1291 * @invariant level < surface levels
1292 * @invariant logical_array_layer < logical array length of surface
1293 * @invariant logical_z_offset_px < logical depth of surface at level
1296 get_image_offset_sa(const struct isl_surf
*surf
,
1298 uint32_t logical_array_layer
,
1299 uint32_t logical_z_offset_px
,
1300 uint32_t *x_offset_sa
,
1301 uint32_t *y_offset_sa
)
1303 assert(level
< surf
->levels
);
1304 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1305 assert(logical_z_offset_px
1306 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1308 switch (surf
->dim_layout
) {
1309 case ISL_DIM_LAYOUT_GEN9_1D
:
1310 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1311 x_offset_sa
, y_offset_sa
);
1313 case ISL_DIM_LAYOUT_GEN4_2D
:
1314 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1315 + logical_z_offset_px
,
1316 x_offset_sa
, y_offset_sa
);
1318 case ISL_DIM_LAYOUT_GEN4_3D
:
1319 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1320 x_offset_sa
, y_offset_sa
);
1326 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1328 uint32_t logical_array_layer
,
1329 uint32_t logical_z_offset_px
,
1330 uint32_t *x_offset_el
,
1331 uint32_t *y_offset_el
)
1333 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1335 assert(level
< surf
->levels
);
1336 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1337 assert(logical_z_offset_px
1338 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1340 uint32_t x_offset_sa
, y_offset_sa
;
1341 get_image_offset_sa(surf
, level
,
1342 logical_array_layer
,
1343 logical_z_offset_px
,
1347 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1348 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1352 isl_surf_get_image_intratile_offset_el(const struct isl_device
*dev
,
1353 const struct isl_surf
*surf
,
1355 uint32_t logical_array_layer
,
1356 uint32_t logical_z_offset
,
1357 uint32_t *base_address_offset
,
1358 uint32_t *x_offset_el
,
1359 uint32_t *y_offset_el
)
1361 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1363 struct isl_tile_info tile_info
;
1364 isl_surf_get_tile_info(dev
, surf
, &tile_info
);
1366 uint32_t total_x_offset_el
;
1367 uint32_t total_y_offset_el
;
1368 isl_surf_get_image_offset_el(surf
, level
,
1369 logical_array_layer
,
1372 &total_y_offset_el
);
1374 uint32_t small_y_offset_el
= total_y_offset_el
% tile_info
.height
;
1375 uint32_t big_y_offset_el
= total_y_offset_el
- small_y_offset_el
;
1376 uint32_t big_y_offset_B
= big_y_offset_el
* surf
->row_pitch
;
1378 uint32_t total_x_offset_B
= total_x_offset_el
* fmtl
->bs
;
1379 uint32_t small_x_offset_B
= total_x_offset_B
% tile_info
.width
;
1380 uint32_t small_x_offset_el
= small_x_offset_B
/ fmtl
->bs
;
1381 uint32_t big_x_offset_B
= (total_x_offset_B
/ tile_info
.width
) * tile_info
.size
;
1383 *base_address_offset
= big_y_offset_B
+ big_x_offset_B
;
1384 *x_offset_el
= small_x_offset_el
;
1385 *y_offset_el
= small_y_offset_el
;
1389 isl_surf_get_depth_format(const struct isl_device
*dev
,
1390 const struct isl_surf
*surf
)
1392 /* Support for separate stencil buffers began in gen5. Support for
1393 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1394 * those that supported separate and interleaved stencil, were gen5 and
1397 * For a list of all available formats, see the Sandybridge PRM >> Volume
1398 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1402 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1404 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1407 assert(ISL_DEV_GEN(dev
) < 7);
1409 switch (surf
->format
) {
1411 unreachable("bad isl depth format");
1412 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1413 assert(ISL_DEV_GEN(dev
) < 7);
1414 return 0; /* D32_FLOAT_S8X24_UINT */
1415 case ISL_FORMAT_R32_FLOAT
:
1416 assert(!has_stencil
);
1417 return 1; /* D32_FLOAT */
1418 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1420 assert(ISL_DEV_GEN(dev
) < 7);
1421 return 2; /* D24_UNORM_S8_UINT */
1423 assert(ISL_DEV_GEN(dev
) >= 5);
1424 return 3; /* D24_UNORM_X8_UINT */
1426 case ISL_FORMAT_R16_UNORM
:
1427 assert(!has_stencil
);
1428 return 5; /* D16_UNORM */