2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct brw_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 assert(ISL_DEV_GEN(dev
) == dev
->info
->gen
);
63 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
) == dev
->use_separate_stencil
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
110 uint32_t format_block_size
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_block_size
;
114 uint32_t width
, height
;
119 case ISL_TILING_LINEAR
:
135 /* XXX: Should W tile be same as Y? */
141 case ISL_TILING_Ys
: {
142 if (ISL_DEV_GEN(dev
) < 9)
145 if (!isl_is_pow2(bs
))
148 bool is_Ys
= tiling
== ISL_TILING_Ys
;
150 width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
151 height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
156 *tile_info
= (struct isl_tile_info
) {
160 .size
= width
* height
,
167 isl_tiling_get_extent(const struct isl_device
*dev
,
168 enum isl_tiling tiling
,
169 uint32_t format_block_size
,
170 struct isl_extent2d
*e
)
172 struct isl_tile_info tile_info
;
173 isl_tiling_get_info(dev
, tiling
, format_block_size
, &tile_info
);
174 *e
= isl_extent2d(tile_info
.width
, tile_info
.height
);
178 * @param[out] tiling is set only on success
181 isl_surf_choose_tiling(const struct isl_device
*dev
,
182 const struct isl_surf_init_info
*restrict info
,
183 enum isl_tiling
*tiling
)
185 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
187 /* Filter if multiple tiling options are given */
188 if (!isl_is_pow2(tiling_flags
)) {
189 if (ISL_DEV_GEN(dev
) >= 7) {
190 gen7_filter_tiling(dev
, info
, &tiling_flags
);
192 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
193 gen7_filter_tiling(dev
, info
, &tiling_flags
);
197 #define CHOOSE(__tiling) \
199 if (tiling_flags & (1u << (__tiling))) { \
200 *tiling = (__tiling); \
205 /* Of the tiling modes remaining, choose the one that offers the best
209 if (info
->dim
== ISL_SURF_DIM_1D
) {
210 /* Prefer linear for 1D surfaces because they do not benefit from
211 * tiling. To the contrary, tiling leads to wasted memory and poor
212 * memory locality due to the swizzling and alignment restrictions
213 * required in tiled surfaces.
215 CHOOSE(ISL_TILING_LINEAR
);
218 CHOOSE(ISL_TILING_Ys
);
219 CHOOSE(ISL_TILING_Yf
);
220 CHOOSE(ISL_TILING_Y0
);
221 CHOOSE(ISL_TILING_X
);
222 CHOOSE(ISL_TILING_W
);
223 CHOOSE(ISL_TILING_LINEAR
);
227 /* No tiling mode accomodates the inputs. */
232 isl_choose_msaa_layout(const struct isl_device
*dev
,
233 const struct isl_surf_init_info
*info
,
234 enum isl_tiling tiling
,
235 enum isl_msaa_layout
*msaa_layout
)
237 if (ISL_DEV_GEN(dev
) >= 8) {
238 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
239 } else if (ISL_DEV_GEN(dev
) >= 7) {
240 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
241 } else if (ISL_DEV_GEN(dev
) >= 6) {
242 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
244 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
249 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
250 uint32_t *width
, uint32_t *height
)
252 assert(isl_is_pow2(samples
));
254 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
257 * If the surface is multisampled and it is a depth or stencil surface
258 * or Multisampled Surface StorageFormat in SURFACE_STATE is
259 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
263 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
265 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
268 static enum isl_array_pitch_span
269 isl_choose_array_pitch_span(const struct isl_device
*dev
,
270 const struct isl_surf_init_info
*restrict info
,
271 enum isl_dim_layout dim_layout
,
272 const struct isl_extent4d
*phys_level0_sa
)
274 switch (dim_layout
) {
275 case ISL_DIM_LAYOUT_GEN9_1D
:
276 case ISL_DIM_LAYOUT_GEN4_2D
:
277 if (ISL_DEV_GEN(dev
) >= 8) {
278 /* QPitch becomes programmable in Broadwell. So choose the
279 * most compact QPitch possible in order to conserve memory.
281 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
282 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
284 * - Software must ensure that this field is set to a value
285 * sufficiently large such that the array slices in the surface
286 * do not overlap. Refer to the Memory Data Formats section for
287 * information on how surfaces are stored in memory.
289 * - This field specifies the distance in rows between array
290 * slices. It is used only in the following cases:
292 * - Surface Array is enabled OR
293 * - Number of Mulitsamples is not NUMSAMPLES_1 and
294 * Multisampled Surface Storage Format set to MSFMT_MSS OR
295 * - Surface Type is SURFTYPE_CUBE
297 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
298 } else if (ISL_DEV_GEN(dev
) >= 7) {
299 /* Note that Ivybridge introduces
300 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
301 * driver more control over the QPitch.
304 if (phys_level0_sa
->array_len
== 1) {
305 /* The hardware will never use the QPitch. So choose the most
306 * compact QPitch possible in order to conserve memory.
308 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
311 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
312 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
313 * Section 6.18.4.7: Surface Arrays (p112):
315 * If Surface Array Spacing is set to ARYSPC_FULL (note that
316 * the depth buffer and stencil buffer have an implied value of
319 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
322 if (info
->levels
== 1) {
323 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
326 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
329 return ISL_ARRAY_PITCH_SPAN_FULL
;
330 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
331 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
332 isl_surf_usage_is_stencil(info
->usage
)) {
333 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
334 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
336 * The separate stencil buffer does not support mip mapping, thus
337 * the storage for LODs other than LOD 0 is not needed.
339 assert(info
->levels
== 1);
340 assert(phys_level0_sa
->array_len
== 1);
341 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
343 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
344 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
345 isl_surf_usage_is_stencil(info
->usage
)) {
346 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
347 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
349 * The separate stencil buffer does not support mip mapping,
350 * thus the storage for LODs other than LOD 0 is not needed.
352 assert(info
->levels
== 1);
353 assert(phys_level0_sa
->array_len
== 1);
354 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
357 if (phys_level0_sa
->array_len
== 1) {
358 /* The hardware will never use the QPitch. So choose the most
359 * compact QPitch possible in order to conserve memory.
361 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
364 return ISL_ARRAY_PITCH_SPAN_FULL
;
367 case ISL_DIM_LAYOUT_GEN4_3D
:
368 /* The hardware will never use the QPitch. So choose the most
369 * compact QPitch possible in order to conserve memory.
371 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
374 unreachable("bad isl_dim_layout");
375 return ISL_ARRAY_PITCH_SPAN_FULL
;
379 isl_choose_image_alignment_el(const struct isl_device
*dev
,
380 const struct isl_surf_init_info
*restrict info
,
381 enum isl_tiling tiling
,
382 enum isl_msaa_layout msaa_layout
,
383 struct isl_extent3d
*image_align_el
)
385 if (ISL_DEV_GEN(dev
) >= 9) {
386 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
388 } else if (ISL_DEV_GEN(dev
) >= 8) {
389 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
391 } else if (ISL_DEV_GEN(dev
) >= 7) {
392 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
394 } else if (ISL_DEV_GEN(dev
) >= 6) {
395 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
398 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
403 static enum isl_dim_layout
404 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
405 enum isl_surf_dim logical_dim
)
407 if (ISL_DEV_GEN(dev
) >= 9) {
408 switch (logical_dim
) {
409 case ISL_SURF_DIM_1D
:
410 return ISL_DIM_LAYOUT_GEN9_1D
;
411 case ISL_SURF_DIM_2D
:
412 case ISL_SURF_DIM_3D
:
413 return ISL_DIM_LAYOUT_GEN4_2D
;
416 switch (logical_dim
) {
417 case ISL_SURF_DIM_1D
:
418 case ISL_SURF_DIM_2D
:
419 return ISL_DIM_LAYOUT_GEN4_2D
;
420 case ISL_SURF_DIM_3D
:
421 return ISL_DIM_LAYOUT_GEN4_3D
;
425 unreachable("bad isl_surf_dim");
426 return ISL_DIM_LAYOUT_GEN4_2D
;
430 * Calculate the physical extent of the surface's first level, in units of
431 * surface samples. The result is aligned to the format's compression block.
434 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
435 const struct isl_surf_init_info
*restrict info
,
436 enum isl_dim_layout dim_layout
,
437 enum isl_tiling tiling
,
438 enum isl_msaa_layout msaa_layout
,
439 struct isl_extent4d
*phys_level0_sa
)
441 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
443 if (isl_format_is_yuv(info
->format
))
444 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
447 case ISL_SURF_DIM_1D
:
448 assert(info
->height
== 1);
449 assert(info
->depth
== 1);
450 assert(info
->samples
== 1);
451 assert(!isl_format_is_compressed(info
->format
));
453 switch (dim_layout
) {
454 case ISL_DIM_LAYOUT_GEN4_3D
:
455 unreachable("bad isl_dim_layout");
457 case ISL_DIM_LAYOUT_GEN9_1D
:
458 case ISL_DIM_LAYOUT_GEN4_2D
:
459 *phys_level0_sa
= (struct isl_extent4d
) {
463 .a
= info
->array_len
,
469 case ISL_SURF_DIM_2D
:
470 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
472 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
473 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
475 switch (msaa_layout
) {
476 case ISL_MSAA_LAYOUT_NONE
:
477 assert(info
->depth
== 1);
478 assert(info
->samples
== 1);
480 *phys_level0_sa
= (struct isl_extent4d
) {
481 .w
= isl_align(info
->width
, fmtl
->bw
),
482 .h
= isl_align(info
->height
, fmtl
->bh
),
484 .a
= info
->array_len
,
488 case ISL_MSAA_LAYOUT_ARRAY
:
489 assert(info
->depth
== 1);
490 assert(info
->array_len
== 1);
491 assert(!isl_format_is_compressed(info
->format
));
493 *phys_level0_sa
= (struct isl_extent4d
) {
501 case ISL_MSAA_LAYOUT_INTERLEAVED
:
502 assert(info
->depth
== 1);
503 assert(info
->array_len
== 1);
504 assert(!isl_format_is_compressed(info
->format
));
506 *phys_level0_sa
= (struct isl_extent4d
) {
513 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
520 case ISL_SURF_DIM_3D
:
521 assert(info
->array_len
== 1);
522 assert(info
->samples
== 1);
525 isl_finishme("%s:%s: compression block with depth > 1",
529 switch (dim_layout
) {
530 case ISL_DIM_LAYOUT_GEN9_1D
:
531 unreachable("bad isl_dim_layout");
533 case ISL_DIM_LAYOUT_GEN4_2D
:
534 assert(ISL_DEV_GEN(dev
) >= 9);
536 *phys_level0_sa
= (struct isl_extent4d
) {
537 .w
= isl_align(info
->width
, fmtl
->bw
),
538 .h
= isl_align(info
->height
, fmtl
->bh
),
544 case ISL_DIM_LAYOUT_GEN4_3D
:
545 assert(ISL_DEV_GEN(dev
) < 9);
546 *phys_level0_sa
= (struct isl_extent4d
) {
547 .w
= isl_align(info
->width
, fmtl
->bw
),
548 .h
= isl_align(info
->height
, fmtl
->bh
),
559 * A variant of isl_calc_phys_slice0_extent_sa() specific to
560 * ISL_DIM_LAYOUT_GEN4_2D.
563 isl_calc_phys_slice0_extent_sa_gen4_2d(
564 const struct isl_device
*dev
,
565 const struct isl_surf_init_info
*restrict info
,
566 enum isl_msaa_layout msaa_layout
,
567 const struct isl_extent3d
*image_align_sa
,
568 const struct isl_extent4d
*phys_level0_sa
,
569 struct isl_extent2d
*phys_slice0_sa
)
571 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
573 assert(phys_level0_sa
->depth
== 1);
575 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
576 /* Do not pad the surface to the image alignment. Instead, pad it only
577 * to the pixel format's block alignment.
579 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
580 * cycles on the below mipmap layout caluclations. Reducing the
581 * alignment here is safe because we later align the row pitch and array
582 * pitch to the tile boundary. It is safe even for
583 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
584 * to accomodate the interleaved samples.
586 * For linear surfaces, reducing the alignment here permits us to later
587 * choose an arbitrary, non-aligned row pitch. If the surface backs
588 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
589 * VkBufferImageCopy::bufferRowLength.
591 *phys_slice0_sa
= (struct isl_extent2d
) {
592 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
593 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
598 uint32_t slice_top_w
= 0;
599 uint32_t slice_bottom_w
= 0;
600 uint32_t slice_left_h
= 0;
601 uint32_t slice_right_h
= 0;
603 uint32_t W0
= phys_level0_sa
->w
;
604 uint32_t H0
= phys_level0_sa
->h
;
606 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
607 uint32_t W
= isl_minify(W0
, l
);
608 uint32_t H
= isl_minify(H0
, l
);
610 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
611 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
614 * If the surface is multisampled and it is a depth or stencil
615 * surface or Multisampled Surface StorageFormat in
616 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
617 * adjusted as follows before proceeding: [...]
619 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
622 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
623 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
640 *phys_slice0_sa
= (struct isl_extent2d
) {
641 .w
= MAX(slice_top_w
, slice_bottom_w
),
642 .h
= MAX(slice_left_h
, slice_right_h
),
647 * A variant of isl_calc_phys_slice0_extent_sa() specific to
648 * ISL_DIM_LAYOUT_GEN4_3D.
651 isl_calc_phys_slice0_extent_sa_gen4_3d(
652 const struct isl_device
*dev
,
653 const struct isl_surf_init_info
*restrict info
,
654 const struct isl_extent3d
*image_align_sa
,
655 const struct isl_extent4d
*phys_level0_sa
,
656 struct isl_extent2d
*phys_slice0_sa
)
658 assert(info
->samples
== 1);
659 assert(phys_level0_sa
->array_len
== 1);
661 uint32_t slice_w
= 0;
662 uint32_t slice_h
= 0;
664 uint32_t W0
= phys_level0_sa
->w
;
665 uint32_t H0
= phys_level0_sa
->h
;
666 uint32_t D0
= phys_level0_sa
->d
;
668 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
669 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
670 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
671 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
673 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
674 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
676 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
677 slice_h
+= level_h
* max_layers_vert
;
680 *phys_slice0_sa
= (struct isl_extent2d
) {
687 * A variant of isl_calc_phys_slice0_extent_sa() specific to
688 * ISL_DIM_LAYOUT_GEN9_1D.
691 isl_calc_phys_slice0_extent_sa_gen9_1d(
692 const struct isl_device
*dev
,
693 const struct isl_surf_init_info
*restrict info
,
694 const struct isl_extent3d
*image_align_sa
,
695 const struct isl_extent4d
*phys_level0_sa
,
696 struct isl_extent2d
*phys_slice0_sa
)
698 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
700 assert(phys_level0_sa
->height
== 1);
701 assert(phys_level0_sa
->depth
== 1);
702 assert(info
->samples
== 1);
703 assert(image_align_sa
->w
>= fmtl
->bw
);
705 uint32_t slice_w
= 0;
706 const uint32_t W0
= phys_level0_sa
->w
;
708 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
709 uint32_t W
= isl_minify(W0
, l
);
710 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
715 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
719 * Calculate the physical extent of the surface's first array slice, in units
720 * of surface samples. If the surface is multi-leveled, then the result will
721 * be aligned to \a image_align_sa.
724 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
725 const struct isl_surf_init_info
*restrict info
,
726 enum isl_dim_layout dim_layout
,
727 enum isl_msaa_layout msaa_layout
,
728 const struct isl_extent3d
*image_align_sa
,
729 const struct isl_extent4d
*phys_level0_sa
,
730 struct isl_extent2d
*phys_slice0_sa
)
732 switch (dim_layout
) {
733 case ISL_DIM_LAYOUT_GEN9_1D
:
734 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
735 image_align_sa
, phys_level0_sa
,
738 case ISL_DIM_LAYOUT_GEN4_2D
:
739 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
740 image_align_sa
, phys_level0_sa
,
743 case ISL_DIM_LAYOUT_GEN4_3D
:
744 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
745 phys_level0_sa
, phys_slice0_sa
);
751 * Calculate the pitch between physical array slices, in units of rows of
755 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
756 const struct isl_surf_init_info
*restrict info
,
757 const struct isl_tile_info
*tile_info
,
758 enum isl_dim_layout dim_layout
,
759 enum isl_array_pitch_span array_pitch_span
,
760 const struct isl_extent3d
*image_align_sa
,
761 const struct isl_extent4d
*phys_level0_sa
,
762 const struct isl_extent2d
*phys_slice0_sa
)
764 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
765 uint32_t pitch_sa_rows
= 0;
767 switch (dim_layout
) {
768 case ISL_DIM_LAYOUT_GEN9_1D
:
769 /* Each row is an array slice */
772 case ISL_DIM_LAYOUT_GEN4_2D
:
773 switch (array_pitch_span
) {
774 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
775 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
777 case ISL_ARRAY_PITCH_SPAN_FULL
: {
778 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
779 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
780 * Surfaces >> Surface Arrays.
782 uint32_t H0_sa
= phys_level0_sa
->h
;
783 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
785 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
786 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
789 if (ISL_DEV_GEN(dev
) >= 7) {
790 /* The QPitch equation changed slightly in Ivybridge. */
796 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
798 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
799 (info
->height
% 4 == 1)) {
800 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
801 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
803 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
804 * the value calculated in the equation above , for every
805 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
807 * XXX(chadv): Is the errata natural corollary of the physical
808 * layout of interleaved samples?
813 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
818 case ISL_DIM_LAYOUT_GEN4_3D
:
819 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
820 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
823 unreachable("bad isl_dim_layout");
827 assert(pitch_sa_rows
% fmtl
->bh
== 0);
828 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
830 if (ISL_DEV_GEN(dev
) >= 9 &&
831 info
->dim
== ISL_SURF_DIM_3D
&&
832 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
833 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
835 * Tile Mode != Linear: This field must be set to an integer multiple
838 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->height
);
841 return pitch_el_rows
;
845 * Calculate the pitch of each surface row, in bytes.
848 isl_calc_row_pitch(const struct isl_device
*dev
,
849 const struct isl_surf_init_info
*restrict info
,
850 const struct isl_tile_info
*tile_info
,
851 const struct isl_extent3d
*image_align_sa
,
852 const struct isl_extent2d
*phys_slice0_sa
)
854 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
856 uint32_t row_pitch
= info
->min_pitch
;
858 /* First, align the surface to a cache line boundary, as the PRM explains
861 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
862 * Formats >> Surface Padding Requirements >> Render Target and Media
865 * The data port accesses data (pixels) outside of the surface if they
866 * are contained in the same cache request as pixels that are within the
867 * surface. These pixels will not be returned by the requesting message,
868 * however if these pixels lie outside of defined pages in the GTT,
869 * a GTT error will result when the cache request is processed. In order
870 * to avoid these GTT errors, “padding” at the bottom of the surface is
871 * sometimes necessary.
873 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
874 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
876 * The sampling engine accesses texels outside of the surface if they
877 * are contained in the same cache line as texels that are within the
878 * surface. These texels will not participate in any calculation
879 * performed by the sampling engine and will not affect the result of
880 * any sampling engine operation, however if these texels lie outside of
881 * defined pages in the GTT, a GTT error will result when the cache line
882 * is accessed. In order to avoid these GTT errors, “padding” at the
883 * bottom and right side of a sampling engine surface is sometimes
886 * It is possible that a cache line will straddle a page boundary if the
887 * base address or pitch is not aligned. All pages included in the cache
888 * lines that are part of the surface must map to valid GTT entries to
889 * avoid errors. To determine the necessary padding on the bottom and
890 * right side of the surface, refer to the table in Alignment Unit Size
891 * section for the i and j parameters for the surface format in use. The
892 * surface must then be extended to the next multiple of the alignment
893 * unit size in each dimension, and all texels contained in this
894 * extended surface must have valid GTT entries.
896 * For example, suppose the surface size is 15 texels by 10 texels and
897 * the alignment parameters are i=4 and j=2. In this case, the extended
898 * surface would be 16 by 10. Note that these calculations are done in
899 * texels, and must be converted to bytes based on the surface format
900 * being used to determine whether additional pages need to be defined.
902 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
903 row_pitch
= MAX(row_pitch
, fmtl
->bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
905 switch (tile_info
->tiling
) {
906 case ISL_TILING_LINEAR
:
907 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
908 * RENDER_SURFACE_STATE Surface Pitch (p349):
910 * - For linear render target surfaces and surfaces accessed with the
911 * typed data port messages, the pitch must be a multiple of the
912 * element size for non-YUV surface formats. Pitch must be
913 * a multiple of 2 * element size for YUV surface formats.
915 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
916 * ignore because isl doesn't do buffers.]
918 * - For other linear surfaces, the pitch can be any multiple of
921 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
922 if (isl_format_is_yuv(info
->format
)) {
923 row_pitch
= isl_align_npot(row_pitch
, 2 * fmtl
->bs
);
925 row_pitch
= isl_align_npot(row_pitch
, fmtl
->bs
);
930 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
931 * RENDER_SURFACE_STATE Surface Pitch (p349):
933 * - For tiled surfaces, the pitch must be a multiple of the tile
936 row_pitch
= isl_align(row_pitch
, tile_info
->width
);
944 * Calculate the surface's total height, including padding, in units of
948 isl_calc_total_height_el(const struct isl_device
*dev
,
949 const struct isl_surf_init_info
*restrict info
,
950 const struct isl_tile_info
*tile_info
,
951 uint32_t phys_array_len
,
953 uint32_t array_pitch_el_rows
)
955 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
957 uint32_t total_h_el
= phys_array_len
* array_pitch_el_rows
;
958 uint32_t pad_bytes
= 0;
960 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
961 * Formats >> Surface Padding Requirements >> Render Target and Media
964 * The data port accesses data (pixels) outside of the surface if they
965 * are contained in the same cache request as pixels that are within the
966 * surface. These pixels will not be returned by the requesting message,
967 * however if these pixels lie outside of defined pages in the GTT,
968 * a GTT error will result when the cache request is processed. In
969 * order to avoid these GTT errors, “padding” at the bottom of the
970 * surface is sometimes necessary.
972 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
973 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
975 * ... Lots of padding requirements, all listed separately below.
978 /* We can safely ignore the first padding requirement, quoted below,
979 * because isl doesn't do buffers.
981 * - [pre-BDW] For buffers, which have no inherent “height,” padding
982 * requirements are different. A buffer must be padded to the next
983 * multiple of 256 array elements, with an additional 16 bytes added
984 * beyond that to account for the L1 cache line.
988 * - For compressed textures [...], padding at the bottom of the surface
989 * is to an even compressed row.
991 if (isl_format_is_compressed(info
->format
))
992 total_h_el
= isl_align(total_h_el
, 2);
995 * - For cube surfaces, an additional two rows of padding are required
996 * at the bottom of the surface.
998 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1002 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1003 * additional padding is required. These surfaces require an extra row
1004 * plus 16 bytes of padding at the bottom in addition to the general
1005 * padding requirements.
1007 if (isl_format_is_yuv(info
->format
) &&
1008 (fmtl
->bs
== 96 || fmtl
->bs
== 48|| fmtl
->bs
== 24)) {
1014 * - For linear surfaces, additional padding of 64 bytes is required at
1015 * the bottom of the surface. This is in addition to the padding
1018 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1021 /* The below text weakens, not strengthens, the padding requirements for
1022 * linear surfaces. Therefore we can safely ignore it.
1024 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1025 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1026 * padding requirement is to the next aligned 64-byte boundary beyond
1027 * the end of the surface. The rest of the padding requirements
1028 * documented above do not apply to these surfaces.
1032 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1033 * height % 4 != 0, the surface must be padded with
1034 * 4-(height % 4)*Surface Pitch # of bytes.
1036 if (ISL_DEV_GEN(dev
) >= 9 &&
1037 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1038 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1039 total_h_el
= isl_align(total_h_el
, 4);
1043 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1044 * to 4 times the Surface Pitch # of bytes
1046 if (ISL_DEV_GEN(dev
) >= 9 &&
1047 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1048 info
->dim
== ISL_SURF_DIM_1D
) {
1052 /* Be sloppy. Align any leftover padding to a row boundary. */
1053 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1059 isl_surf_init_s(const struct isl_device
*dev
,
1060 struct isl_surf
*surf
,
1061 const struct isl_surf_init_info
*restrict info
)
1063 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1065 const struct isl_extent4d logical_level0_px
= {
1069 .a
= info
->array_len
,
1072 enum isl_dim_layout dim_layout
=
1073 isl_surf_choose_dim_layout(dev
, info
->dim
);
1075 enum isl_tiling tiling
;
1076 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1079 struct isl_tile_info tile_info
;
1080 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bs
, &tile_info
))
1083 enum isl_msaa_layout msaa_layout
;
1084 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1087 struct isl_extent3d image_align_el
;
1088 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1091 struct isl_extent3d image_align_sa
=
1092 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1094 struct isl_extent4d phys_level0_sa
;
1095 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1097 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1098 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1100 enum isl_array_pitch_span array_pitch_span
=
1101 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1103 struct isl_extent2d phys_slice0_sa
;
1104 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1105 &image_align_sa
, &phys_level0_sa
,
1107 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1108 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1110 const uint32_t row_pitch
= isl_calc_row_pitch(dev
, info
, &tile_info
,
1114 const uint32_t array_pitch_el_rows
=
1115 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1116 array_pitch_span
, &image_align_sa
,
1117 &phys_level0_sa
, &phys_slice0_sa
);
1119 const uint32_t total_h_el
=
1120 isl_calc_total_height_el(dev
, info
, &tile_info
,
1121 phys_level0_sa
.array_len
, row_pitch
,
1122 array_pitch_el_rows
);
1124 const uint32_t total_h_sa
= total_h_el
* fmtl
->bh
;
1125 const uint32_t size
= row_pitch
* isl_align(total_h_sa
, tile_info
.height
);
1127 /* Alignment of surface base address, in bytes */
1128 uint32_t base_alignment
= MAX(1, info
->min_alignment
);
1129 assert(isl_is_pow2(base_alignment
) && isl_is_pow2(tile_info
.size
));
1130 base_alignment
= MAX(base_alignment
, tile_info
.size
);
1132 *surf
= (struct isl_surf
) {
1134 .dim_layout
= dim_layout
,
1135 .msaa_layout
= msaa_layout
,
1137 .format
= info
->format
,
1139 .levels
= info
->levels
,
1140 .samples
= info
->samples
,
1142 .image_alignment_el
= image_align_el
,
1143 .logical_level0_px
= logical_level0_px
,
1144 .phys_level0_sa
= phys_level0_sa
,
1147 .alignment
= base_alignment
,
1148 .row_pitch
= row_pitch
,
1149 .array_pitch_el_rows
= array_pitch_el_rows
,
1150 .array_pitch_span
= array_pitch_span
,
1152 .usage
= info
->usage
,
1159 isl_surf_get_tile_info(const struct isl_device
*dev
,
1160 const struct isl_surf
*surf
,
1161 struct isl_tile_info
*tile_info
)
1163 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1164 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bs
, tile_info
);
1168 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1169 const struct isl_surf_fill_state_info
*restrict info
)
1172 isl_surf_usage_flags_t _base_usage
=
1173 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1174 ISL_SURF_USAGE_TEXTURE_BIT
|
1175 ISL_SURF_USAGE_STORAGE_BIT
);
1176 /* They may only specify one of the above bits at a time */
1177 assert(__builtin_popcount(_base_usage
) == 1);
1178 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1179 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1182 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1183 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1184 info
->surf
->logical_level0_px
.depth
);
1186 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1187 info
->surf
->logical_level0_px
.array_len
);
1190 switch (ISL_DEV_GEN(dev
)) {
1192 if (ISL_DEV_IS_HASWELL(dev
)) {
1193 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1195 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1199 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1202 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1205 assert(!"Cannot fill surface state for this gen");
1210 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1211 const struct isl_buffer_fill_state_info
*restrict info
)
1213 switch (ISL_DEV_GEN(dev
)) {
1215 if (ISL_DEV_IS_HASWELL(dev
)) {
1216 isl_gen75_buffer_fill_state_s(state
, info
);
1218 isl_gen7_buffer_fill_state_s(state
, info
);
1222 isl_gen8_buffer_fill_state_s(state
, info
);
1225 isl_gen9_buffer_fill_state_s(state
, info
);
1228 assert(!"Cannot fill surface state for this gen");
1233 * A variant of isl_surf_get_image_offset_sa() specific to
1234 * ISL_DIM_LAYOUT_GEN4_2D.
1237 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1238 uint32_t level
, uint32_t layer
,
1239 uint32_t *x_offset_sa
,
1240 uint32_t *y_offset_sa
)
1242 assert(level
< surf
->levels
);
1243 assert(layer
< surf
->phys_level0_sa
.array_len
);
1244 assert(surf
->phys_level0_sa
.depth
== 1);
1246 const struct isl_extent3d image_align_sa
=
1247 isl_surf_get_image_alignment_sa(surf
);
1249 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1250 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1253 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1255 for (uint32_t l
= 0; l
< level
; ++l
) {
1257 uint32_t W
= isl_minify(W0
, l
);
1259 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1260 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1262 x
+= isl_align_npot(W
, image_align_sa
.w
);
1264 uint32_t H
= isl_minify(H0
, l
);
1266 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1267 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1269 y
+= isl_align_npot(H
, image_align_sa
.h
);
1278 * A variant of isl_surf_get_image_offset_sa() specific to
1279 * ISL_DIM_LAYOUT_GEN4_3D.
1282 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1283 uint32_t level
, uint32_t logical_z_offset_px
,
1284 uint32_t *x_offset_sa
,
1285 uint32_t *y_offset_sa
)
1287 assert(level
< surf
->levels
);
1288 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1289 assert(surf
->phys_level0_sa
.array_len
== 1);
1291 const struct isl_extent3d image_align_sa
=
1292 isl_surf_get_image_alignment_sa(surf
);
1294 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1295 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1296 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1301 for (uint32_t l
= 0; l
< level
; ++l
) {
1302 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1303 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1304 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1306 y
+= level_h
* max_layers_vert
;
1309 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1310 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1311 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1313 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1315 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1316 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1323 * A variant of isl_surf_get_image_offset_sa() specific to
1324 * ISL_DIM_LAYOUT_GEN9_1D.
1327 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1328 uint32_t level
, uint32_t layer
,
1329 uint32_t *x_offset_sa
,
1330 uint32_t *y_offset_sa
)
1332 assert(level
< surf
->levels
);
1333 assert(layer
< surf
->phys_level0_sa
.array_len
);
1334 assert(surf
->phys_level0_sa
.height
== 1);
1335 assert(surf
->phys_level0_sa
.depth
== 1);
1336 assert(surf
->samples
== 1);
1338 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1339 const struct isl_extent3d image_align_sa
=
1340 isl_surf_get_image_alignment_sa(surf
);
1344 for (uint32_t l
= 0; l
< level
; ++l
) {
1345 uint32_t W
= isl_minify(W0
, l
);
1346 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1352 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1356 * Calculate the offset, in units of surface samples, to a subimage in the
1359 * @invariant level < surface levels
1360 * @invariant logical_array_layer < logical array length of surface
1361 * @invariant logical_z_offset_px < logical depth of surface at level
1364 get_image_offset_sa(const struct isl_surf
*surf
,
1366 uint32_t logical_array_layer
,
1367 uint32_t logical_z_offset_px
,
1368 uint32_t *x_offset_sa
,
1369 uint32_t *y_offset_sa
)
1371 assert(level
< surf
->levels
);
1372 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1373 assert(logical_z_offset_px
1374 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1376 switch (surf
->dim_layout
) {
1377 case ISL_DIM_LAYOUT_GEN9_1D
:
1378 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1379 x_offset_sa
, y_offset_sa
);
1381 case ISL_DIM_LAYOUT_GEN4_2D
:
1382 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1383 + logical_z_offset_px
,
1384 x_offset_sa
, y_offset_sa
);
1386 case ISL_DIM_LAYOUT_GEN4_3D
:
1387 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1388 x_offset_sa
, y_offset_sa
);
1394 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1396 uint32_t logical_array_layer
,
1397 uint32_t logical_z_offset_px
,
1398 uint32_t *x_offset_el
,
1399 uint32_t *y_offset_el
)
1401 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1403 assert(level
< surf
->levels
);
1404 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1405 assert(logical_z_offset_px
1406 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1408 uint32_t x_offset_sa
, y_offset_sa
;
1409 get_image_offset_sa(surf
, level
,
1410 logical_array_layer
,
1411 logical_z_offset_px
,
1415 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1416 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1420 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1421 enum isl_tiling tiling
,
1424 uint32_t total_x_offset_el
,
1425 uint32_t total_y_offset_el
,
1426 uint32_t *base_address_offset
,
1427 uint32_t *x_offset_el
,
1428 uint32_t *y_offset_el
)
1430 struct isl_tile_info tile_info
;
1431 isl_tiling_get_info(dev
, tiling
, bs
, &tile_info
);
1433 /* This function only really works for power-of-two surfaces. In
1434 * theory, we could make it work for non-power-of-two surfaces by going
1435 * to the left until we find a block that is bs-aligned. The Vulkan
1436 * driver doesn't use non-power-of-two tiled surfaces so we'll leave
1437 * this unimplemented for now.
1439 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
1441 uint32_t small_y_offset_el
= total_y_offset_el
% tile_info
.height
;
1442 uint32_t big_y_offset_el
= total_y_offset_el
- small_y_offset_el
;
1443 uint32_t big_y_offset_B
= big_y_offset_el
* row_pitch
;
1445 uint32_t total_x_offset_B
= total_x_offset_el
* bs
;
1446 uint32_t small_x_offset_B
= total_x_offset_B
% tile_info
.width
;
1447 uint32_t small_x_offset_el
= small_x_offset_B
/ bs
;
1448 uint32_t big_x_offset_B
= (total_x_offset_B
/ tile_info
.width
) * tile_info
.size
;
1450 *base_address_offset
= big_y_offset_B
+ big_x_offset_B
;
1451 *x_offset_el
= small_x_offset_el
;
1452 *y_offset_el
= small_y_offset_el
;
1456 isl_surf_get_depth_format(const struct isl_device
*dev
,
1457 const struct isl_surf
*surf
)
1459 /* Support for separate stencil buffers began in gen5. Support for
1460 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1461 * those that supported separate and interleaved stencil, were gen5 and
1464 * For a list of all available formats, see the Sandybridge PRM >> Volume
1465 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1469 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1471 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1474 assert(ISL_DEV_GEN(dev
) < 7);
1476 switch (surf
->format
) {
1478 unreachable("bad isl depth format");
1479 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1480 assert(ISL_DEV_GEN(dev
) < 7);
1481 return 0; /* D32_FLOAT_S8X24_UINT */
1482 case ISL_FORMAT_R32_FLOAT
:
1483 assert(!has_stencil
);
1484 return 1; /* D32_FLOAT */
1485 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1487 assert(ISL_DEV_GEN(dev
) < 7);
1488 return 2; /* D24_UNORM_S8_UINT */
1490 assert(ISL_DEV_GEN(dev
) >= 5);
1491 return 3; /* D24_UNORM_X8_UINT */
1493 case ISL_FORMAT_R16_UNORM
:
1494 assert(!has_stencil
);
1495 return 5; /* D16_UNORM */