2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
52 isl_device_init(struct isl_device
*dev
,
53 const struct gen_device_info
*info
,
54 bool has_bit6_swizzling
)
57 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
58 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
60 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
61 * device properties at buildtime. Verify that the macros with the device
62 * properties chosen during runtime.
64 ISL_DEV_GEN_SANITIZE(dev
);
65 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
67 /* Did we break hiz or stencil? */
68 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
69 assert(info
->has_hiz_and_separate_stencil
);
70 if (info
->must_use_separate_stencil
)
71 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
74 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
76 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
78 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
80 /* The "Auxiliary Surface Base Address" field starts a bit higher up
81 * because the bottom 12 bits are used for other things. Round down to
82 * the nearest dword before.
84 dev
->ss
.aux_addr_offset
=
85 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
87 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
88 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
89 dev
->ds
.depth_offset
=
90 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
92 if (dev
->use_separate_stencil
) {
93 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
94 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
95 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
97 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
98 dev
->ds
.stencil_offset
=
99 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
100 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
102 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
104 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
105 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
106 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
108 dev
->ds
.stencil_offset
= 0;
109 dev
->ds
.hiz_offset
= 0;
114 * @brief Query the set of multisamples supported by the device.
116 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
119 isl_sample_count_mask_t ATTRIBUTE_CONST
120 isl_device_get_sample_counts(struct isl_device
*dev
)
122 if (ISL_DEV_GEN(dev
) >= 9) {
123 return ISL_SAMPLE_COUNT_1_BIT
|
124 ISL_SAMPLE_COUNT_2_BIT
|
125 ISL_SAMPLE_COUNT_4_BIT
|
126 ISL_SAMPLE_COUNT_8_BIT
|
127 ISL_SAMPLE_COUNT_16_BIT
;
128 } else if (ISL_DEV_GEN(dev
) >= 8) {
129 return ISL_SAMPLE_COUNT_1_BIT
|
130 ISL_SAMPLE_COUNT_2_BIT
|
131 ISL_SAMPLE_COUNT_4_BIT
|
132 ISL_SAMPLE_COUNT_8_BIT
;
133 } else if (ISL_DEV_GEN(dev
) >= 7) {
134 return ISL_SAMPLE_COUNT_1_BIT
|
135 ISL_SAMPLE_COUNT_4_BIT
|
136 ISL_SAMPLE_COUNT_8_BIT
;
137 } else if (ISL_DEV_GEN(dev
) >= 6) {
138 return ISL_SAMPLE_COUNT_1_BIT
|
139 ISL_SAMPLE_COUNT_4_BIT
;
141 return ISL_SAMPLE_COUNT_1_BIT
;
146 * @param[out] info is written only on success
149 isl_tiling_get_info(enum isl_tiling tiling
,
151 struct isl_tile_info
*tile_info
)
153 const uint32_t bs
= format_bpb
/ 8;
154 struct isl_extent2d logical_el
, phys_B
;
156 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
157 /* It is possible to have non-power-of-two formats in a tiled buffer.
158 * The easiest way to handle this is to treat the tile as if it is three
159 * times as wide. This way no pixel will ever cross a tile boundary.
160 * This really only works on legacy X and Y tiling formats.
162 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
163 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
164 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
169 case ISL_TILING_LINEAR
:
171 logical_el
= isl_extent2d(1, 1);
172 phys_B
= isl_extent2d(bs
, 1);
177 logical_el
= isl_extent2d(512 / bs
, 8);
178 phys_B
= isl_extent2d(512, 8);
183 logical_el
= isl_extent2d(128 / bs
, 32);
184 phys_B
= isl_extent2d(128, 32);
189 logical_el
= isl_extent2d(64, 64);
190 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
192 * "If the surface is a stencil buffer (and thus has Tile Mode set
193 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
194 * computed based on width, as the stencil buffer is stored with two
197 * This, together with the fact that stencil buffers are referred to as
198 * being Y-tiled in the PRMs for older hardware implies that the
199 * physical size of a W-tile is actually the same as for a Y-tile.
201 phys_B
= isl_extent2d(128, 32);
205 case ISL_TILING_Ys
: {
206 bool is_Ys
= tiling
== ISL_TILING_Ys
;
209 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
210 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
212 logical_el
= isl_extent2d(width
/ bs
, height
);
213 phys_B
= isl_extent2d(width
, height
);
218 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
219 * 128bpb format. The tiling has the same physical dimensions as
220 * Y-tiling but actually has two HiZ columns per Y-tiled column.
223 logical_el
= isl_extent2d(16, 16);
224 phys_B
= isl_extent2d(128, 32);
228 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
229 * have a block size of 1 or 2 bits per block and each CCS element
230 * corresponds to one cache-line pair in the main surface. From the Sky
231 * Lake PRM Vol. 12 in the section on planes:
233 * "The Color Control Surface (CCS) contains the compression status
234 * of the cache-line pairs. The compression state of the cache-line
235 * pair is specified by 2 bits in the CCS. Each CCS cache-line
236 * represents an area on the main surface of 16x16 sets of 128 byte
237 * Y-tiled cache-line-pairs. CCS is always Y tiled."
239 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
240 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
241 * that yields total tile area of 128x128 cache-line pairs or CCS
242 * elements. On older hardware, each CCS element is 1 bit and the tile
243 * is 128x256 elements.
245 assert(format_bpb
== 1 || format_bpb
== 2);
246 logical_el
= isl_extent2d(128, 256 / format_bpb
);
247 phys_B
= isl_extent2d(128, 32);
251 unreachable("not reached");
254 *tile_info
= (struct isl_tile_info
) {
256 .format_bpb
= format_bpb
,
257 .logical_extent_el
= logical_el
,
258 .phys_extent_B
= phys_B
,
263 * @param[out] tiling is set only on success
266 isl_surf_choose_tiling(const struct isl_device
*dev
,
267 const struct isl_surf_init_info
*restrict info
,
268 enum isl_tiling
*tiling
)
270 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
272 /* HiZ surfaces always use the HiZ tiling */
273 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
274 assert(info
->format
== ISL_FORMAT_HIZ
);
275 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
276 *tiling
= ISL_TILING_HIZ
;
280 /* CCS surfaces always use the CCS tiling */
281 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
282 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
283 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
284 *tiling
= ISL_TILING_CCS
;
288 if (ISL_DEV_GEN(dev
) >= 6) {
289 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
291 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
294 #define CHOOSE(__tiling) \
296 if (tiling_flags & (1u << (__tiling))) { \
297 *tiling = (__tiling); \
302 /* Of the tiling modes remaining, choose the one that offers the best
306 if (info
->dim
== ISL_SURF_DIM_1D
) {
307 /* Prefer linear for 1D surfaces because they do not benefit from
308 * tiling. To the contrary, tiling leads to wasted memory and poor
309 * memory locality due to the swizzling and alignment restrictions
310 * required in tiled surfaces.
312 CHOOSE(ISL_TILING_LINEAR
);
315 CHOOSE(ISL_TILING_Ys
);
316 CHOOSE(ISL_TILING_Yf
);
317 CHOOSE(ISL_TILING_Y0
);
318 CHOOSE(ISL_TILING_X
);
319 CHOOSE(ISL_TILING_W
);
320 CHOOSE(ISL_TILING_LINEAR
);
324 /* No tiling mode accomodates the inputs. */
329 isl_choose_msaa_layout(const struct isl_device
*dev
,
330 const struct isl_surf_init_info
*info
,
331 enum isl_tiling tiling
,
332 enum isl_msaa_layout
*msaa_layout
)
334 if (ISL_DEV_GEN(dev
) >= 8) {
335 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
336 } else if (ISL_DEV_GEN(dev
) >= 7) {
337 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
338 } else if (ISL_DEV_GEN(dev
) >= 6) {
339 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
341 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
346 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
348 assert(isl_is_pow2(samples
));
350 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
353 * If the surface is multisampled and it is a depth or stencil surface
354 * or Multisampled Surface StorageFormat in SURFACE_STATE is
355 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
358 return (struct isl_extent2d
) {
359 .width
= 1 << ((ffs(samples
) - 0) / 2),
360 .height
= 1 << ((ffs(samples
) - 1) / 2),
365 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
366 uint32_t *width
, uint32_t *height
)
368 const struct isl_extent2d px_size_sa
=
369 isl_get_interleaved_msaa_px_size_sa(samples
);
372 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
374 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
377 static enum isl_array_pitch_span
378 isl_choose_array_pitch_span(const struct isl_device
*dev
,
379 const struct isl_surf_init_info
*restrict info
,
380 enum isl_dim_layout dim_layout
,
381 const struct isl_extent4d
*phys_level0_sa
)
383 switch (dim_layout
) {
384 case ISL_DIM_LAYOUT_GEN9_1D
:
385 case ISL_DIM_LAYOUT_GEN4_2D
:
386 if (ISL_DEV_GEN(dev
) >= 8) {
387 /* QPitch becomes programmable in Broadwell. So choose the
388 * most compact QPitch possible in order to conserve memory.
390 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
391 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
393 * - Software must ensure that this field is set to a value
394 * sufficiently large such that the array slices in the surface
395 * do not overlap. Refer to the Memory Data Formats section for
396 * information on how surfaces are stored in memory.
398 * - This field specifies the distance in rows between array
399 * slices. It is used only in the following cases:
401 * - Surface Array is enabled OR
402 * - Number of Mulitsamples is not NUMSAMPLES_1 and
403 * Multisampled Surface Storage Format set to MSFMT_MSS OR
404 * - Surface Type is SURFTYPE_CUBE
406 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
407 } else if (ISL_DEV_GEN(dev
) >= 7) {
408 /* Note that Ivybridge introduces
409 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
410 * driver more control over the QPitch.
413 if (phys_level0_sa
->array_len
== 1) {
414 /* The hardware will never use the QPitch. So choose the most
415 * compact QPitch possible in order to conserve memory.
417 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
420 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
421 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
422 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
423 * Section 6.18.4.7: Surface Arrays (p112):
425 * If Surface Array Spacing is set to ARYSPC_FULL (note that
426 * the depth buffer and stencil buffer have an implied value of
429 return ISL_ARRAY_PITCH_SPAN_FULL
;
432 if (info
->levels
== 1) {
433 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
436 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
439 return ISL_ARRAY_PITCH_SPAN_FULL
;
440 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
441 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
442 isl_surf_usage_is_stencil(info
->usage
)) {
443 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
444 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
446 * The separate stencil buffer does not support mip mapping, thus
447 * the storage for LODs other than LOD 0 is not needed.
449 assert(info
->levels
== 1);
450 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
452 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
453 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
454 isl_surf_usage_is_stencil(info
->usage
)) {
455 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
456 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
458 * The separate stencil buffer does not support mip mapping,
459 * thus the storage for LODs other than LOD 0 is not needed.
461 assert(info
->levels
== 1);
462 assert(phys_level0_sa
->array_len
== 1);
463 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
466 if (phys_level0_sa
->array_len
== 1) {
467 /* The hardware will never use the QPitch. So choose the most
468 * compact QPitch possible in order to conserve memory.
470 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
473 return ISL_ARRAY_PITCH_SPAN_FULL
;
476 case ISL_DIM_LAYOUT_GEN4_3D
:
477 /* The hardware will never use the QPitch. So choose the most
478 * compact QPitch possible in order to conserve memory.
480 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
482 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
483 /* Each array image in the gen6 stencil of HiZ surface is compact in the
484 * sense that every LOD is a compact array of the same size as LOD0.
486 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
489 unreachable("bad isl_dim_layout");
490 return ISL_ARRAY_PITCH_SPAN_FULL
;
494 isl_choose_image_alignment_el(const struct isl_device
*dev
,
495 const struct isl_surf_init_info
*restrict info
,
496 enum isl_tiling tiling
,
497 enum isl_dim_layout dim_layout
,
498 enum isl_msaa_layout msaa_layout
,
499 struct isl_extent3d
*image_align_el
)
501 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
502 if (fmtl
->txc
== ISL_TXC_MCS
) {
503 assert(tiling
== ISL_TILING_Y0
);
506 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
508 * Height, width, and layout of MCS buffer in this case must match with
509 * Render Target height, width, and layout. MCS buffer is tiledY.
511 * To avoid wasting memory, choose the smallest alignment possible:
512 * HALIGN_4 and VALIGN_4.
514 *image_align_el
= isl_extent3d(4, 4, 1);
516 } else if (info
->format
== ISL_FORMAT_HIZ
) {
517 assert(ISL_DEV_GEN(dev
) >= 6);
518 if (ISL_DEV_GEN(dev
) == 6) {
519 /* HiZ surfaces on Sandy Bridge are packed tightly. */
520 *image_align_el
= isl_extent3d(1, 1, 1);
522 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
523 * primary surface which works out to 2x2 HiZ elments.
525 *image_align_el
= isl_extent3d(2, 2, 1);
530 if (ISL_DEV_GEN(dev
) >= 9) {
531 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
532 msaa_layout
, image_align_el
);
533 } else if (ISL_DEV_GEN(dev
) >= 8) {
534 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
535 msaa_layout
, image_align_el
);
536 } else if (ISL_DEV_GEN(dev
) >= 7) {
537 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
538 msaa_layout
, image_align_el
);
539 } else if (ISL_DEV_GEN(dev
) >= 6) {
540 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
541 msaa_layout
, image_align_el
);
543 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
544 msaa_layout
, image_align_el
);
548 static enum isl_dim_layout
549 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
550 enum isl_surf_dim logical_dim
,
551 enum isl_tiling tiling
,
552 isl_surf_usage_flags_t usage
)
554 /* Sandy bridge needs a special layout for HiZ and stencil. */
555 if (ISL_DEV_GEN(dev
) == 6 &&
556 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
557 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
559 if (ISL_DEV_GEN(dev
) >= 9) {
560 switch (logical_dim
) {
561 case ISL_SURF_DIM_1D
:
562 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
564 * One-dimensional surfaces use a tiling mode of linear.
565 * Technically, they are not tiled resources, but the Tiled
566 * Resource Mode field in RENDER_SURFACE_STATE is still used to
567 * indicate the alignment requirements for this linear surface
568 * (See 1D Alignment requirements for how 4K and 64KB Tiled
569 * Resource Modes impact alignment). Alternatively, a 1D surface
570 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
573 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
574 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
576 if (tiling
== ISL_TILING_LINEAR
)
577 return ISL_DIM_LAYOUT_GEN9_1D
;
579 return ISL_DIM_LAYOUT_GEN4_2D
;
580 case ISL_SURF_DIM_2D
:
581 case ISL_SURF_DIM_3D
:
582 return ISL_DIM_LAYOUT_GEN4_2D
;
585 switch (logical_dim
) {
586 case ISL_SURF_DIM_1D
:
587 case ISL_SURF_DIM_2D
:
588 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
590 * The cube face textures are stored in the same way as 3D surfaces
591 * are stored (see section 6.17.5 for details). For cube surfaces,
592 * however, the depth is equal to the number of faces (always 6) and
593 * is not reduced for each MIP.
595 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
596 return ISL_DIM_LAYOUT_GEN4_3D
;
598 return ISL_DIM_LAYOUT_GEN4_2D
;
599 case ISL_SURF_DIM_3D
:
600 return ISL_DIM_LAYOUT_GEN4_3D
;
604 unreachable("bad isl_surf_dim");
605 return ISL_DIM_LAYOUT_GEN4_2D
;
609 * Calculate the physical extent of the surface's first level, in units of
610 * surface samples. The result is aligned to the format's compression block.
613 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
614 const struct isl_surf_init_info
*restrict info
,
615 enum isl_dim_layout dim_layout
,
616 enum isl_tiling tiling
,
617 enum isl_msaa_layout msaa_layout
,
618 struct isl_extent4d
*phys_level0_sa
)
620 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
622 if (isl_format_is_yuv(info
->format
))
623 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
626 case ISL_SURF_DIM_1D
:
627 assert(info
->height
== 1);
628 assert(info
->depth
== 1);
629 assert(info
->samples
== 1);
631 switch (dim_layout
) {
632 case ISL_DIM_LAYOUT_GEN4_3D
:
633 unreachable("bad isl_dim_layout");
635 case ISL_DIM_LAYOUT_GEN9_1D
:
636 case ISL_DIM_LAYOUT_GEN4_2D
:
637 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
638 *phys_level0_sa
= (struct isl_extent4d
) {
639 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
642 .a
= info
->array_len
,
648 case ISL_SURF_DIM_2D
:
649 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
650 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
652 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
653 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
655 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
656 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
658 switch (msaa_layout
) {
659 case ISL_MSAA_LAYOUT_NONE
:
660 assert(info
->depth
== 1);
661 assert(info
->samples
== 1);
663 *phys_level0_sa
= (struct isl_extent4d
) {
664 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
665 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
667 .a
= info
->array_len
,
671 case ISL_MSAA_LAYOUT_ARRAY
:
672 assert(info
->depth
== 1);
673 assert(info
->levels
== 1);
674 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
675 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
677 *phys_level0_sa
= (struct isl_extent4d
) {
681 .a
= info
->array_len
* info
->samples
,
685 case ISL_MSAA_LAYOUT_INTERLEAVED
:
686 assert(info
->depth
== 1);
687 assert(info
->levels
== 1);
688 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
690 *phys_level0_sa
= (struct isl_extent4d
) {
694 .a
= info
->array_len
,
697 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
701 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
702 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
707 case ISL_SURF_DIM_3D
:
708 assert(info
->array_len
== 1);
709 assert(info
->samples
== 1);
712 isl_finishme("%s:%s: compression block with depth > 1",
716 switch (dim_layout
) {
717 case ISL_DIM_LAYOUT_GEN9_1D
:
718 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
719 unreachable("bad isl_dim_layout");
721 case ISL_DIM_LAYOUT_GEN4_2D
:
722 assert(ISL_DEV_GEN(dev
) >= 9);
724 *phys_level0_sa
= (struct isl_extent4d
) {
725 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
726 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
732 case ISL_DIM_LAYOUT_GEN4_3D
:
733 assert(ISL_DEV_GEN(dev
) < 9);
734 *phys_level0_sa
= (struct isl_extent4d
) {
735 .w
= isl_align(info
->width
, fmtl
->bw
),
736 .h
= isl_align(info
->height
, fmtl
->bh
),
747 * Calculate the pitch between physical array slices, in units of rows of
751 isl_calc_array_pitch_el_rows_gen4_2d(
752 const struct isl_device
*dev
,
753 const struct isl_surf_init_info
*restrict info
,
754 const struct isl_tile_info
*tile_info
,
755 const struct isl_extent3d
*image_align_sa
,
756 const struct isl_extent4d
*phys_level0_sa
,
757 enum isl_array_pitch_span array_pitch_span
,
758 const struct isl_extent2d
*phys_slice0_sa
)
760 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
761 uint32_t pitch_sa_rows
= 0;
763 switch (array_pitch_span
) {
764 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
765 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
767 case ISL_ARRAY_PITCH_SPAN_FULL
: {
768 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
769 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
770 * Surfaces >> Surface Arrays.
772 uint32_t H0_sa
= phys_level0_sa
->h
;
773 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
775 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
776 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
779 if (ISL_DEV_GEN(dev
) >= 7) {
780 /* The QPitch equation changed slightly in Ivybridge. */
786 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
788 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
789 (info
->height
% 4 == 1)) {
790 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
791 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
793 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
794 * the value calculated in the equation above , for every
795 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
797 * XXX(chadv): Is the errata natural corollary of the physical
798 * layout of interleaved samples?
803 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
808 assert(pitch_sa_rows
% fmtl
->bh
== 0);
809 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
811 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
813 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
815 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
816 * layout with these alignments in the RT space: Horizontal
817 * Alignment = 128 and Vertical Alignment = 64."
819 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
821 * "For non-multisampled render target's CCS auxiliary surface,
822 * QPitch must be computed with Horizontal Alignment = 128 and
823 * Surface Vertical Alignment = 256. These alignments are only for
824 * CCS buffer and not for associated render target."
826 * The first restriction is already handled by isl_choose_image_alignment_el
827 * but the second restriction, which is an extension of the first, only
828 * applies to qpitch and must be applied here.
830 assert(fmtl
->bh
== 4);
831 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
834 if (ISL_DEV_GEN(dev
) >= 9 &&
835 info
->dim
== ISL_SURF_DIM_3D
&&
836 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
837 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
839 * Tile Mode != Linear: This field must be set to an integer multiple
842 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
845 return pitch_el_rows
;
849 * A variant of isl_calc_phys_slice0_extent_sa() specific to
850 * ISL_DIM_LAYOUT_GEN4_2D.
853 isl_calc_phys_slice0_extent_sa_gen4_2d(
854 const struct isl_device
*dev
,
855 const struct isl_surf_init_info
*restrict info
,
856 enum isl_msaa_layout msaa_layout
,
857 const struct isl_extent3d
*image_align_sa
,
858 const struct isl_extent4d
*phys_level0_sa
,
859 struct isl_extent2d
*phys_slice0_sa
)
861 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
863 assert(phys_level0_sa
->depth
== 1);
865 if (info
->levels
== 1) {
866 /* Do not pad the surface to the image alignment. Instead, pad it only
867 * to the pixel format's block alignment.
869 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
870 * cycles on the below mipmap layout caluclations. Reducing the
871 * alignment here is safe because we later align the row pitch and array
872 * pitch to the tile boundary. It is safe even for
873 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
874 * to accomodate the interleaved samples.
876 * For linear surfaces, reducing the alignment here permits us to later
877 * choose an arbitrary, non-aligned row pitch. If the surface backs
878 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
879 * VkBufferImageCopy::bufferRowLength.
881 *phys_slice0_sa
= (struct isl_extent2d
) {
882 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
883 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
888 uint32_t slice_top_w
= 0;
889 uint32_t slice_bottom_w
= 0;
890 uint32_t slice_left_h
= 0;
891 uint32_t slice_right_h
= 0;
893 uint32_t W0
= phys_level0_sa
->w
;
894 uint32_t H0
= phys_level0_sa
->h
;
896 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
897 uint32_t W
= isl_minify(W0
, l
);
898 uint32_t H
= isl_minify(H0
, l
);
900 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
901 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
918 *phys_slice0_sa
= (struct isl_extent2d
) {
919 .w
= MAX(slice_top_w
, slice_bottom_w
),
920 .h
= MAX(slice_left_h
, slice_right_h
),
925 isl_calc_phys_total_extent_el_gen4_2d(
926 const struct isl_device
*dev
,
927 const struct isl_surf_init_info
*restrict info
,
928 const struct isl_tile_info
*tile_info
,
929 enum isl_msaa_layout msaa_layout
,
930 const struct isl_extent3d
*image_align_sa
,
931 const struct isl_extent4d
*phys_level0_sa
,
932 enum isl_array_pitch_span array_pitch_span
,
933 uint32_t *array_pitch_el_rows
,
934 struct isl_extent2d
*total_extent_el
)
936 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
938 struct isl_extent2d phys_slice0_sa
;
939 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
940 image_align_sa
, phys_level0_sa
,
942 *array_pitch_el_rows
=
943 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
944 image_align_sa
, phys_level0_sa
,
947 *total_extent_el
= (struct isl_extent2d
) {
948 .w
= isl_assert_div(phys_slice0_sa
.w
, fmtl
->bw
),
949 .h
= *array_pitch_el_rows
* phys_level0_sa
->array_len
,
954 * A variant of isl_calc_phys_slice0_extent_sa() specific to
955 * ISL_DIM_LAYOUT_GEN4_3D.
958 isl_calc_phys_total_extent_el_gen4_3d(
959 const struct isl_device
*dev
,
960 const struct isl_surf_init_info
*restrict info
,
961 const struct isl_extent3d
*image_align_sa
,
962 const struct isl_extent4d
*phys_level0_sa
,
963 uint32_t *array_pitch_el_rows
,
964 struct isl_extent2d
*phys_total_el
)
966 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
968 assert(info
->samples
== 1);
970 if (info
->dim
!= ISL_SURF_DIM_3D
) {
971 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
973 * The cube face textures are stored in the same way as 3D surfaces
974 * are stored (see section 6.17.5 for details). For cube surfaces,
975 * however, the depth is equal to the number of faces (always 6) and
976 * is not reduced for each MIP.
978 assert(ISL_DEV_GEN(dev
) == 4);
979 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
980 assert(phys_level0_sa
->array_len
== 6);
982 assert(phys_level0_sa
->array_len
== 1);
985 uint32_t total_w
= 0;
986 uint32_t total_h
= 0;
988 uint32_t W0
= phys_level0_sa
->w
;
989 uint32_t H0
= phys_level0_sa
->h
;
990 uint32_t D0
= phys_level0_sa
->d
;
991 uint32_t A0
= phys_level0_sa
->a
;
993 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
994 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
995 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
996 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
998 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
999 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1001 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1002 total_h
+= level_h
* max_layers_vert
;
1005 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1006 * different number of horizontal and vertical layers. We have to set it
1007 * to something, so at least make it true for LOD0.
1009 *array_pitch_el_rows
=
1010 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1011 *phys_total_el
= (struct isl_extent2d
) {
1012 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1013 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1018 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1019 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1022 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1023 const struct isl_device
*dev
,
1024 const struct isl_surf_init_info
*restrict info
,
1025 const struct isl_tile_info
*tile_info
,
1026 const struct isl_extent3d
*image_align_sa
,
1027 const struct isl_extent4d
*phys_level0_sa
,
1028 uint32_t *array_pitch_el_rows
,
1029 struct isl_extent2d
*phys_total_el
)
1031 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1033 const struct isl_extent2d tile_extent_sa
= {
1034 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1035 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1037 /* Tile size is a multiple of image alignment */
1038 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1039 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1041 const uint32_t W0
= phys_level0_sa
->w
;
1042 const uint32_t H0
= phys_level0_sa
->h
;
1044 /* Each image has the same height as LOD0 because the hardware thinks
1045 * everything is LOD0
1047 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1049 uint32_t total_top_w
= 0;
1050 uint32_t total_bottom_w
= 0;
1051 uint32_t total_h
= 0;
1053 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1054 const uint32_t W
= isl_minify(W0
, l
);
1056 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1057 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1062 } else if (l
== 1) {
1066 total_bottom_w
+= w
;
1070 *array_pitch_el_rows
=
1071 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1072 *phys_total_el
= (struct isl_extent2d
) {
1073 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1074 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1079 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1080 * ISL_DIM_LAYOUT_GEN9_1D.
1083 isl_calc_phys_total_extent_el_gen9_1d(
1084 const struct isl_device
*dev
,
1085 const struct isl_surf_init_info
*restrict info
,
1086 const struct isl_extent3d
*image_align_sa
,
1087 const struct isl_extent4d
*phys_level0_sa
,
1088 uint32_t *array_pitch_el_rows
,
1089 struct isl_extent2d
*phys_total_el
)
1091 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1093 assert(phys_level0_sa
->height
== 1);
1094 assert(phys_level0_sa
->depth
== 1);
1095 assert(info
->samples
== 1);
1096 assert(image_align_sa
->w
>= fmtl
->bw
);
1098 uint32_t slice_w
= 0;
1099 const uint32_t W0
= phys_level0_sa
->w
;
1101 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1102 uint32_t W
= isl_minify(W0
, l
);
1103 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1108 *array_pitch_el_rows
= 1;
1109 *phys_total_el
= (struct isl_extent2d
) {
1110 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1111 .h
= phys_level0_sa
->array_len
,
1116 * Calculate the two-dimensional total physical extent of the surface, in
1117 * units of surface elements.
1120 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1121 const struct isl_surf_init_info
*restrict info
,
1122 const struct isl_tile_info
*tile_info
,
1123 enum isl_dim_layout dim_layout
,
1124 enum isl_msaa_layout msaa_layout
,
1125 const struct isl_extent3d
*image_align_sa
,
1126 const struct isl_extent4d
*phys_level0_sa
,
1127 enum isl_array_pitch_span array_pitch_span
,
1128 uint32_t *array_pitch_el_rows
,
1129 struct isl_extent2d
*total_extent_el
)
1131 switch (dim_layout
) {
1132 case ISL_DIM_LAYOUT_GEN9_1D
:
1133 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1134 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1135 image_align_sa
, phys_level0_sa
,
1136 array_pitch_el_rows
,
1139 case ISL_DIM_LAYOUT_GEN4_2D
:
1140 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1141 image_align_sa
, phys_level0_sa
,
1143 array_pitch_el_rows
,
1146 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1147 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1148 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1151 array_pitch_el_rows
,
1154 case ISL_DIM_LAYOUT_GEN4_3D
:
1155 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1156 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1157 image_align_sa
, phys_level0_sa
,
1158 array_pitch_el_rows
,
1165 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1166 const struct isl_tile_info
*tile_info
)
1168 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1169 return tile_info
->phys_extent_B
.width
;
1171 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1172 * RENDER_SURFACE_STATE Surface Pitch (p349):
1174 * - For linear render target surfaces and surfaces accessed with the
1175 * typed data port messages, the pitch must be a multiple of the
1176 * element size for non-YUV surface formats. Pitch must be
1177 * a multiple of 2 * element size for YUV surface formats.
1179 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1180 * ignore because isl doesn't do buffers.]
1182 * - For other linear surfaces, the pitch can be any multiple of
1185 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1186 const uint32_t bs
= fmtl
->bpb
/ 8;
1188 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1189 if (isl_format_is_yuv(surf_info
->format
)) {
1200 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1201 const struct isl_surf_init_info
*info
,
1202 const struct isl_extent2d
*phys_total_el
,
1205 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1206 const uint32_t bs
= fmtl
->bpb
/ 8;
1208 return isl_align_npot(bs
* phys_total_el
->w
, alignment
);
1212 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1213 const struct isl_surf_init_info
*surf_info
,
1214 const struct isl_tile_info
*tile_info
,
1215 const struct isl_extent2d
*phys_total_el
,
1218 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1220 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1222 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1223 const uint32_t total_w_tl
=
1224 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1225 tile_info
->logical_extent_el
.width
);
1227 assert(alignment
== tile_info
->phys_extent_B
.width
);
1228 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1232 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1233 const struct isl_surf_init_info
*surf_info
,
1234 const struct isl_tile_info
*tile_info
,
1235 const struct isl_extent2d
*phys_total_el
,
1238 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1239 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1242 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1243 phys_total_el
, alignment
);
1248 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1249 * size is `bits` bits?
1251 * Hardware pitch fields are offset by 1. For example, if the size of
1252 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1253 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1254 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1257 pitch_in_range(uint32_t n
, uint32_t bits
)
1260 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1264 isl_calc_row_pitch(const struct isl_device
*dev
,
1265 const struct isl_surf_init_info
*surf_info
,
1266 const struct isl_tile_info
*tile_info
,
1267 enum isl_dim_layout dim_layout
,
1268 const struct isl_extent2d
*phys_total_el
,
1269 uint32_t *out_row_pitch
)
1271 const uint32_t alignment
=
1272 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1274 const uint32_t min_row_pitch
=
1275 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1278 uint32_t row_pitch
= min_row_pitch
;
1280 if (surf_info
->row_pitch
!= 0) {
1281 row_pitch
= surf_info
->row_pitch
;
1283 if (row_pitch
< min_row_pitch
)
1286 if (row_pitch
% alignment
!= 0)
1290 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1295 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1296 /* SurfacePitch is ignored for this layout. */
1300 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1301 ISL_SURF_USAGE_TEXTURE_BIT
|
1302 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1303 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1306 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1307 ISL_SURF_USAGE_MCS_BIT
)) &&
1308 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1311 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1312 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1315 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1316 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1319 if (surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
1320 isl_finishme("validate row pitch of stencil surfaces");
1323 *out_row_pitch
= row_pitch
;
1328 * Calculate and apply any padding required for the surface.
1330 * @param[inout] total_h_el is updated with the new height
1331 * @param[out] pad_bytes is overwritten with additional padding requirements.
1334 isl_apply_surface_padding(const struct isl_device
*dev
,
1335 const struct isl_surf_init_info
*restrict info
,
1336 const struct isl_tile_info
*tile_info
,
1337 uint32_t *total_h_el
,
1338 uint32_t *pad_bytes
)
1340 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1344 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1345 * Formats >> Surface Padding Requirements >> Render Target and Media
1348 * The data port accesses data (pixels) outside of the surface if they
1349 * are contained in the same cache request as pixels that are within the
1350 * surface. These pixels will not be returned by the requesting message,
1351 * however if these pixels lie outside of defined pages in the GTT,
1352 * a GTT error will result when the cache request is processed. In
1353 * order to avoid these GTT errors, “padding” at the bottom of the
1354 * surface is sometimes necessary.
1356 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1357 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1359 * ... Lots of padding requirements, all listed separately below.
1362 /* We can safely ignore the first padding requirement, quoted below,
1363 * because isl doesn't do buffers.
1365 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1366 * requirements are different. A buffer must be padded to the next
1367 * multiple of 256 array elements, with an additional 16 bytes added
1368 * beyond that to account for the L1 cache line.
1372 * - For compressed textures [...], padding at the bottom of the surface
1373 * is to an even compressed row.
1375 if (isl_format_is_compressed(info
->format
))
1376 *total_h_el
= isl_align(*total_h_el
, 2);
1379 * - For cube surfaces, an additional two rows of padding are required
1380 * at the bottom of the surface.
1382 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1386 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1387 * additional padding is required. These surfaces require an extra row
1388 * plus 16 bytes of padding at the bottom in addition to the general
1389 * padding requirements.
1391 if (isl_format_is_yuv(info
->format
) &&
1392 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1398 * - For linear surfaces, additional padding of 64 bytes is required at
1399 * the bottom of the surface. This is in addition to the padding
1402 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1405 /* The below text weakens, not strengthens, the padding requirements for
1406 * linear surfaces. Therefore we can safely ignore it.
1408 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1409 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1410 * padding requirement is to the next aligned 64-byte boundary beyond
1411 * the end of the surface. The rest of the padding requirements
1412 * documented above do not apply to these surfaces.
1416 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1417 * height % 4 != 0, the surface must be padded with
1418 * 4-(height % 4)*Surface Pitch # of bytes.
1420 if (ISL_DEV_GEN(dev
) >= 9 &&
1421 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1422 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1423 *total_h_el
= isl_align(*total_h_el
, 4);
1427 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1428 * to 4 times the Surface Pitch # of bytes
1430 if (ISL_DEV_GEN(dev
) >= 9 &&
1431 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1432 info
->dim
== ISL_SURF_DIM_1D
) {
1438 isl_surf_init_s(const struct isl_device
*dev
,
1439 struct isl_surf
*surf
,
1440 const struct isl_surf_init_info
*restrict info
)
1442 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1444 const struct isl_extent4d logical_level0_px
= {
1448 .a
= info
->array_len
,
1451 enum isl_tiling tiling
;
1452 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1455 struct isl_tile_info tile_info
;
1456 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1458 const enum isl_dim_layout dim_layout
=
1459 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1461 enum isl_msaa_layout msaa_layout
;
1462 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1465 struct isl_extent3d image_align_el
;
1466 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1469 struct isl_extent3d image_align_sa
=
1470 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1472 struct isl_extent4d phys_level0_sa
;
1473 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1475 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1476 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1478 enum isl_array_pitch_span array_pitch_span
=
1479 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1481 uint32_t array_pitch_el_rows
;
1482 struct isl_extent2d phys_total_el
;
1483 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1484 dim_layout
, msaa_layout
,
1485 &image_align_sa
, &phys_level0_sa
,
1486 array_pitch_span
, &array_pitch_el_rows
,
1489 uint32_t padded_h_el
= phys_total_el
.h
;
1491 isl_apply_surface_padding(dev
, info
, &tile_info
, &padded_h_el
, &pad_bytes
);
1494 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1495 &phys_total_el
, &row_pitch
))
1498 uint32_t base_alignment
;
1500 if (tiling
== ISL_TILING_LINEAR
) {
1501 size
= (uint64_t) row_pitch
* padded_h_el
+ pad_bytes
;
1503 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1505 * "The Base Address for linear render target surfaces and surfaces
1506 * accessed with the typed surface read/write data port messages must
1507 * be element-size aligned, for non-YUV surface formats, or a
1508 * multiple of 2 element-sizes for YUV surface formats. Other linear
1509 * surfaces have no alignment requirements (byte alignment is
1512 base_alignment
= MAX(1, info
->min_alignment
);
1513 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1514 if (isl_format_is_yuv(info
->format
)) {
1515 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1517 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1520 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1522 padded_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1523 const uint32_t total_h_tl
=
1524 isl_align_div(padded_h_el
, tile_info
.logical_extent_el
.height
);
1526 size
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1528 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1529 tile_info
.phys_extent_B
.height
;
1530 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1531 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1534 if (ISL_DEV_GEN(dev
) < 9) {
1535 /* From the Broadwell PRM Vol 5, Surface Layout:
1537 * "In addition to restrictions on maximum height, width, and depth,
1538 * surfaces are also restricted to a maximum size in bytes. This
1539 * maximum is 2 GB for all products and all surface types."
1541 * This comment is applicable to all Pre-gen9 platforms.
1543 if (size
> (uint64_t) 1 << 31)
1546 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1547 * "In addition to restrictions on maximum height, width, and depth,
1548 * surfaces are also restricted to a maximum size of 2^38 bytes.
1549 * All pixels within the surface must be contained within 2^38 bytes
1550 * of the base address."
1552 if (size
> (uint64_t) 1 << 38)
1556 *surf
= (struct isl_surf
) {
1558 .dim_layout
= dim_layout
,
1559 .msaa_layout
= msaa_layout
,
1561 .format
= info
->format
,
1563 .levels
= info
->levels
,
1564 .samples
= info
->samples
,
1566 .image_alignment_el
= image_align_el
,
1567 .logical_level0_px
= logical_level0_px
,
1568 .phys_level0_sa
= phys_level0_sa
,
1571 .alignment
= base_alignment
,
1572 .row_pitch
= row_pitch
,
1573 .array_pitch_el_rows
= array_pitch_el_rows
,
1574 .array_pitch_span
= array_pitch_span
,
1576 .usage
= info
->usage
,
1583 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1584 struct isl_tile_info
*tile_info
)
1586 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1587 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1591 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1592 const struct isl_surf
*surf
,
1593 struct isl_surf
*hiz_surf
)
1595 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1597 /* Multisampled depth is always interleaved */
1598 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1599 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1601 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1603 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1604 * Target View Extent, and Depth Coordinate Offset X/Y of the
1605 * hierarchical depth buffer are inherited from the depth buffer. The
1606 * height and width of the hierarchical depth buffer that must be
1607 * allocated are computed by the following formulas, where HZ is the
1608 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1609 * Z_Width, and Z_Depth values given in these formulas are those present
1610 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1612 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1613 * being applied to the table below if Number of Multisamples is set to
1614 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1615 * Z_Width must be multiplied by 4 before being applied to the table
1616 * below if Number of Multisamples is set to NUMSAMPLES_8."
1618 * In the Sky Lake PRM, the second paragraph is replaced with this:
1620 * "The Z_Height and Z_Width values must equal those present in
1621 * 3DSTATE_DEPTH_BUFFER incremented by one."
1623 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1624 * block corresponds to a region of 8x4 samples in the primary depth
1625 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1626 * a region of 8x4 pixels in the primary depth surface regardless of the
1627 * number of samples. The dimensions of a HiZ block in both pixels and
1628 * samples are given in the table below:
1630 * | SNB - BDW | SKL+
1631 * ------+-----------+-------------
1632 * 1x | 8 x 4 sa | 8 x 4 sa
1633 * MSAA | 8 x 4 px | 8 x 4 px
1634 * ------+-----------+-------------
1635 * 2x | 8 x 4 sa | 16 x 4 sa
1636 * MSAA | 4 x 4 px | 8 x 4 px
1637 * ------+-----------+-------------
1638 * 4x | 8 x 4 sa | 16 x 8 sa
1639 * MSAA | 4 x 2 px | 8 x 4 px
1640 * ------+-----------+-------------
1641 * 8x | 8 x 4 sa | 32 x 8 sa
1642 * MSAA | 2 x 2 px | 8 x 4 px
1643 * ------+-----------+-------------
1644 * 16x | N/A | 32 x 16 sa
1645 * MSAA | N/A | 8 x 4 px
1646 * ------+-----------+-------------
1648 * There are a number of different ways that this discrepency could be
1649 * handled. The way we have chosen is to simply make MSAA HiZ have the
1650 * same number of samples as the parent surface pre-Sky Lake and always be
1651 * single-sampled on Sky Lake and above. Since the block sizes of
1652 * compressed formats are given in samples, this neatly handles everything
1653 * without the need for additional HiZ formats with different block sizes
1656 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1658 return isl_surf_init(dev
, hiz_surf
,
1660 .format
= ISL_FORMAT_HIZ
,
1661 .width
= surf
->logical_level0_px
.width
,
1662 .height
= surf
->logical_level0_px
.height
,
1663 .depth
= surf
->logical_level0_px
.depth
,
1664 .levels
= surf
->levels
,
1665 .array_len
= surf
->logical_level0_px
.array_len
,
1667 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1668 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1672 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1673 const struct isl_surf
*surf
,
1674 struct isl_surf
*mcs_surf
)
1676 /* It must be multisampled with an array layout */
1677 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1679 /* The following are true of all multisampled surfaces */
1680 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1681 assert(surf
->levels
== 1);
1682 assert(surf
->logical_level0_px
.depth
== 1);
1684 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1685 * bits which means the maximum pitch of a compression surface is 512
1686 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1687 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1688 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1689 * and 8x, we have enough room for the full 16k supported by the hardware.
1691 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1694 enum isl_format mcs_format
;
1695 switch (surf
->samples
) {
1696 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1697 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1698 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1699 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1701 unreachable("Invalid sample count");
1704 return isl_surf_init(dev
, mcs_surf
,
1705 .dim
= ISL_SURF_DIM_2D
,
1706 .format
= mcs_format
,
1707 .width
= surf
->logical_level0_px
.width
,
1708 .height
= surf
->logical_level0_px
.height
,
1711 .array_len
= surf
->logical_level0_px
.array_len
,
1712 .samples
= 1, /* MCS surfaces are really single-sampled */
1713 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1714 .tiling_flags
= ISL_TILING_Y0_BIT
);
1718 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1719 const struct isl_surf
*surf
,
1720 struct isl_surf
*ccs_surf
,
1723 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1724 assert(ISL_DEV_GEN(dev
) >= 7);
1726 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1729 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1732 if (isl_format_is_compressed(surf
->format
))
1735 /* TODO: More conditions where it can fail. */
1737 enum isl_format ccs_format
;
1738 if (ISL_DEV_GEN(dev
) >= 9) {
1739 if (!isl_tiling_is_any_y(surf
->tiling
))
1742 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1743 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1744 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1745 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1749 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1750 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1751 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1752 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1753 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1757 } else if (surf
->tiling
== ISL_TILING_X
) {
1758 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1759 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1760 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1761 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1769 /* Multi-LOD and multi-layer CCS isn't supported on gen7. */
1770 const uint8_t levels
= ISL_DEV_GEN(dev
) <= 7 ? 1 : surf
->levels
;
1771 const uint32_t array_len
= ISL_DEV_GEN(dev
) <= 7 ?
1772 1 : surf
->logical_level0_px
.array_len
;
1774 return isl_surf_init(dev
, ccs_surf
,
1776 .format
= ccs_format
,
1777 .width
= surf
->logical_level0_px
.width
,
1778 .height
= surf
->logical_level0_px
.height
,
1779 .depth
= surf
->logical_level0_px
.depth
,
1781 .array_len
= array_len
,
1783 .row_pitch
= row_pitch
,
1784 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1785 .tiling_flags
= ISL_TILING_CCS_BIT
);
1789 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1790 const struct isl_surf_fill_state_info
*restrict info
)
1793 isl_surf_usage_flags_t _base_usage
=
1794 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1795 ISL_SURF_USAGE_TEXTURE_BIT
|
1796 ISL_SURF_USAGE_STORAGE_BIT
);
1797 /* They may only specify one of the above bits at a time */
1798 assert(__builtin_popcount(_base_usage
) == 1);
1799 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1800 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1803 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1804 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1805 info
->surf
->logical_level0_px
.depth
);
1807 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1808 info
->surf
->logical_level0_px
.array_len
);
1811 switch (ISL_DEV_GEN(dev
)) {
1813 if (ISL_DEV_IS_G4X(dev
)) {
1814 /* G45 surface state is the same as gen5 */
1815 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1817 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1821 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1824 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1827 if (ISL_DEV_IS_HASWELL(dev
)) {
1828 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1830 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1834 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1837 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1840 isl_gen10_surf_fill_state_s(dev
, state
, info
);
1843 assert(!"Cannot fill surface state for this gen");
1848 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1849 const struct isl_buffer_fill_state_info
*restrict info
)
1851 switch (ISL_DEV_GEN(dev
)) {
1854 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1855 isl_gen5_buffer_fill_state_s(state
, info
);
1858 isl_gen6_buffer_fill_state_s(state
, info
);
1861 if (ISL_DEV_IS_HASWELL(dev
)) {
1862 isl_gen75_buffer_fill_state_s(state
, info
);
1864 isl_gen7_buffer_fill_state_s(state
, info
);
1868 isl_gen8_buffer_fill_state_s(state
, info
);
1871 isl_gen9_buffer_fill_state_s(state
, info
);
1874 isl_gen10_buffer_fill_state_s(state
, info
);
1877 assert(!"Cannot fill surface state for this gen");
1882 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1883 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1885 if (info
->depth_surf
&& info
->stencil_surf
) {
1886 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1887 assert(info
->depth_surf
== info
->stencil_surf
);
1888 assert(info
->depth_address
== info
->stencil_address
);
1890 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1893 if (info
->depth_surf
) {
1894 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1895 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1896 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1897 info
->depth_surf
->logical_level0_px
.depth
);
1899 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1900 info
->depth_surf
->logical_level0_px
.array_len
);
1904 if (info
->stencil_surf
) {
1905 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1906 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1907 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1908 info
->stencil_surf
->logical_level0_px
.depth
);
1910 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1911 info
->stencil_surf
->logical_level0_px
.array_len
);
1915 switch (ISL_DEV_GEN(dev
)) {
1917 if (ISL_DEV_IS_G4X(dev
)) {
1918 /* G45 surface state is the same as gen5 */
1919 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1921 isl_gen4_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1925 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1928 isl_gen6_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1931 if (ISL_DEV_IS_HASWELL(dev
)) {
1932 isl_gen75_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1934 isl_gen7_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1938 isl_gen8_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1941 isl_gen9_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1944 isl_gen10_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1947 assert(!"Cannot fill surface state for this gen");
1952 * A variant of isl_surf_get_image_offset_sa() specific to
1953 * ISL_DIM_LAYOUT_GEN4_2D.
1956 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1957 uint32_t level
, uint32_t logical_array_layer
,
1958 uint32_t *x_offset_sa
,
1959 uint32_t *y_offset_sa
)
1961 assert(level
< surf
->levels
);
1962 if (surf
->dim
== ISL_SURF_DIM_3D
)
1963 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1965 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1967 const struct isl_extent3d image_align_sa
=
1968 isl_surf_get_image_alignment_sa(surf
);
1970 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1971 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1973 const uint32_t phys_layer
= logical_array_layer
*
1974 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1977 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1979 for (uint32_t l
= 0; l
< level
; ++l
) {
1981 uint32_t W
= isl_minify(W0
, l
);
1982 x
+= isl_align_npot(W
, image_align_sa
.w
);
1984 uint32_t H
= isl_minify(H0
, l
);
1985 y
+= isl_align_npot(H
, image_align_sa
.h
);
1994 * A variant of isl_surf_get_image_offset_sa() specific to
1995 * ISL_DIM_LAYOUT_GEN4_3D.
1998 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1999 uint32_t level
, uint32_t logical_z_offset_px
,
2000 uint32_t *x_offset_sa
,
2001 uint32_t *y_offset_sa
)
2003 assert(level
< surf
->levels
);
2004 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2005 assert(surf
->phys_level0_sa
.array_len
== 1);
2006 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2008 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2009 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2010 assert(surf
->phys_level0_sa
.array_len
== 6);
2011 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2014 const struct isl_extent3d image_align_sa
=
2015 isl_surf_get_image_alignment_sa(surf
);
2017 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2018 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2019 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2020 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2025 for (uint32_t l
= 0; l
< level
; ++l
) {
2026 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2027 const uint32_t level_d
=
2028 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2030 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2032 y
+= level_h
* max_layers_vert
;
2035 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2036 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2037 const uint32_t level_d
=
2038 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2041 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2043 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2044 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2051 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2053 uint32_t logical_array_layer
,
2054 uint32_t *x_offset_sa
,
2055 uint32_t *y_offset_sa
)
2057 assert(level
< surf
->levels
);
2058 assert(surf
->logical_level0_px
.depth
== 1);
2059 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2061 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2063 const struct isl_extent3d image_align_sa
=
2064 isl_surf_get_image_alignment_sa(surf
);
2066 struct isl_tile_info tile_info
;
2067 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2068 const struct isl_extent2d tile_extent_sa
= {
2069 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2070 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2072 /* Tile size is a multiple of image alignment */
2073 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2074 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2076 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2077 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2079 /* Each image has the same height as LOD0 because the hardware thinks
2080 * everything is LOD0
2082 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2084 /* Quick sanity check for consistency */
2085 if (surf
->phys_level0_sa
.array_len
> 1)
2086 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2088 uint32_t x
= 0, y
= 0;
2089 for (uint32_t l
= 0; l
< level
; ++l
) {
2090 const uint32_t W
= isl_minify(W0
, l
);
2092 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2093 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2103 y
+= H
* logical_array_layer
;
2110 * A variant of isl_surf_get_image_offset_sa() specific to
2111 * ISL_DIM_LAYOUT_GEN9_1D.
2114 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2115 uint32_t level
, uint32_t layer
,
2116 uint32_t *x_offset_sa
,
2117 uint32_t *y_offset_sa
)
2119 assert(level
< surf
->levels
);
2120 assert(layer
< surf
->phys_level0_sa
.array_len
);
2121 assert(surf
->phys_level0_sa
.height
== 1);
2122 assert(surf
->phys_level0_sa
.depth
== 1);
2123 assert(surf
->samples
== 1);
2125 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2126 const struct isl_extent3d image_align_sa
=
2127 isl_surf_get_image_alignment_sa(surf
);
2131 for (uint32_t l
= 0; l
< level
; ++l
) {
2132 uint32_t W
= isl_minify(W0
, l
);
2133 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2139 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2143 * Calculate the offset, in units of surface samples, to a subimage in the
2146 * @invariant level < surface levels
2147 * @invariant logical_array_layer < logical array length of surface
2148 * @invariant logical_z_offset_px < logical depth of surface at level
2151 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2153 uint32_t logical_array_layer
,
2154 uint32_t logical_z_offset_px
,
2155 uint32_t *x_offset_sa
,
2156 uint32_t *y_offset_sa
)
2158 assert(level
< surf
->levels
);
2159 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2160 assert(logical_z_offset_px
2161 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2163 switch (surf
->dim_layout
) {
2164 case ISL_DIM_LAYOUT_GEN9_1D
:
2165 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2166 x_offset_sa
, y_offset_sa
);
2168 case ISL_DIM_LAYOUT_GEN4_2D
:
2169 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2170 + logical_z_offset_px
,
2171 x_offset_sa
, y_offset_sa
);
2173 case ISL_DIM_LAYOUT_GEN4_3D
:
2174 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2175 logical_z_offset_px
,
2176 x_offset_sa
, y_offset_sa
);
2178 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2179 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2180 logical_z_offset_px
,
2181 x_offset_sa
, y_offset_sa
);
2185 unreachable("not reached");
2190 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2192 uint32_t logical_array_layer
,
2193 uint32_t logical_z_offset_px
,
2194 uint32_t *x_offset_el
,
2195 uint32_t *y_offset_el
)
2197 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2199 assert(level
< surf
->levels
);
2200 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2201 assert(logical_z_offset_px
2202 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2204 uint32_t x_offset_sa
, y_offset_sa
;
2205 isl_surf_get_image_offset_sa(surf
, level
,
2206 logical_array_layer
,
2207 logical_z_offset_px
,
2211 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2212 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2216 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2218 uint32_t logical_array_layer
,
2219 uint32_t logical_z_offset_px
,
2221 uint32_t *x_offset_sa
,
2222 uint32_t *y_offset_sa
)
2224 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2226 uint32_t total_x_offset_el
, total_y_offset_el
;
2227 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2228 logical_z_offset_px
,
2230 &total_y_offset_el
);
2232 uint32_t x_offset_el
, y_offset_el
;
2233 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2242 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2244 assert(x_offset_el
== 0);
2248 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2250 assert(y_offset_el
== 0);
2255 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2258 uint32_t total_x_offset_el
,
2259 uint32_t total_y_offset_el
,
2260 uint32_t *base_address_offset
,
2261 uint32_t *x_offset_el
,
2262 uint32_t *y_offset_el
)
2264 if (tiling
== ISL_TILING_LINEAR
) {
2265 assert(bpb
% 8 == 0);
2266 *base_address_offset
= total_y_offset_el
* row_pitch
+
2267 total_x_offset_el
* (bpb
/ 8);
2273 struct isl_tile_info tile_info
;
2274 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2276 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
2278 /* For non-power-of-two formats, we need the address to be both tile and
2279 * element-aligned. The easiest way to achieve this is to work with a tile
2280 * that is three times as wide as the regular tile.
2282 * The tile info returned by get_tile_info has a logical size that is an
2283 * integer number of tile_info.format_bpb size elements. To scale the
2284 * tile, we scale up the physical width and then treat the logical tile
2285 * size as if it has bpb size elements.
2287 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2288 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2290 /* Compute the offset into the tile */
2291 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2292 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2294 /* Compute the offset of the tile in units of whole tiles */
2295 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2296 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2298 *base_address_offset
=
2299 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
2300 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2304 isl_surf_get_depth_format(const struct isl_device
*dev
,
2305 const struct isl_surf
*surf
)
2307 /* Support for separate stencil buffers began in gen5. Support for
2308 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2309 * those that supported separate and interleaved stencil, were gen5 and
2312 * For a list of all available formats, see the Sandybridge PRM >> Volume
2313 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2317 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2319 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2322 assert(ISL_DEV_GEN(dev
) < 7);
2324 switch (surf
->format
) {
2326 unreachable("bad isl depth format");
2327 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2328 assert(ISL_DEV_GEN(dev
) < 7);
2329 return 0; /* D32_FLOAT_S8X24_UINT */
2330 case ISL_FORMAT_R32_FLOAT
:
2331 assert(!has_stencil
);
2332 return 1; /* D32_FLOAT */
2333 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2335 assert(ISL_DEV_GEN(dev
) < 7);
2336 return 2; /* D24_UNORM_S8_UINT */
2338 assert(ISL_DEV_GEN(dev
) >= 5);
2339 return 3; /* D24_UNORM_X8_UINT */
2341 case ISL_FORMAT_R16_UNORM
:
2342 assert(!has_stencil
);
2343 return 5; /* D16_UNORM */