2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
36 #include "isl_gen12.h"
40 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
41 uint32_t yt1
, uint32_t yt2
,
42 char *dst
, const char *src
,
43 uint32_t dst_pitch
, int32_t src_pitch
,
45 enum isl_tiling tiling
,
46 isl_memcpy_type copy_type
)
49 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
50 _isl_memcpy_linear_to_tiled_sse41(
51 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
57 _isl_memcpy_linear_to_tiled(
58 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
63 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
64 uint32_t yt1
, uint32_t yt2
,
65 char *dst
, const char *src
,
66 int32_t dst_pitch
, uint32_t src_pitch
,
68 enum isl_tiling tiling
,
69 isl_memcpy_type copy_type
)
72 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
73 _isl_memcpy_tiled_to_linear_sse41(
74 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
80 _isl_memcpy_tiled_to_linear(
81 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
85 void PRINTFLIKE(3, 4) UNUSED
86 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
92 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
95 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
99 isl_device_setup_mocs(struct isl_device
*dev
)
101 if (dev
->info
->gen
>= 12) {
102 /* TODO: Set PTE to MOCS 61 when the kernel is ready */
103 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
104 dev
->mocs
.external
= 3 << 1;
105 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
106 dev
->mocs
.internal
= 2 << 1;
107 } else if (dev
->info
->gen
>= 9) {
108 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
109 dev
->mocs
.external
= 1 << 1;
110 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
111 dev
->mocs
.internal
= 2 << 1;
112 } else if (dev
->info
->gen
>= 8) {
113 /* MEMORY_OBJECT_CONTROL_STATE:
114 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
115 * .TargetCache = L3DefertoPATforLLCeLLCselection,
118 dev
->mocs
.external
= 0x18;
119 /* MEMORY_OBJECT_CONTROL_STATE:
120 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
121 * .TargetCache = L3DefertoPATforLLCeLLCselection,
124 dev
->mocs
.internal
= 0x78;
125 } else if (dev
->info
->gen
>= 7) {
126 if (dev
->info
->is_haswell
) {
127 /* MEMORY_OBJECT_CONTROL_STATE:
128 * .LLCeLLCCacheabilityControlLLCCC = 0,
129 * .L3CacheabilityControlL3CC = 1,
131 dev
->mocs
.internal
= 1;
132 dev
->mocs
.external
= 1;
134 /* MEMORY_OBJECT_CONTROL_STATE:
135 * .GraphicsDataTypeGFDT = 0,
136 * .LLCCacheabilityControlLLCCC = 0,
137 * .L3CacheabilityControlL3CC = 1,
139 dev
->mocs
.internal
= 1;
140 dev
->mocs
.external
= 1;
143 dev
->mocs
.internal
= 0;
144 dev
->mocs
.external
= 0;
149 isl_device_init(struct isl_device
*dev
,
150 const struct gen_device_info
*info
,
151 bool has_bit6_swizzling
)
153 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
154 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
157 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
158 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
160 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
161 * device properties at buildtime. Verify that the macros with the device
162 * properties chosen during runtime.
164 ISL_DEV_GEN_SANITIZE(dev
);
165 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
167 /* Did we break hiz or stencil? */
168 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
169 assert(info
->has_hiz_and_separate_stencil
);
170 if (info
->must_use_separate_stencil
)
171 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
173 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
174 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
176 dev
->ss
.clear_color_state_size
=
177 isl_align(CLEAR_COLOR_length(info
) * 4, 64);
178 dev
->ss
.clear_color_state_offset
=
179 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
181 dev
->ss
.clear_value_size
=
182 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
183 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
184 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
185 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
187 dev
->ss
.clear_value_offset
=
188 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
190 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
191 dev
->ss
.addr_offset
=
192 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
194 /* The "Auxiliary Surface Base Address" field starts a bit higher up
195 * because the bottom 12 bits are used for other things. Round down to
196 * the nearest dword before.
198 dev
->ss
.aux_addr_offset
=
199 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
201 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
202 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
203 dev
->ds
.depth_offset
=
204 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
206 if (dev
->use_separate_stencil
) {
207 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
208 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
209 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
211 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
212 dev
->ds
.stencil_offset
=
213 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
214 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
216 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
218 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
219 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
220 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
222 dev
->ds
.stencil_offset
= 0;
223 dev
->ds
.hiz_offset
= 0;
226 if (ISL_DEV_GEN(dev
) >= 12) {
227 dev
->ds
.size
+= GEN12_MI_LOAD_REGISTER_IMM_length
* 4 * 2;
230 isl_device_setup_mocs(dev
);
234 * @brief Query the set of multisamples supported by the device.
236 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
239 isl_sample_count_mask_t ATTRIBUTE_CONST
240 isl_device_get_sample_counts(struct isl_device
*dev
)
242 if (ISL_DEV_GEN(dev
) >= 9) {
243 return ISL_SAMPLE_COUNT_1_BIT
|
244 ISL_SAMPLE_COUNT_2_BIT
|
245 ISL_SAMPLE_COUNT_4_BIT
|
246 ISL_SAMPLE_COUNT_8_BIT
|
247 ISL_SAMPLE_COUNT_16_BIT
;
248 } else if (ISL_DEV_GEN(dev
) >= 8) {
249 return ISL_SAMPLE_COUNT_1_BIT
|
250 ISL_SAMPLE_COUNT_2_BIT
|
251 ISL_SAMPLE_COUNT_4_BIT
|
252 ISL_SAMPLE_COUNT_8_BIT
;
253 } else if (ISL_DEV_GEN(dev
) >= 7) {
254 return ISL_SAMPLE_COUNT_1_BIT
|
255 ISL_SAMPLE_COUNT_4_BIT
|
256 ISL_SAMPLE_COUNT_8_BIT
;
257 } else if (ISL_DEV_GEN(dev
) >= 6) {
258 return ISL_SAMPLE_COUNT_1_BIT
|
259 ISL_SAMPLE_COUNT_4_BIT
;
261 return ISL_SAMPLE_COUNT_1_BIT
;
266 * @param[out] info is written only on success
269 isl_tiling_get_info(enum isl_tiling tiling
,
271 struct isl_tile_info
*tile_info
)
273 const uint32_t bs
= format_bpb
/ 8;
274 struct isl_extent2d logical_el
, phys_B
;
276 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
277 /* It is possible to have non-power-of-two formats in a tiled buffer.
278 * The easiest way to handle this is to treat the tile as if it is three
279 * times as wide. This way no pixel will ever cross a tile boundary.
280 * This really only works on legacy X and Y tiling formats.
282 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
283 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
284 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
289 case ISL_TILING_LINEAR
:
291 logical_el
= isl_extent2d(1, 1);
292 phys_B
= isl_extent2d(bs
, 1);
297 logical_el
= isl_extent2d(512 / bs
, 8);
298 phys_B
= isl_extent2d(512, 8);
303 logical_el
= isl_extent2d(128 / bs
, 32);
304 phys_B
= isl_extent2d(128, 32);
309 logical_el
= isl_extent2d(64, 64);
310 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
312 * "If the surface is a stencil buffer (and thus has Tile Mode set
313 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
314 * computed based on width, as the stencil buffer is stored with two
317 * This, together with the fact that stencil buffers are referred to as
318 * being Y-tiled in the PRMs for older hardware implies that the
319 * physical size of a W-tile is actually the same as for a Y-tile.
321 phys_B
= isl_extent2d(128, 32);
325 case ISL_TILING_Ys
: {
326 bool is_Ys
= tiling
== ISL_TILING_Ys
;
329 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
330 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
332 logical_el
= isl_extent2d(width
/ bs
, height
);
333 phys_B
= isl_extent2d(width
, height
);
338 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
339 * 128bpb format. The tiling has the same physical dimensions as
340 * Y-tiling but actually has two HiZ columns per Y-tiled column.
343 logical_el
= isl_extent2d(16, 16);
344 phys_B
= isl_extent2d(128, 32);
348 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
349 * have a block size of 1 or 2 bits per block and each CCS element
350 * corresponds to one cache-line pair in the main surface. From the Sky
351 * Lake PRM Vol. 12 in the section on planes:
353 * "The Color Control Surface (CCS) contains the compression status
354 * of the cache-line pairs. The compression state of the cache-line
355 * pair is specified by 2 bits in the CCS. Each CCS cache-line
356 * represents an area on the main surface of 16x16 sets of 128 byte
357 * Y-tiled cache-line-pairs. CCS is always Y tiled."
359 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
360 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
361 * that yields total tile area of 128x128 cache-line pairs or CCS
362 * elements. On older hardware, each CCS element is 1 bit and the tile
363 * is 128x256 elements.
365 assert(format_bpb
== 1 || format_bpb
== 2);
366 logical_el
= isl_extent2d(128, 256 / format_bpb
);
367 phys_B
= isl_extent2d(128, 32);
370 case ISL_TILING_GEN12_CCS
:
371 /* From the Bspec, Gen Graphics > Gen12 > Memory Data Formats > Memory
372 * Compression > Memory Compression - Gen12:
374 * 4 bits of auxiliary plane data are required for 2 cachelines of
375 * main surface data. This results in a single cacheline of auxiliary
376 * plane data mapping to 4 4K pages of main surface data for the 4K
377 * pages (tile Y ) and 1 64K Tile Ys page.
379 * The Y-tiled pairing bit of 9 shown in the table below that Bspec
380 * section expresses that the 2 cachelines of main surface data are
381 * horizontally adjacent.
383 * TODO: Handle Ys, Yf and their pairing bits.
385 * Therefore, each CCS cacheline represents a 512Bx32 row area and each
386 * element represents a 32Bx4 row area.
388 assert(format_bpb
== 4);
389 logical_el
= isl_extent2d(16, 8);
390 phys_B
= isl_extent2d(64, 1);
394 unreachable("not reached");
397 *tile_info
= (struct isl_tile_info
) {
399 .format_bpb
= format_bpb
,
400 .logical_extent_el
= logical_el
,
401 .phys_extent_B
= phys_B
,
406 isl_color_value_is_zero(union isl_color_value value
,
407 enum isl_format format
)
409 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
411 #define RETURN_FALSE_IF_NOT_0(c, i) \
412 if (fmtl->channels.c.bits && value.u32[i] != 0) \
415 RETURN_FALSE_IF_NOT_0(r
, 0);
416 RETURN_FALSE_IF_NOT_0(g
, 1);
417 RETURN_FALSE_IF_NOT_0(b
, 2);
418 RETURN_FALSE_IF_NOT_0(a
, 3);
420 #undef RETURN_FALSE_IF_NOT_0
426 isl_color_value_is_zero_one(union isl_color_value value
,
427 enum isl_format format
)
429 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
431 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
432 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
435 if (isl_format_has_int_channel(format
)) {
436 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
437 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
438 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
439 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
441 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
442 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
443 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
444 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
447 #undef RETURN_FALSE_IF_NOT_0_1
453 * @param[out] tiling is set only on success
456 isl_surf_choose_tiling(const struct isl_device
*dev
,
457 const struct isl_surf_init_info
*restrict info
,
458 enum isl_tiling
*tiling
)
460 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
462 /* HiZ surfaces always use the HiZ tiling */
463 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
464 assert(info
->format
== ISL_FORMAT_HIZ
);
465 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
466 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
470 /* CCS surfaces always use the CCS tiling */
471 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
472 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
473 UNUSED
bool ivb_ccs
= ISL_DEV_GEN(dev
) < 12 &&
474 tiling_flags
== ISL_TILING_CCS_BIT
;
475 UNUSED
bool tgl_ccs
= ISL_DEV_GEN(dev
) >= 12 &&
476 tiling_flags
== ISL_TILING_GEN12_CCS_BIT
;
477 assert(ivb_ccs
!= tgl_ccs
);
478 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
482 if (ISL_DEV_GEN(dev
) >= 6) {
483 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
485 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
488 #define CHOOSE(__tiling) \
490 if (tiling_flags & (1u << (__tiling))) { \
491 *tiling = (__tiling); \
496 /* Of the tiling modes remaining, choose the one that offers the best
500 if (info
->dim
== ISL_SURF_DIM_1D
) {
501 /* Prefer linear for 1D surfaces because they do not benefit from
502 * tiling. To the contrary, tiling leads to wasted memory and poor
503 * memory locality due to the swizzling and alignment restrictions
504 * required in tiled surfaces.
506 CHOOSE(ISL_TILING_LINEAR
);
509 CHOOSE(ISL_TILING_Ys
);
510 CHOOSE(ISL_TILING_Yf
);
511 CHOOSE(ISL_TILING_Y0
);
512 CHOOSE(ISL_TILING_X
);
513 CHOOSE(ISL_TILING_W
);
514 CHOOSE(ISL_TILING_LINEAR
);
518 /* No tiling mode accomodates the inputs. */
523 isl_choose_msaa_layout(const struct isl_device
*dev
,
524 const struct isl_surf_init_info
*info
,
525 enum isl_tiling tiling
,
526 enum isl_msaa_layout
*msaa_layout
)
528 if (ISL_DEV_GEN(dev
) >= 8) {
529 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
530 } else if (ISL_DEV_GEN(dev
) >= 7) {
531 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
532 } else if (ISL_DEV_GEN(dev
) >= 6) {
533 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
535 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
540 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
542 assert(isl_is_pow2(samples
));
544 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
547 * If the surface is multisampled and it is a depth or stencil surface
548 * or Multisampled Surface StorageFormat in SURFACE_STATE is
549 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
552 return (struct isl_extent2d
) {
553 .width
= 1 << ((ffs(samples
) - 0) / 2),
554 .height
= 1 << ((ffs(samples
) - 1) / 2),
559 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
560 uint32_t *width
, uint32_t *height
)
562 const struct isl_extent2d px_size_sa
=
563 isl_get_interleaved_msaa_px_size_sa(samples
);
566 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
568 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
571 static enum isl_array_pitch_span
572 isl_choose_array_pitch_span(const struct isl_device
*dev
,
573 const struct isl_surf_init_info
*restrict info
,
574 enum isl_dim_layout dim_layout
,
575 const struct isl_extent4d
*phys_level0_sa
)
577 switch (dim_layout
) {
578 case ISL_DIM_LAYOUT_GEN9_1D
:
579 case ISL_DIM_LAYOUT_GEN4_2D
:
580 if (ISL_DEV_GEN(dev
) >= 8) {
581 /* QPitch becomes programmable in Broadwell. So choose the
582 * most compact QPitch possible in order to conserve memory.
584 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
585 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
587 * - Software must ensure that this field is set to a value
588 * sufficiently large such that the array slices in the surface
589 * do not overlap. Refer to the Memory Data Formats section for
590 * information on how surfaces are stored in memory.
592 * - This field specifies the distance in rows between array
593 * slices. It is used only in the following cases:
595 * - Surface Array is enabled OR
596 * - Number of Mulitsamples is not NUMSAMPLES_1 and
597 * Multisampled Surface Storage Format set to MSFMT_MSS OR
598 * - Surface Type is SURFTYPE_CUBE
600 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
601 } else if (ISL_DEV_GEN(dev
) >= 7) {
602 /* Note that Ivybridge introduces
603 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
604 * driver more control over the QPitch.
607 if (phys_level0_sa
->array_len
== 1) {
608 /* The hardware will never use the QPitch. So choose the most
609 * compact QPitch possible in order to conserve memory.
611 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
614 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
615 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
616 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
617 * Section 6.18.4.7: Surface Arrays (p112):
619 * If Surface Array Spacing is set to ARYSPC_FULL (note that
620 * the depth buffer and stencil buffer have an implied value of
623 return ISL_ARRAY_PITCH_SPAN_FULL
;
626 if (info
->levels
== 1) {
627 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
630 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
633 return ISL_ARRAY_PITCH_SPAN_FULL
;
634 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
635 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
636 isl_surf_usage_is_stencil(info
->usage
)) {
637 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
638 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
640 * The separate stencil buffer does not support mip mapping, thus
641 * the storage for LODs other than LOD 0 is not needed.
643 assert(info
->levels
== 1);
644 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
646 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
647 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
648 isl_surf_usage_is_stencil(info
->usage
)) {
649 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
650 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
652 * The separate stencil buffer does not support mip mapping,
653 * thus the storage for LODs other than LOD 0 is not needed.
655 assert(info
->levels
== 1);
656 assert(phys_level0_sa
->array_len
== 1);
657 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
660 if (phys_level0_sa
->array_len
== 1) {
661 /* The hardware will never use the QPitch. So choose the most
662 * compact QPitch possible in order to conserve memory.
664 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
667 return ISL_ARRAY_PITCH_SPAN_FULL
;
670 case ISL_DIM_LAYOUT_GEN4_3D
:
671 /* The hardware will never use the QPitch. So choose the most
672 * compact QPitch possible in order to conserve memory.
674 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
676 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
677 /* Each array image in the gen6 stencil of HiZ surface is compact in the
678 * sense that every LOD is a compact array of the same size as LOD0.
680 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
683 unreachable("bad isl_dim_layout");
684 return ISL_ARRAY_PITCH_SPAN_FULL
;
688 isl_choose_image_alignment_el(const struct isl_device
*dev
,
689 const struct isl_surf_init_info
*restrict info
,
690 enum isl_tiling tiling
,
691 enum isl_dim_layout dim_layout
,
692 enum isl_msaa_layout msaa_layout
,
693 struct isl_extent3d
*image_align_el
)
695 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
696 if (fmtl
->txc
== ISL_TXC_MCS
) {
697 assert(tiling
== ISL_TILING_Y0
);
700 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
702 * Height, width, and layout of MCS buffer in this case must match with
703 * Render Target height, width, and layout. MCS buffer is tiledY.
705 * To avoid wasting memory, choose the smallest alignment possible:
706 * HALIGN_4 and VALIGN_4.
708 *image_align_el
= isl_extent3d(4, 4, 1);
710 } else if (info
->format
== ISL_FORMAT_HIZ
) {
711 assert(ISL_DEV_GEN(dev
) >= 6);
712 if (ISL_DEV_GEN(dev
) == 6) {
713 /* HiZ surfaces on Sandy Bridge are packed tightly. */
714 *image_align_el
= isl_extent3d(1, 1, 1);
715 } else if (ISL_DEV_GEN(dev
) < 12) {
716 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
717 * primary surface which works out to 2x2 HiZ elments.
719 *image_align_el
= isl_extent3d(2, 2, 1);
721 /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the
722 * primary surface which works out to 2x4 HiZ elments.
725 *image_align_el
= isl_extent3d(2, 4, 1);
730 if (ISL_DEV_GEN(dev
) >= 12) {
731 isl_gen12_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
732 msaa_layout
, image_align_el
);
733 } else if (ISL_DEV_GEN(dev
) >= 9) {
734 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
735 msaa_layout
, image_align_el
);
736 } else if (ISL_DEV_GEN(dev
) >= 8) {
737 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
738 msaa_layout
, image_align_el
);
739 } else if (ISL_DEV_GEN(dev
) >= 7) {
740 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
741 msaa_layout
, image_align_el
);
742 } else if (ISL_DEV_GEN(dev
) >= 6) {
743 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
744 msaa_layout
, image_align_el
);
746 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
747 msaa_layout
, image_align_el
);
751 static enum isl_dim_layout
752 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
753 enum isl_surf_dim logical_dim
,
754 enum isl_tiling tiling
,
755 isl_surf_usage_flags_t usage
)
757 /* Sandy bridge needs a special layout for HiZ and stencil. */
758 if (ISL_DEV_GEN(dev
) == 6 &&
759 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
760 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
762 if (ISL_DEV_GEN(dev
) >= 9) {
763 switch (logical_dim
) {
764 case ISL_SURF_DIM_1D
:
765 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
767 * One-dimensional surfaces use a tiling mode of linear.
768 * Technically, they are not tiled resources, but the Tiled
769 * Resource Mode field in RENDER_SURFACE_STATE is still used to
770 * indicate the alignment requirements for this linear surface
771 * (See 1D Alignment requirements for how 4K and 64KB Tiled
772 * Resource Modes impact alignment). Alternatively, a 1D surface
773 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
776 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
777 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
779 if (tiling
== ISL_TILING_LINEAR
)
780 return ISL_DIM_LAYOUT_GEN9_1D
;
782 return ISL_DIM_LAYOUT_GEN4_2D
;
783 case ISL_SURF_DIM_2D
:
784 case ISL_SURF_DIM_3D
:
785 return ISL_DIM_LAYOUT_GEN4_2D
;
788 switch (logical_dim
) {
789 case ISL_SURF_DIM_1D
:
790 case ISL_SURF_DIM_2D
:
791 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
793 * The cube face textures are stored in the same way as 3D surfaces
794 * are stored (see section 6.17.5 for details). For cube surfaces,
795 * however, the depth is equal to the number of faces (always 6) and
796 * is not reduced for each MIP.
798 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
799 return ISL_DIM_LAYOUT_GEN4_3D
;
801 return ISL_DIM_LAYOUT_GEN4_2D
;
802 case ISL_SURF_DIM_3D
:
803 return ISL_DIM_LAYOUT_GEN4_3D
;
807 unreachable("bad isl_surf_dim");
808 return ISL_DIM_LAYOUT_GEN4_2D
;
812 * Calculate the physical extent of the surface's first level, in units of
816 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
817 const struct isl_surf_init_info
*restrict info
,
818 enum isl_dim_layout dim_layout
,
819 enum isl_tiling tiling
,
820 enum isl_msaa_layout msaa_layout
,
821 struct isl_extent4d
*phys_level0_sa
)
823 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
825 if (isl_format_is_yuv(info
->format
))
826 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
829 case ISL_SURF_DIM_1D
:
830 assert(info
->height
== 1);
831 assert(info
->depth
== 1);
832 assert(info
->samples
== 1);
834 switch (dim_layout
) {
835 case ISL_DIM_LAYOUT_GEN4_3D
:
836 unreachable("bad isl_dim_layout");
838 case ISL_DIM_LAYOUT_GEN9_1D
:
839 case ISL_DIM_LAYOUT_GEN4_2D
:
840 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
841 *phys_level0_sa
= (struct isl_extent4d
) {
845 .a
= info
->array_len
,
851 case ISL_SURF_DIM_2D
:
852 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
853 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
855 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
856 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
858 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
859 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
861 switch (msaa_layout
) {
862 case ISL_MSAA_LAYOUT_NONE
:
863 assert(info
->depth
== 1);
864 assert(info
->samples
== 1);
866 *phys_level0_sa
= (struct isl_extent4d
) {
870 .a
= info
->array_len
,
874 case ISL_MSAA_LAYOUT_ARRAY
:
875 assert(info
->depth
== 1);
876 assert(info
->levels
== 1);
877 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
878 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
880 *phys_level0_sa
= (struct isl_extent4d
) {
884 .a
= info
->array_len
* info
->samples
,
888 case ISL_MSAA_LAYOUT_INTERLEAVED
:
889 assert(info
->depth
== 1);
890 assert(info
->levels
== 1);
891 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
893 *phys_level0_sa
= (struct isl_extent4d
) {
897 .a
= info
->array_len
,
900 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
907 case ISL_SURF_DIM_3D
:
908 assert(info
->array_len
== 1);
909 assert(info
->samples
== 1);
912 isl_finishme("%s:%s: compression block with depth > 1",
916 switch (dim_layout
) {
917 case ISL_DIM_LAYOUT_GEN9_1D
:
918 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
919 unreachable("bad isl_dim_layout");
921 case ISL_DIM_LAYOUT_GEN4_2D
:
922 assert(ISL_DEV_GEN(dev
) >= 9);
924 *phys_level0_sa
= (struct isl_extent4d
) {
932 case ISL_DIM_LAYOUT_GEN4_3D
:
933 assert(ISL_DEV_GEN(dev
) < 9);
934 *phys_level0_sa
= (struct isl_extent4d
) {
947 * Calculate the pitch between physical array slices, in units of rows of
951 isl_calc_array_pitch_el_rows_gen4_2d(
952 const struct isl_device
*dev
,
953 const struct isl_surf_init_info
*restrict info
,
954 const struct isl_tile_info
*tile_info
,
955 const struct isl_extent3d
*image_align_sa
,
956 const struct isl_extent4d
*phys_level0_sa
,
957 enum isl_array_pitch_span array_pitch_span
,
958 const struct isl_extent2d
*phys_slice0_sa
)
960 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
961 uint32_t pitch_sa_rows
= 0;
963 switch (array_pitch_span
) {
964 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
965 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
967 case ISL_ARRAY_PITCH_SPAN_FULL
: {
968 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
969 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
970 * Surfaces >> Surface Arrays.
972 uint32_t H0_sa
= phys_level0_sa
->h
;
973 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
975 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
976 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
979 if (ISL_DEV_GEN(dev
) >= 7) {
980 /* The QPitch equation changed slightly in Ivybridge. */
986 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
988 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
989 (info
->height
% 4 == 1)) {
990 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
991 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
993 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
994 * the value calculated in the equation above , for every
995 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
997 * XXX(chadv): Is the errata natural corollary of the physical
998 * layout of interleaved samples?
1003 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
1008 assert(pitch_sa_rows
% fmtl
->bh
== 0);
1009 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
1011 if (ISL_DEV_GEN(dev
) >= 9 && ISL_DEV_GEN(dev
) <= 11 &&
1012 fmtl
->txc
== ISL_TXC_CCS
) {
1014 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
1016 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
1017 * layout with these alignments in the RT space: Horizontal
1018 * Alignment = 128 and Vertical Alignment = 64."
1020 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
1022 * "For non-multisampled render target's CCS auxiliary surface,
1023 * QPitch must be computed with Horizontal Alignment = 128 and
1024 * Surface Vertical Alignment = 256. These alignments are only for
1025 * CCS buffer and not for associated render target."
1027 * The first restriction is already handled by isl_choose_image_alignment_el
1028 * but the second restriction, which is an extension of the first, only
1029 * applies to qpitch and must be applied here.
1031 * The second restriction disappears on Gen12.
1033 assert(fmtl
->bh
== 4);
1034 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
1037 if (ISL_DEV_GEN(dev
) >= 9 &&
1038 info
->dim
== ISL_SURF_DIM_3D
&&
1039 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
1040 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
1042 * Tile Mode != Linear: This field must be set to an integer multiple
1043 * of the tile height
1045 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
1048 return pitch_el_rows
;
1052 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1053 * ISL_DIM_LAYOUT_GEN4_2D.
1056 isl_calc_phys_slice0_extent_sa_gen4_2d(
1057 const struct isl_device
*dev
,
1058 const struct isl_surf_init_info
*restrict info
,
1059 enum isl_msaa_layout msaa_layout
,
1060 const struct isl_extent3d
*image_align_sa
,
1061 const struct isl_extent4d
*phys_level0_sa
,
1062 struct isl_extent2d
*phys_slice0_sa
)
1064 assert(phys_level0_sa
->depth
== 1);
1066 if (info
->levels
== 1) {
1067 /* Do not pad the surface to the image alignment.
1069 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
1070 * cycles on the below mipmap layout caluclations. Reducing the
1071 * alignment here is safe because we later align the row pitch and array
1072 * pitch to the tile boundary. It is safe even for
1073 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1074 * to accomodate the interleaved samples.
1076 * For linear surfaces, reducing the alignment here permits us to later
1077 * choose an arbitrary, non-aligned row pitch. If the surface backs
1078 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
1079 * VkBufferImageCopy::bufferRowLength.
1081 *phys_slice0_sa
= (struct isl_extent2d
) {
1082 .w
= phys_level0_sa
->w
,
1083 .h
= phys_level0_sa
->h
,
1088 uint32_t slice_top_w
= 0;
1089 uint32_t slice_bottom_w
= 0;
1090 uint32_t slice_left_h
= 0;
1091 uint32_t slice_right_h
= 0;
1093 uint32_t W0
= phys_level0_sa
->w
;
1094 uint32_t H0
= phys_level0_sa
->h
;
1096 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1097 uint32_t W
= isl_minify(W0
, l
);
1098 uint32_t H
= isl_minify(H0
, l
);
1100 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1101 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1107 } else if (l
== 1) {
1110 } else if (l
== 2) {
1111 slice_bottom_w
+= w
;
1118 *phys_slice0_sa
= (struct isl_extent2d
) {
1119 .w
= MAX(slice_top_w
, slice_bottom_w
),
1120 .h
= MAX(slice_left_h
, slice_right_h
),
1125 isl_calc_phys_total_extent_el_gen4_2d(
1126 const struct isl_device
*dev
,
1127 const struct isl_surf_init_info
*restrict info
,
1128 const struct isl_tile_info
*tile_info
,
1129 enum isl_msaa_layout msaa_layout
,
1130 const struct isl_extent3d
*image_align_sa
,
1131 const struct isl_extent4d
*phys_level0_sa
,
1132 enum isl_array_pitch_span array_pitch_span
,
1133 uint32_t *array_pitch_el_rows
,
1134 struct isl_extent2d
*total_extent_el
)
1136 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1138 struct isl_extent2d phys_slice0_sa
;
1139 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1140 image_align_sa
, phys_level0_sa
,
1142 *array_pitch_el_rows
=
1143 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1144 image_align_sa
, phys_level0_sa
,
1147 *total_extent_el
= (struct isl_extent2d
) {
1148 .w
= isl_align_div_npot(phys_slice0_sa
.w
, fmtl
->bw
),
1149 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1150 isl_align_div_npot(phys_slice0_sa
.h
, fmtl
->bh
),
1155 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1156 * ISL_DIM_LAYOUT_GEN4_3D.
1159 isl_calc_phys_total_extent_el_gen4_3d(
1160 const struct isl_device
*dev
,
1161 const struct isl_surf_init_info
*restrict info
,
1162 const struct isl_extent3d
*image_align_sa
,
1163 const struct isl_extent4d
*phys_level0_sa
,
1164 uint32_t *array_pitch_el_rows
,
1165 struct isl_extent2d
*phys_total_el
)
1167 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1169 assert(info
->samples
== 1);
1171 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1172 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1174 * The cube face textures are stored in the same way as 3D surfaces
1175 * are stored (see section 6.17.5 for details). For cube surfaces,
1176 * however, the depth is equal to the number of faces (always 6) and
1177 * is not reduced for each MIP.
1179 assert(ISL_DEV_GEN(dev
) == 4);
1180 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1181 assert(phys_level0_sa
->array_len
== 6);
1183 assert(phys_level0_sa
->array_len
== 1);
1186 uint32_t total_w
= 0;
1187 uint32_t total_h
= 0;
1189 uint32_t W0
= phys_level0_sa
->w
;
1190 uint32_t H0
= phys_level0_sa
->h
;
1191 uint32_t D0
= phys_level0_sa
->d
;
1192 uint32_t A0
= phys_level0_sa
->a
;
1194 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1195 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1196 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1197 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1199 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1200 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1202 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1203 total_h
+= level_h
* max_layers_vert
;
1206 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1207 * different number of horizontal and vertical layers. We have to set it
1208 * to something, so at least make it true for LOD0.
1210 *array_pitch_el_rows
=
1211 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1212 *phys_total_el
= (struct isl_extent2d
) {
1213 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1214 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1219 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1220 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1223 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1224 const struct isl_device
*dev
,
1225 const struct isl_surf_init_info
*restrict info
,
1226 const struct isl_tile_info
*tile_info
,
1227 const struct isl_extent3d
*image_align_sa
,
1228 const struct isl_extent4d
*phys_level0_sa
,
1229 uint32_t *array_pitch_el_rows
,
1230 struct isl_extent2d
*phys_total_el
)
1232 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1234 const struct isl_extent2d tile_extent_sa
= {
1235 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1236 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1238 /* Tile size is a multiple of image alignment */
1239 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1240 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1242 const uint32_t W0
= phys_level0_sa
->w
;
1243 const uint32_t H0
= phys_level0_sa
->h
;
1245 /* Each image has the same height as LOD0 because the hardware thinks
1246 * everything is LOD0
1248 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1250 uint32_t total_top_w
= 0;
1251 uint32_t total_bottom_w
= 0;
1252 uint32_t total_h
= 0;
1254 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1255 const uint32_t W
= isl_minify(W0
, l
);
1257 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1258 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1263 } else if (l
== 1) {
1267 total_bottom_w
+= w
;
1271 *array_pitch_el_rows
=
1272 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1273 *phys_total_el
= (struct isl_extent2d
) {
1274 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1275 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1280 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1281 * ISL_DIM_LAYOUT_GEN9_1D.
1284 isl_calc_phys_total_extent_el_gen9_1d(
1285 const struct isl_device
*dev
,
1286 const struct isl_surf_init_info
*restrict info
,
1287 const struct isl_extent3d
*image_align_sa
,
1288 const struct isl_extent4d
*phys_level0_sa
,
1289 uint32_t *array_pitch_el_rows
,
1290 struct isl_extent2d
*phys_total_el
)
1292 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1294 assert(phys_level0_sa
->height
== 1);
1295 assert(phys_level0_sa
->depth
== 1);
1296 assert(info
->samples
== 1);
1297 assert(image_align_sa
->w
>= fmtl
->bw
);
1299 uint32_t slice_w
= 0;
1300 const uint32_t W0
= phys_level0_sa
->w
;
1302 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1303 uint32_t W
= isl_minify(W0
, l
);
1304 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1309 *array_pitch_el_rows
= 1;
1310 *phys_total_el
= (struct isl_extent2d
) {
1311 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1312 .h
= phys_level0_sa
->array_len
,
1317 * Calculate the two-dimensional total physical extent of the surface, in
1318 * units of surface elements.
1321 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1322 const struct isl_surf_init_info
*restrict info
,
1323 const struct isl_tile_info
*tile_info
,
1324 enum isl_dim_layout dim_layout
,
1325 enum isl_msaa_layout msaa_layout
,
1326 const struct isl_extent3d
*image_align_sa
,
1327 const struct isl_extent4d
*phys_level0_sa
,
1328 enum isl_array_pitch_span array_pitch_span
,
1329 uint32_t *array_pitch_el_rows
,
1330 struct isl_extent2d
*total_extent_el
)
1332 switch (dim_layout
) {
1333 case ISL_DIM_LAYOUT_GEN9_1D
:
1334 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1335 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1336 image_align_sa
, phys_level0_sa
,
1337 array_pitch_el_rows
,
1340 case ISL_DIM_LAYOUT_GEN4_2D
:
1341 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1342 image_align_sa
, phys_level0_sa
,
1344 array_pitch_el_rows
,
1347 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1348 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1349 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1352 array_pitch_el_rows
,
1355 case ISL_DIM_LAYOUT_GEN4_3D
:
1356 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1357 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1358 image_align_sa
, phys_level0_sa
,
1359 array_pitch_el_rows
,
1364 unreachable("invalid value for dim_layout");
1368 isl_calc_row_pitch_alignment(const struct isl_device
*dev
,
1369 const struct isl_surf_init_info
*surf_info
,
1370 const struct isl_tile_info
*tile_info
)
1372 if (tile_info
->tiling
!= ISL_TILING_LINEAR
) {
1373 /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches must
1374 * be 512B-aligned. CCS is only support on Y tilings.
1376 if (ISL_DEV_GEN(dev
) >= 12 &&
1377 isl_format_supports_ccs_e(dev
->info
, surf_info
->format
) &&
1378 tile_info
->tiling
!= ISL_TILING_X
) {
1379 return isl_align(tile_info
->phys_extent_B
.width
, 512);
1382 return tile_info
->phys_extent_B
.width
;
1385 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1386 * RENDER_SURFACE_STATE Surface Pitch (p349):
1388 * - For linear render target surfaces and surfaces accessed with the
1389 * typed data port messages, the pitch must be a multiple of the
1390 * element size for non-YUV surface formats. Pitch must be
1391 * a multiple of 2 * element size for YUV surface formats.
1393 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1394 * ignore because isl doesn't do buffers.]
1396 * - For other linear surfaces, the pitch can be any multiple of
1399 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1400 const uint32_t bs
= fmtl
->bpb
/ 8;
1403 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1404 if (isl_format_is_yuv(surf_info
->format
)) {
1413 /* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >>
1414 * PRI_STRIDE Stride (p1254):
1416 * "When using linear memory, this must be at least 64 byte aligned."
1418 if (surf_info
->usage
& ISL_SURF_USAGE_DISPLAY_BIT
)
1419 alignment
= isl_align(alignment
, 64);
1425 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1426 const struct isl_surf_init_info
*info
,
1427 const struct isl_extent2d
*phys_total_el
,
1428 uint32_t alignment_B
)
1430 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1431 const uint32_t bs
= fmtl
->bpb
/ 8;
1433 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1437 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1438 const struct isl_surf_init_info
*surf_info
,
1439 const struct isl_tile_info
*tile_info
,
1440 const struct isl_extent2d
*phys_total_el
,
1441 uint32_t alignment_B
)
1443 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1445 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1447 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1448 const uint32_t total_w_tl
=
1449 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1450 tile_info
->logical_extent_el
.width
);
1452 /* In some cases the alignment of the pitch might be > to the tile size
1453 * (for example Gen12 CCS requires 512B alignment while the tile's width
1454 * can be 128B), so align the row pitch to the alignment.
1456 assert(alignment_B
>= tile_info
->phys_extent_B
.width
);
1457 return isl_align(total_w_tl
* tile_info
->phys_extent_B
.width
, alignment_B
);
1461 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1462 const struct isl_surf_init_info
*surf_info
,
1463 const struct isl_tile_info
*tile_info
,
1464 const struct isl_extent2d
*phys_total_el
,
1465 uint32_t alignment_B
)
1467 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1468 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1471 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1472 phys_total_el
, alignment_B
);
1477 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1478 * size is `bits` bits?
1480 * Hardware pitch fields are offset by 1. For example, if the size of
1481 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1482 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1483 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1486 pitch_in_range(uint32_t n
, uint32_t bits
)
1489 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1493 isl_calc_row_pitch(const struct isl_device
*dev
,
1494 const struct isl_surf_init_info
*surf_info
,
1495 const struct isl_tile_info
*tile_info
,
1496 enum isl_dim_layout dim_layout
,
1497 const struct isl_extent2d
*phys_total_el
,
1498 uint32_t *out_row_pitch_B
)
1500 uint32_t alignment_B
=
1501 isl_calc_row_pitch_alignment(dev
, surf_info
, tile_info
);
1503 const uint32_t min_row_pitch_B
=
1504 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1507 if (surf_info
->row_pitch_B
!= 0) {
1508 if (surf_info
->row_pitch_B
< min_row_pitch_B
)
1511 if (surf_info
->row_pitch_B
% alignment_B
!= 0)
1515 const uint32_t row_pitch_B
=
1516 surf_info
->row_pitch_B
!= 0 ? surf_info
->row_pitch_B
: min_row_pitch_B
;
1518 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1520 if (row_pitch_B
== 0)
1523 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1524 /* SurfacePitch is ignored for this layout. */
1528 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1529 ISL_SURF_USAGE_TEXTURE_BIT
|
1530 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1531 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1534 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1535 ISL_SURF_USAGE_MCS_BIT
)) &&
1536 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1539 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1540 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1543 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1544 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1547 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1548 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1549 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1551 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1552 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1556 *out_row_pitch_B
= row_pitch_B
;
1561 isl_surf_init_s(const struct isl_device
*dev
,
1562 struct isl_surf
*surf
,
1563 const struct isl_surf_init_info
*restrict info
)
1565 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1567 const struct isl_extent4d logical_level0_px
= {
1571 .a
= info
->array_len
,
1574 enum isl_tiling tiling
;
1575 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1578 struct isl_tile_info tile_info
;
1579 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1581 const enum isl_dim_layout dim_layout
=
1582 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1584 enum isl_msaa_layout msaa_layout
;
1585 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1588 struct isl_extent3d image_align_el
;
1589 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1592 struct isl_extent3d image_align_sa
=
1593 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1595 struct isl_extent4d phys_level0_sa
;
1596 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1599 enum isl_array_pitch_span array_pitch_span
=
1600 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1602 uint32_t array_pitch_el_rows
;
1603 struct isl_extent2d phys_total_el
;
1604 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1605 dim_layout
, msaa_layout
,
1606 &image_align_sa
, &phys_level0_sa
,
1607 array_pitch_span
, &array_pitch_el_rows
,
1610 uint32_t row_pitch_B
;
1611 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1612 &phys_total_el
, &row_pitch_B
))
1615 uint32_t base_alignment_B
;
1617 if (tiling
== ISL_TILING_LINEAR
) {
1618 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1620 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1622 * "The Base Address for linear render target surfaces and surfaces
1623 * accessed with the typed surface read/write data port messages must
1624 * be element-size aligned, for non-YUV surface formats, or a
1625 * multiple of 2 element-sizes for YUV surface formats. Other linear
1626 * surfaces have no alignment requirements (byte alignment is
1629 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1630 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1631 if (isl_format_is_yuv(info
->format
)) {
1632 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1634 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1637 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1639 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1641 * "For Linear memory, this field specifies the stride in chunks of
1642 * 64 bytes (1 cache line)."
1644 if (isl_surf_usage_is_display(info
->usage
))
1645 base_alignment_B
= MAX(base_alignment_B
, 64);
1647 const uint32_t total_h_tl
=
1648 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1650 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1652 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1653 tile_info
.phys_extent_B
.height
;
1654 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1655 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1657 /* The diagram in the Bspec section Memory Compression - Gen12, shows
1658 * that the CCS is indexed in 256B chunks. However, the
1659 * PLANE_AUX_DIST::Auxiliary Surface Distance field is in units of 4K
1660 * pages. We currently don't assign the usage field like we do for main
1661 * surfaces, so just use 4K for now.
1663 if (tiling
== ISL_TILING_GEN12_CCS
)
1664 base_alignment_B
= MAX(base_alignment_B
, 4096);
1666 /* Gen12+ requires that images be 64K-aligned if they're going to used
1667 * with CCS. This is because the Aux translation table maps main
1668 * surface addresses to aux addresses at a 64K (in the main surface)
1669 * granularity. Because we don't know for sure in ISL if a surface will
1670 * use CCS, we have to guess based on the DISABLE_AUX usage bit. The
1671 * one thing we do know is that we haven't enable CCS on linear images
1672 * yet so we can avoid the extra alignment there.
1674 if (ISL_DEV_GEN(dev
) >= 12 &&
1675 !(info
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)) {
1676 base_alignment_B
= MAX(base_alignment_B
, 64 * 1024);
1680 if (ISL_DEV_GEN(dev
) < 9) {
1681 /* From the Broadwell PRM Vol 5, Surface Layout:
1683 * "In addition to restrictions on maximum height, width, and depth,
1684 * surfaces are also restricted to a maximum size in bytes. This
1685 * maximum is 2 GB for all products and all surface types."
1687 * This comment is applicable to all Pre-gen9 platforms.
1689 if (size_B
> (uint64_t) 1 << 31)
1691 } else if (ISL_DEV_GEN(dev
) < 11) {
1692 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1693 * "In addition to restrictions on maximum height, width, and depth,
1694 * surfaces are also restricted to a maximum size of 2^38 bytes.
1695 * All pixels within the surface must be contained within 2^38 bytes
1696 * of the base address."
1698 if (size_B
> (uint64_t) 1 << 38)
1701 /* gen11+ platforms raised this limit to 2^44 bytes. */
1702 if (size_B
> (uint64_t) 1 << 44)
1706 *surf
= (struct isl_surf
) {
1708 .dim_layout
= dim_layout
,
1709 .msaa_layout
= msaa_layout
,
1711 .format
= info
->format
,
1713 .levels
= info
->levels
,
1714 .samples
= info
->samples
,
1716 .image_alignment_el
= image_align_el
,
1717 .logical_level0_px
= logical_level0_px
,
1718 .phys_level0_sa
= phys_level0_sa
,
1721 .alignment_B
= base_alignment_B
,
1722 .row_pitch_B
= row_pitch_B
,
1723 .array_pitch_el_rows
= array_pitch_el_rows
,
1724 .array_pitch_span
= array_pitch_span
,
1726 .usage
= info
->usage
,
1733 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1734 struct isl_tile_info
*tile_info
)
1736 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1737 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1741 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1742 const struct isl_surf
*surf
,
1743 struct isl_surf
*hiz_surf
)
1745 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1747 if (!isl_surf_usage_is_depth(surf
->usage
))
1750 /* HiZ only works with Y-tiled depth buffers */
1751 if (!isl_tiling_is_any_y(surf
->tiling
))
1754 /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
1755 switch (surf
->format
) {
1756 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1757 if (isl_surf_usage_is_depth_and_stencil(surf
->usage
)) {
1758 assert(ISL_DEV_GEN(dev
) == 5);
1759 unreachable("This should work, but is untested");
1762 case ISL_FORMAT_R16_UNORM
:
1763 case ISL_FORMAT_R32_FLOAT
:
1765 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1766 if (ISL_DEV_GEN(dev
) == 5) {
1767 assert(isl_surf_usage_is_depth_and_stencil(surf
->usage
));
1768 unreachable("This should work, but is untested");
1775 /* Multisampled depth is always interleaved */
1776 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1777 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1779 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1781 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1782 * Target View Extent, and Depth Coordinate Offset X/Y of the
1783 * hierarchical depth buffer are inherited from the depth buffer. The
1784 * height and width of the hierarchical depth buffer that must be
1785 * allocated are computed by the following formulas, where HZ is the
1786 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1787 * Z_Width, and Z_Depth values given in these formulas are those present
1788 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1790 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1791 * being applied to the table below if Number of Multisamples is set to
1792 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1793 * Z_Width must be multiplied by 4 before being applied to the table
1794 * below if Number of Multisamples is set to NUMSAMPLES_8."
1796 * In the Sky Lake PRM, the second paragraph is replaced with this:
1798 * "The Z_Height and Z_Width values must equal those present in
1799 * 3DSTATE_DEPTH_BUFFER incremented by one."
1801 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1802 * block corresponds to a region of 8x4 samples in the primary depth
1803 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1804 * a region of 8x4 pixels in the primary depth surface regardless of the
1805 * number of samples. The dimensions of a HiZ block in both pixels and
1806 * samples are given in the table below:
1808 * | SNB - BDW | SKL+
1809 * ------+-----------+-------------
1810 * 1x | 8 x 4 sa | 8 x 4 sa
1811 * MSAA | 8 x 4 px | 8 x 4 px
1812 * ------+-----------+-------------
1813 * 2x | 8 x 4 sa | 16 x 4 sa
1814 * MSAA | 4 x 4 px | 8 x 4 px
1815 * ------+-----------+-------------
1816 * 4x | 8 x 4 sa | 16 x 8 sa
1817 * MSAA | 4 x 2 px | 8 x 4 px
1818 * ------+-----------+-------------
1819 * 8x | 8 x 4 sa | 32 x 8 sa
1820 * MSAA | 2 x 2 px | 8 x 4 px
1821 * ------+-----------+-------------
1822 * 16x | N/A | 32 x 16 sa
1823 * MSAA | N/A | 8 x 4 px
1824 * ------+-----------+-------------
1826 * There are a number of different ways that this discrepency could be
1827 * handled. The way we have chosen is to simply make MSAA HiZ have the
1828 * same number of samples as the parent surface pre-Sky Lake and always be
1829 * single-sampled on Sky Lake and above. Since the block sizes of
1830 * compressed formats are given in samples, this neatly handles everything
1831 * without the need for additional HiZ formats with different block sizes
1834 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1836 return isl_surf_init(dev
, hiz_surf
,
1838 .format
= ISL_FORMAT_HIZ
,
1839 .width
= surf
->logical_level0_px
.width
,
1840 .height
= surf
->logical_level0_px
.height
,
1841 .depth
= surf
->logical_level0_px
.depth
,
1842 .levels
= surf
->levels
,
1843 .array_len
= surf
->logical_level0_px
.array_len
,
1845 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1846 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1850 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1851 const struct isl_surf
*surf
,
1852 struct isl_surf
*mcs_surf
)
1854 /* It must be multisampled with an array layout */
1855 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_ARRAY
)
1858 if (mcs_surf
->size_B
> 0)
1861 /* The following are true of all multisampled surfaces */
1862 assert(surf
->samples
> 1);
1863 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1864 assert(surf
->levels
== 1);
1865 assert(surf
->logical_level0_px
.depth
== 1);
1867 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
1869 * This field must be set to 0 for all SINT MSRTs when all RT channels
1872 * In practice this means that we have to disable MCS for all signed
1873 * integer MSAA buffers. The alternative, to disable MCS only when one
1874 * of the render target channels is disabled, is impractical because it
1875 * would require converting between CMS and UMS MSAA layouts on the fly,
1876 * which is expensive.
1878 if (ISL_DEV_GEN(dev
) == 7 && isl_format_has_sint_channel(surf
->format
))
1881 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1882 * bits which means the maximum pitch of a compression surface is 512
1883 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1884 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1885 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1886 * and 8x, we have enough room for the full 16k supported by the hardware.
1888 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1891 enum isl_format mcs_format
;
1892 switch (surf
->samples
) {
1893 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1894 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1895 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1896 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1898 unreachable("Invalid sample count");
1901 return isl_surf_init(dev
, mcs_surf
,
1902 .dim
= ISL_SURF_DIM_2D
,
1903 .format
= mcs_format
,
1904 .width
= surf
->logical_level0_px
.width
,
1905 .height
= surf
->logical_level0_px
.height
,
1908 .array_len
= surf
->logical_level0_px
.array_len
,
1909 .samples
= 1, /* MCS surfaces are really single-sampled */
1910 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1911 .tiling_flags
= ISL_TILING_Y0_BIT
);
1915 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1916 const struct isl_surf
*surf
,
1917 struct isl_surf
*aux_surf
,
1918 struct isl_surf
*extra_aux_surf
,
1919 uint32_t row_pitch_B
)
1923 /* An uninitialized surface is needed to get a CCS surface. */
1924 if (aux_surf
->size_B
> 0 &&
1925 (extra_aux_surf
== NULL
|| extra_aux_surf
->size_B
> 0)) {
1929 /* A surface can't have two CCS surfaces. */
1930 if (aux_surf
->usage
& ISL_SURF_USAGE_CCS_BIT
)
1933 if (ISL_DEV_GEN(dev
) < 12 && surf
->samples
> 1)
1936 /* CCS support does not exist prior to Gen7 */
1937 if (ISL_DEV_GEN(dev
) <= 6)
1940 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1943 /* Allow CCS for single-sampled stencil buffers Gen12+. */
1944 if (isl_surf_usage_is_stencil(surf
->usage
) &&
1945 (ISL_DEV_GEN(dev
) < 12 || surf
->samples
> 1))
1948 /* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if it
1949 * has HiZ. If not for GEN:BUG:1406512483 "deprecate compression enable
1950 * states", D16 would be supported. Supporting D16 requires being able to
1951 * specify that the control surface is present and simultaneously disabling
1952 * compression. The above bug makes it so that it's not possible to specify
1953 * this configuration.
1955 if (isl_surf_usage_is_depth(surf
->usage
) && (aux_surf
->size_B
== 0 ||
1956 ISL_DEV_GEN(dev
) < 12 || surf
->format
== ISL_FORMAT_R16_UNORM
)) {
1960 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1961 * work for 3D textures until gen9 where the layout of 3D textures changes
1962 * to match 2D array textures.
1964 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1967 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1968 * Non-MultiSampler Render Target Restrictions):
1970 * "Support is for non-mip-mapped and non-array surface types only."
1972 * This restriction is lifted on gen8+. Technically, it may be possible to
1973 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1974 * when rendering to the base slice. However, there is no documentation
1975 * tell us what the hardware would do in that case or what it does if you
1976 * walk off the bases slice. (Does it ignore CCS or does it start
1977 * scribbling over random memory?) We play it safe and just follow the
1978 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1980 if (ISL_DEV_GEN(dev
) <= 7 &&
1981 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1984 /* On Gen12, 8BPP surfaces cannot be compressed if any level is not
1985 * 32Bx4row-aligned. For now, just reject the cases where alignment
1988 if (ISL_DEV_GEN(dev
) >= 12 &&
1989 isl_format_get_layout(surf
->format
)->bpb
== 8 && surf
->levels
>= 3) {
1990 isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
1991 "disabled, but support for more levels is possible.",
1992 __FILE__
, __func__
);
1996 /* On Gen12, all CCS-compressed surface pitches must be multiples of 512B.
1998 if (ISL_DEV_GEN(dev
) >= 12 && surf
->row_pitch_B
% 512 != 0)
2001 if (isl_format_is_compressed(surf
->format
))
2004 /* According to GEN:BUG:1406738321, 3D textures need a blit to a new
2005 * surface in order to perform a resolve. For now, just disable CCS.
2007 if (ISL_DEV_GEN(dev
) >= 12 && surf
->dim
== ISL_SURF_DIM_3D
) {
2008 isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
2009 " is available.", __FILE__
, __func__
);
2013 /* GEN:BUG:1207137018
2015 * TODO: implement following workaround currently covered by the restriction
2016 * above. If following conditions are met:
2018 * - RENDER_SURFACE_STATE.Surface Type == 3D
2019 * - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE
2020 * - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS
2022 * Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip that
2023 * larger than those present in the surface (i.e. 15)
2026 /* TODO: More conditions where it can fail. */
2028 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
2029 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
2031 * - Support is limited to tiled render targets.
2032 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
2033 * 64bpp, and 128bpp.
2035 * From the Skylake documentation, it is made clear that X-tiling is no
2038 * - MCS and Lossless compression is supported for
2039 * TiledY/TileYs/TileYf non-MSRTs only.
2041 enum isl_format ccs_format
;
2042 if (ISL_DEV_GEN(dev
) >= 12) {
2043 /* TODO: Handle the other tiling formats */
2044 if (surf
->tiling
!= ISL_TILING_Y0
)
2049 * Linear CCS is only allowed for Untyped Buffers but only via HDC
2050 * Data-Port messages.
2052 * We probably want to limit linear CCS to storage usage and check that
2053 * the shaders actually use only untyped messages.
2055 assert(surf
->tiling
!= ISL_TILING_LINEAR
);
2057 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2058 case 8: ccs_format
= ISL_FORMAT_GEN12_CCS_8BPP_Y0
; break;
2059 case 16: ccs_format
= ISL_FORMAT_GEN12_CCS_16BPP_Y0
; break;
2060 case 32: ccs_format
= ISL_FORMAT_GEN12_CCS_32BPP_Y0
; break;
2061 case 64: ccs_format
= ISL_FORMAT_GEN12_CCS_64BPP_Y0
; break;
2062 case 128: ccs_format
= ISL_FORMAT_GEN12_CCS_128BPP_Y0
; break;
2066 } else if (ISL_DEV_GEN(dev
) >= 9) {
2067 if (!isl_tiling_is_any_y(surf
->tiling
))
2070 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2071 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
2072 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
2073 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
2077 } else if (surf
->tiling
== ISL_TILING_Y0
) {
2078 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2079 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
2080 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
2081 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
2085 } else if (surf
->tiling
== ISL_TILING_X
) {
2086 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2087 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
2088 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
2089 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
2097 if (ISL_DEV_GEN(dev
) >= 12) {
2098 /* On Gen12, the CCS is a scaled-down version of the main surface. We
2099 * model this as the CCS compressing a 2D-view of the entire surface.
2101 struct isl_surf
*ccs_surf
=
2102 aux_surf
->size_B
> 0 ? extra_aux_surf
: aux_surf
;
2104 isl_surf_init(dev
, ccs_surf
,
2105 .dim
= ISL_SURF_DIM_2D
,
2106 .format
= ccs_format
,
2107 .width
= isl_surf_get_row_pitch_el(surf
),
2108 .height
= surf
->size_B
/ surf
->row_pitch_B
,
2113 .row_pitch_B
= row_pitch_B
,
2114 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2115 .tiling_flags
= ISL_TILING_GEN12_CCS_BIT
);
2116 assert(!ok
|| ccs_surf
->size_B
== surf
->size_B
/ 256);
2119 return isl_surf_init(dev
, aux_surf
,
2121 .format
= ccs_format
,
2122 .width
= surf
->logical_level0_px
.width
,
2123 .height
= surf
->logical_level0_px
.height
,
2124 .depth
= surf
->logical_level0_px
.depth
,
2125 .levels
= surf
->levels
,
2126 .array_len
= surf
->logical_level0_px
.array_len
,
2128 .row_pitch_B
= row_pitch_B
,
2129 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2130 .tiling_flags
= ISL_TILING_CCS_BIT
);
2134 #define isl_genX_call(dev, func, ...) \
2135 switch (ISL_DEV_GEN(dev)) { \
2137 /* G45 surface state is the same as gen5 */ \
2138 if (ISL_DEV_IS_G4X(dev)) { \
2139 isl_gen5_##func(__VA_ARGS__); \
2141 isl_gen4_##func(__VA_ARGS__); \
2145 isl_gen5_##func(__VA_ARGS__); \
2148 isl_gen6_##func(__VA_ARGS__); \
2151 if (ISL_DEV_IS_HASWELL(dev)) { \
2152 isl_gen75_##func(__VA_ARGS__); \
2154 isl_gen7_##func(__VA_ARGS__); \
2158 isl_gen8_##func(__VA_ARGS__); \
2161 isl_gen9_##func(__VA_ARGS__); \
2164 isl_gen10_##func(__VA_ARGS__); \
2167 isl_gen11_##func(__VA_ARGS__); \
2170 isl_gen12_##func(__VA_ARGS__); \
2173 assert(!"Unknown hardware generation"); \
2177 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
2178 const struct isl_surf_fill_state_info
*restrict info
)
2181 isl_surf_usage_flags_t _base_usage
=
2182 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
2183 ISL_SURF_USAGE_TEXTURE_BIT
|
2184 ISL_SURF_USAGE_STORAGE_BIT
);
2185 /* They may only specify one of the above bits at a time */
2186 assert(__builtin_popcount(_base_usage
) == 1);
2187 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
2188 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
2191 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
2192 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2193 info
->surf
->logical_level0_px
.depth
);
2195 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2196 info
->surf
->logical_level0_px
.array_len
);
2199 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
2203 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
2204 const struct isl_buffer_fill_state_info
*restrict info
)
2206 isl_genX_call(dev
, buffer_fill_state_s
, dev
, state
, info
);
2210 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
2211 struct isl_extent3d size
)
2213 isl_genX_call(dev
, null_fill_state
, state
, size
);
2217 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
2218 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
2220 if (info
->depth_surf
&& info
->stencil_surf
) {
2221 if (!dev
->info
->has_hiz_and_separate_stencil
) {
2222 assert(info
->depth_surf
== info
->stencil_surf
);
2223 assert(info
->depth_address
== info
->stencil_address
);
2225 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
2228 if (info
->depth_surf
) {
2229 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
2230 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
2231 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2232 info
->depth_surf
->logical_level0_px
.depth
);
2234 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2235 info
->depth_surf
->logical_level0_px
.array_len
);
2239 if (info
->stencil_surf
) {
2240 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
2241 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
2242 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2243 info
->stencil_surf
->logical_level0_px
.depth
);
2245 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2246 info
->stencil_surf
->logical_level0_px
.array_len
);
2250 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
2254 * A variant of isl_surf_get_image_offset_sa() specific to
2255 * ISL_DIM_LAYOUT_GEN4_2D.
2258 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
2259 uint32_t level
, uint32_t logical_array_layer
,
2260 uint32_t *x_offset_sa
,
2261 uint32_t *y_offset_sa
)
2263 assert(level
< surf
->levels
);
2264 if (surf
->dim
== ISL_SURF_DIM_3D
)
2265 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2267 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2269 const struct isl_extent3d image_align_sa
=
2270 isl_surf_get_image_alignment_sa(surf
);
2272 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2273 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2275 const uint32_t phys_layer
= logical_array_layer
*
2276 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2279 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2281 for (uint32_t l
= 0; l
< level
; ++l
) {
2283 uint32_t W
= isl_minify(W0
, l
);
2284 x
+= isl_align_npot(W
, image_align_sa
.w
);
2286 uint32_t H
= isl_minify(H0
, l
);
2287 y
+= isl_align_npot(H
, image_align_sa
.h
);
2296 * A variant of isl_surf_get_image_offset_sa() specific to
2297 * ISL_DIM_LAYOUT_GEN4_3D.
2300 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2301 uint32_t level
, uint32_t logical_z_offset_px
,
2302 uint32_t *x_offset_sa
,
2303 uint32_t *y_offset_sa
)
2305 assert(level
< surf
->levels
);
2306 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2307 assert(surf
->phys_level0_sa
.array_len
== 1);
2308 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2310 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2311 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2312 assert(surf
->phys_level0_sa
.array_len
== 6);
2313 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2316 const struct isl_extent3d image_align_sa
=
2317 isl_surf_get_image_alignment_sa(surf
);
2319 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2320 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2321 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2322 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2327 for (uint32_t l
= 0; l
< level
; ++l
) {
2328 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2329 const uint32_t level_d
=
2330 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2332 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2334 y
+= level_h
* max_layers_vert
;
2337 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2338 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2339 const uint32_t level_d
=
2340 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2343 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2345 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2346 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2353 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2355 uint32_t logical_array_layer
,
2356 uint32_t *x_offset_sa
,
2357 uint32_t *y_offset_sa
)
2359 assert(level
< surf
->levels
);
2360 assert(surf
->logical_level0_px
.depth
== 1);
2361 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2363 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2365 const struct isl_extent3d image_align_sa
=
2366 isl_surf_get_image_alignment_sa(surf
);
2368 struct isl_tile_info tile_info
;
2369 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2370 const struct isl_extent2d tile_extent_sa
= {
2371 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2372 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2374 /* Tile size is a multiple of image alignment */
2375 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2376 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2378 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2379 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2381 /* Each image has the same height as LOD0 because the hardware thinks
2382 * everything is LOD0
2384 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2386 /* Quick sanity check for consistency */
2387 if (surf
->phys_level0_sa
.array_len
> 1)
2388 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2390 uint32_t x
= 0, y
= 0;
2391 for (uint32_t l
= 0; l
< level
; ++l
) {
2392 const uint32_t W
= isl_minify(W0
, l
);
2394 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2395 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2405 y
+= H
* logical_array_layer
;
2412 * A variant of isl_surf_get_image_offset_sa() specific to
2413 * ISL_DIM_LAYOUT_GEN9_1D.
2416 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2417 uint32_t level
, uint32_t layer
,
2418 uint32_t *x_offset_sa
,
2419 uint32_t *y_offset_sa
)
2421 assert(level
< surf
->levels
);
2422 assert(layer
< surf
->phys_level0_sa
.array_len
);
2423 assert(surf
->phys_level0_sa
.height
== 1);
2424 assert(surf
->phys_level0_sa
.depth
== 1);
2425 assert(surf
->samples
== 1);
2427 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2428 const struct isl_extent3d image_align_sa
=
2429 isl_surf_get_image_alignment_sa(surf
);
2433 for (uint32_t l
= 0; l
< level
; ++l
) {
2434 uint32_t W
= isl_minify(W0
, l
);
2435 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2441 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2445 * Calculate the offset, in units of surface samples, to a subimage in the
2448 * @invariant level < surface levels
2449 * @invariant logical_array_layer < logical array length of surface
2450 * @invariant logical_z_offset_px < logical depth of surface at level
2453 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2455 uint32_t logical_array_layer
,
2456 uint32_t logical_z_offset_px
,
2457 uint32_t *x_offset_sa
,
2458 uint32_t *y_offset_sa
)
2460 assert(level
< surf
->levels
);
2461 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2462 assert(logical_z_offset_px
2463 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2465 switch (surf
->dim_layout
) {
2466 case ISL_DIM_LAYOUT_GEN9_1D
:
2467 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2468 x_offset_sa
, y_offset_sa
);
2470 case ISL_DIM_LAYOUT_GEN4_2D
:
2471 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2472 + logical_z_offset_px
,
2473 x_offset_sa
, y_offset_sa
);
2475 case ISL_DIM_LAYOUT_GEN4_3D
:
2476 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2477 logical_z_offset_px
,
2478 x_offset_sa
, y_offset_sa
);
2480 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2481 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2482 logical_z_offset_px
,
2483 x_offset_sa
, y_offset_sa
);
2487 unreachable("not reached");
2492 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2494 uint32_t logical_array_layer
,
2495 uint32_t logical_z_offset_px
,
2496 uint32_t *x_offset_el
,
2497 uint32_t *y_offset_el
)
2499 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2501 assert(level
< surf
->levels
);
2502 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2503 assert(logical_z_offset_px
2504 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2506 uint32_t x_offset_sa
, y_offset_sa
;
2507 isl_surf_get_image_offset_sa(surf
, level
,
2508 logical_array_layer
,
2509 logical_z_offset_px
,
2513 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2514 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2518 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2520 uint32_t logical_array_layer
,
2521 uint32_t logical_z_offset_px
,
2523 uint32_t *x_offset_sa
,
2524 uint32_t *y_offset_sa
)
2526 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2528 uint32_t total_x_offset_el
, total_y_offset_el
;
2529 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2530 logical_z_offset_px
,
2532 &total_y_offset_el
);
2534 uint32_t x_offset_el
, y_offset_el
;
2535 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2544 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2546 assert(x_offset_el
== 0);
2550 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2552 assert(y_offset_el
== 0);
2557 isl_surf_get_image_range_B_tile(const struct isl_surf
*surf
,
2559 uint32_t logical_array_layer
,
2560 uint32_t logical_z_offset_px
,
2561 uint32_t *start_tile_B
,
2562 uint32_t *end_tile_B
)
2564 uint32_t start_x_offset_el
, start_y_offset_el
;
2565 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2566 logical_z_offset_px
,
2568 &start_y_offset_el
);
2570 /* Compute the size of the subimage in surface elements */
2571 const uint32_t subimage_w_sa
= isl_minify(surf
->phys_level0_sa
.w
, level
);
2572 const uint32_t subimage_h_sa
= isl_minify(surf
->phys_level0_sa
.h
, level
);
2573 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2574 const uint32_t subimage_w_el
= isl_align_div_npot(subimage_w_sa
, fmtl
->bw
);
2575 const uint32_t subimage_h_el
= isl_align_div_npot(subimage_h_sa
, fmtl
->bh
);
2577 /* Find the last pixel */
2578 uint32_t end_x_offset_el
= start_x_offset_el
+ subimage_w_el
- 1;
2579 uint32_t end_y_offset_el
= start_y_offset_el
+ subimage_h_el
- 1;
2581 UNUSED
uint32_t x_offset_el
, y_offset_el
;
2582 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2590 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2598 /* We want the range we return to be exclusive but the tile containing the
2599 * last pixel (what we just calculated) is inclusive. Add one.
2603 assert(*end_tile_B
<= surf
->size_B
);
2607 isl_surf_get_image_surf(const struct isl_device
*dev
,
2608 const struct isl_surf
*surf
,
2610 uint32_t logical_array_layer
,
2611 uint32_t logical_z_offset_px
,
2612 struct isl_surf
*image_surf
,
2614 uint32_t *x_offset_sa
,
2615 uint32_t *y_offset_sa
)
2617 isl_surf_get_image_offset_B_tile_sa(surf
,
2619 logical_array_layer
,
2620 logical_z_offset_px
,
2625 /* Even for cube maps there will be only single face, therefore drop the
2626 * corresponding flag if present.
2628 const isl_surf_usage_flags_t usage
=
2629 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2632 ok
= isl_surf_init(dev
, image_surf
,
2633 .dim
= ISL_SURF_DIM_2D
,
2634 .format
= surf
->format
,
2635 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2636 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2640 .samples
= surf
->samples
,
2641 .row_pitch_B
= surf
->row_pitch_B
,
2643 .tiling_flags
= (1 << surf
->tiling
));
2648 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2650 uint32_t row_pitch_B
,
2651 uint32_t total_x_offset_el
,
2652 uint32_t total_y_offset_el
,
2653 uint32_t *base_address_offset
,
2654 uint32_t *x_offset_el
,
2655 uint32_t *y_offset_el
)
2657 if (tiling
== ISL_TILING_LINEAR
) {
2658 assert(bpb
% 8 == 0);
2659 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2660 total_x_offset_el
* (bpb
/ 8);
2666 struct isl_tile_info tile_info
;
2667 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2669 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2671 /* For non-power-of-two formats, we need the address to be both tile and
2672 * element-aligned. The easiest way to achieve this is to work with a tile
2673 * that is three times as wide as the regular tile.
2675 * The tile info returned by get_tile_info has a logical size that is an
2676 * integer number of tile_info.format_bpb size elements. To scale the
2677 * tile, we scale up the physical width and then treat the logical tile
2678 * size as if it has bpb size elements.
2680 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2681 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2683 /* Compute the offset into the tile */
2684 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2685 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2687 /* Compute the offset of the tile in units of whole tiles */
2688 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2689 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2691 *base_address_offset
=
2692 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2693 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2697 isl_surf_get_depth_format(const struct isl_device
*dev
,
2698 const struct isl_surf
*surf
)
2700 /* Support for separate stencil buffers began in gen5. Support for
2701 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2702 * those that supported separate and interleaved stencil, were gen5 and
2705 * For a list of all available formats, see the Sandybridge PRM >> Volume
2706 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2710 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2712 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2715 assert(ISL_DEV_GEN(dev
) < 7);
2717 switch (surf
->format
) {
2719 unreachable("bad isl depth format");
2720 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2721 assert(ISL_DEV_GEN(dev
) < 7);
2722 return 0; /* D32_FLOAT_S8X24_UINT */
2723 case ISL_FORMAT_R32_FLOAT
:
2724 assert(!has_stencil
);
2725 return 1; /* D32_FLOAT */
2726 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2728 assert(ISL_DEV_GEN(dev
) < 7);
2729 return 2; /* D24_UNORM_S8_UINT */
2731 assert(ISL_DEV_GEN(dev
) >= 5);
2732 return 3; /* D24_UNORM_X8_UINT */
2734 case ISL_FORMAT_R16_UNORM
:
2735 assert(!has_stencil
);
2736 return 5; /* D16_UNORM */
2741 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2742 struct isl_swizzle swizzle
)
2744 if (devinfo
->is_haswell
) {
2745 /* From the Haswell PRM,
2746 * RENDER_SURFACE_STATE::Shader Channel Select Red
2748 * "The Shader channel selects also define which shader channels are
2749 * written to which surface channel. If the Shader channel select is
2750 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2751 * shader channel select is SCS_RED it is written to the surface red
2752 * channel and so on. If more than one shader channel select is set
2753 * to the same surface channel only the first shader channel in RGBA
2754 * order will be written."
2757 } else if (devinfo
->gen
<= 7) {
2758 /* Ivy Bridge and early doesn't have any swizzling */
2759 return isl_swizzle_is_identity(swizzle
);
2761 /* From the Sky Lake PRM Vol. 2d,
2762 * RENDER_SURFACE_STATE::Shader Channel Select Red
2764 * "For Render Target, Red, Green and Blue Shader Channel Selects
2765 * MUST be such that only valid components can be swapped i.e. only
2766 * change the order of components in the pixel. Any other values for
2767 * these Shader Channel Select fields are not valid for Render
2768 * Targets. This also means that there MUST not be multiple shader
2769 * channels mapped to the same RT channel."
2771 * From the Sky Lake PRM Vol. 2d,
2772 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2774 * "For Render Target, this field MUST be programmed to
2775 * value = SCS_ALPHA."
2777 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2778 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2779 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2780 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2781 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2782 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2783 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2784 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2785 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2786 swizzle
.r
!= swizzle
.g
&&
2787 swizzle
.r
!= swizzle
.b
&&
2788 swizzle
.g
!= swizzle
.b
&&
2789 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2793 static enum isl_channel_select
2794 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2797 case ISL_CHANNEL_SELECT_ZERO
:
2798 case ISL_CHANNEL_SELECT_ONE
:
2800 case ISL_CHANNEL_SELECT_RED
:
2802 case ISL_CHANNEL_SELECT_GREEN
:
2804 case ISL_CHANNEL_SELECT_BLUE
:
2806 case ISL_CHANNEL_SELECT_ALPHA
:
2809 unreachable("Invalid swizzle component");
2814 * Returns the single swizzle that is equivalent to applying the two given
2815 * swizzles in sequence.
2818 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2820 return (struct isl_swizzle
) {
2821 .r
= swizzle_select(first
.r
, second
),
2822 .g
= swizzle_select(first
.g
, second
),
2823 .b
= swizzle_select(first
.b
, second
),
2824 .a
= swizzle_select(first
.a
, second
),
2829 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2832 isl_swizzle_invert(struct isl_swizzle swizzle
)
2834 /* Default to zero for channels which do not show up in the swizzle */
2835 enum isl_channel_select chans
[4] = {
2836 ISL_CHANNEL_SELECT_ZERO
,
2837 ISL_CHANNEL_SELECT_ZERO
,
2838 ISL_CHANNEL_SELECT_ZERO
,
2839 ISL_CHANNEL_SELECT_ZERO
,
2842 /* We go in ABGR order so that, if there are any duplicates, the first one
2843 * is taken if you look at it in RGBA order. This is what Haswell hardware
2844 * does for render target swizzles.
2846 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2847 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2848 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2849 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2850 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2851 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2852 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2853 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2855 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };
2859 isl_format_get_aux_map_encoding(enum isl_format format
)
2862 case ISL_FORMAT_R32G32B32A32_FLOAT
: return 0x11;
2863 case ISL_FORMAT_R32G32B32X32_FLOAT
: return 0x11;
2864 case ISL_FORMAT_R32G32B32A32_SINT
: return 0x12;
2865 case ISL_FORMAT_R32G32B32A32_UINT
: return 0x13;
2866 case ISL_FORMAT_R16G16B16A16_UNORM
: return 0x14;
2867 case ISL_FORMAT_R16G16B16A16_SNORM
: return 0x15;
2868 case ISL_FORMAT_R16G16B16A16_SINT
: return 0x16;
2869 case ISL_FORMAT_R16G16B16A16_UINT
: return 0x17;
2870 case ISL_FORMAT_R16G16B16A16_FLOAT
: return 0x10;
2871 case ISL_FORMAT_R16G16B16X16_FLOAT
: return 0x10;
2872 case ISL_FORMAT_R32G32_FLOAT
: return 0x11;
2873 case ISL_FORMAT_R32G32_SINT
: return 0x12;
2874 case ISL_FORMAT_R32G32_UINT
: return 0x13;
2875 case ISL_FORMAT_B8G8R8A8_UNORM
: return 0xA;
2876 case ISL_FORMAT_B8G8R8X8_UNORM
: return 0xA;
2877 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
: return 0xA;
2878 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: return 0xA;
2879 case ISL_FORMAT_R10G10B10A2_UNORM
: return 0x18;
2880 case ISL_FORMAT_R10G10B10A2_UNORM_SRGB
: return 0x18;
2881 case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM
: return 0x19;
2882 case ISL_FORMAT_R10G10B10A2_UINT
: return 0x1A;
2883 case ISL_FORMAT_R8G8B8A8_UNORM
: return 0xA;
2884 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
: return 0xA;
2885 case ISL_FORMAT_R8G8B8A8_SNORM
: return 0x1B;
2886 case ISL_FORMAT_R8G8B8A8_SINT
: return 0x1C;
2887 case ISL_FORMAT_R8G8B8A8_UINT
: return 0x1D;
2888 case ISL_FORMAT_R16G16_UNORM
: return 0x14;
2889 case ISL_FORMAT_R16G16_SNORM
: return 0x15;
2890 case ISL_FORMAT_R16G16_SINT
: return 0x16;
2891 case ISL_FORMAT_R16G16_UINT
: return 0x17;
2892 case ISL_FORMAT_R16G16_FLOAT
: return 0x10;
2893 case ISL_FORMAT_B10G10R10A2_UNORM
: return 0x18;
2894 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
: return 0x18;
2895 case ISL_FORMAT_R11G11B10_FLOAT
: return 0x1E;
2896 case ISL_FORMAT_R32_SINT
: return 0x12;
2897 case ISL_FORMAT_R32_UINT
: return 0x13;
2898 case ISL_FORMAT_R32_FLOAT
: return 0x11;
2899 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
: return 0x11;
2900 case ISL_FORMAT_B5G6R5_UNORM
: return 0xA;
2901 case ISL_FORMAT_B5G6R5_UNORM_SRGB
: return 0xA;
2902 case ISL_FORMAT_B5G5R5A1_UNORM
: return 0xA;
2903 case ISL_FORMAT_B5G5R5A1_UNORM_SRGB
: return 0xA;
2904 case ISL_FORMAT_B4G4R4A4_UNORM
: return 0xA;
2905 case ISL_FORMAT_B4G4R4A4_UNORM_SRGB
: return 0xA;
2906 case ISL_FORMAT_R8G8_UNORM
: return 0xA;
2907 case ISL_FORMAT_R8G8_SNORM
: return 0x1B;
2908 case ISL_FORMAT_R8G8_SINT
: return 0x1C;
2909 case ISL_FORMAT_R8G8_UINT
: return 0x1D;
2910 case ISL_FORMAT_R16_UNORM
: return 0x14;
2911 case ISL_FORMAT_R16_SNORM
: return 0x15;
2912 case ISL_FORMAT_R16_SINT
: return 0x16;
2913 case ISL_FORMAT_R16_UINT
: return 0x17;
2914 case ISL_FORMAT_R16_FLOAT
: return 0x10;
2915 case ISL_FORMAT_B5G5R5X1_UNORM
: return 0xA;
2916 case ISL_FORMAT_B5G5R5X1_UNORM_SRGB
: return 0xA;
2917 case ISL_FORMAT_A1B5G5R5_UNORM
: return 0xA;
2918 case ISL_FORMAT_A4B4G4R4_UNORM
: return 0xA;
2919 case ISL_FORMAT_R8_UNORM
: return 0xA;
2920 case ISL_FORMAT_R8_SNORM
: return 0x1B;
2921 case ISL_FORMAT_R8_SINT
: return 0x1C;
2922 case ISL_FORMAT_R8_UINT
: return 0x1D;
2923 case ISL_FORMAT_A8_UNORM
: return 0xA;
2925 unreachable("Unsupported aux-map format!");