2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
36 #include "isl_gen12.h"
40 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
41 uint32_t yt1
, uint32_t yt2
,
42 char *dst
, const char *src
,
43 uint32_t dst_pitch
, int32_t src_pitch
,
45 enum isl_tiling tiling
,
46 isl_memcpy_type copy_type
)
49 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
50 _isl_memcpy_linear_to_tiled_sse41(
51 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
57 _isl_memcpy_linear_to_tiled(
58 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
63 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
64 uint32_t yt1
, uint32_t yt2
,
65 char *dst
, const char *src
,
66 int32_t dst_pitch
, uint32_t src_pitch
,
68 enum isl_tiling tiling
,
69 isl_memcpy_type copy_type
)
72 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
73 _isl_memcpy_tiled_to_linear_sse41(
74 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
80 _isl_memcpy_tiled_to_linear(
81 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
85 void PRINTFLIKE(3, 4) UNUSED
86 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
92 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
95 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
99 isl_device_init(struct isl_device
*dev
,
100 const struct gen_device_info
*info
,
101 bool has_bit6_swizzling
)
103 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
104 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
107 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
108 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
110 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
111 * device properties at buildtime. Verify that the macros with the device
112 * properties chosen during runtime.
114 ISL_DEV_GEN_SANITIZE(dev
);
115 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
117 /* Did we break hiz or stencil? */
118 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
119 assert(info
->has_hiz_and_separate_stencil
);
120 if (info
->must_use_separate_stencil
)
121 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
123 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
124 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
126 dev
->ss
.clear_color_state_size
=
127 isl_align(CLEAR_COLOR_length(info
) * 4, 64);
128 dev
->ss
.clear_color_state_offset
=
129 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
131 dev
->ss
.clear_value_size
=
132 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
133 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
134 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
135 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
137 dev
->ss
.clear_value_offset
=
138 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
140 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
141 dev
->ss
.addr_offset
=
142 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
144 /* The "Auxiliary Surface Base Address" field starts a bit higher up
145 * because the bottom 12 bits are used for other things. Round down to
146 * the nearest dword before.
148 dev
->ss
.aux_addr_offset
=
149 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
151 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
152 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
153 dev
->ds
.depth_offset
=
154 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
156 if (dev
->use_separate_stencil
) {
157 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
158 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
159 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
161 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
162 dev
->ds
.stencil_offset
=
163 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
164 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
166 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
168 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
169 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
170 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
172 dev
->ds
.stencil_offset
= 0;
173 dev
->ds
.hiz_offset
= 0;
178 * @brief Query the set of multisamples supported by the device.
180 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
183 isl_sample_count_mask_t ATTRIBUTE_CONST
184 isl_device_get_sample_counts(struct isl_device
*dev
)
186 if (ISL_DEV_GEN(dev
) >= 9) {
187 return ISL_SAMPLE_COUNT_1_BIT
|
188 ISL_SAMPLE_COUNT_2_BIT
|
189 ISL_SAMPLE_COUNT_4_BIT
|
190 ISL_SAMPLE_COUNT_8_BIT
|
191 ISL_SAMPLE_COUNT_16_BIT
;
192 } else if (ISL_DEV_GEN(dev
) >= 8) {
193 return ISL_SAMPLE_COUNT_1_BIT
|
194 ISL_SAMPLE_COUNT_2_BIT
|
195 ISL_SAMPLE_COUNT_4_BIT
|
196 ISL_SAMPLE_COUNT_8_BIT
;
197 } else if (ISL_DEV_GEN(dev
) >= 7) {
198 return ISL_SAMPLE_COUNT_1_BIT
|
199 ISL_SAMPLE_COUNT_4_BIT
|
200 ISL_SAMPLE_COUNT_8_BIT
;
201 } else if (ISL_DEV_GEN(dev
) >= 6) {
202 return ISL_SAMPLE_COUNT_1_BIT
|
203 ISL_SAMPLE_COUNT_4_BIT
;
205 return ISL_SAMPLE_COUNT_1_BIT
;
210 * @param[out] info is written only on success
213 isl_tiling_get_info(enum isl_tiling tiling
,
215 struct isl_tile_info
*tile_info
)
217 const uint32_t bs
= format_bpb
/ 8;
218 struct isl_extent2d logical_el
, phys_B
;
220 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
221 /* It is possible to have non-power-of-two formats in a tiled buffer.
222 * The easiest way to handle this is to treat the tile as if it is three
223 * times as wide. This way no pixel will ever cross a tile boundary.
224 * This really only works on legacy X and Y tiling formats.
226 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
227 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
228 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
233 case ISL_TILING_LINEAR
:
235 logical_el
= isl_extent2d(1, 1);
236 phys_B
= isl_extent2d(bs
, 1);
241 logical_el
= isl_extent2d(512 / bs
, 8);
242 phys_B
= isl_extent2d(512, 8);
247 logical_el
= isl_extent2d(128 / bs
, 32);
248 phys_B
= isl_extent2d(128, 32);
253 logical_el
= isl_extent2d(64, 64);
254 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
256 * "If the surface is a stencil buffer (and thus has Tile Mode set
257 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
258 * computed based on width, as the stencil buffer is stored with two
261 * This, together with the fact that stencil buffers are referred to as
262 * being Y-tiled in the PRMs for older hardware implies that the
263 * physical size of a W-tile is actually the same as for a Y-tile.
265 phys_B
= isl_extent2d(128, 32);
269 case ISL_TILING_Ys
: {
270 bool is_Ys
= tiling
== ISL_TILING_Ys
;
273 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
274 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
276 logical_el
= isl_extent2d(width
/ bs
, height
);
277 phys_B
= isl_extent2d(width
, height
);
282 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
283 * 128bpb format. The tiling has the same physical dimensions as
284 * Y-tiling but actually has two HiZ columns per Y-tiled column.
287 logical_el
= isl_extent2d(16, 16);
288 phys_B
= isl_extent2d(128, 32);
292 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
293 * have a block size of 1 or 2 bits per block and each CCS element
294 * corresponds to one cache-line pair in the main surface. From the Sky
295 * Lake PRM Vol. 12 in the section on planes:
297 * "The Color Control Surface (CCS) contains the compression status
298 * of the cache-line pairs. The compression state of the cache-line
299 * pair is specified by 2 bits in the CCS. Each CCS cache-line
300 * represents an area on the main surface of 16x16 sets of 128 byte
301 * Y-tiled cache-line-pairs. CCS is always Y tiled."
303 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
304 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
305 * that yields total tile area of 128x128 cache-line pairs or CCS
306 * elements. On older hardware, each CCS element is 1 bit and the tile
307 * is 128x256 elements.
309 assert(format_bpb
== 1 || format_bpb
== 2);
310 logical_el
= isl_extent2d(128, 256 / format_bpb
);
311 phys_B
= isl_extent2d(128, 32);
315 unreachable("not reached");
318 *tile_info
= (struct isl_tile_info
) {
320 .format_bpb
= format_bpb
,
321 .logical_extent_el
= logical_el
,
322 .phys_extent_B
= phys_B
,
327 isl_color_value_is_zero(union isl_color_value value
,
328 enum isl_format format
)
330 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
332 #define RETURN_FALSE_IF_NOT_0(c, i) \
333 if (fmtl->channels.c.bits && value.u32[i] != 0) \
336 RETURN_FALSE_IF_NOT_0(r
, 0);
337 RETURN_FALSE_IF_NOT_0(g
, 1);
338 RETURN_FALSE_IF_NOT_0(b
, 2);
339 RETURN_FALSE_IF_NOT_0(a
, 3);
341 #undef RETURN_FALSE_IF_NOT_0
347 isl_color_value_is_zero_one(union isl_color_value value
,
348 enum isl_format format
)
350 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
352 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
353 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
356 if (isl_format_has_int_channel(format
)) {
357 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
358 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
359 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
360 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
362 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
363 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
364 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
365 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
368 #undef RETURN_FALSE_IF_NOT_0_1
374 * @param[out] tiling is set only on success
377 isl_surf_choose_tiling(const struct isl_device
*dev
,
378 const struct isl_surf_init_info
*restrict info
,
379 enum isl_tiling
*tiling
)
381 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
383 /* HiZ surfaces always use the HiZ tiling */
384 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
385 assert(info
->format
== ISL_FORMAT_HIZ
);
386 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
387 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
391 /* CCS surfaces always use the CCS tiling */
392 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
393 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
394 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
395 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
399 if (ISL_DEV_GEN(dev
) >= 6) {
400 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
402 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
405 #define CHOOSE(__tiling) \
407 if (tiling_flags & (1u << (__tiling))) { \
408 *tiling = (__tiling); \
413 /* Of the tiling modes remaining, choose the one that offers the best
417 if (info
->dim
== ISL_SURF_DIM_1D
) {
418 /* Prefer linear for 1D surfaces because they do not benefit from
419 * tiling. To the contrary, tiling leads to wasted memory and poor
420 * memory locality due to the swizzling and alignment restrictions
421 * required in tiled surfaces.
423 CHOOSE(ISL_TILING_LINEAR
);
426 CHOOSE(ISL_TILING_Ys
);
427 CHOOSE(ISL_TILING_Yf
);
428 CHOOSE(ISL_TILING_Y0
);
429 CHOOSE(ISL_TILING_X
);
430 CHOOSE(ISL_TILING_W
);
431 CHOOSE(ISL_TILING_LINEAR
);
435 /* No tiling mode accomodates the inputs. */
440 isl_choose_msaa_layout(const struct isl_device
*dev
,
441 const struct isl_surf_init_info
*info
,
442 enum isl_tiling tiling
,
443 enum isl_msaa_layout
*msaa_layout
)
445 if (ISL_DEV_GEN(dev
) >= 8) {
446 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
447 } else if (ISL_DEV_GEN(dev
) >= 7) {
448 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
449 } else if (ISL_DEV_GEN(dev
) >= 6) {
450 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
452 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
457 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
459 assert(isl_is_pow2(samples
));
461 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
464 * If the surface is multisampled and it is a depth or stencil surface
465 * or Multisampled Surface StorageFormat in SURFACE_STATE is
466 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
469 return (struct isl_extent2d
) {
470 .width
= 1 << ((ffs(samples
) - 0) / 2),
471 .height
= 1 << ((ffs(samples
) - 1) / 2),
476 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
477 uint32_t *width
, uint32_t *height
)
479 const struct isl_extent2d px_size_sa
=
480 isl_get_interleaved_msaa_px_size_sa(samples
);
483 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
485 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
488 static enum isl_array_pitch_span
489 isl_choose_array_pitch_span(const struct isl_device
*dev
,
490 const struct isl_surf_init_info
*restrict info
,
491 enum isl_dim_layout dim_layout
,
492 const struct isl_extent4d
*phys_level0_sa
)
494 switch (dim_layout
) {
495 case ISL_DIM_LAYOUT_GEN9_1D
:
496 case ISL_DIM_LAYOUT_GEN4_2D
:
497 if (ISL_DEV_GEN(dev
) >= 8) {
498 /* QPitch becomes programmable in Broadwell. So choose the
499 * most compact QPitch possible in order to conserve memory.
501 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
502 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
504 * - Software must ensure that this field is set to a value
505 * sufficiently large such that the array slices in the surface
506 * do not overlap. Refer to the Memory Data Formats section for
507 * information on how surfaces are stored in memory.
509 * - This field specifies the distance in rows between array
510 * slices. It is used only in the following cases:
512 * - Surface Array is enabled OR
513 * - Number of Mulitsamples is not NUMSAMPLES_1 and
514 * Multisampled Surface Storage Format set to MSFMT_MSS OR
515 * - Surface Type is SURFTYPE_CUBE
517 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
518 } else if (ISL_DEV_GEN(dev
) >= 7) {
519 /* Note that Ivybridge introduces
520 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
521 * driver more control over the QPitch.
524 if (phys_level0_sa
->array_len
== 1) {
525 /* The hardware will never use the QPitch. So choose the most
526 * compact QPitch possible in order to conserve memory.
528 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
531 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
532 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
533 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
534 * Section 6.18.4.7: Surface Arrays (p112):
536 * If Surface Array Spacing is set to ARYSPC_FULL (note that
537 * the depth buffer and stencil buffer have an implied value of
540 return ISL_ARRAY_PITCH_SPAN_FULL
;
543 if (info
->levels
== 1) {
544 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
547 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
550 return ISL_ARRAY_PITCH_SPAN_FULL
;
551 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
552 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
553 isl_surf_usage_is_stencil(info
->usage
)) {
554 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
555 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
557 * The separate stencil buffer does not support mip mapping, thus
558 * the storage for LODs other than LOD 0 is not needed.
560 assert(info
->levels
== 1);
561 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
563 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
564 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
565 isl_surf_usage_is_stencil(info
->usage
)) {
566 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
567 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
569 * The separate stencil buffer does not support mip mapping,
570 * thus the storage for LODs other than LOD 0 is not needed.
572 assert(info
->levels
== 1);
573 assert(phys_level0_sa
->array_len
== 1);
574 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
577 if (phys_level0_sa
->array_len
== 1) {
578 /* The hardware will never use the QPitch. So choose the most
579 * compact QPitch possible in order to conserve memory.
581 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
584 return ISL_ARRAY_PITCH_SPAN_FULL
;
587 case ISL_DIM_LAYOUT_GEN4_3D
:
588 /* The hardware will never use the QPitch. So choose the most
589 * compact QPitch possible in order to conserve memory.
591 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
593 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
594 /* Each array image in the gen6 stencil of HiZ surface is compact in the
595 * sense that every LOD is a compact array of the same size as LOD0.
597 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
600 unreachable("bad isl_dim_layout");
601 return ISL_ARRAY_PITCH_SPAN_FULL
;
605 isl_choose_image_alignment_el(const struct isl_device
*dev
,
606 const struct isl_surf_init_info
*restrict info
,
607 enum isl_tiling tiling
,
608 enum isl_dim_layout dim_layout
,
609 enum isl_msaa_layout msaa_layout
,
610 struct isl_extent3d
*image_align_el
)
612 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
613 if (fmtl
->txc
== ISL_TXC_MCS
) {
614 assert(tiling
== ISL_TILING_Y0
);
617 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
619 * Height, width, and layout of MCS buffer in this case must match with
620 * Render Target height, width, and layout. MCS buffer is tiledY.
622 * To avoid wasting memory, choose the smallest alignment possible:
623 * HALIGN_4 and VALIGN_4.
625 *image_align_el
= isl_extent3d(4, 4, 1);
627 } else if (info
->format
== ISL_FORMAT_HIZ
) {
628 assert(ISL_DEV_GEN(dev
) >= 6);
629 if (ISL_DEV_GEN(dev
) == 6) {
630 /* HiZ surfaces on Sandy Bridge are packed tightly. */
631 *image_align_el
= isl_extent3d(1, 1, 1);
633 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
634 * primary surface which works out to 2x2 HiZ elments.
636 *image_align_el
= isl_extent3d(2, 2, 1);
641 if (ISL_DEV_GEN(dev
) >= 12) {
642 isl_gen12_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
643 msaa_layout
, image_align_el
);
644 } else if (ISL_DEV_GEN(dev
) >= 9) {
645 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
646 msaa_layout
, image_align_el
);
647 } else if (ISL_DEV_GEN(dev
) >= 8) {
648 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
649 msaa_layout
, image_align_el
);
650 } else if (ISL_DEV_GEN(dev
) >= 7) {
651 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
652 msaa_layout
, image_align_el
);
653 } else if (ISL_DEV_GEN(dev
) >= 6) {
654 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
655 msaa_layout
, image_align_el
);
657 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
658 msaa_layout
, image_align_el
);
662 static enum isl_dim_layout
663 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
664 enum isl_surf_dim logical_dim
,
665 enum isl_tiling tiling
,
666 isl_surf_usage_flags_t usage
)
668 /* Sandy bridge needs a special layout for HiZ and stencil. */
669 if (ISL_DEV_GEN(dev
) == 6 &&
670 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
671 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
673 if (ISL_DEV_GEN(dev
) >= 9) {
674 switch (logical_dim
) {
675 case ISL_SURF_DIM_1D
:
676 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
678 * One-dimensional surfaces use a tiling mode of linear.
679 * Technically, they are not tiled resources, but the Tiled
680 * Resource Mode field in RENDER_SURFACE_STATE is still used to
681 * indicate the alignment requirements for this linear surface
682 * (See 1D Alignment requirements for how 4K and 64KB Tiled
683 * Resource Modes impact alignment). Alternatively, a 1D surface
684 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
687 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
688 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
690 if (tiling
== ISL_TILING_LINEAR
)
691 return ISL_DIM_LAYOUT_GEN9_1D
;
693 return ISL_DIM_LAYOUT_GEN4_2D
;
694 case ISL_SURF_DIM_2D
:
695 case ISL_SURF_DIM_3D
:
696 return ISL_DIM_LAYOUT_GEN4_2D
;
699 switch (logical_dim
) {
700 case ISL_SURF_DIM_1D
:
701 case ISL_SURF_DIM_2D
:
702 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
704 * The cube face textures are stored in the same way as 3D surfaces
705 * are stored (see section 6.17.5 for details). For cube surfaces,
706 * however, the depth is equal to the number of faces (always 6) and
707 * is not reduced for each MIP.
709 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
710 return ISL_DIM_LAYOUT_GEN4_3D
;
712 return ISL_DIM_LAYOUT_GEN4_2D
;
713 case ISL_SURF_DIM_3D
:
714 return ISL_DIM_LAYOUT_GEN4_3D
;
718 unreachable("bad isl_surf_dim");
719 return ISL_DIM_LAYOUT_GEN4_2D
;
723 * Calculate the physical extent of the surface's first level, in units of
727 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
728 const struct isl_surf_init_info
*restrict info
,
729 enum isl_dim_layout dim_layout
,
730 enum isl_tiling tiling
,
731 enum isl_msaa_layout msaa_layout
,
732 struct isl_extent4d
*phys_level0_sa
)
734 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
736 if (isl_format_is_yuv(info
->format
))
737 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
740 case ISL_SURF_DIM_1D
:
741 assert(info
->height
== 1);
742 assert(info
->depth
== 1);
743 assert(info
->samples
== 1);
745 switch (dim_layout
) {
746 case ISL_DIM_LAYOUT_GEN4_3D
:
747 unreachable("bad isl_dim_layout");
749 case ISL_DIM_LAYOUT_GEN9_1D
:
750 case ISL_DIM_LAYOUT_GEN4_2D
:
751 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
752 *phys_level0_sa
= (struct isl_extent4d
) {
756 .a
= info
->array_len
,
762 case ISL_SURF_DIM_2D
:
763 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
764 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
766 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
767 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
769 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
770 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
772 switch (msaa_layout
) {
773 case ISL_MSAA_LAYOUT_NONE
:
774 assert(info
->depth
== 1);
775 assert(info
->samples
== 1);
777 *phys_level0_sa
= (struct isl_extent4d
) {
781 .a
= info
->array_len
,
785 case ISL_MSAA_LAYOUT_ARRAY
:
786 assert(info
->depth
== 1);
787 assert(info
->levels
== 1);
788 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
789 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
791 *phys_level0_sa
= (struct isl_extent4d
) {
795 .a
= info
->array_len
* info
->samples
,
799 case ISL_MSAA_LAYOUT_INTERLEAVED
:
800 assert(info
->depth
== 1);
801 assert(info
->levels
== 1);
802 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
804 *phys_level0_sa
= (struct isl_extent4d
) {
808 .a
= info
->array_len
,
811 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
818 case ISL_SURF_DIM_3D
:
819 assert(info
->array_len
== 1);
820 assert(info
->samples
== 1);
823 isl_finishme("%s:%s: compression block with depth > 1",
827 switch (dim_layout
) {
828 case ISL_DIM_LAYOUT_GEN9_1D
:
829 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
830 unreachable("bad isl_dim_layout");
832 case ISL_DIM_LAYOUT_GEN4_2D
:
833 assert(ISL_DEV_GEN(dev
) >= 9);
835 *phys_level0_sa
= (struct isl_extent4d
) {
843 case ISL_DIM_LAYOUT_GEN4_3D
:
844 assert(ISL_DEV_GEN(dev
) < 9);
845 *phys_level0_sa
= (struct isl_extent4d
) {
858 * Calculate the pitch between physical array slices, in units of rows of
862 isl_calc_array_pitch_el_rows_gen4_2d(
863 const struct isl_device
*dev
,
864 const struct isl_surf_init_info
*restrict info
,
865 const struct isl_tile_info
*tile_info
,
866 const struct isl_extent3d
*image_align_sa
,
867 const struct isl_extent4d
*phys_level0_sa
,
868 enum isl_array_pitch_span array_pitch_span
,
869 const struct isl_extent2d
*phys_slice0_sa
)
871 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
872 uint32_t pitch_sa_rows
= 0;
874 switch (array_pitch_span
) {
875 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
876 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
878 case ISL_ARRAY_PITCH_SPAN_FULL
: {
879 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
880 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
881 * Surfaces >> Surface Arrays.
883 uint32_t H0_sa
= phys_level0_sa
->h
;
884 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
886 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
887 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
890 if (ISL_DEV_GEN(dev
) >= 7) {
891 /* The QPitch equation changed slightly in Ivybridge. */
897 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
899 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
900 (info
->height
% 4 == 1)) {
901 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
902 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
904 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
905 * the value calculated in the equation above , for every
906 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
908 * XXX(chadv): Is the errata natural corollary of the physical
909 * layout of interleaved samples?
914 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
919 assert(pitch_sa_rows
% fmtl
->bh
== 0);
920 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
922 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
924 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
926 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
927 * layout with these alignments in the RT space: Horizontal
928 * Alignment = 128 and Vertical Alignment = 64."
930 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
932 * "For non-multisampled render target's CCS auxiliary surface,
933 * QPitch must be computed with Horizontal Alignment = 128 and
934 * Surface Vertical Alignment = 256. These alignments are only for
935 * CCS buffer and not for associated render target."
937 * The first restriction is already handled by isl_choose_image_alignment_el
938 * but the second restriction, which is an extension of the first, only
939 * applies to qpitch and must be applied here.
941 assert(fmtl
->bh
== 4);
942 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
945 if (ISL_DEV_GEN(dev
) >= 9 &&
946 info
->dim
== ISL_SURF_DIM_3D
&&
947 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
948 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
950 * Tile Mode != Linear: This field must be set to an integer multiple
953 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
956 return pitch_el_rows
;
960 * A variant of isl_calc_phys_slice0_extent_sa() specific to
961 * ISL_DIM_LAYOUT_GEN4_2D.
964 isl_calc_phys_slice0_extent_sa_gen4_2d(
965 const struct isl_device
*dev
,
966 const struct isl_surf_init_info
*restrict info
,
967 enum isl_msaa_layout msaa_layout
,
968 const struct isl_extent3d
*image_align_sa
,
969 const struct isl_extent4d
*phys_level0_sa
,
970 struct isl_extent2d
*phys_slice0_sa
)
972 assert(phys_level0_sa
->depth
== 1);
974 if (info
->levels
== 1) {
975 /* Do not pad the surface to the image alignment.
977 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
978 * cycles on the below mipmap layout caluclations. Reducing the
979 * alignment here is safe because we later align the row pitch and array
980 * pitch to the tile boundary. It is safe even for
981 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
982 * to accomodate the interleaved samples.
984 * For linear surfaces, reducing the alignment here permits us to later
985 * choose an arbitrary, non-aligned row pitch. If the surface backs
986 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
987 * VkBufferImageCopy::bufferRowLength.
989 *phys_slice0_sa
= (struct isl_extent2d
) {
990 .w
= phys_level0_sa
->w
,
991 .h
= phys_level0_sa
->h
,
996 uint32_t slice_top_w
= 0;
997 uint32_t slice_bottom_w
= 0;
998 uint32_t slice_left_h
= 0;
999 uint32_t slice_right_h
= 0;
1001 uint32_t W0
= phys_level0_sa
->w
;
1002 uint32_t H0
= phys_level0_sa
->h
;
1004 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1005 uint32_t W
= isl_minify(W0
, l
);
1006 uint32_t H
= isl_minify(H0
, l
);
1008 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1009 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1015 } else if (l
== 1) {
1018 } else if (l
== 2) {
1019 slice_bottom_w
+= w
;
1026 *phys_slice0_sa
= (struct isl_extent2d
) {
1027 .w
= MAX(slice_top_w
, slice_bottom_w
),
1028 .h
= MAX(slice_left_h
, slice_right_h
),
1033 isl_calc_phys_total_extent_el_gen4_2d(
1034 const struct isl_device
*dev
,
1035 const struct isl_surf_init_info
*restrict info
,
1036 const struct isl_tile_info
*tile_info
,
1037 enum isl_msaa_layout msaa_layout
,
1038 const struct isl_extent3d
*image_align_sa
,
1039 const struct isl_extent4d
*phys_level0_sa
,
1040 enum isl_array_pitch_span array_pitch_span
,
1041 uint32_t *array_pitch_el_rows
,
1042 struct isl_extent2d
*total_extent_el
)
1044 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1046 struct isl_extent2d phys_slice0_sa
;
1047 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1048 image_align_sa
, phys_level0_sa
,
1050 *array_pitch_el_rows
=
1051 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1052 image_align_sa
, phys_level0_sa
,
1055 *total_extent_el
= (struct isl_extent2d
) {
1056 .w
= isl_align_div_npot(phys_slice0_sa
.w
, fmtl
->bw
),
1057 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1058 isl_align_div_npot(phys_slice0_sa
.h
, fmtl
->bh
),
1063 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1064 * ISL_DIM_LAYOUT_GEN4_3D.
1067 isl_calc_phys_total_extent_el_gen4_3d(
1068 const struct isl_device
*dev
,
1069 const struct isl_surf_init_info
*restrict info
,
1070 const struct isl_extent3d
*image_align_sa
,
1071 const struct isl_extent4d
*phys_level0_sa
,
1072 uint32_t *array_pitch_el_rows
,
1073 struct isl_extent2d
*phys_total_el
)
1075 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1077 assert(info
->samples
== 1);
1079 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1080 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1082 * The cube face textures are stored in the same way as 3D surfaces
1083 * are stored (see section 6.17.5 for details). For cube surfaces,
1084 * however, the depth is equal to the number of faces (always 6) and
1085 * is not reduced for each MIP.
1087 assert(ISL_DEV_GEN(dev
) == 4);
1088 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1089 assert(phys_level0_sa
->array_len
== 6);
1091 assert(phys_level0_sa
->array_len
== 1);
1094 uint32_t total_w
= 0;
1095 uint32_t total_h
= 0;
1097 uint32_t W0
= phys_level0_sa
->w
;
1098 uint32_t H0
= phys_level0_sa
->h
;
1099 uint32_t D0
= phys_level0_sa
->d
;
1100 uint32_t A0
= phys_level0_sa
->a
;
1102 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1103 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1104 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1105 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1107 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1108 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1110 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1111 total_h
+= level_h
* max_layers_vert
;
1114 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1115 * different number of horizontal and vertical layers. We have to set it
1116 * to something, so at least make it true for LOD0.
1118 *array_pitch_el_rows
=
1119 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1120 *phys_total_el
= (struct isl_extent2d
) {
1121 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1122 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1127 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1128 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1131 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1132 const struct isl_device
*dev
,
1133 const struct isl_surf_init_info
*restrict info
,
1134 const struct isl_tile_info
*tile_info
,
1135 const struct isl_extent3d
*image_align_sa
,
1136 const struct isl_extent4d
*phys_level0_sa
,
1137 uint32_t *array_pitch_el_rows
,
1138 struct isl_extent2d
*phys_total_el
)
1140 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1142 const struct isl_extent2d tile_extent_sa
= {
1143 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1144 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1146 /* Tile size is a multiple of image alignment */
1147 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1148 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1150 const uint32_t W0
= phys_level0_sa
->w
;
1151 const uint32_t H0
= phys_level0_sa
->h
;
1153 /* Each image has the same height as LOD0 because the hardware thinks
1154 * everything is LOD0
1156 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1158 uint32_t total_top_w
= 0;
1159 uint32_t total_bottom_w
= 0;
1160 uint32_t total_h
= 0;
1162 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1163 const uint32_t W
= isl_minify(W0
, l
);
1165 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1166 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1171 } else if (l
== 1) {
1175 total_bottom_w
+= w
;
1179 *array_pitch_el_rows
=
1180 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1181 *phys_total_el
= (struct isl_extent2d
) {
1182 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1183 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1188 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1189 * ISL_DIM_LAYOUT_GEN9_1D.
1192 isl_calc_phys_total_extent_el_gen9_1d(
1193 const struct isl_device
*dev
,
1194 const struct isl_surf_init_info
*restrict info
,
1195 const struct isl_extent3d
*image_align_sa
,
1196 const struct isl_extent4d
*phys_level0_sa
,
1197 uint32_t *array_pitch_el_rows
,
1198 struct isl_extent2d
*phys_total_el
)
1200 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1202 assert(phys_level0_sa
->height
== 1);
1203 assert(phys_level0_sa
->depth
== 1);
1204 assert(info
->samples
== 1);
1205 assert(image_align_sa
->w
>= fmtl
->bw
);
1207 uint32_t slice_w
= 0;
1208 const uint32_t W0
= phys_level0_sa
->w
;
1210 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1211 uint32_t W
= isl_minify(W0
, l
);
1212 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1217 *array_pitch_el_rows
= 1;
1218 *phys_total_el
= (struct isl_extent2d
) {
1219 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1220 .h
= phys_level0_sa
->array_len
,
1225 * Calculate the two-dimensional total physical extent of the surface, in
1226 * units of surface elements.
1229 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1230 const struct isl_surf_init_info
*restrict info
,
1231 const struct isl_tile_info
*tile_info
,
1232 enum isl_dim_layout dim_layout
,
1233 enum isl_msaa_layout msaa_layout
,
1234 const struct isl_extent3d
*image_align_sa
,
1235 const struct isl_extent4d
*phys_level0_sa
,
1236 enum isl_array_pitch_span array_pitch_span
,
1237 uint32_t *array_pitch_el_rows
,
1238 struct isl_extent2d
*total_extent_el
)
1240 switch (dim_layout
) {
1241 case ISL_DIM_LAYOUT_GEN9_1D
:
1242 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1243 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1244 image_align_sa
, phys_level0_sa
,
1245 array_pitch_el_rows
,
1248 case ISL_DIM_LAYOUT_GEN4_2D
:
1249 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1250 image_align_sa
, phys_level0_sa
,
1252 array_pitch_el_rows
,
1255 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1256 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1257 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1260 array_pitch_el_rows
,
1263 case ISL_DIM_LAYOUT_GEN4_3D
:
1264 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1265 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1266 image_align_sa
, phys_level0_sa
,
1267 array_pitch_el_rows
,
1272 unreachable("invalid value for dim_layout");
1276 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1277 const struct isl_tile_info
*tile_info
)
1279 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1280 return tile_info
->phys_extent_B
.width
;
1282 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1283 * RENDER_SURFACE_STATE Surface Pitch (p349):
1285 * - For linear render target surfaces and surfaces accessed with the
1286 * typed data port messages, the pitch must be a multiple of the
1287 * element size for non-YUV surface formats. Pitch must be
1288 * a multiple of 2 * element size for YUV surface formats.
1290 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1291 * ignore because isl doesn't do buffers.]
1293 * - For other linear surfaces, the pitch can be any multiple of
1296 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1297 const uint32_t bs
= fmtl
->bpb
/ 8;
1299 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1300 if (isl_format_is_yuv(surf_info
->format
)) {
1311 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1312 const struct isl_surf_init_info
*info
,
1313 const struct isl_extent2d
*phys_total_el
,
1314 uint32_t alignment_B
)
1316 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1317 const uint32_t bs
= fmtl
->bpb
/ 8;
1319 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1323 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1324 const struct isl_surf_init_info
*surf_info
,
1325 const struct isl_tile_info
*tile_info
,
1326 const struct isl_extent2d
*phys_total_el
,
1327 uint32_t alignment_B
)
1329 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1331 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1333 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1334 const uint32_t total_w_tl
=
1335 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1336 tile_info
->logical_extent_el
.width
);
1338 assert(alignment_B
== tile_info
->phys_extent_B
.width
);
1339 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1343 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1344 const struct isl_surf_init_info
*surf_info
,
1345 const struct isl_tile_info
*tile_info
,
1346 const struct isl_extent2d
*phys_total_el
,
1347 uint32_t alignment_B
)
1349 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1350 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1353 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1354 phys_total_el
, alignment_B
);
1359 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1360 * size is `bits` bits?
1362 * Hardware pitch fields are offset by 1. For example, if the size of
1363 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1364 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1365 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1368 pitch_in_range(uint32_t n
, uint32_t bits
)
1371 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1375 isl_calc_row_pitch(const struct isl_device
*dev
,
1376 const struct isl_surf_init_info
*surf_info
,
1377 const struct isl_tile_info
*tile_info
,
1378 enum isl_dim_layout dim_layout
,
1379 const struct isl_extent2d
*phys_total_el
,
1380 uint32_t *out_row_pitch_B
)
1382 uint32_t alignment_B
=
1383 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1385 const uint32_t min_row_pitch_B
=
1386 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1389 if (surf_info
->row_pitch_B
!= 0) {
1390 if (surf_info
->row_pitch_B
< min_row_pitch_B
)
1393 if (surf_info
->row_pitch_B
% alignment_B
!= 0)
1397 const uint32_t row_pitch_B
=
1398 surf_info
->row_pitch_B
!= 0 ?
1399 surf_info
->row_pitch_B
:
1400 /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches
1401 * must be 512B-aligned.
1403 ISL_DEV_GEN(dev
) >= 12 &&
1404 isl_format_supports_ccs_e(dev
->info
, surf_info
->format
) ?
1405 isl_align(min_row_pitch_B
, 512) :
1409 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1411 if (row_pitch_B
== 0)
1414 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1415 /* SurfacePitch is ignored for this layout. */
1419 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1420 ISL_SURF_USAGE_TEXTURE_BIT
|
1421 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1422 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1425 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1426 ISL_SURF_USAGE_MCS_BIT
)) &&
1427 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1430 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1431 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1434 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1435 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1438 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1439 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1440 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1442 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1443 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1447 *out_row_pitch_B
= row_pitch_B
;
1452 isl_surf_init_s(const struct isl_device
*dev
,
1453 struct isl_surf
*surf
,
1454 const struct isl_surf_init_info
*restrict info
)
1456 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1458 const struct isl_extent4d logical_level0_px
= {
1462 .a
= info
->array_len
,
1465 enum isl_tiling tiling
;
1466 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1469 struct isl_tile_info tile_info
;
1470 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1472 const enum isl_dim_layout dim_layout
=
1473 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1475 enum isl_msaa_layout msaa_layout
;
1476 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1479 struct isl_extent3d image_align_el
;
1480 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1483 struct isl_extent3d image_align_sa
=
1484 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1486 struct isl_extent4d phys_level0_sa
;
1487 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1490 enum isl_array_pitch_span array_pitch_span
=
1491 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1493 uint32_t array_pitch_el_rows
;
1494 struct isl_extent2d phys_total_el
;
1495 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1496 dim_layout
, msaa_layout
,
1497 &image_align_sa
, &phys_level0_sa
,
1498 array_pitch_span
, &array_pitch_el_rows
,
1501 uint32_t row_pitch_B
;
1502 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1503 &phys_total_el
, &row_pitch_B
))
1506 uint32_t base_alignment_B
;
1508 if (tiling
== ISL_TILING_LINEAR
) {
1509 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1511 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1513 * "The Base Address for linear render target surfaces and surfaces
1514 * accessed with the typed surface read/write data port messages must
1515 * be element-size aligned, for non-YUV surface formats, or a
1516 * multiple of 2 element-sizes for YUV surface formats. Other linear
1517 * surfaces have no alignment requirements (byte alignment is
1520 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1521 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1522 if (isl_format_is_yuv(info
->format
)) {
1523 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1525 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1528 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1530 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1532 * "For Linear memory, this field specifies the stride in chunks of
1533 * 64 bytes (1 cache line)."
1535 if (isl_surf_usage_is_display(info
->usage
))
1536 base_alignment_B
= MAX(base_alignment_B
, 64);
1538 const uint32_t total_h_tl
=
1539 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1541 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1543 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1544 tile_info
.phys_extent_B
.height
;
1545 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1546 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1549 if (ISL_DEV_GEN(dev
) >= 12) {
1550 base_alignment_B
= MAX(base_alignment_B
, 64 * 1024);
1553 if (ISL_DEV_GEN(dev
) < 9) {
1554 /* From the Broadwell PRM Vol 5, Surface Layout:
1556 * "In addition to restrictions on maximum height, width, and depth,
1557 * surfaces are also restricted to a maximum size in bytes. This
1558 * maximum is 2 GB for all products and all surface types."
1560 * This comment is applicable to all Pre-gen9 platforms.
1562 if (size_B
> (uint64_t) 1 << 31)
1564 } else if (ISL_DEV_GEN(dev
) < 11) {
1565 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1566 * "In addition to restrictions on maximum height, width, and depth,
1567 * surfaces are also restricted to a maximum size of 2^38 bytes.
1568 * All pixels within the surface must be contained within 2^38 bytes
1569 * of the base address."
1571 if (size_B
> (uint64_t) 1 << 38)
1574 /* gen11+ platforms raised this limit to 2^44 bytes. */
1575 if (size_B
> (uint64_t) 1 << 44)
1579 *surf
= (struct isl_surf
) {
1581 .dim_layout
= dim_layout
,
1582 .msaa_layout
= msaa_layout
,
1584 .format
= info
->format
,
1586 .levels
= info
->levels
,
1587 .samples
= info
->samples
,
1589 .image_alignment_el
= image_align_el
,
1590 .logical_level0_px
= logical_level0_px
,
1591 .phys_level0_sa
= phys_level0_sa
,
1594 .alignment_B
= base_alignment_B
,
1595 .row_pitch_B
= row_pitch_B
,
1596 .array_pitch_el_rows
= array_pitch_el_rows
,
1597 .array_pitch_span
= array_pitch_span
,
1599 .usage
= info
->usage
,
1606 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1607 struct isl_tile_info
*tile_info
)
1609 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1610 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1614 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1615 const struct isl_surf
*surf
,
1616 struct isl_surf
*hiz_surf
)
1618 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1620 /* HiZ only works with Y-tiled depth buffers */
1621 if (!isl_tiling_is_any_y(surf
->tiling
))
1624 /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
1625 switch (surf
->format
) {
1626 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1627 if (isl_surf_usage_is_depth_and_stencil(surf
->usage
)) {
1628 assert(ISL_DEV_GEN(dev
) == 5);
1629 unreachable("This should work, but is untested");
1632 case ISL_FORMAT_R16_UNORM
:
1633 case ISL_FORMAT_R32_FLOAT
:
1635 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1636 if (ISL_DEV_GEN(dev
) == 5) {
1637 assert(isl_surf_usage_is_depth_and_stencil(surf
->usage
));
1638 unreachable("This should work, but is untested");
1645 /* Multisampled depth is always interleaved */
1646 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1647 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1649 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1651 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1652 * Target View Extent, and Depth Coordinate Offset X/Y of the
1653 * hierarchical depth buffer are inherited from the depth buffer. The
1654 * height and width of the hierarchical depth buffer that must be
1655 * allocated are computed by the following formulas, where HZ is the
1656 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1657 * Z_Width, and Z_Depth values given in these formulas are those present
1658 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1660 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1661 * being applied to the table below if Number of Multisamples is set to
1662 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1663 * Z_Width must be multiplied by 4 before being applied to the table
1664 * below if Number of Multisamples is set to NUMSAMPLES_8."
1666 * In the Sky Lake PRM, the second paragraph is replaced with this:
1668 * "The Z_Height and Z_Width values must equal those present in
1669 * 3DSTATE_DEPTH_BUFFER incremented by one."
1671 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1672 * block corresponds to a region of 8x4 samples in the primary depth
1673 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1674 * a region of 8x4 pixels in the primary depth surface regardless of the
1675 * number of samples. The dimensions of a HiZ block in both pixels and
1676 * samples are given in the table below:
1678 * | SNB - BDW | SKL+
1679 * ------+-----------+-------------
1680 * 1x | 8 x 4 sa | 8 x 4 sa
1681 * MSAA | 8 x 4 px | 8 x 4 px
1682 * ------+-----------+-------------
1683 * 2x | 8 x 4 sa | 16 x 4 sa
1684 * MSAA | 4 x 4 px | 8 x 4 px
1685 * ------+-----------+-------------
1686 * 4x | 8 x 4 sa | 16 x 8 sa
1687 * MSAA | 4 x 2 px | 8 x 4 px
1688 * ------+-----------+-------------
1689 * 8x | 8 x 4 sa | 32 x 8 sa
1690 * MSAA | 2 x 2 px | 8 x 4 px
1691 * ------+-----------+-------------
1692 * 16x | N/A | 32 x 16 sa
1693 * MSAA | N/A | 8 x 4 px
1694 * ------+-----------+-------------
1696 * There are a number of different ways that this discrepency could be
1697 * handled. The way we have chosen is to simply make MSAA HiZ have the
1698 * same number of samples as the parent surface pre-Sky Lake and always be
1699 * single-sampled on Sky Lake and above. Since the block sizes of
1700 * compressed formats are given in samples, this neatly handles everything
1701 * without the need for additional HiZ formats with different block sizes
1704 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1706 return isl_surf_init(dev
, hiz_surf
,
1708 .format
= ISL_FORMAT_HIZ
,
1709 .width
= surf
->logical_level0_px
.width
,
1710 .height
= surf
->logical_level0_px
.height
,
1711 .depth
= surf
->logical_level0_px
.depth
,
1712 .levels
= surf
->levels
,
1713 .array_len
= surf
->logical_level0_px
.array_len
,
1715 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1716 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1720 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1721 const struct isl_surf
*surf
,
1722 struct isl_surf
*mcs_surf
)
1724 /* The following are true of all multisampled surfaces */
1725 assert(surf
->samples
> 1);
1726 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1727 assert(surf
->levels
== 1);
1728 assert(surf
->logical_level0_px
.depth
== 1);
1730 /* It must be multisampled with an array layout */
1731 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_ARRAY
)
1734 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
1736 * This field must be set to 0 for all SINT MSRTs when all RT channels
1739 * In practice this means that we have to disable MCS for all signed
1740 * integer MSAA buffers. The alternative, to disable MCS only when one
1741 * of the render target channels is disabled, is impractical because it
1742 * would require converting between CMS and UMS MSAA layouts on the fly,
1743 * which is expensive.
1745 if (ISL_DEV_GEN(dev
) == 7 && isl_format_has_sint_channel(surf
->format
))
1748 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1749 * bits which means the maximum pitch of a compression surface is 512
1750 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1751 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1752 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1753 * and 8x, we have enough room for the full 16k supported by the hardware.
1755 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1758 enum isl_format mcs_format
;
1759 switch (surf
->samples
) {
1760 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1761 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1762 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1763 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1765 unreachable("Invalid sample count");
1768 return isl_surf_init(dev
, mcs_surf
,
1769 .dim
= ISL_SURF_DIM_2D
,
1770 .format
= mcs_format
,
1771 .width
= surf
->logical_level0_px
.width
,
1772 .height
= surf
->logical_level0_px
.height
,
1775 .array_len
= surf
->logical_level0_px
.array_len
,
1776 .samples
= 1, /* MCS surfaces are really single-sampled */
1777 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1778 .tiling_flags
= ISL_TILING_Y0_BIT
);
1782 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1783 const struct isl_surf
*surf
,
1784 struct isl_surf
*ccs_surf
,
1785 uint32_t row_pitch_B
)
1787 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1789 /* CCS support does not exist prior to Gen7 */
1790 if (ISL_DEV_GEN(dev
) <= 6)
1793 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1796 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1797 * work for 3D textures until gen9 where the layout of 3D textures changes
1798 * to match 2D array textures.
1800 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1803 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1804 * Non-MultiSampler Render Target Restrictions):
1806 * "Support is for non-mip-mapped and non-array surface types only."
1808 * This restriction is lifted on gen8+. Technically, it may be possible to
1809 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1810 * when rendering to the base slice. However, there is no documentation
1811 * tell us what the hardware would do in that case or what it does if you
1812 * walk off the bases slice. (Does it ignore CCS or does it start
1813 * scribbling over random memory?) We play it safe and just follow the
1814 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1816 if (ISL_DEV_GEN(dev
) <= 7 &&
1817 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1820 if (isl_format_is_compressed(surf
->format
))
1823 /* TODO: More conditions where it can fail. */
1825 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
1826 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
1828 * - Support is limited to tiled render targets.
1829 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
1830 * 64bpp, and 128bpp.
1832 * From the Skylake documentation, it is made clear that X-tiling is no
1835 * - MCS and Lossless compression is supported for
1836 * TiledY/TileYs/TileYf non-MSRTs only.
1838 enum isl_format ccs_format
;
1839 if (ISL_DEV_GEN(dev
) >= 9) {
1840 if (!isl_tiling_is_any_y(surf
->tiling
))
1843 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1844 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1845 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1846 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1850 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1851 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1852 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1853 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1854 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1858 } else if (surf
->tiling
== ISL_TILING_X
) {
1859 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1860 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1861 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1862 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1870 return isl_surf_init(dev
, ccs_surf
,
1872 .format
= ccs_format
,
1873 .width
= surf
->logical_level0_px
.width
,
1874 .height
= surf
->logical_level0_px
.height
,
1875 .depth
= surf
->logical_level0_px
.depth
,
1876 .levels
= surf
->levels
,
1877 .array_len
= surf
->logical_level0_px
.array_len
,
1879 .row_pitch_B
= row_pitch_B
,
1880 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1881 .tiling_flags
= ISL_TILING_CCS_BIT
);
1884 #define isl_genX_call(dev, func, ...) \
1885 switch (ISL_DEV_GEN(dev)) { \
1887 /* G45 surface state is the same as gen5 */ \
1888 if (ISL_DEV_IS_G4X(dev)) { \
1889 isl_gen5_##func(__VA_ARGS__); \
1891 isl_gen4_##func(__VA_ARGS__); \
1895 isl_gen5_##func(__VA_ARGS__); \
1898 isl_gen6_##func(__VA_ARGS__); \
1901 if (ISL_DEV_IS_HASWELL(dev)) { \
1902 isl_gen75_##func(__VA_ARGS__); \
1904 isl_gen7_##func(__VA_ARGS__); \
1908 isl_gen8_##func(__VA_ARGS__); \
1911 isl_gen9_##func(__VA_ARGS__); \
1914 isl_gen10_##func(__VA_ARGS__); \
1917 isl_gen11_##func(__VA_ARGS__); \
1920 isl_gen12_##func(__VA_ARGS__); \
1923 assert(!"Unknown hardware generation"); \
1927 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1928 const struct isl_surf_fill_state_info
*restrict info
)
1931 isl_surf_usage_flags_t _base_usage
=
1932 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1933 ISL_SURF_USAGE_TEXTURE_BIT
|
1934 ISL_SURF_USAGE_STORAGE_BIT
);
1935 /* They may only specify one of the above bits at a time */
1936 assert(__builtin_popcount(_base_usage
) == 1);
1937 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1938 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1941 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1942 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1943 info
->surf
->logical_level0_px
.depth
);
1945 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1946 info
->surf
->logical_level0_px
.array_len
);
1949 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
1953 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1954 const struct isl_buffer_fill_state_info
*restrict info
)
1956 isl_genX_call(dev
, buffer_fill_state_s
, state
, info
);
1960 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1961 struct isl_extent3d size
)
1963 isl_genX_call(dev
, null_fill_state
, state
, size
);
1967 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1968 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1970 if (info
->depth_surf
&& info
->stencil_surf
) {
1971 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1972 assert(info
->depth_surf
== info
->stencil_surf
);
1973 assert(info
->depth_address
== info
->stencil_address
);
1975 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1978 if (info
->depth_surf
) {
1979 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1980 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1981 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1982 info
->depth_surf
->logical_level0_px
.depth
);
1984 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1985 info
->depth_surf
->logical_level0_px
.array_len
);
1989 if (info
->stencil_surf
) {
1990 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1991 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1992 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1993 info
->stencil_surf
->logical_level0_px
.depth
);
1995 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1996 info
->stencil_surf
->logical_level0_px
.array_len
);
2000 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
2004 * A variant of isl_surf_get_image_offset_sa() specific to
2005 * ISL_DIM_LAYOUT_GEN4_2D.
2008 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
2009 uint32_t level
, uint32_t logical_array_layer
,
2010 uint32_t *x_offset_sa
,
2011 uint32_t *y_offset_sa
)
2013 assert(level
< surf
->levels
);
2014 if (surf
->dim
== ISL_SURF_DIM_3D
)
2015 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2017 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2019 const struct isl_extent3d image_align_sa
=
2020 isl_surf_get_image_alignment_sa(surf
);
2022 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2023 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2025 const uint32_t phys_layer
= logical_array_layer
*
2026 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2029 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2031 for (uint32_t l
= 0; l
< level
; ++l
) {
2033 uint32_t W
= isl_minify(W0
, l
);
2034 x
+= isl_align_npot(W
, image_align_sa
.w
);
2036 uint32_t H
= isl_minify(H0
, l
);
2037 y
+= isl_align_npot(H
, image_align_sa
.h
);
2046 * A variant of isl_surf_get_image_offset_sa() specific to
2047 * ISL_DIM_LAYOUT_GEN4_3D.
2050 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2051 uint32_t level
, uint32_t logical_z_offset_px
,
2052 uint32_t *x_offset_sa
,
2053 uint32_t *y_offset_sa
)
2055 assert(level
< surf
->levels
);
2056 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2057 assert(surf
->phys_level0_sa
.array_len
== 1);
2058 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2060 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2061 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2062 assert(surf
->phys_level0_sa
.array_len
== 6);
2063 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2066 const struct isl_extent3d image_align_sa
=
2067 isl_surf_get_image_alignment_sa(surf
);
2069 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2070 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2071 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2072 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2077 for (uint32_t l
= 0; l
< level
; ++l
) {
2078 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2079 const uint32_t level_d
=
2080 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2082 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2084 y
+= level_h
* max_layers_vert
;
2087 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2088 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2089 const uint32_t level_d
=
2090 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2093 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2095 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2096 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2103 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2105 uint32_t logical_array_layer
,
2106 uint32_t *x_offset_sa
,
2107 uint32_t *y_offset_sa
)
2109 assert(level
< surf
->levels
);
2110 assert(surf
->logical_level0_px
.depth
== 1);
2111 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2113 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2115 const struct isl_extent3d image_align_sa
=
2116 isl_surf_get_image_alignment_sa(surf
);
2118 struct isl_tile_info tile_info
;
2119 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2120 const struct isl_extent2d tile_extent_sa
= {
2121 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2122 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2124 /* Tile size is a multiple of image alignment */
2125 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2126 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2128 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2129 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2131 /* Each image has the same height as LOD0 because the hardware thinks
2132 * everything is LOD0
2134 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2136 /* Quick sanity check for consistency */
2137 if (surf
->phys_level0_sa
.array_len
> 1)
2138 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2140 uint32_t x
= 0, y
= 0;
2141 for (uint32_t l
= 0; l
< level
; ++l
) {
2142 const uint32_t W
= isl_minify(W0
, l
);
2144 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2145 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2155 y
+= H
* logical_array_layer
;
2162 * A variant of isl_surf_get_image_offset_sa() specific to
2163 * ISL_DIM_LAYOUT_GEN9_1D.
2166 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2167 uint32_t level
, uint32_t layer
,
2168 uint32_t *x_offset_sa
,
2169 uint32_t *y_offset_sa
)
2171 assert(level
< surf
->levels
);
2172 assert(layer
< surf
->phys_level0_sa
.array_len
);
2173 assert(surf
->phys_level0_sa
.height
== 1);
2174 assert(surf
->phys_level0_sa
.depth
== 1);
2175 assert(surf
->samples
== 1);
2177 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2178 const struct isl_extent3d image_align_sa
=
2179 isl_surf_get_image_alignment_sa(surf
);
2183 for (uint32_t l
= 0; l
< level
; ++l
) {
2184 uint32_t W
= isl_minify(W0
, l
);
2185 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2191 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2195 * Calculate the offset, in units of surface samples, to a subimage in the
2198 * @invariant level < surface levels
2199 * @invariant logical_array_layer < logical array length of surface
2200 * @invariant logical_z_offset_px < logical depth of surface at level
2203 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2205 uint32_t logical_array_layer
,
2206 uint32_t logical_z_offset_px
,
2207 uint32_t *x_offset_sa
,
2208 uint32_t *y_offset_sa
)
2210 assert(level
< surf
->levels
);
2211 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2212 assert(logical_z_offset_px
2213 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2215 switch (surf
->dim_layout
) {
2216 case ISL_DIM_LAYOUT_GEN9_1D
:
2217 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2218 x_offset_sa
, y_offset_sa
);
2220 case ISL_DIM_LAYOUT_GEN4_2D
:
2221 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2222 + logical_z_offset_px
,
2223 x_offset_sa
, y_offset_sa
);
2225 case ISL_DIM_LAYOUT_GEN4_3D
:
2226 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2227 logical_z_offset_px
,
2228 x_offset_sa
, y_offset_sa
);
2230 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2231 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2232 logical_z_offset_px
,
2233 x_offset_sa
, y_offset_sa
);
2237 unreachable("not reached");
2242 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2244 uint32_t logical_array_layer
,
2245 uint32_t logical_z_offset_px
,
2246 uint32_t *x_offset_el
,
2247 uint32_t *y_offset_el
)
2249 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2251 assert(level
< surf
->levels
);
2252 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2253 assert(logical_z_offset_px
2254 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2256 uint32_t x_offset_sa
, y_offset_sa
;
2257 isl_surf_get_image_offset_sa(surf
, level
,
2258 logical_array_layer
,
2259 logical_z_offset_px
,
2263 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2264 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2268 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2270 uint32_t logical_array_layer
,
2271 uint32_t logical_z_offset_px
,
2273 uint32_t *x_offset_sa
,
2274 uint32_t *y_offset_sa
)
2276 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2278 uint32_t total_x_offset_el
, total_y_offset_el
;
2279 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2280 logical_z_offset_px
,
2282 &total_y_offset_el
);
2284 uint32_t x_offset_el
, y_offset_el
;
2285 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2294 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2296 assert(x_offset_el
== 0);
2300 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2302 assert(y_offset_el
== 0);
2307 isl_surf_get_image_surf(const struct isl_device
*dev
,
2308 const struct isl_surf
*surf
,
2310 uint32_t logical_array_layer
,
2311 uint32_t logical_z_offset_px
,
2312 struct isl_surf
*image_surf
,
2314 uint32_t *x_offset_sa
,
2315 uint32_t *y_offset_sa
)
2317 isl_surf_get_image_offset_B_tile_sa(surf
,
2319 logical_array_layer
,
2320 logical_z_offset_px
,
2325 /* Even for cube maps there will be only single face, therefore drop the
2326 * corresponding flag if present.
2328 const isl_surf_usage_flags_t usage
=
2329 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2332 ok
= isl_surf_init(dev
, image_surf
,
2333 .dim
= ISL_SURF_DIM_2D
,
2334 .format
= surf
->format
,
2335 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2336 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2340 .samples
= surf
->samples
,
2341 .row_pitch_B
= surf
->row_pitch_B
,
2343 .tiling_flags
= (1 << surf
->tiling
));
2348 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2350 uint32_t row_pitch_B
,
2351 uint32_t total_x_offset_el
,
2352 uint32_t total_y_offset_el
,
2353 uint32_t *base_address_offset
,
2354 uint32_t *x_offset_el
,
2355 uint32_t *y_offset_el
)
2357 if (tiling
== ISL_TILING_LINEAR
) {
2358 assert(bpb
% 8 == 0);
2359 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2360 total_x_offset_el
* (bpb
/ 8);
2366 struct isl_tile_info tile_info
;
2367 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2369 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2371 /* For non-power-of-two formats, we need the address to be both tile and
2372 * element-aligned. The easiest way to achieve this is to work with a tile
2373 * that is three times as wide as the regular tile.
2375 * The tile info returned by get_tile_info has a logical size that is an
2376 * integer number of tile_info.format_bpb size elements. To scale the
2377 * tile, we scale up the physical width and then treat the logical tile
2378 * size as if it has bpb size elements.
2380 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2381 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2383 /* Compute the offset into the tile */
2384 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2385 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2387 /* Compute the offset of the tile in units of whole tiles */
2388 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2389 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2391 *base_address_offset
=
2392 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2393 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2397 isl_surf_get_depth_format(const struct isl_device
*dev
,
2398 const struct isl_surf
*surf
)
2400 /* Support for separate stencil buffers began in gen5. Support for
2401 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2402 * those that supported separate and interleaved stencil, were gen5 and
2405 * For a list of all available formats, see the Sandybridge PRM >> Volume
2406 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2410 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2412 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2415 assert(ISL_DEV_GEN(dev
) < 7);
2417 switch (surf
->format
) {
2419 unreachable("bad isl depth format");
2420 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2421 assert(ISL_DEV_GEN(dev
) < 7);
2422 return 0; /* D32_FLOAT_S8X24_UINT */
2423 case ISL_FORMAT_R32_FLOAT
:
2424 assert(!has_stencil
);
2425 return 1; /* D32_FLOAT */
2426 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2428 assert(ISL_DEV_GEN(dev
) < 7);
2429 return 2; /* D24_UNORM_S8_UINT */
2431 assert(ISL_DEV_GEN(dev
) >= 5);
2432 return 3; /* D24_UNORM_X8_UINT */
2434 case ISL_FORMAT_R16_UNORM
:
2435 assert(!has_stencil
);
2436 return 5; /* D16_UNORM */
2441 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2442 struct isl_swizzle swizzle
)
2444 if (devinfo
->is_haswell
) {
2445 /* From the Haswell PRM,
2446 * RENDER_SURFACE_STATE::Shader Channel Select Red
2448 * "The Shader channel selects also define which shader channels are
2449 * written to which surface channel. If the Shader channel select is
2450 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2451 * shader channel select is SCS_RED it is written to the surface red
2452 * channel and so on. If more than one shader channel select is set
2453 * to the same surface channel only the first shader channel in RGBA
2454 * order will be written."
2457 } else if (devinfo
->gen
<= 7) {
2458 /* Ivy Bridge and early doesn't have any swizzling */
2459 return isl_swizzle_is_identity(swizzle
);
2461 /* From the Sky Lake PRM Vol. 2d,
2462 * RENDER_SURFACE_STATE::Shader Channel Select Red
2464 * "For Render Target, Red, Green and Blue Shader Channel Selects
2465 * MUST be such that only valid components can be swapped i.e. only
2466 * change the order of components in the pixel. Any other values for
2467 * these Shader Channel Select fields are not valid for Render
2468 * Targets. This also means that there MUST not be multiple shader
2469 * channels mapped to the same RT channel."
2471 * From the Sky Lake PRM Vol. 2d,
2472 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2474 * "For Render Target, this field MUST be programmed to
2475 * value = SCS_ALPHA."
2477 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2478 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2479 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2480 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2481 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2482 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2483 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2484 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2485 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2486 swizzle
.r
!= swizzle
.g
&&
2487 swizzle
.r
!= swizzle
.b
&&
2488 swizzle
.g
!= swizzle
.b
&&
2489 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2493 static enum isl_channel_select
2494 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2497 case ISL_CHANNEL_SELECT_ZERO
:
2498 case ISL_CHANNEL_SELECT_ONE
:
2500 case ISL_CHANNEL_SELECT_RED
:
2502 case ISL_CHANNEL_SELECT_GREEN
:
2504 case ISL_CHANNEL_SELECT_BLUE
:
2506 case ISL_CHANNEL_SELECT_ALPHA
:
2509 unreachable("Invalid swizzle component");
2514 * Returns the single swizzle that is equivalent to applying the two given
2515 * swizzles in sequence.
2518 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2520 return (struct isl_swizzle
) {
2521 .r
= swizzle_select(first
.r
, second
),
2522 .g
= swizzle_select(first
.g
, second
),
2523 .b
= swizzle_select(first
.b
, second
),
2524 .a
= swizzle_select(first
.a
, second
),
2529 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2532 isl_swizzle_invert(struct isl_swizzle swizzle
)
2534 /* Default to zero for channels which do not show up in the swizzle */
2535 enum isl_channel_select chans
[4] = {
2536 ISL_CHANNEL_SELECT_ZERO
,
2537 ISL_CHANNEL_SELECT_ZERO
,
2538 ISL_CHANNEL_SELECT_ZERO
,
2539 ISL_CHANNEL_SELECT_ZERO
,
2542 /* We go in ABGR order so that, if there are any duplicates, the first one
2543 * is taken if you look at it in RGBA order. This is what Haswell hardware
2544 * does for render target swizzles.
2546 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2547 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2548 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2549 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2550 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2551 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2552 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2553 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2555 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };