2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
36 #include "isl_gen12.h"
40 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
41 uint32_t yt1
, uint32_t yt2
,
42 char *dst
, const char *src
,
43 uint32_t dst_pitch
, int32_t src_pitch
,
45 enum isl_tiling tiling
,
46 isl_memcpy_type copy_type
)
49 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
50 _isl_memcpy_linear_to_tiled_sse41(
51 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
57 _isl_memcpy_linear_to_tiled(
58 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
63 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
64 uint32_t yt1
, uint32_t yt2
,
65 char *dst
, const char *src
,
66 int32_t dst_pitch
, uint32_t src_pitch
,
68 enum isl_tiling tiling
,
69 isl_memcpy_type copy_type
)
72 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
73 _isl_memcpy_tiled_to_linear_sse41(
74 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
80 _isl_memcpy_tiled_to_linear(
81 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
85 void PRINTFLIKE(3, 4) UNUSED
86 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
92 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
95 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
99 isl_device_init(struct isl_device
*dev
,
100 const struct gen_device_info
*info
,
101 bool has_bit6_swizzling
)
103 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
104 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
107 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
108 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
110 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
111 * device properties at buildtime. Verify that the macros with the device
112 * properties chosen during runtime.
114 ISL_DEV_GEN_SANITIZE(dev
);
115 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
117 /* Did we break hiz or stencil? */
118 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
119 assert(info
->has_hiz_and_separate_stencil
);
120 if (info
->must_use_separate_stencil
)
121 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
123 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
124 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
126 dev
->ss
.clear_color_state_size
=
127 isl_align(CLEAR_COLOR_length(info
) * 4, 64);
128 dev
->ss
.clear_color_state_offset
=
129 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
131 dev
->ss
.clear_value_size
=
132 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
133 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
134 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
135 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
137 dev
->ss
.clear_value_offset
=
138 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
140 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
141 dev
->ss
.addr_offset
=
142 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
144 /* The "Auxiliary Surface Base Address" field starts a bit higher up
145 * because the bottom 12 bits are used for other things. Round down to
146 * the nearest dword before.
148 dev
->ss
.aux_addr_offset
=
149 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
151 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
152 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
153 dev
->ds
.depth_offset
=
154 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
156 if (dev
->use_separate_stencil
) {
157 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
158 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
159 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
161 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
162 dev
->ds
.stencil_offset
=
163 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
164 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
166 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
168 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
169 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
170 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
172 dev
->ds
.stencil_offset
= 0;
173 dev
->ds
.hiz_offset
= 0;
178 * @brief Query the set of multisamples supported by the device.
180 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
183 isl_sample_count_mask_t ATTRIBUTE_CONST
184 isl_device_get_sample_counts(struct isl_device
*dev
)
186 if (ISL_DEV_GEN(dev
) >= 9) {
187 return ISL_SAMPLE_COUNT_1_BIT
|
188 ISL_SAMPLE_COUNT_2_BIT
|
189 ISL_SAMPLE_COUNT_4_BIT
|
190 ISL_SAMPLE_COUNT_8_BIT
|
191 ISL_SAMPLE_COUNT_16_BIT
;
192 } else if (ISL_DEV_GEN(dev
) >= 8) {
193 return ISL_SAMPLE_COUNT_1_BIT
|
194 ISL_SAMPLE_COUNT_2_BIT
|
195 ISL_SAMPLE_COUNT_4_BIT
|
196 ISL_SAMPLE_COUNT_8_BIT
;
197 } else if (ISL_DEV_GEN(dev
) >= 7) {
198 return ISL_SAMPLE_COUNT_1_BIT
|
199 ISL_SAMPLE_COUNT_4_BIT
|
200 ISL_SAMPLE_COUNT_8_BIT
;
201 } else if (ISL_DEV_GEN(dev
) >= 6) {
202 return ISL_SAMPLE_COUNT_1_BIT
|
203 ISL_SAMPLE_COUNT_4_BIT
;
205 return ISL_SAMPLE_COUNT_1_BIT
;
210 * @param[out] info is written only on success
213 isl_tiling_get_info(enum isl_tiling tiling
,
215 struct isl_tile_info
*tile_info
)
217 const uint32_t bs
= format_bpb
/ 8;
218 struct isl_extent2d logical_el
, phys_B
;
220 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
221 /* It is possible to have non-power-of-two formats in a tiled buffer.
222 * The easiest way to handle this is to treat the tile as if it is three
223 * times as wide. This way no pixel will ever cross a tile boundary.
224 * This really only works on legacy X and Y tiling formats.
226 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
227 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
228 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
233 case ISL_TILING_LINEAR
:
235 logical_el
= isl_extent2d(1, 1);
236 phys_B
= isl_extent2d(bs
, 1);
241 logical_el
= isl_extent2d(512 / bs
, 8);
242 phys_B
= isl_extent2d(512, 8);
247 logical_el
= isl_extent2d(128 / bs
, 32);
248 phys_B
= isl_extent2d(128, 32);
253 logical_el
= isl_extent2d(64, 64);
254 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
256 * "If the surface is a stencil buffer (and thus has Tile Mode set
257 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
258 * computed based on width, as the stencil buffer is stored with two
261 * This, together with the fact that stencil buffers are referred to as
262 * being Y-tiled in the PRMs for older hardware implies that the
263 * physical size of a W-tile is actually the same as for a Y-tile.
265 phys_B
= isl_extent2d(128, 32);
269 case ISL_TILING_Ys
: {
270 bool is_Ys
= tiling
== ISL_TILING_Ys
;
273 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
274 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
276 logical_el
= isl_extent2d(width
/ bs
, height
);
277 phys_B
= isl_extent2d(width
, height
);
282 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
283 * 128bpb format. The tiling has the same physical dimensions as
284 * Y-tiling but actually has two HiZ columns per Y-tiled column.
287 logical_el
= isl_extent2d(16, 16);
288 phys_B
= isl_extent2d(128, 32);
292 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
293 * have a block size of 1 or 2 bits per block and each CCS element
294 * corresponds to one cache-line pair in the main surface. From the Sky
295 * Lake PRM Vol. 12 in the section on planes:
297 * "The Color Control Surface (CCS) contains the compression status
298 * of the cache-line pairs. The compression state of the cache-line
299 * pair is specified by 2 bits in the CCS. Each CCS cache-line
300 * represents an area on the main surface of 16x16 sets of 128 byte
301 * Y-tiled cache-line-pairs. CCS is always Y tiled."
303 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
304 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
305 * that yields total tile area of 128x128 cache-line pairs or CCS
306 * elements. On older hardware, each CCS element is 1 bit and the tile
307 * is 128x256 elements.
309 assert(format_bpb
== 1 || format_bpb
== 2);
310 logical_el
= isl_extent2d(128, 256 / format_bpb
);
311 phys_B
= isl_extent2d(128, 32);
314 case ISL_TILING_GEN12_CCS
:
315 /* From the Bspec, Gen Graphics > Gen12 > Memory Data Formats > Memory
316 * Compression > Memory Compression - Gen12:
318 * 4 bits of auxiliary plane data are required for 2 cachelines of
319 * main surface data. This results in a single cacheline of auxiliary
320 * plane data mapping to 4 4K pages of main surface data for the 4K
321 * pages (tile Y ) and 1 64K Tile Ys page.
323 * The Y-tiled pairing bit of 9 shown in the table below that Bspec
324 * section expresses that the 2 cachelines of main surface data are
325 * horizontally adjacent.
327 * TODO: Handle Ys, Yf and their pairing bits.
329 * Therefore, each CCS cacheline represents a 512Bx32 row area and each
330 * element represents a 32Bx4 row area.
332 assert(format_bpb
== 4);
333 logical_el
= isl_extent2d(16, 8);
334 phys_B
= isl_extent2d(64, 1);
338 unreachable("not reached");
341 *tile_info
= (struct isl_tile_info
) {
343 .format_bpb
= format_bpb
,
344 .logical_extent_el
= logical_el
,
345 .phys_extent_B
= phys_B
,
350 isl_color_value_is_zero(union isl_color_value value
,
351 enum isl_format format
)
353 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
355 #define RETURN_FALSE_IF_NOT_0(c, i) \
356 if (fmtl->channels.c.bits && value.u32[i] != 0) \
359 RETURN_FALSE_IF_NOT_0(r
, 0);
360 RETURN_FALSE_IF_NOT_0(g
, 1);
361 RETURN_FALSE_IF_NOT_0(b
, 2);
362 RETURN_FALSE_IF_NOT_0(a
, 3);
364 #undef RETURN_FALSE_IF_NOT_0
370 isl_color_value_is_zero_one(union isl_color_value value
,
371 enum isl_format format
)
373 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
375 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
376 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
379 if (isl_format_has_int_channel(format
)) {
380 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
381 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
382 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
383 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
385 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
386 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
387 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
388 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
391 #undef RETURN_FALSE_IF_NOT_0_1
397 * @param[out] tiling is set only on success
400 isl_surf_choose_tiling(const struct isl_device
*dev
,
401 const struct isl_surf_init_info
*restrict info
,
402 enum isl_tiling
*tiling
)
404 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
406 /* HiZ surfaces always use the HiZ tiling */
407 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
408 assert(info
->format
== ISL_FORMAT_HIZ
);
409 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
410 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
414 /* CCS surfaces always use the CCS tiling */
415 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
416 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
417 UNUSED
bool ivb_ccs
= ISL_DEV_GEN(dev
) < 12 &&
418 tiling_flags
== ISL_TILING_CCS_BIT
;
419 UNUSED
bool tgl_ccs
= ISL_DEV_GEN(dev
) >= 12 &&
420 tiling_flags
== ISL_TILING_GEN12_CCS_BIT
;
421 assert(ivb_ccs
!= tgl_ccs
);
422 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
426 if (ISL_DEV_GEN(dev
) >= 6) {
427 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
429 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
432 #define CHOOSE(__tiling) \
434 if (tiling_flags & (1u << (__tiling))) { \
435 *tiling = (__tiling); \
440 /* Of the tiling modes remaining, choose the one that offers the best
444 if (info
->dim
== ISL_SURF_DIM_1D
) {
445 /* Prefer linear for 1D surfaces because they do not benefit from
446 * tiling. To the contrary, tiling leads to wasted memory and poor
447 * memory locality due to the swizzling and alignment restrictions
448 * required in tiled surfaces.
450 CHOOSE(ISL_TILING_LINEAR
);
453 CHOOSE(ISL_TILING_Ys
);
454 CHOOSE(ISL_TILING_Yf
);
455 CHOOSE(ISL_TILING_Y0
);
456 CHOOSE(ISL_TILING_X
);
457 CHOOSE(ISL_TILING_W
);
458 CHOOSE(ISL_TILING_LINEAR
);
462 /* No tiling mode accomodates the inputs. */
467 isl_choose_msaa_layout(const struct isl_device
*dev
,
468 const struct isl_surf_init_info
*info
,
469 enum isl_tiling tiling
,
470 enum isl_msaa_layout
*msaa_layout
)
472 if (ISL_DEV_GEN(dev
) >= 8) {
473 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
474 } else if (ISL_DEV_GEN(dev
) >= 7) {
475 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
476 } else if (ISL_DEV_GEN(dev
) >= 6) {
477 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
479 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
484 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
486 assert(isl_is_pow2(samples
));
488 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
491 * If the surface is multisampled and it is a depth or stencil surface
492 * or Multisampled Surface StorageFormat in SURFACE_STATE is
493 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
496 return (struct isl_extent2d
) {
497 .width
= 1 << ((ffs(samples
) - 0) / 2),
498 .height
= 1 << ((ffs(samples
) - 1) / 2),
503 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
504 uint32_t *width
, uint32_t *height
)
506 const struct isl_extent2d px_size_sa
=
507 isl_get_interleaved_msaa_px_size_sa(samples
);
510 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
512 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
515 static enum isl_array_pitch_span
516 isl_choose_array_pitch_span(const struct isl_device
*dev
,
517 const struct isl_surf_init_info
*restrict info
,
518 enum isl_dim_layout dim_layout
,
519 const struct isl_extent4d
*phys_level0_sa
)
521 switch (dim_layout
) {
522 case ISL_DIM_LAYOUT_GEN9_1D
:
523 case ISL_DIM_LAYOUT_GEN4_2D
:
524 if (ISL_DEV_GEN(dev
) >= 8) {
525 /* QPitch becomes programmable in Broadwell. So choose the
526 * most compact QPitch possible in order to conserve memory.
528 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
529 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
531 * - Software must ensure that this field is set to a value
532 * sufficiently large such that the array slices in the surface
533 * do not overlap. Refer to the Memory Data Formats section for
534 * information on how surfaces are stored in memory.
536 * - This field specifies the distance in rows between array
537 * slices. It is used only in the following cases:
539 * - Surface Array is enabled OR
540 * - Number of Mulitsamples is not NUMSAMPLES_1 and
541 * Multisampled Surface Storage Format set to MSFMT_MSS OR
542 * - Surface Type is SURFTYPE_CUBE
544 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
545 } else if (ISL_DEV_GEN(dev
) >= 7) {
546 /* Note that Ivybridge introduces
547 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
548 * driver more control over the QPitch.
551 if (phys_level0_sa
->array_len
== 1) {
552 /* The hardware will never use the QPitch. So choose the most
553 * compact QPitch possible in order to conserve memory.
555 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
558 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
559 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
560 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
561 * Section 6.18.4.7: Surface Arrays (p112):
563 * If Surface Array Spacing is set to ARYSPC_FULL (note that
564 * the depth buffer and stencil buffer have an implied value of
567 return ISL_ARRAY_PITCH_SPAN_FULL
;
570 if (info
->levels
== 1) {
571 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
574 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
577 return ISL_ARRAY_PITCH_SPAN_FULL
;
578 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
579 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
580 isl_surf_usage_is_stencil(info
->usage
)) {
581 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
582 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
584 * The separate stencil buffer does not support mip mapping, thus
585 * the storage for LODs other than LOD 0 is not needed.
587 assert(info
->levels
== 1);
588 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
590 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
591 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
592 isl_surf_usage_is_stencil(info
->usage
)) {
593 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
594 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
596 * The separate stencil buffer does not support mip mapping,
597 * thus the storage for LODs other than LOD 0 is not needed.
599 assert(info
->levels
== 1);
600 assert(phys_level0_sa
->array_len
== 1);
601 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
604 if (phys_level0_sa
->array_len
== 1) {
605 /* The hardware will never use the QPitch. So choose the most
606 * compact QPitch possible in order to conserve memory.
608 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
611 return ISL_ARRAY_PITCH_SPAN_FULL
;
614 case ISL_DIM_LAYOUT_GEN4_3D
:
615 /* The hardware will never use the QPitch. So choose the most
616 * compact QPitch possible in order to conserve memory.
618 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
620 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
621 /* Each array image in the gen6 stencil of HiZ surface is compact in the
622 * sense that every LOD is a compact array of the same size as LOD0.
624 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
627 unreachable("bad isl_dim_layout");
628 return ISL_ARRAY_PITCH_SPAN_FULL
;
632 isl_choose_image_alignment_el(const struct isl_device
*dev
,
633 const struct isl_surf_init_info
*restrict info
,
634 enum isl_tiling tiling
,
635 enum isl_dim_layout dim_layout
,
636 enum isl_msaa_layout msaa_layout
,
637 struct isl_extent3d
*image_align_el
)
639 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
640 if (fmtl
->txc
== ISL_TXC_MCS
) {
641 assert(tiling
== ISL_TILING_Y0
);
644 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
646 * Height, width, and layout of MCS buffer in this case must match with
647 * Render Target height, width, and layout. MCS buffer is tiledY.
649 * To avoid wasting memory, choose the smallest alignment possible:
650 * HALIGN_4 and VALIGN_4.
652 *image_align_el
= isl_extent3d(4, 4, 1);
654 } else if (info
->format
== ISL_FORMAT_HIZ
) {
655 assert(ISL_DEV_GEN(dev
) >= 6);
656 if (ISL_DEV_GEN(dev
) == 6) {
657 /* HiZ surfaces on Sandy Bridge are packed tightly. */
658 *image_align_el
= isl_extent3d(1, 1, 1);
659 } else if (ISL_DEV_GEN(dev
) < 12) {
660 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
661 * primary surface which works out to 2x2 HiZ elments.
663 *image_align_el
= isl_extent3d(2, 2, 1);
665 /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the
666 * primary surface which works out to 2x4 HiZ elments.
669 *image_align_el
= isl_extent3d(2, 4, 1);
674 if (ISL_DEV_GEN(dev
) >= 12) {
675 isl_gen12_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
676 msaa_layout
, image_align_el
);
677 } else if (ISL_DEV_GEN(dev
) >= 9) {
678 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
679 msaa_layout
, image_align_el
);
680 } else if (ISL_DEV_GEN(dev
) >= 8) {
681 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
682 msaa_layout
, image_align_el
);
683 } else if (ISL_DEV_GEN(dev
) >= 7) {
684 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
685 msaa_layout
, image_align_el
);
686 } else if (ISL_DEV_GEN(dev
) >= 6) {
687 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
688 msaa_layout
, image_align_el
);
690 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
691 msaa_layout
, image_align_el
);
695 static enum isl_dim_layout
696 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
697 enum isl_surf_dim logical_dim
,
698 enum isl_tiling tiling
,
699 isl_surf_usage_flags_t usage
)
701 /* Sandy bridge needs a special layout for HiZ and stencil. */
702 if (ISL_DEV_GEN(dev
) == 6 &&
703 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
704 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
706 if (ISL_DEV_GEN(dev
) >= 9) {
707 switch (logical_dim
) {
708 case ISL_SURF_DIM_1D
:
709 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
711 * One-dimensional surfaces use a tiling mode of linear.
712 * Technically, they are not tiled resources, but the Tiled
713 * Resource Mode field in RENDER_SURFACE_STATE is still used to
714 * indicate the alignment requirements for this linear surface
715 * (See 1D Alignment requirements for how 4K and 64KB Tiled
716 * Resource Modes impact alignment). Alternatively, a 1D surface
717 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
720 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
721 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
723 if (tiling
== ISL_TILING_LINEAR
)
724 return ISL_DIM_LAYOUT_GEN9_1D
;
726 return ISL_DIM_LAYOUT_GEN4_2D
;
727 case ISL_SURF_DIM_2D
:
728 case ISL_SURF_DIM_3D
:
729 return ISL_DIM_LAYOUT_GEN4_2D
;
732 switch (logical_dim
) {
733 case ISL_SURF_DIM_1D
:
734 case ISL_SURF_DIM_2D
:
735 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
737 * The cube face textures are stored in the same way as 3D surfaces
738 * are stored (see section 6.17.5 for details). For cube surfaces,
739 * however, the depth is equal to the number of faces (always 6) and
740 * is not reduced for each MIP.
742 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
743 return ISL_DIM_LAYOUT_GEN4_3D
;
745 return ISL_DIM_LAYOUT_GEN4_2D
;
746 case ISL_SURF_DIM_3D
:
747 return ISL_DIM_LAYOUT_GEN4_3D
;
751 unreachable("bad isl_surf_dim");
752 return ISL_DIM_LAYOUT_GEN4_2D
;
756 * Calculate the physical extent of the surface's first level, in units of
760 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
761 const struct isl_surf_init_info
*restrict info
,
762 enum isl_dim_layout dim_layout
,
763 enum isl_tiling tiling
,
764 enum isl_msaa_layout msaa_layout
,
765 struct isl_extent4d
*phys_level0_sa
)
767 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
769 if (isl_format_is_yuv(info
->format
))
770 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
773 case ISL_SURF_DIM_1D
:
774 assert(info
->height
== 1);
775 assert(info
->depth
== 1);
776 assert(info
->samples
== 1);
778 switch (dim_layout
) {
779 case ISL_DIM_LAYOUT_GEN4_3D
:
780 unreachable("bad isl_dim_layout");
782 case ISL_DIM_LAYOUT_GEN9_1D
:
783 case ISL_DIM_LAYOUT_GEN4_2D
:
784 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
785 *phys_level0_sa
= (struct isl_extent4d
) {
789 .a
= info
->array_len
,
795 case ISL_SURF_DIM_2D
:
796 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
797 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
799 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
800 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
802 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
803 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
805 switch (msaa_layout
) {
806 case ISL_MSAA_LAYOUT_NONE
:
807 assert(info
->depth
== 1);
808 assert(info
->samples
== 1);
810 *phys_level0_sa
= (struct isl_extent4d
) {
814 .a
= info
->array_len
,
818 case ISL_MSAA_LAYOUT_ARRAY
:
819 assert(info
->depth
== 1);
820 assert(info
->levels
== 1);
821 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
822 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
824 *phys_level0_sa
= (struct isl_extent4d
) {
828 .a
= info
->array_len
* info
->samples
,
832 case ISL_MSAA_LAYOUT_INTERLEAVED
:
833 assert(info
->depth
== 1);
834 assert(info
->levels
== 1);
835 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
837 *phys_level0_sa
= (struct isl_extent4d
) {
841 .a
= info
->array_len
,
844 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
851 case ISL_SURF_DIM_3D
:
852 assert(info
->array_len
== 1);
853 assert(info
->samples
== 1);
856 isl_finishme("%s:%s: compression block with depth > 1",
860 switch (dim_layout
) {
861 case ISL_DIM_LAYOUT_GEN9_1D
:
862 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
863 unreachable("bad isl_dim_layout");
865 case ISL_DIM_LAYOUT_GEN4_2D
:
866 assert(ISL_DEV_GEN(dev
) >= 9);
868 *phys_level0_sa
= (struct isl_extent4d
) {
876 case ISL_DIM_LAYOUT_GEN4_3D
:
877 assert(ISL_DEV_GEN(dev
) < 9);
878 *phys_level0_sa
= (struct isl_extent4d
) {
891 * Calculate the pitch between physical array slices, in units of rows of
895 isl_calc_array_pitch_el_rows_gen4_2d(
896 const struct isl_device
*dev
,
897 const struct isl_surf_init_info
*restrict info
,
898 const struct isl_tile_info
*tile_info
,
899 const struct isl_extent3d
*image_align_sa
,
900 const struct isl_extent4d
*phys_level0_sa
,
901 enum isl_array_pitch_span array_pitch_span
,
902 const struct isl_extent2d
*phys_slice0_sa
)
904 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
905 uint32_t pitch_sa_rows
= 0;
907 switch (array_pitch_span
) {
908 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
909 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
911 case ISL_ARRAY_PITCH_SPAN_FULL
: {
912 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
913 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
914 * Surfaces >> Surface Arrays.
916 uint32_t H0_sa
= phys_level0_sa
->h
;
917 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
919 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
920 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
923 if (ISL_DEV_GEN(dev
) >= 7) {
924 /* The QPitch equation changed slightly in Ivybridge. */
930 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
932 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
933 (info
->height
% 4 == 1)) {
934 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
935 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
937 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
938 * the value calculated in the equation above , for every
939 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
941 * XXX(chadv): Is the errata natural corollary of the physical
942 * layout of interleaved samples?
947 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
952 assert(pitch_sa_rows
% fmtl
->bh
== 0);
953 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
955 if (ISL_DEV_GEN(dev
) >= 9 && ISL_DEV_GEN(dev
) <= 11 &&
956 fmtl
->txc
== ISL_TXC_CCS
) {
958 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
960 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
961 * layout with these alignments in the RT space: Horizontal
962 * Alignment = 128 and Vertical Alignment = 64."
964 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
966 * "For non-multisampled render target's CCS auxiliary surface,
967 * QPitch must be computed with Horizontal Alignment = 128 and
968 * Surface Vertical Alignment = 256. These alignments are only for
969 * CCS buffer and not for associated render target."
971 * The first restriction is already handled by isl_choose_image_alignment_el
972 * but the second restriction, which is an extension of the first, only
973 * applies to qpitch and must be applied here.
975 * The second restriction disappears on Gen12.
977 assert(fmtl
->bh
== 4);
978 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
981 if (ISL_DEV_GEN(dev
) >= 9 &&
982 info
->dim
== ISL_SURF_DIM_3D
&&
983 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
984 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
986 * Tile Mode != Linear: This field must be set to an integer multiple
989 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
992 return pitch_el_rows
;
996 * A variant of isl_calc_phys_slice0_extent_sa() specific to
997 * ISL_DIM_LAYOUT_GEN4_2D.
1000 isl_calc_phys_slice0_extent_sa_gen4_2d(
1001 const struct isl_device
*dev
,
1002 const struct isl_surf_init_info
*restrict info
,
1003 enum isl_msaa_layout msaa_layout
,
1004 const struct isl_extent3d
*image_align_sa
,
1005 const struct isl_extent4d
*phys_level0_sa
,
1006 struct isl_extent2d
*phys_slice0_sa
)
1008 assert(phys_level0_sa
->depth
== 1);
1010 if (info
->levels
== 1) {
1011 /* Do not pad the surface to the image alignment.
1013 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
1014 * cycles on the below mipmap layout caluclations. Reducing the
1015 * alignment here is safe because we later align the row pitch and array
1016 * pitch to the tile boundary. It is safe even for
1017 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1018 * to accomodate the interleaved samples.
1020 * For linear surfaces, reducing the alignment here permits us to later
1021 * choose an arbitrary, non-aligned row pitch. If the surface backs
1022 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
1023 * VkBufferImageCopy::bufferRowLength.
1025 *phys_slice0_sa
= (struct isl_extent2d
) {
1026 .w
= phys_level0_sa
->w
,
1027 .h
= phys_level0_sa
->h
,
1032 uint32_t slice_top_w
= 0;
1033 uint32_t slice_bottom_w
= 0;
1034 uint32_t slice_left_h
= 0;
1035 uint32_t slice_right_h
= 0;
1037 uint32_t W0
= phys_level0_sa
->w
;
1038 uint32_t H0
= phys_level0_sa
->h
;
1040 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1041 uint32_t W
= isl_minify(W0
, l
);
1042 uint32_t H
= isl_minify(H0
, l
);
1044 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1045 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1051 } else if (l
== 1) {
1054 } else if (l
== 2) {
1055 slice_bottom_w
+= w
;
1062 *phys_slice0_sa
= (struct isl_extent2d
) {
1063 .w
= MAX(slice_top_w
, slice_bottom_w
),
1064 .h
= MAX(slice_left_h
, slice_right_h
),
1069 isl_calc_phys_total_extent_el_gen4_2d(
1070 const struct isl_device
*dev
,
1071 const struct isl_surf_init_info
*restrict info
,
1072 const struct isl_tile_info
*tile_info
,
1073 enum isl_msaa_layout msaa_layout
,
1074 const struct isl_extent3d
*image_align_sa
,
1075 const struct isl_extent4d
*phys_level0_sa
,
1076 enum isl_array_pitch_span array_pitch_span
,
1077 uint32_t *array_pitch_el_rows
,
1078 struct isl_extent2d
*total_extent_el
)
1080 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1082 struct isl_extent2d phys_slice0_sa
;
1083 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1084 image_align_sa
, phys_level0_sa
,
1086 *array_pitch_el_rows
=
1087 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1088 image_align_sa
, phys_level0_sa
,
1091 *total_extent_el
= (struct isl_extent2d
) {
1092 .w
= isl_align_div_npot(phys_slice0_sa
.w
, fmtl
->bw
),
1093 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1094 isl_align_div_npot(phys_slice0_sa
.h
, fmtl
->bh
),
1099 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1100 * ISL_DIM_LAYOUT_GEN4_3D.
1103 isl_calc_phys_total_extent_el_gen4_3d(
1104 const struct isl_device
*dev
,
1105 const struct isl_surf_init_info
*restrict info
,
1106 const struct isl_extent3d
*image_align_sa
,
1107 const struct isl_extent4d
*phys_level0_sa
,
1108 uint32_t *array_pitch_el_rows
,
1109 struct isl_extent2d
*phys_total_el
)
1111 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1113 assert(info
->samples
== 1);
1115 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1116 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1118 * The cube face textures are stored in the same way as 3D surfaces
1119 * are stored (see section 6.17.5 for details). For cube surfaces,
1120 * however, the depth is equal to the number of faces (always 6) and
1121 * is not reduced for each MIP.
1123 assert(ISL_DEV_GEN(dev
) == 4);
1124 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1125 assert(phys_level0_sa
->array_len
== 6);
1127 assert(phys_level0_sa
->array_len
== 1);
1130 uint32_t total_w
= 0;
1131 uint32_t total_h
= 0;
1133 uint32_t W0
= phys_level0_sa
->w
;
1134 uint32_t H0
= phys_level0_sa
->h
;
1135 uint32_t D0
= phys_level0_sa
->d
;
1136 uint32_t A0
= phys_level0_sa
->a
;
1138 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1139 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1140 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1141 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1143 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1144 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1146 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1147 total_h
+= level_h
* max_layers_vert
;
1150 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1151 * different number of horizontal and vertical layers. We have to set it
1152 * to something, so at least make it true for LOD0.
1154 *array_pitch_el_rows
=
1155 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1156 *phys_total_el
= (struct isl_extent2d
) {
1157 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1158 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1163 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1164 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1167 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1168 const struct isl_device
*dev
,
1169 const struct isl_surf_init_info
*restrict info
,
1170 const struct isl_tile_info
*tile_info
,
1171 const struct isl_extent3d
*image_align_sa
,
1172 const struct isl_extent4d
*phys_level0_sa
,
1173 uint32_t *array_pitch_el_rows
,
1174 struct isl_extent2d
*phys_total_el
)
1176 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1178 const struct isl_extent2d tile_extent_sa
= {
1179 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1180 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1182 /* Tile size is a multiple of image alignment */
1183 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1184 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1186 const uint32_t W0
= phys_level0_sa
->w
;
1187 const uint32_t H0
= phys_level0_sa
->h
;
1189 /* Each image has the same height as LOD0 because the hardware thinks
1190 * everything is LOD0
1192 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1194 uint32_t total_top_w
= 0;
1195 uint32_t total_bottom_w
= 0;
1196 uint32_t total_h
= 0;
1198 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1199 const uint32_t W
= isl_minify(W0
, l
);
1201 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1202 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1207 } else if (l
== 1) {
1211 total_bottom_w
+= w
;
1215 *array_pitch_el_rows
=
1216 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1217 *phys_total_el
= (struct isl_extent2d
) {
1218 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1219 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1224 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1225 * ISL_DIM_LAYOUT_GEN9_1D.
1228 isl_calc_phys_total_extent_el_gen9_1d(
1229 const struct isl_device
*dev
,
1230 const struct isl_surf_init_info
*restrict info
,
1231 const struct isl_extent3d
*image_align_sa
,
1232 const struct isl_extent4d
*phys_level0_sa
,
1233 uint32_t *array_pitch_el_rows
,
1234 struct isl_extent2d
*phys_total_el
)
1236 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1238 assert(phys_level0_sa
->height
== 1);
1239 assert(phys_level0_sa
->depth
== 1);
1240 assert(info
->samples
== 1);
1241 assert(image_align_sa
->w
>= fmtl
->bw
);
1243 uint32_t slice_w
= 0;
1244 const uint32_t W0
= phys_level0_sa
->w
;
1246 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1247 uint32_t W
= isl_minify(W0
, l
);
1248 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1253 *array_pitch_el_rows
= 1;
1254 *phys_total_el
= (struct isl_extent2d
) {
1255 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1256 .h
= phys_level0_sa
->array_len
,
1261 * Calculate the two-dimensional total physical extent of the surface, in
1262 * units of surface elements.
1265 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1266 const struct isl_surf_init_info
*restrict info
,
1267 const struct isl_tile_info
*tile_info
,
1268 enum isl_dim_layout dim_layout
,
1269 enum isl_msaa_layout msaa_layout
,
1270 const struct isl_extent3d
*image_align_sa
,
1271 const struct isl_extent4d
*phys_level0_sa
,
1272 enum isl_array_pitch_span array_pitch_span
,
1273 uint32_t *array_pitch_el_rows
,
1274 struct isl_extent2d
*total_extent_el
)
1276 switch (dim_layout
) {
1277 case ISL_DIM_LAYOUT_GEN9_1D
:
1278 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1279 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1280 image_align_sa
, phys_level0_sa
,
1281 array_pitch_el_rows
,
1284 case ISL_DIM_LAYOUT_GEN4_2D
:
1285 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1286 image_align_sa
, phys_level0_sa
,
1288 array_pitch_el_rows
,
1291 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1292 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1293 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1296 array_pitch_el_rows
,
1299 case ISL_DIM_LAYOUT_GEN4_3D
:
1300 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1301 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1302 image_align_sa
, phys_level0_sa
,
1303 array_pitch_el_rows
,
1308 unreachable("invalid value for dim_layout");
1312 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1313 const struct isl_tile_info
*tile_info
)
1315 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1316 return tile_info
->phys_extent_B
.width
;
1318 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1319 * RENDER_SURFACE_STATE Surface Pitch (p349):
1321 * - For linear render target surfaces and surfaces accessed with the
1322 * typed data port messages, the pitch must be a multiple of the
1323 * element size for non-YUV surface formats. Pitch must be
1324 * a multiple of 2 * element size for YUV surface formats.
1326 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1327 * ignore because isl doesn't do buffers.]
1329 * - For other linear surfaces, the pitch can be any multiple of
1332 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1333 const uint32_t bs
= fmtl
->bpb
/ 8;
1335 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1336 if (isl_format_is_yuv(surf_info
->format
)) {
1347 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1348 const struct isl_surf_init_info
*info
,
1349 const struct isl_extent2d
*phys_total_el
,
1350 uint32_t alignment_B
)
1352 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1353 const uint32_t bs
= fmtl
->bpb
/ 8;
1355 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1359 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1360 const struct isl_surf_init_info
*surf_info
,
1361 const struct isl_tile_info
*tile_info
,
1362 const struct isl_extent2d
*phys_total_el
,
1363 uint32_t alignment_B
)
1365 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1367 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1369 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1370 const uint32_t total_w_tl
=
1371 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1372 tile_info
->logical_extent_el
.width
);
1374 assert(alignment_B
== tile_info
->phys_extent_B
.width
);
1375 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1379 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1380 const struct isl_surf_init_info
*surf_info
,
1381 const struct isl_tile_info
*tile_info
,
1382 const struct isl_extent2d
*phys_total_el
,
1383 uint32_t alignment_B
)
1385 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1386 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1389 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1390 phys_total_el
, alignment_B
);
1395 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1396 * size is `bits` bits?
1398 * Hardware pitch fields are offset by 1. For example, if the size of
1399 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1400 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1401 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1404 pitch_in_range(uint32_t n
, uint32_t bits
)
1407 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1411 isl_calc_row_pitch(const struct isl_device
*dev
,
1412 const struct isl_surf_init_info
*surf_info
,
1413 const struct isl_tile_info
*tile_info
,
1414 enum isl_dim_layout dim_layout
,
1415 const struct isl_extent2d
*phys_total_el
,
1416 uint32_t *out_row_pitch_B
)
1418 uint32_t alignment_B
=
1419 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1421 const uint32_t min_row_pitch_B
=
1422 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1425 if (surf_info
->row_pitch_B
!= 0) {
1426 if (surf_info
->row_pitch_B
< min_row_pitch_B
)
1429 if (surf_info
->row_pitch_B
% alignment_B
!= 0)
1433 const uint32_t row_pitch_B
=
1434 surf_info
->row_pitch_B
!= 0 ?
1435 surf_info
->row_pitch_B
:
1436 /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches
1437 * must be 512B-aligned.
1439 ISL_DEV_GEN(dev
) >= 12 &&
1440 isl_format_supports_ccs_e(dev
->info
, surf_info
->format
) ?
1441 isl_align(min_row_pitch_B
, 512) :
1445 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1447 if (row_pitch_B
== 0)
1450 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1451 /* SurfacePitch is ignored for this layout. */
1455 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1456 ISL_SURF_USAGE_TEXTURE_BIT
|
1457 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1458 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1461 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1462 ISL_SURF_USAGE_MCS_BIT
)) &&
1463 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1466 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1467 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1470 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1471 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1474 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1475 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1476 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1478 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1479 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1483 *out_row_pitch_B
= row_pitch_B
;
1488 isl_surf_init_s(const struct isl_device
*dev
,
1489 struct isl_surf
*surf
,
1490 const struct isl_surf_init_info
*restrict info
)
1492 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1494 const struct isl_extent4d logical_level0_px
= {
1498 .a
= info
->array_len
,
1501 enum isl_tiling tiling
;
1502 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1505 struct isl_tile_info tile_info
;
1506 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1508 const enum isl_dim_layout dim_layout
=
1509 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1511 enum isl_msaa_layout msaa_layout
;
1512 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1515 struct isl_extent3d image_align_el
;
1516 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1519 struct isl_extent3d image_align_sa
=
1520 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1522 struct isl_extent4d phys_level0_sa
;
1523 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1526 enum isl_array_pitch_span array_pitch_span
=
1527 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1529 uint32_t array_pitch_el_rows
;
1530 struct isl_extent2d phys_total_el
;
1531 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1532 dim_layout
, msaa_layout
,
1533 &image_align_sa
, &phys_level0_sa
,
1534 array_pitch_span
, &array_pitch_el_rows
,
1537 uint32_t row_pitch_B
;
1538 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1539 &phys_total_el
, &row_pitch_B
))
1542 uint32_t base_alignment_B
;
1544 if (tiling
== ISL_TILING_LINEAR
) {
1545 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1547 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1549 * "The Base Address for linear render target surfaces and surfaces
1550 * accessed with the typed surface read/write data port messages must
1551 * be element-size aligned, for non-YUV surface formats, or a
1552 * multiple of 2 element-sizes for YUV surface formats. Other linear
1553 * surfaces have no alignment requirements (byte alignment is
1556 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1557 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1558 if (isl_format_is_yuv(info
->format
)) {
1559 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1561 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1564 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1566 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1568 * "For Linear memory, this field specifies the stride in chunks of
1569 * 64 bytes (1 cache line)."
1571 if (isl_surf_usage_is_display(info
->usage
))
1572 base_alignment_B
= MAX(base_alignment_B
, 64);
1574 const uint32_t total_h_tl
=
1575 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1577 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1579 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1580 tile_info
.phys_extent_B
.height
;
1581 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1582 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1584 /* The diagram in the Bspec section Memory Compression - Gen12, shows
1585 * that the CCS is indexed in 256B chunks. However, the
1586 * PLANE_AUX_DIST::Auxiliary Surface Distance field is in units of 4K
1587 * pages. We currently don't assign the usage field like we do for main
1588 * surfaces, so just use 4K for now.
1590 if (tiling
== ISL_TILING_GEN12_CCS
)
1591 base_alignment_B
= MAX(base_alignment_B
, 4096);
1594 if (ISL_DEV_GEN(dev
) >= 12) {
1595 base_alignment_B
= MAX(base_alignment_B
, 64 * 1024);
1598 if (ISL_DEV_GEN(dev
) < 9) {
1599 /* From the Broadwell PRM Vol 5, Surface Layout:
1601 * "In addition to restrictions on maximum height, width, and depth,
1602 * surfaces are also restricted to a maximum size in bytes. This
1603 * maximum is 2 GB for all products and all surface types."
1605 * This comment is applicable to all Pre-gen9 platforms.
1607 if (size_B
> (uint64_t) 1 << 31)
1609 } else if (ISL_DEV_GEN(dev
) < 11) {
1610 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1611 * "In addition to restrictions on maximum height, width, and depth,
1612 * surfaces are also restricted to a maximum size of 2^38 bytes.
1613 * All pixels within the surface must be contained within 2^38 bytes
1614 * of the base address."
1616 if (size_B
> (uint64_t) 1 << 38)
1619 /* gen11+ platforms raised this limit to 2^44 bytes. */
1620 if (size_B
> (uint64_t) 1 << 44)
1624 *surf
= (struct isl_surf
) {
1626 .dim_layout
= dim_layout
,
1627 .msaa_layout
= msaa_layout
,
1629 .format
= info
->format
,
1631 .levels
= info
->levels
,
1632 .samples
= info
->samples
,
1634 .image_alignment_el
= image_align_el
,
1635 .logical_level0_px
= logical_level0_px
,
1636 .phys_level0_sa
= phys_level0_sa
,
1639 .alignment_B
= base_alignment_B
,
1640 .row_pitch_B
= row_pitch_B
,
1641 .array_pitch_el_rows
= array_pitch_el_rows
,
1642 .array_pitch_span
= array_pitch_span
,
1644 .usage
= info
->usage
,
1651 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1652 struct isl_tile_info
*tile_info
)
1654 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1655 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1659 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1660 const struct isl_surf
*surf
,
1661 struct isl_surf
*hiz_surf
)
1663 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1665 if (!isl_surf_usage_is_depth(surf
->usage
))
1668 /* HiZ only works with Y-tiled depth buffers */
1669 if (!isl_tiling_is_any_y(surf
->tiling
))
1672 /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
1673 switch (surf
->format
) {
1674 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1675 if (isl_surf_usage_is_depth_and_stencil(surf
->usage
)) {
1676 assert(ISL_DEV_GEN(dev
) == 5);
1677 unreachable("This should work, but is untested");
1680 case ISL_FORMAT_R16_UNORM
:
1681 case ISL_FORMAT_R32_FLOAT
:
1683 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1684 if (ISL_DEV_GEN(dev
) == 5) {
1685 assert(isl_surf_usage_is_depth_and_stencil(surf
->usage
));
1686 unreachable("This should work, but is untested");
1693 /* Multisampled depth is always interleaved */
1694 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1695 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1697 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1699 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1700 * Target View Extent, and Depth Coordinate Offset X/Y of the
1701 * hierarchical depth buffer are inherited from the depth buffer. The
1702 * height and width of the hierarchical depth buffer that must be
1703 * allocated are computed by the following formulas, where HZ is the
1704 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1705 * Z_Width, and Z_Depth values given in these formulas are those present
1706 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1708 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1709 * being applied to the table below if Number of Multisamples is set to
1710 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1711 * Z_Width must be multiplied by 4 before being applied to the table
1712 * below if Number of Multisamples is set to NUMSAMPLES_8."
1714 * In the Sky Lake PRM, the second paragraph is replaced with this:
1716 * "The Z_Height and Z_Width values must equal those present in
1717 * 3DSTATE_DEPTH_BUFFER incremented by one."
1719 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1720 * block corresponds to a region of 8x4 samples in the primary depth
1721 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1722 * a region of 8x4 pixels in the primary depth surface regardless of the
1723 * number of samples. The dimensions of a HiZ block in both pixels and
1724 * samples are given in the table below:
1726 * | SNB - BDW | SKL+
1727 * ------+-----------+-------------
1728 * 1x | 8 x 4 sa | 8 x 4 sa
1729 * MSAA | 8 x 4 px | 8 x 4 px
1730 * ------+-----------+-------------
1731 * 2x | 8 x 4 sa | 16 x 4 sa
1732 * MSAA | 4 x 4 px | 8 x 4 px
1733 * ------+-----------+-------------
1734 * 4x | 8 x 4 sa | 16 x 8 sa
1735 * MSAA | 4 x 2 px | 8 x 4 px
1736 * ------+-----------+-------------
1737 * 8x | 8 x 4 sa | 32 x 8 sa
1738 * MSAA | 2 x 2 px | 8 x 4 px
1739 * ------+-----------+-------------
1740 * 16x | N/A | 32 x 16 sa
1741 * MSAA | N/A | 8 x 4 px
1742 * ------+-----------+-------------
1744 * There are a number of different ways that this discrepency could be
1745 * handled. The way we have chosen is to simply make MSAA HiZ have the
1746 * same number of samples as the parent surface pre-Sky Lake and always be
1747 * single-sampled on Sky Lake and above. Since the block sizes of
1748 * compressed formats are given in samples, this neatly handles everything
1749 * without the need for additional HiZ formats with different block sizes
1752 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1754 return isl_surf_init(dev
, hiz_surf
,
1756 .format
= ISL_FORMAT_HIZ
,
1757 .width
= surf
->logical_level0_px
.width
,
1758 .height
= surf
->logical_level0_px
.height
,
1759 .depth
= surf
->logical_level0_px
.depth
,
1760 .levels
= surf
->levels
,
1761 .array_len
= surf
->logical_level0_px
.array_len
,
1763 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1764 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1768 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1769 const struct isl_surf
*surf
,
1770 struct isl_surf
*mcs_surf
)
1772 /* It must be multisampled with an array layout */
1773 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_ARRAY
)
1776 if (mcs_surf
->size_B
> 0)
1779 /* The following are true of all multisampled surfaces */
1780 assert(surf
->samples
> 1);
1781 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1782 assert(surf
->levels
== 1);
1783 assert(surf
->logical_level0_px
.depth
== 1);
1785 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
1787 * This field must be set to 0 for all SINT MSRTs when all RT channels
1790 * In practice this means that we have to disable MCS for all signed
1791 * integer MSAA buffers. The alternative, to disable MCS only when one
1792 * of the render target channels is disabled, is impractical because it
1793 * would require converting between CMS and UMS MSAA layouts on the fly,
1794 * which is expensive.
1796 if (ISL_DEV_GEN(dev
) == 7 && isl_format_has_sint_channel(surf
->format
))
1799 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1800 * bits which means the maximum pitch of a compression surface is 512
1801 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1802 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1803 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1804 * and 8x, we have enough room for the full 16k supported by the hardware.
1806 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1809 enum isl_format mcs_format
;
1810 switch (surf
->samples
) {
1811 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1812 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1813 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1814 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1816 unreachable("Invalid sample count");
1819 return isl_surf_init(dev
, mcs_surf
,
1820 .dim
= ISL_SURF_DIM_2D
,
1821 .format
= mcs_format
,
1822 .width
= surf
->logical_level0_px
.width
,
1823 .height
= surf
->logical_level0_px
.height
,
1826 .array_len
= surf
->logical_level0_px
.array_len
,
1827 .samples
= 1, /* MCS surfaces are really single-sampled */
1828 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1829 .tiling_flags
= ISL_TILING_Y0_BIT
);
1833 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1834 const struct isl_surf
*surf
,
1835 struct isl_surf
*aux_surf
,
1836 struct isl_surf
*extra_aux_surf
,
1837 uint32_t row_pitch_B
)
1841 /* An uninitialized surface is needed to get a CCS surface. */
1842 if (aux_surf
->size_B
> 0 &&
1843 (extra_aux_surf
== NULL
|| extra_aux_surf
->size_B
> 0)) {
1847 /* A surface can't have two CCS surfaces. */
1848 if (aux_surf
->usage
& ISL_SURF_USAGE_CCS_BIT
)
1851 /* Only multisampled depth buffers with HiZ can have CCS. */
1852 if (surf
->samples
> 1 && !(aux_surf
->usage
& ISL_SURF_USAGE_HIZ_BIT
))
1855 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1856 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1858 /* CCS support does not exist prior to Gen7 */
1859 if (ISL_DEV_GEN(dev
) <= 6)
1862 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1865 /* Callers don't yet support this configuration. */
1866 if (isl_surf_usage_is_stencil(surf
->usage
))
1869 /* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if it
1870 * has HiZ. If not for GEN:BUG:1406512483 "deprecate compression enable
1871 * states", D16 would be supported. Supporting D16 requires being able to
1872 * specify that the control surface is present and simultaneously disabling
1873 * compression. The above bug makes it so that it's not possible to specify
1874 * this configuration.
1876 if (isl_surf_usage_is_depth(surf
->usage
) && (aux_surf
->size_B
== 0 ||
1877 ISL_DEV_GEN(dev
) < 12 || surf
->format
== ISL_FORMAT_R16_UNORM
)) {
1881 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1882 * work for 3D textures until gen9 where the layout of 3D textures changes
1883 * to match 2D array textures.
1885 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1888 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1889 * Non-MultiSampler Render Target Restrictions):
1891 * "Support is for non-mip-mapped and non-array surface types only."
1893 * This restriction is lifted on gen8+. Technically, it may be possible to
1894 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1895 * when rendering to the base slice. However, there is no documentation
1896 * tell us what the hardware would do in that case or what it does if you
1897 * walk off the bases slice. (Does it ignore CCS or does it start
1898 * scribbling over random memory?) We play it safe and just follow the
1899 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1901 if (ISL_DEV_GEN(dev
) <= 7 &&
1902 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1905 /* On Gen12, 8BPP surfaces cannot be compressed if any level is not
1906 * 32Bx4row-aligned. For now, just reject the cases where alignment
1909 if (ISL_DEV_GEN(dev
) >= 12 &&
1910 isl_format_get_layout(surf
->format
)->bpb
== 8 && surf
->levels
>= 3) {
1911 isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
1912 "disabled, but support for more levels is possible.",
1913 __FILE__
, __func__
);
1917 /* On Gen12, all CCS-compressed surface pitches must be multiples of 512B.
1919 if (ISL_DEV_GEN(dev
) >= 12 && surf
->row_pitch_B
% 512 != 0)
1922 if (isl_format_is_compressed(surf
->format
))
1925 /* According to GEN:BUG:1406738321, 3D textures need a blit to a new
1926 * surface in order to perform a resolve. For now, just disable CCS.
1928 if (ISL_DEV_GEN(dev
) >= 12 && surf
->dim
== ISL_SURF_DIM_3D
) {
1929 isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
1930 " is available.", __FILE__
, __func__
);
1934 /* TODO: More conditions where it can fail. */
1936 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
1937 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
1939 * - Support is limited to tiled render targets.
1940 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
1941 * 64bpp, and 128bpp.
1943 * From the Skylake documentation, it is made clear that X-tiling is no
1946 * - MCS and Lossless compression is supported for
1947 * TiledY/TileYs/TileYf non-MSRTs only.
1949 enum isl_format ccs_format
;
1950 if (ISL_DEV_GEN(dev
) >= 12) {
1951 /* TODO: Handle the other tiling formats */
1952 if (surf
->tiling
!= ISL_TILING_Y0
)
1955 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1956 case 8: ccs_format
= ISL_FORMAT_GEN12_CCS_8BPP_Y0
; break;
1957 case 16: ccs_format
= ISL_FORMAT_GEN12_CCS_16BPP_Y0
; break;
1958 case 32: ccs_format
= ISL_FORMAT_GEN12_CCS_32BPP_Y0
; break;
1959 case 64: ccs_format
= ISL_FORMAT_GEN12_CCS_64BPP_Y0
; break;
1960 case 128: ccs_format
= ISL_FORMAT_GEN12_CCS_128BPP_Y0
; break;
1964 } else if (ISL_DEV_GEN(dev
) >= 9) {
1965 if (!isl_tiling_is_any_y(surf
->tiling
))
1968 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1969 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1970 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1971 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1975 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1976 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1977 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1978 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1979 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1983 } else if (surf
->tiling
== ISL_TILING_X
) {
1984 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1985 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1986 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1987 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1995 if (ISL_DEV_GEN(dev
) >= 12) {
1996 /* On Gen12, the CCS is a scaled-down version of the main surface. We
1997 * model this as the CCS compressing a 2D-view of the entire surface.
1999 struct isl_surf
*ccs_surf
=
2000 aux_surf
->size_B
> 0 ? extra_aux_surf
: aux_surf
;
2002 isl_surf_init(dev
, ccs_surf
,
2003 .dim
= ISL_SURF_DIM_2D
,
2004 .format
= ccs_format
,
2005 .width
= isl_surf_get_row_pitch_el(surf
),
2006 .height
= surf
->size_B
/ surf
->row_pitch_B
,
2011 .row_pitch_B
= row_pitch_B
,
2012 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2013 .tiling_flags
= ISL_TILING_GEN12_CCS_BIT
);
2014 assert(!ok
|| ccs_surf
->size_B
== surf
->size_B
/ 256);
2017 return isl_surf_init(dev
, aux_surf
,
2019 .format
= ccs_format
,
2020 .width
= surf
->logical_level0_px
.width
,
2021 .height
= surf
->logical_level0_px
.height
,
2022 .depth
= surf
->logical_level0_px
.depth
,
2023 .levels
= surf
->levels
,
2024 .array_len
= surf
->logical_level0_px
.array_len
,
2026 .row_pitch_B
= row_pitch_B
,
2027 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2028 .tiling_flags
= ISL_TILING_CCS_BIT
);
2032 #define isl_genX_call(dev, func, ...) \
2033 switch (ISL_DEV_GEN(dev)) { \
2035 /* G45 surface state is the same as gen5 */ \
2036 if (ISL_DEV_IS_G4X(dev)) { \
2037 isl_gen5_##func(__VA_ARGS__); \
2039 isl_gen4_##func(__VA_ARGS__); \
2043 isl_gen5_##func(__VA_ARGS__); \
2046 isl_gen6_##func(__VA_ARGS__); \
2049 if (ISL_DEV_IS_HASWELL(dev)) { \
2050 isl_gen75_##func(__VA_ARGS__); \
2052 isl_gen7_##func(__VA_ARGS__); \
2056 isl_gen8_##func(__VA_ARGS__); \
2059 isl_gen9_##func(__VA_ARGS__); \
2062 isl_gen10_##func(__VA_ARGS__); \
2065 isl_gen11_##func(__VA_ARGS__); \
2068 isl_gen12_##func(__VA_ARGS__); \
2071 assert(!"Unknown hardware generation"); \
2075 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
2076 const struct isl_surf_fill_state_info
*restrict info
)
2079 isl_surf_usage_flags_t _base_usage
=
2080 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
2081 ISL_SURF_USAGE_TEXTURE_BIT
|
2082 ISL_SURF_USAGE_STORAGE_BIT
);
2083 /* They may only specify one of the above bits at a time */
2084 assert(__builtin_popcount(_base_usage
) == 1);
2085 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
2086 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
2089 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
2090 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2091 info
->surf
->logical_level0_px
.depth
);
2093 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2094 info
->surf
->logical_level0_px
.array_len
);
2097 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
2101 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
2102 const struct isl_buffer_fill_state_info
*restrict info
)
2104 isl_genX_call(dev
, buffer_fill_state_s
, state
, info
);
2108 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
2109 struct isl_extent3d size
)
2111 isl_genX_call(dev
, null_fill_state
, state
, size
);
2115 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
2116 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
2118 if (info
->depth_surf
&& info
->stencil_surf
) {
2119 if (!dev
->info
->has_hiz_and_separate_stencil
) {
2120 assert(info
->depth_surf
== info
->stencil_surf
);
2121 assert(info
->depth_address
== info
->stencil_address
);
2123 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
2126 if (info
->depth_surf
) {
2127 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
2128 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
2129 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2130 info
->depth_surf
->logical_level0_px
.depth
);
2132 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2133 info
->depth_surf
->logical_level0_px
.array_len
);
2137 if (info
->stencil_surf
) {
2138 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
2139 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
2140 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2141 info
->stencil_surf
->logical_level0_px
.depth
);
2143 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2144 info
->stencil_surf
->logical_level0_px
.array_len
);
2148 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
2152 * A variant of isl_surf_get_image_offset_sa() specific to
2153 * ISL_DIM_LAYOUT_GEN4_2D.
2156 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
2157 uint32_t level
, uint32_t logical_array_layer
,
2158 uint32_t *x_offset_sa
,
2159 uint32_t *y_offset_sa
)
2161 assert(level
< surf
->levels
);
2162 if (surf
->dim
== ISL_SURF_DIM_3D
)
2163 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2165 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2167 const struct isl_extent3d image_align_sa
=
2168 isl_surf_get_image_alignment_sa(surf
);
2170 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2171 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2173 const uint32_t phys_layer
= logical_array_layer
*
2174 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2177 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2179 for (uint32_t l
= 0; l
< level
; ++l
) {
2181 uint32_t W
= isl_minify(W0
, l
);
2182 x
+= isl_align_npot(W
, image_align_sa
.w
);
2184 uint32_t H
= isl_minify(H0
, l
);
2185 y
+= isl_align_npot(H
, image_align_sa
.h
);
2194 * A variant of isl_surf_get_image_offset_sa() specific to
2195 * ISL_DIM_LAYOUT_GEN4_3D.
2198 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2199 uint32_t level
, uint32_t logical_z_offset_px
,
2200 uint32_t *x_offset_sa
,
2201 uint32_t *y_offset_sa
)
2203 assert(level
< surf
->levels
);
2204 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2205 assert(surf
->phys_level0_sa
.array_len
== 1);
2206 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2208 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2209 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2210 assert(surf
->phys_level0_sa
.array_len
== 6);
2211 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2214 const struct isl_extent3d image_align_sa
=
2215 isl_surf_get_image_alignment_sa(surf
);
2217 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2218 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2219 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2220 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2225 for (uint32_t l
= 0; l
< level
; ++l
) {
2226 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2227 const uint32_t level_d
=
2228 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2230 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2232 y
+= level_h
* max_layers_vert
;
2235 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2236 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2237 const uint32_t level_d
=
2238 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2241 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2243 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2244 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2251 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2253 uint32_t logical_array_layer
,
2254 uint32_t *x_offset_sa
,
2255 uint32_t *y_offset_sa
)
2257 assert(level
< surf
->levels
);
2258 assert(surf
->logical_level0_px
.depth
== 1);
2259 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2261 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2263 const struct isl_extent3d image_align_sa
=
2264 isl_surf_get_image_alignment_sa(surf
);
2266 struct isl_tile_info tile_info
;
2267 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2268 const struct isl_extent2d tile_extent_sa
= {
2269 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2270 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2272 /* Tile size is a multiple of image alignment */
2273 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2274 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2276 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2277 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2279 /* Each image has the same height as LOD0 because the hardware thinks
2280 * everything is LOD0
2282 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2284 /* Quick sanity check for consistency */
2285 if (surf
->phys_level0_sa
.array_len
> 1)
2286 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2288 uint32_t x
= 0, y
= 0;
2289 for (uint32_t l
= 0; l
< level
; ++l
) {
2290 const uint32_t W
= isl_minify(W0
, l
);
2292 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2293 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2303 y
+= H
* logical_array_layer
;
2310 * A variant of isl_surf_get_image_offset_sa() specific to
2311 * ISL_DIM_LAYOUT_GEN9_1D.
2314 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2315 uint32_t level
, uint32_t layer
,
2316 uint32_t *x_offset_sa
,
2317 uint32_t *y_offset_sa
)
2319 assert(level
< surf
->levels
);
2320 assert(layer
< surf
->phys_level0_sa
.array_len
);
2321 assert(surf
->phys_level0_sa
.height
== 1);
2322 assert(surf
->phys_level0_sa
.depth
== 1);
2323 assert(surf
->samples
== 1);
2325 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2326 const struct isl_extent3d image_align_sa
=
2327 isl_surf_get_image_alignment_sa(surf
);
2331 for (uint32_t l
= 0; l
< level
; ++l
) {
2332 uint32_t W
= isl_minify(W0
, l
);
2333 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2339 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2343 * Calculate the offset, in units of surface samples, to a subimage in the
2346 * @invariant level < surface levels
2347 * @invariant logical_array_layer < logical array length of surface
2348 * @invariant logical_z_offset_px < logical depth of surface at level
2351 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2353 uint32_t logical_array_layer
,
2354 uint32_t logical_z_offset_px
,
2355 uint32_t *x_offset_sa
,
2356 uint32_t *y_offset_sa
)
2358 assert(level
< surf
->levels
);
2359 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2360 assert(logical_z_offset_px
2361 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2363 switch (surf
->dim_layout
) {
2364 case ISL_DIM_LAYOUT_GEN9_1D
:
2365 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2366 x_offset_sa
, y_offset_sa
);
2368 case ISL_DIM_LAYOUT_GEN4_2D
:
2369 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2370 + logical_z_offset_px
,
2371 x_offset_sa
, y_offset_sa
);
2373 case ISL_DIM_LAYOUT_GEN4_3D
:
2374 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2375 logical_z_offset_px
,
2376 x_offset_sa
, y_offset_sa
);
2378 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2379 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2380 logical_z_offset_px
,
2381 x_offset_sa
, y_offset_sa
);
2385 unreachable("not reached");
2390 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2392 uint32_t logical_array_layer
,
2393 uint32_t logical_z_offset_px
,
2394 uint32_t *x_offset_el
,
2395 uint32_t *y_offset_el
)
2397 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2399 assert(level
< surf
->levels
);
2400 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2401 assert(logical_z_offset_px
2402 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2404 uint32_t x_offset_sa
, y_offset_sa
;
2405 isl_surf_get_image_offset_sa(surf
, level
,
2406 logical_array_layer
,
2407 logical_z_offset_px
,
2411 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2412 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2416 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2418 uint32_t logical_array_layer
,
2419 uint32_t logical_z_offset_px
,
2421 uint32_t *x_offset_sa
,
2422 uint32_t *y_offset_sa
)
2424 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2426 uint32_t total_x_offset_el
, total_y_offset_el
;
2427 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2428 logical_z_offset_px
,
2430 &total_y_offset_el
);
2432 uint32_t x_offset_el
, y_offset_el
;
2433 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2442 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2444 assert(x_offset_el
== 0);
2448 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2450 assert(y_offset_el
== 0);
2455 isl_surf_get_image_surf(const struct isl_device
*dev
,
2456 const struct isl_surf
*surf
,
2458 uint32_t logical_array_layer
,
2459 uint32_t logical_z_offset_px
,
2460 struct isl_surf
*image_surf
,
2462 uint32_t *x_offset_sa
,
2463 uint32_t *y_offset_sa
)
2465 isl_surf_get_image_offset_B_tile_sa(surf
,
2467 logical_array_layer
,
2468 logical_z_offset_px
,
2473 /* Even for cube maps there will be only single face, therefore drop the
2474 * corresponding flag if present.
2476 const isl_surf_usage_flags_t usage
=
2477 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2480 ok
= isl_surf_init(dev
, image_surf
,
2481 .dim
= ISL_SURF_DIM_2D
,
2482 .format
= surf
->format
,
2483 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2484 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2488 .samples
= surf
->samples
,
2489 .row_pitch_B
= surf
->row_pitch_B
,
2491 .tiling_flags
= (1 << surf
->tiling
));
2496 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2498 uint32_t row_pitch_B
,
2499 uint32_t total_x_offset_el
,
2500 uint32_t total_y_offset_el
,
2501 uint32_t *base_address_offset
,
2502 uint32_t *x_offset_el
,
2503 uint32_t *y_offset_el
)
2505 if (tiling
== ISL_TILING_LINEAR
) {
2506 assert(bpb
% 8 == 0);
2507 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2508 total_x_offset_el
* (bpb
/ 8);
2514 struct isl_tile_info tile_info
;
2515 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2517 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2519 /* For non-power-of-two formats, we need the address to be both tile and
2520 * element-aligned. The easiest way to achieve this is to work with a tile
2521 * that is three times as wide as the regular tile.
2523 * The tile info returned by get_tile_info has a logical size that is an
2524 * integer number of tile_info.format_bpb size elements. To scale the
2525 * tile, we scale up the physical width and then treat the logical tile
2526 * size as if it has bpb size elements.
2528 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2529 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2531 /* Compute the offset into the tile */
2532 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2533 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2535 /* Compute the offset of the tile in units of whole tiles */
2536 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2537 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2539 *base_address_offset
=
2540 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2541 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2545 isl_surf_get_depth_format(const struct isl_device
*dev
,
2546 const struct isl_surf
*surf
)
2548 /* Support for separate stencil buffers began in gen5. Support for
2549 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2550 * those that supported separate and interleaved stencil, were gen5 and
2553 * For a list of all available formats, see the Sandybridge PRM >> Volume
2554 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2558 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2560 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2563 assert(ISL_DEV_GEN(dev
) < 7);
2565 switch (surf
->format
) {
2567 unreachable("bad isl depth format");
2568 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2569 assert(ISL_DEV_GEN(dev
) < 7);
2570 return 0; /* D32_FLOAT_S8X24_UINT */
2571 case ISL_FORMAT_R32_FLOAT
:
2572 assert(!has_stencil
);
2573 return 1; /* D32_FLOAT */
2574 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2576 assert(ISL_DEV_GEN(dev
) < 7);
2577 return 2; /* D24_UNORM_S8_UINT */
2579 assert(ISL_DEV_GEN(dev
) >= 5);
2580 return 3; /* D24_UNORM_X8_UINT */
2582 case ISL_FORMAT_R16_UNORM
:
2583 assert(!has_stencil
);
2584 return 5; /* D16_UNORM */
2589 isl_surf_supports_hiz_ccs_wt(const struct gen_device_info
*dev
,
2590 const struct isl_surf
*surf
,
2591 enum isl_aux_usage aux_usage
)
2593 return aux_usage
== ISL_AUX_USAGE_HIZ_CCS
&&
2594 surf
->samples
== 1 &&
2595 surf
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
;
2599 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2600 struct isl_swizzle swizzle
)
2602 if (devinfo
->is_haswell
) {
2603 /* From the Haswell PRM,
2604 * RENDER_SURFACE_STATE::Shader Channel Select Red
2606 * "The Shader channel selects also define which shader channels are
2607 * written to which surface channel. If the Shader channel select is
2608 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2609 * shader channel select is SCS_RED it is written to the surface red
2610 * channel and so on. If more than one shader channel select is set
2611 * to the same surface channel only the first shader channel in RGBA
2612 * order will be written."
2615 } else if (devinfo
->gen
<= 7) {
2616 /* Ivy Bridge and early doesn't have any swizzling */
2617 return isl_swizzle_is_identity(swizzle
);
2619 /* From the Sky Lake PRM Vol. 2d,
2620 * RENDER_SURFACE_STATE::Shader Channel Select Red
2622 * "For Render Target, Red, Green and Blue Shader Channel Selects
2623 * MUST be such that only valid components can be swapped i.e. only
2624 * change the order of components in the pixel. Any other values for
2625 * these Shader Channel Select fields are not valid for Render
2626 * Targets. This also means that there MUST not be multiple shader
2627 * channels mapped to the same RT channel."
2629 * From the Sky Lake PRM Vol. 2d,
2630 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2632 * "For Render Target, this field MUST be programmed to
2633 * value = SCS_ALPHA."
2635 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2636 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2637 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2638 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2639 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2640 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2641 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2642 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2643 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2644 swizzle
.r
!= swizzle
.g
&&
2645 swizzle
.r
!= swizzle
.b
&&
2646 swizzle
.g
!= swizzle
.b
&&
2647 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2651 static enum isl_channel_select
2652 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2655 case ISL_CHANNEL_SELECT_ZERO
:
2656 case ISL_CHANNEL_SELECT_ONE
:
2658 case ISL_CHANNEL_SELECT_RED
:
2660 case ISL_CHANNEL_SELECT_GREEN
:
2662 case ISL_CHANNEL_SELECT_BLUE
:
2664 case ISL_CHANNEL_SELECT_ALPHA
:
2667 unreachable("Invalid swizzle component");
2672 * Returns the single swizzle that is equivalent to applying the two given
2673 * swizzles in sequence.
2676 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2678 return (struct isl_swizzle
) {
2679 .r
= swizzle_select(first
.r
, second
),
2680 .g
= swizzle_select(first
.g
, second
),
2681 .b
= swizzle_select(first
.b
, second
),
2682 .a
= swizzle_select(first
.a
, second
),
2687 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2690 isl_swizzle_invert(struct isl_swizzle swizzle
)
2692 /* Default to zero for channels which do not show up in the swizzle */
2693 enum isl_channel_select chans
[4] = {
2694 ISL_CHANNEL_SELECT_ZERO
,
2695 ISL_CHANNEL_SELECT_ZERO
,
2696 ISL_CHANNEL_SELECT_ZERO
,
2697 ISL_CHANNEL_SELECT_ZERO
,
2700 /* We go in ABGR order so that, if there are any duplicates, the first one
2701 * is taken if you look at it in RGBA order. This is what Haswell hardware
2702 * does for render target swizzles.
2704 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2705 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2706 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2707 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2708 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2709 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2710 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2711 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2713 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };