2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
36 #include "isl_gen12.h"
40 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
41 uint32_t yt1
, uint32_t yt2
,
42 char *dst
, const char *src
,
43 uint32_t dst_pitch
, int32_t src_pitch
,
45 enum isl_tiling tiling
,
46 isl_memcpy_type copy_type
)
49 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
50 _isl_memcpy_linear_to_tiled_sse41(
51 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
57 _isl_memcpy_linear_to_tiled(
58 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
63 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
64 uint32_t yt1
, uint32_t yt2
,
65 char *dst
, const char *src
,
66 int32_t dst_pitch
, uint32_t src_pitch
,
68 enum isl_tiling tiling
,
69 isl_memcpy_type copy_type
)
72 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
73 _isl_memcpy_tiled_to_linear_sse41(
74 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
80 _isl_memcpy_tiled_to_linear(
81 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
85 void PRINTFLIKE(3, 4) UNUSED
86 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
92 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
95 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
99 isl_device_setup_mocs(struct isl_device
*dev
)
101 if (dev
->info
->gen
>= 12) {
102 if (dev
->info
->is_dg1
) {
104 dev
->mocs
.internal
= 5 << 1;
105 /* Displayables on DG1 are free to cache in L3 since L3 is transient
106 * and flushed at bottom of each submission.
108 dev
->mocs
.external
= 5 << 1;
110 /* TODO: Set PTE to MOCS 61 when the kernel is ready */
111 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
112 dev
->mocs
.external
= 3 << 1;
113 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
114 dev
->mocs
.internal
= 2 << 1;
116 } else if (dev
->info
->gen
>= 9) {
117 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
118 dev
->mocs
.external
= 1 << 1;
119 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
120 dev
->mocs
.internal
= 2 << 1;
121 } else if (dev
->info
->gen
>= 8) {
122 /* MEMORY_OBJECT_CONTROL_STATE:
123 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
124 * .TargetCache = L3DefertoPATforLLCeLLCselection,
127 dev
->mocs
.external
= 0x18;
128 /* MEMORY_OBJECT_CONTROL_STATE:
129 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
130 * .TargetCache = L3DefertoPATforLLCeLLCselection,
133 dev
->mocs
.internal
= 0x78;
134 } else if (dev
->info
->gen
>= 7) {
135 if (dev
->info
->is_haswell
) {
136 /* MEMORY_OBJECT_CONTROL_STATE:
137 * .LLCeLLCCacheabilityControlLLCCC = 0,
138 * .L3CacheabilityControlL3CC = 1,
140 dev
->mocs
.internal
= 1;
141 dev
->mocs
.external
= 1;
143 /* MEMORY_OBJECT_CONTROL_STATE:
144 * .GraphicsDataTypeGFDT = 0,
145 * .LLCCacheabilityControlLLCCC = 0,
146 * .L3CacheabilityControlL3CC = 1,
148 dev
->mocs
.internal
= 1;
149 dev
->mocs
.external
= 1;
152 dev
->mocs
.internal
= 0;
153 dev
->mocs
.external
= 0;
158 isl_device_init(struct isl_device
*dev
,
159 const struct gen_device_info
*info
,
160 bool has_bit6_swizzling
)
162 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
163 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
166 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
167 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
169 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
170 * device properties at buildtime. Verify that the macros with the device
171 * properties chosen during runtime.
173 ISL_DEV_GEN_SANITIZE(dev
);
174 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
176 /* Did we break hiz or stencil? */
177 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
178 assert(info
->has_hiz_and_separate_stencil
);
179 if (info
->must_use_separate_stencil
)
180 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
182 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
183 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
185 dev
->ss
.clear_color_state_size
=
186 isl_align(CLEAR_COLOR_length(info
) * 4, 64);
187 dev
->ss
.clear_color_state_offset
=
188 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
190 dev
->ss
.clear_value_size
=
191 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
192 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
193 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
194 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
196 dev
->ss
.clear_value_offset
=
197 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
199 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
200 dev
->ss
.addr_offset
=
201 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
203 /* The "Auxiliary Surface Base Address" field starts a bit higher up
204 * because the bottom 12 bits are used for other things. Round down to
205 * the nearest dword before.
207 dev
->ss
.aux_addr_offset
=
208 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
210 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
211 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
212 dev
->ds
.depth_offset
=
213 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
215 if (dev
->use_separate_stencil
) {
216 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
217 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
218 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
220 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
221 dev
->ds
.stencil_offset
=
222 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
223 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
225 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
227 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
228 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
229 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
231 dev
->ds
.stencil_offset
= 0;
232 dev
->ds
.hiz_offset
= 0;
235 if (ISL_DEV_GEN(dev
) >= 12) {
236 dev
->ds
.size
+= GEN12_MI_LOAD_REGISTER_IMM_length
* 4 * 2;
239 isl_device_setup_mocs(dev
);
243 * @brief Query the set of multisamples supported by the device.
245 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
248 isl_sample_count_mask_t ATTRIBUTE_CONST
249 isl_device_get_sample_counts(struct isl_device
*dev
)
251 if (ISL_DEV_GEN(dev
) >= 9) {
252 return ISL_SAMPLE_COUNT_1_BIT
|
253 ISL_SAMPLE_COUNT_2_BIT
|
254 ISL_SAMPLE_COUNT_4_BIT
|
255 ISL_SAMPLE_COUNT_8_BIT
|
256 ISL_SAMPLE_COUNT_16_BIT
;
257 } else if (ISL_DEV_GEN(dev
) >= 8) {
258 return ISL_SAMPLE_COUNT_1_BIT
|
259 ISL_SAMPLE_COUNT_2_BIT
|
260 ISL_SAMPLE_COUNT_4_BIT
|
261 ISL_SAMPLE_COUNT_8_BIT
;
262 } else if (ISL_DEV_GEN(dev
) >= 7) {
263 return ISL_SAMPLE_COUNT_1_BIT
|
264 ISL_SAMPLE_COUNT_4_BIT
|
265 ISL_SAMPLE_COUNT_8_BIT
;
266 } else if (ISL_DEV_GEN(dev
) >= 6) {
267 return ISL_SAMPLE_COUNT_1_BIT
|
268 ISL_SAMPLE_COUNT_4_BIT
;
270 return ISL_SAMPLE_COUNT_1_BIT
;
275 * @param[out] info is written only on success
278 isl_tiling_get_info(enum isl_tiling tiling
,
280 struct isl_tile_info
*tile_info
)
282 const uint32_t bs
= format_bpb
/ 8;
283 struct isl_extent2d logical_el
, phys_B
;
285 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
286 /* It is possible to have non-power-of-two formats in a tiled buffer.
287 * The easiest way to handle this is to treat the tile as if it is three
288 * times as wide. This way no pixel will ever cross a tile boundary.
289 * This really only works on legacy X and Y tiling formats.
291 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
292 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
293 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
298 case ISL_TILING_LINEAR
:
300 logical_el
= isl_extent2d(1, 1);
301 phys_B
= isl_extent2d(bs
, 1);
306 logical_el
= isl_extent2d(512 / bs
, 8);
307 phys_B
= isl_extent2d(512, 8);
312 logical_el
= isl_extent2d(128 / bs
, 32);
313 phys_B
= isl_extent2d(128, 32);
318 logical_el
= isl_extent2d(64, 64);
319 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
321 * "If the surface is a stencil buffer (and thus has Tile Mode set
322 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
323 * computed based on width, as the stencil buffer is stored with two
326 * This, together with the fact that stencil buffers are referred to as
327 * being Y-tiled in the PRMs for older hardware implies that the
328 * physical size of a W-tile is actually the same as for a Y-tile.
330 phys_B
= isl_extent2d(128, 32);
334 case ISL_TILING_Ys
: {
335 bool is_Ys
= tiling
== ISL_TILING_Ys
;
338 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
339 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
341 logical_el
= isl_extent2d(width
/ bs
, height
);
342 phys_B
= isl_extent2d(width
, height
);
347 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
348 * 128bpb format. The tiling has the same physical dimensions as
349 * Y-tiling but actually has two HiZ columns per Y-tiled column.
352 logical_el
= isl_extent2d(16, 16);
353 phys_B
= isl_extent2d(128, 32);
357 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
358 * have a block size of 1 or 2 bits per block and each CCS element
359 * corresponds to one cache-line pair in the main surface. From the Sky
360 * Lake PRM Vol. 12 in the section on planes:
362 * "The Color Control Surface (CCS) contains the compression status
363 * of the cache-line pairs. The compression state of the cache-line
364 * pair is specified by 2 bits in the CCS. Each CCS cache-line
365 * represents an area on the main surface of 16x16 sets of 128 byte
366 * Y-tiled cache-line-pairs. CCS is always Y tiled."
368 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
369 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
370 * that yields total tile area of 128x128 cache-line pairs or CCS
371 * elements. On older hardware, each CCS element is 1 bit and the tile
372 * is 128x256 elements.
374 assert(format_bpb
== 1 || format_bpb
== 2);
375 logical_el
= isl_extent2d(128, 256 / format_bpb
);
376 phys_B
= isl_extent2d(128, 32);
379 case ISL_TILING_GEN12_CCS
:
380 /* From the Bspec, Gen Graphics > Gen12 > Memory Data Formats > Memory
381 * Compression > Memory Compression - Gen12:
383 * 4 bits of auxiliary plane data are required for 2 cachelines of
384 * main surface data. This results in a single cacheline of auxiliary
385 * plane data mapping to 4 4K pages of main surface data for the 4K
386 * pages (tile Y ) and 1 64K Tile Ys page.
388 * The Y-tiled pairing bit of 9 shown in the table below that Bspec
389 * section expresses that the 2 cachelines of main surface data are
390 * horizontally adjacent.
392 * TODO: Handle Ys, Yf and their pairing bits.
394 * Therefore, each CCS cacheline represents a 512Bx32 row area and each
395 * element represents a 32Bx4 row area.
397 assert(format_bpb
== 4);
398 logical_el
= isl_extent2d(16, 8);
399 phys_B
= isl_extent2d(64, 1);
403 unreachable("not reached");
406 *tile_info
= (struct isl_tile_info
) {
408 .format_bpb
= format_bpb
,
409 .logical_extent_el
= logical_el
,
410 .phys_extent_B
= phys_B
,
415 isl_color_value_is_zero(union isl_color_value value
,
416 enum isl_format format
)
418 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
420 #define RETURN_FALSE_IF_NOT_0(c, i) \
421 if (fmtl->channels.c.bits && value.u32[i] != 0) \
424 RETURN_FALSE_IF_NOT_0(r
, 0);
425 RETURN_FALSE_IF_NOT_0(g
, 1);
426 RETURN_FALSE_IF_NOT_0(b
, 2);
427 RETURN_FALSE_IF_NOT_0(a
, 3);
429 #undef RETURN_FALSE_IF_NOT_0
435 isl_color_value_is_zero_one(union isl_color_value value
,
436 enum isl_format format
)
438 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
440 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
441 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
444 if (isl_format_has_int_channel(format
)) {
445 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
446 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
447 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
448 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
450 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
451 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
452 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
453 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
456 #undef RETURN_FALSE_IF_NOT_0_1
462 * @param[out] tiling is set only on success
465 isl_surf_choose_tiling(const struct isl_device
*dev
,
466 const struct isl_surf_init_info
*restrict info
,
467 enum isl_tiling
*tiling
)
469 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
471 /* HiZ surfaces always use the HiZ tiling */
472 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
473 assert(info
->format
== ISL_FORMAT_HIZ
);
474 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
475 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
479 /* CCS surfaces always use the CCS tiling */
480 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
481 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
482 UNUSED
bool ivb_ccs
= ISL_DEV_GEN(dev
) < 12 &&
483 tiling_flags
== ISL_TILING_CCS_BIT
;
484 UNUSED
bool tgl_ccs
= ISL_DEV_GEN(dev
) >= 12 &&
485 tiling_flags
== ISL_TILING_GEN12_CCS_BIT
;
486 assert(ivb_ccs
!= tgl_ccs
);
487 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
491 if (ISL_DEV_GEN(dev
) >= 6) {
492 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
494 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
497 #define CHOOSE(__tiling) \
499 if (tiling_flags & (1u << (__tiling))) { \
500 *tiling = (__tiling); \
505 /* Of the tiling modes remaining, choose the one that offers the best
509 if (info
->dim
== ISL_SURF_DIM_1D
) {
510 /* Prefer linear for 1D surfaces because they do not benefit from
511 * tiling. To the contrary, tiling leads to wasted memory and poor
512 * memory locality due to the swizzling and alignment restrictions
513 * required in tiled surfaces.
515 CHOOSE(ISL_TILING_LINEAR
);
518 CHOOSE(ISL_TILING_Ys
);
519 CHOOSE(ISL_TILING_Yf
);
520 CHOOSE(ISL_TILING_Y0
);
521 CHOOSE(ISL_TILING_X
);
522 CHOOSE(ISL_TILING_W
);
523 CHOOSE(ISL_TILING_LINEAR
);
527 /* No tiling mode accomodates the inputs. */
532 isl_choose_msaa_layout(const struct isl_device
*dev
,
533 const struct isl_surf_init_info
*info
,
534 enum isl_tiling tiling
,
535 enum isl_msaa_layout
*msaa_layout
)
537 if (ISL_DEV_GEN(dev
) >= 8) {
538 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
539 } else if (ISL_DEV_GEN(dev
) >= 7) {
540 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
541 } else if (ISL_DEV_GEN(dev
) >= 6) {
542 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
544 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
549 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
551 assert(isl_is_pow2(samples
));
553 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
556 * If the surface is multisampled and it is a depth or stencil surface
557 * or Multisampled Surface StorageFormat in SURFACE_STATE is
558 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
561 return (struct isl_extent2d
) {
562 .width
= 1 << ((ffs(samples
) - 0) / 2),
563 .height
= 1 << ((ffs(samples
) - 1) / 2),
568 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
569 uint32_t *width
, uint32_t *height
)
571 const struct isl_extent2d px_size_sa
=
572 isl_get_interleaved_msaa_px_size_sa(samples
);
575 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
577 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
580 static enum isl_array_pitch_span
581 isl_choose_array_pitch_span(const struct isl_device
*dev
,
582 const struct isl_surf_init_info
*restrict info
,
583 enum isl_dim_layout dim_layout
,
584 const struct isl_extent4d
*phys_level0_sa
)
586 switch (dim_layout
) {
587 case ISL_DIM_LAYOUT_GEN9_1D
:
588 case ISL_DIM_LAYOUT_GEN4_2D
:
589 if (ISL_DEV_GEN(dev
) >= 8) {
590 /* QPitch becomes programmable in Broadwell. So choose the
591 * most compact QPitch possible in order to conserve memory.
593 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
594 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
596 * - Software must ensure that this field is set to a value
597 * sufficiently large such that the array slices in the surface
598 * do not overlap. Refer to the Memory Data Formats section for
599 * information on how surfaces are stored in memory.
601 * - This field specifies the distance in rows between array
602 * slices. It is used only in the following cases:
604 * - Surface Array is enabled OR
605 * - Number of Mulitsamples is not NUMSAMPLES_1 and
606 * Multisampled Surface Storage Format set to MSFMT_MSS OR
607 * - Surface Type is SURFTYPE_CUBE
609 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
610 } else if (ISL_DEV_GEN(dev
) >= 7) {
611 /* Note that Ivybridge introduces
612 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
613 * driver more control over the QPitch.
616 if (phys_level0_sa
->array_len
== 1) {
617 /* The hardware will never use the QPitch. So choose the most
618 * compact QPitch possible in order to conserve memory.
620 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
623 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
624 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
625 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
626 * Section 6.18.4.7: Surface Arrays (p112):
628 * If Surface Array Spacing is set to ARYSPC_FULL (note that
629 * the depth buffer and stencil buffer have an implied value of
632 return ISL_ARRAY_PITCH_SPAN_FULL
;
635 if (info
->levels
== 1) {
636 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
639 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
642 return ISL_ARRAY_PITCH_SPAN_FULL
;
643 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
644 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
645 isl_surf_usage_is_stencil(info
->usage
)) {
646 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
647 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
649 * The separate stencil buffer does not support mip mapping, thus
650 * the storage for LODs other than LOD 0 is not needed.
652 assert(info
->levels
== 1);
653 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
655 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
656 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
657 isl_surf_usage_is_stencil(info
->usage
)) {
658 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
659 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
661 * The separate stencil buffer does not support mip mapping,
662 * thus the storage for LODs other than LOD 0 is not needed.
664 assert(info
->levels
== 1);
665 assert(phys_level0_sa
->array_len
== 1);
666 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
669 if (phys_level0_sa
->array_len
== 1) {
670 /* The hardware will never use the QPitch. So choose the most
671 * compact QPitch possible in order to conserve memory.
673 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
676 return ISL_ARRAY_PITCH_SPAN_FULL
;
679 case ISL_DIM_LAYOUT_GEN4_3D
:
680 /* The hardware will never use the QPitch. So choose the most
681 * compact QPitch possible in order to conserve memory.
683 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
685 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
686 /* Each array image in the gen6 stencil of HiZ surface is compact in the
687 * sense that every LOD is a compact array of the same size as LOD0.
689 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
692 unreachable("bad isl_dim_layout");
693 return ISL_ARRAY_PITCH_SPAN_FULL
;
697 isl_choose_image_alignment_el(const struct isl_device
*dev
,
698 const struct isl_surf_init_info
*restrict info
,
699 enum isl_tiling tiling
,
700 enum isl_dim_layout dim_layout
,
701 enum isl_msaa_layout msaa_layout
,
702 struct isl_extent3d
*image_align_el
)
704 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
705 if (fmtl
->txc
== ISL_TXC_MCS
) {
706 assert(tiling
== ISL_TILING_Y0
);
709 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
711 * Height, width, and layout of MCS buffer in this case must match with
712 * Render Target height, width, and layout. MCS buffer is tiledY.
714 * To avoid wasting memory, choose the smallest alignment possible:
715 * HALIGN_4 and VALIGN_4.
717 *image_align_el
= isl_extent3d(4, 4, 1);
719 } else if (info
->format
== ISL_FORMAT_HIZ
) {
720 assert(ISL_DEV_GEN(dev
) >= 6);
721 if (ISL_DEV_GEN(dev
) == 6) {
722 /* HiZ surfaces on Sandy Bridge are packed tightly. */
723 *image_align_el
= isl_extent3d(1, 1, 1);
724 } else if (ISL_DEV_GEN(dev
) < 12) {
725 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
726 * primary surface which works out to 2x2 HiZ elments.
728 *image_align_el
= isl_extent3d(2, 2, 1);
730 /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the
731 * primary surface which works out to 2x4 HiZ elments.
734 *image_align_el
= isl_extent3d(2, 4, 1);
739 if (ISL_DEV_GEN(dev
) >= 12) {
740 isl_gen12_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
741 msaa_layout
, image_align_el
);
742 } else if (ISL_DEV_GEN(dev
) >= 9) {
743 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
744 msaa_layout
, image_align_el
);
745 } else if (ISL_DEV_GEN(dev
) >= 8) {
746 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
747 msaa_layout
, image_align_el
);
748 } else if (ISL_DEV_GEN(dev
) >= 7) {
749 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
750 msaa_layout
, image_align_el
);
751 } else if (ISL_DEV_GEN(dev
) >= 6) {
752 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
753 msaa_layout
, image_align_el
);
755 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
756 msaa_layout
, image_align_el
);
760 static enum isl_dim_layout
761 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
762 enum isl_surf_dim logical_dim
,
763 enum isl_tiling tiling
,
764 isl_surf_usage_flags_t usage
)
766 /* Sandy bridge needs a special layout for HiZ and stencil. */
767 if (ISL_DEV_GEN(dev
) == 6 &&
768 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
769 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
771 if (ISL_DEV_GEN(dev
) >= 9) {
772 switch (logical_dim
) {
773 case ISL_SURF_DIM_1D
:
774 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
776 * One-dimensional surfaces use a tiling mode of linear.
777 * Technically, they are not tiled resources, but the Tiled
778 * Resource Mode field in RENDER_SURFACE_STATE is still used to
779 * indicate the alignment requirements for this linear surface
780 * (See 1D Alignment requirements for how 4K and 64KB Tiled
781 * Resource Modes impact alignment). Alternatively, a 1D surface
782 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
785 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
786 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
788 if (tiling
== ISL_TILING_LINEAR
)
789 return ISL_DIM_LAYOUT_GEN9_1D
;
791 return ISL_DIM_LAYOUT_GEN4_2D
;
792 case ISL_SURF_DIM_2D
:
793 case ISL_SURF_DIM_3D
:
794 return ISL_DIM_LAYOUT_GEN4_2D
;
797 switch (logical_dim
) {
798 case ISL_SURF_DIM_1D
:
799 case ISL_SURF_DIM_2D
:
800 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
802 * The cube face textures are stored in the same way as 3D surfaces
803 * are stored (see section 6.17.5 for details). For cube surfaces,
804 * however, the depth is equal to the number of faces (always 6) and
805 * is not reduced for each MIP.
807 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
808 return ISL_DIM_LAYOUT_GEN4_3D
;
810 return ISL_DIM_LAYOUT_GEN4_2D
;
811 case ISL_SURF_DIM_3D
:
812 return ISL_DIM_LAYOUT_GEN4_3D
;
816 unreachable("bad isl_surf_dim");
817 return ISL_DIM_LAYOUT_GEN4_2D
;
821 * Calculate the physical extent of the surface's first level, in units of
825 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
826 const struct isl_surf_init_info
*restrict info
,
827 enum isl_dim_layout dim_layout
,
828 enum isl_tiling tiling
,
829 enum isl_msaa_layout msaa_layout
,
830 struct isl_extent4d
*phys_level0_sa
)
832 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
834 if (isl_format_is_planar(info
->format
))
835 unreachable("Planar formats unsupported");
838 case ISL_SURF_DIM_1D
:
839 assert(info
->height
== 1);
840 assert(info
->depth
== 1);
841 assert(info
->samples
== 1);
843 switch (dim_layout
) {
844 case ISL_DIM_LAYOUT_GEN4_3D
:
845 unreachable("bad isl_dim_layout");
847 case ISL_DIM_LAYOUT_GEN9_1D
:
848 case ISL_DIM_LAYOUT_GEN4_2D
:
849 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
850 *phys_level0_sa
= (struct isl_extent4d
) {
854 .a
= info
->array_len
,
860 case ISL_SURF_DIM_2D
:
861 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
862 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
864 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
865 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
867 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
868 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
870 switch (msaa_layout
) {
871 case ISL_MSAA_LAYOUT_NONE
:
872 assert(info
->depth
== 1);
873 assert(info
->samples
== 1);
875 *phys_level0_sa
= (struct isl_extent4d
) {
879 .a
= info
->array_len
,
883 case ISL_MSAA_LAYOUT_ARRAY
:
884 assert(info
->depth
== 1);
885 assert(info
->levels
== 1);
886 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
887 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
889 *phys_level0_sa
= (struct isl_extent4d
) {
893 .a
= info
->array_len
* info
->samples
,
897 case ISL_MSAA_LAYOUT_INTERLEAVED
:
898 assert(info
->depth
== 1);
899 assert(info
->levels
== 1);
900 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
902 *phys_level0_sa
= (struct isl_extent4d
) {
906 .a
= info
->array_len
,
909 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
916 case ISL_SURF_DIM_3D
:
917 assert(info
->array_len
== 1);
918 assert(info
->samples
== 1);
921 isl_finishme("%s:%s: compression block with depth > 1",
925 switch (dim_layout
) {
926 case ISL_DIM_LAYOUT_GEN9_1D
:
927 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
928 unreachable("bad isl_dim_layout");
930 case ISL_DIM_LAYOUT_GEN4_2D
:
931 assert(ISL_DEV_GEN(dev
) >= 9);
933 *phys_level0_sa
= (struct isl_extent4d
) {
941 case ISL_DIM_LAYOUT_GEN4_3D
:
942 assert(ISL_DEV_GEN(dev
) < 9);
943 *phys_level0_sa
= (struct isl_extent4d
) {
956 * Calculate the pitch between physical array slices, in units of rows of
960 isl_calc_array_pitch_el_rows_gen4_2d(
961 const struct isl_device
*dev
,
962 const struct isl_surf_init_info
*restrict info
,
963 const struct isl_tile_info
*tile_info
,
964 const struct isl_extent3d
*image_align_sa
,
965 const struct isl_extent4d
*phys_level0_sa
,
966 enum isl_array_pitch_span array_pitch_span
,
967 const struct isl_extent2d
*phys_slice0_sa
)
969 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
970 uint32_t pitch_sa_rows
= 0;
972 switch (array_pitch_span
) {
973 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
974 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
976 case ISL_ARRAY_PITCH_SPAN_FULL
: {
977 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
978 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
979 * Surfaces >> Surface Arrays.
981 uint32_t H0_sa
= phys_level0_sa
->h
;
982 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
984 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
985 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
988 if (ISL_DEV_GEN(dev
) >= 7) {
989 /* The QPitch equation changed slightly in Ivybridge. */
995 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
997 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
998 (info
->height
% 4 == 1)) {
999 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
1000 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
1002 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
1003 * the value calculated in the equation above , for every
1004 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
1006 * XXX(chadv): Is the errata natural corollary of the physical
1007 * layout of interleaved samples?
1012 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
1017 assert(pitch_sa_rows
% fmtl
->bh
== 0);
1018 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
1020 if (ISL_DEV_GEN(dev
) >= 9 && ISL_DEV_GEN(dev
) <= 11 &&
1021 fmtl
->txc
== ISL_TXC_CCS
) {
1023 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
1025 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
1026 * layout with these alignments in the RT space: Horizontal
1027 * Alignment = 128 and Vertical Alignment = 64."
1029 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
1031 * "For non-multisampled render target's CCS auxiliary surface,
1032 * QPitch must be computed with Horizontal Alignment = 128 and
1033 * Surface Vertical Alignment = 256. These alignments are only for
1034 * CCS buffer and not for associated render target."
1036 * The first restriction is already handled by isl_choose_image_alignment_el
1037 * but the second restriction, which is an extension of the first, only
1038 * applies to qpitch and must be applied here.
1040 * The second restriction disappears on Gen12.
1042 assert(fmtl
->bh
== 4);
1043 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
1046 if (ISL_DEV_GEN(dev
) >= 9 &&
1047 info
->dim
== ISL_SURF_DIM_3D
&&
1048 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
1049 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
1051 * Tile Mode != Linear: This field must be set to an integer multiple
1052 * of the tile height
1054 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
1057 return pitch_el_rows
;
1061 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1062 * ISL_DIM_LAYOUT_GEN4_2D.
1065 isl_calc_phys_slice0_extent_sa_gen4_2d(
1066 const struct isl_device
*dev
,
1067 const struct isl_surf_init_info
*restrict info
,
1068 enum isl_msaa_layout msaa_layout
,
1069 const struct isl_extent3d
*image_align_sa
,
1070 const struct isl_extent4d
*phys_level0_sa
,
1071 struct isl_extent2d
*phys_slice0_sa
)
1073 assert(phys_level0_sa
->depth
== 1);
1075 if (info
->levels
== 1) {
1076 /* Do not pad the surface to the image alignment.
1078 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
1079 * cycles on the below mipmap layout caluclations. Reducing the
1080 * alignment here is safe because we later align the row pitch and array
1081 * pitch to the tile boundary. It is safe even for
1082 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1083 * to accomodate the interleaved samples.
1085 * For linear surfaces, reducing the alignment here permits us to later
1086 * choose an arbitrary, non-aligned row pitch. If the surface backs
1087 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
1088 * VkBufferImageCopy::bufferRowLength.
1090 *phys_slice0_sa
= (struct isl_extent2d
) {
1091 .w
= phys_level0_sa
->w
,
1092 .h
= phys_level0_sa
->h
,
1097 uint32_t slice_top_w
= 0;
1098 uint32_t slice_bottom_w
= 0;
1099 uint32_t slice_left_h
= 0;
1100 uint32_t slice_right_h
= 0;
1102 uint32_t W0
= phys_level0_sa
->w
;
1103 uint32_t H0
= phys_level0_sa
->h
;
1105 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1106 uint32_t W
= isl_minify(W0
, l
);
1107 uint32_t H
= isl_minify(H0
, l
);
1109 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1110 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1116 } else if (l
== 1) {
1119 } else if (l
== 2) {
1120 slice_bottom_w
+= w
;
1127 *phys_slice0_sa
= (struct isl_extent2d
) {
1128 .w
= MAX(slice_top_w
, slice_bottom_w
),
1129 .h
= MAX(slice_left_h
, slice_right_h
),
1134 isl_calc_phys_total_extent_el_gen4_2d(
1135 const struct isl_device
*dev
,
1136 const struct isl_surf_init_info
*restrict info
,
1137 const struct isl_tile_info
*tile_info
,
1138 enum isl_msaa_layout msaa_layout
,
1139 const struct isl_extent3d
*image_align_sa
,
1140 const struct isl_extent4d
*phys_level0_sa
,
1141 enum isl_array_pitch_span array_pitch_span
,
1142 uint32_t *array_pitch_el_rows
,
1143 struct isl_extent2d
*total_extent_el
)
1145 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1147 struct isl_extent2d phys_slice0_sa
;
1148 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1149 image_align_sa
, phys_level0_sa
,
1151 *array_pitch_el_rows
=
1152 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1153 image_align_sa
, phys_level0_sa
,
1156 *total_extent_el
= (struct isl_extent2d
) {
1157 .w
= isl_align_div_npot(phys_slice0_sa
.w
, fmtl
->bw
),
1158 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1159 isl_align_div_npot(phys_slice0_sa
.h
, fmtl
->bh
),
1164 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1165 * ISL_DIM_LAYOUT_GEN4_3D.
1168 isl_calc_phys_total_extent_el_gen4_3d(
1169 const struct isl_device
*dev
,
1170 const struct isl_surf_init_info
*restrict info
,
1171 const struct isl_extent3d
*image_align_sa
,
1172 const struct isl_extent4d
*phys_level0_sa
,
1173 uint32_t *array_pitch_el_rows
,
1174 struct isl_extent2d
*phys_total_el
)
1176 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1178 assert(info
->samples
== 1);
1180 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1181 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1183 * The cube face textures are stored in the same way as 3D surfaces
1184 * are stored (see section 6.17.5 for details). For cube surfaces,
1185 * however, the depth is equal to the number of faces (always 6) and
1186 * is not reduced for each MIP.
1188 assert(ISL_DEV_GEN(dev
) == 4);
1189 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1190 assert(phys_level0_sa
->array_len
== 6);
1192 assert(phys_level0_sa
->array_len
== 1);
1195 uint32_t total_w
= 0;
1196 uint32_t total_h
= 0;
1198 uint32_t W0
= phys_level0_sa
->w
;
1199 uint32_t H0
= phys_level0_sa
->h
;
1200 uint32_t D0
= phys_level0_sa
->d
;
1201 uint32_t A0
= phys_level0_sa
->a
;
1203 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1204 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1205 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1206 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1208 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1209 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1211 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1212 total_h
+= level_h
* max_layers_vert
;
1215 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1216 * different number of horizontal and vertical layers. We have to set it
1217 * to something, so at least make it true for LOD0.
1219 *array_pitch_el_rows
=
1220 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1221 *phys_total_el
= (struct isl_extent2d
) {
1222 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1223 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1228 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1229 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1232 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1233 const struct isl_device
*dev
,
1234 const struct isl_surf_init_info
*restrict info
,
1235 const struct isl_tile_info
*tile_info
,
1236 const struct isl_extent3d
*image_align_sa
,
1237 const struct isl_extent4d
*phys_level0_sa
,
1238 uint32_t *array_pitch_el_rows
,
1239 struct isl_extent2d
*phys_total_el
)
1241 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1243 const struct isl_extent2d tile_extent_sa
= {
1244 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1245 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1247 /* Tile size is a multiple of image alignment */
1248 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1249 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1251 const uint32_t W0
= phys_level0_sa
->w
;
1252 const uint32_t H0
= phys_level0_sa
->h
;
1254 /* Each image has the same height as LOD0 because the hardware thinks
1255 * everything is LOD0
1257 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1259 uint32_t total_top_w
= 0;
1260 uint32_t total_bottom_w
= 0;
1261 uint32_t total_h
= 0;
1263 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1264 const uint32_t W
= isl_minify(W0
, l
);
1266 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1267 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1272 } else if (l
== 1) {
1276 total_bottom_w
+= w
;
1280 *array_pitch_el_rows
=
1281 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1282 *phys_total_el
= (struct isl_extent2d
) {
1283 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1284 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1289 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1290 * ISL_DIM_LAYOUT_GEN9_1D.
1293 isl_calc_phys_total_extent_el_gen9_1d(
1294 const struct isl_device
*dev
,
1295 const struct isl_surf_init_info
*restrict info
,
1296 const struct isl_extent3d
*image_align_sa
,
1297 const struct isl_extent4d
*phys_level0_sa
,
1298 uint32_t *array_pitch_el_rows
,
1299 struct isl_extent2d
*phys_total_el
)
1301 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1303 assert(phys_level0_sa
->height
== 1);
1304 assert(phys_level0_sa
->depth
== 1);
1305 assert(info
->samples
== 1);
1306 assert(image_align_sa
->w
>= fmtl
->bw
);
1308 uint32_t slice_w
= 0;
1309 const uint32_t W0
= phys_level0_sa
->w
;
1311 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1312 uint32_t W
= isl_minify(W0
, l
);
1313 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1318 *array_pitch_el_rows
= 1;
1319 *phys_total_el
= (struct isl_extent2d
) {
1320 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1321 .h
= phys_level0_sa
->array_len
,
1326 * Calculate the two-dimensional total physical extent of the surface, in
1327 * units of surface elements.
1330 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1331 const struct isl_surf_init_info
*restrict info
,
1332 const struct isl_tile_info
*tile_info
,
1333 enum isl_dim_layout dim_layout
,
1334 enum isl_msaa_layout msaa_layout
,
1335 const struct isl_extent3d
*image_align_sa
,
1336 const struct isl_extent4d
*phys_level0_sa
,
1337 enum isl_array_pitch_span array_pitch_span
,
1338 uint32_t *array_pitch_el_rows
,
1339 struct isl_extent2d
*total_extent_el
)
1341 switch (dim_layout
) {
1342 case ISL_DIM_LAYOUT_GEN9_1D
:
1343 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1344 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1345 image_align_sa
, phys_level0_sa
,
1346 array_pitch_el_rows
,
1349 case ISL_DIM_LAYOUT_GEN4_2D
:
1350 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1351 image_align_sa
, phys_level0_sa
,
1353 array_pitch_el_rows
,
1356 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1357 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1358 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1361 array_pitch_el_rows
,
1364 case ISL_DIM_LAYOUT_GEN4_3D
:
1365 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1366 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1367 image_align_sa
, phys_level0_sa
,
1368 array_pitch_el_rows
,
1373 unreachable("invalid value for dim_layout");
1377 isl_calc_row_pitch_alignment(const struct isl_device
*dev
,
1378 const struct isl_surf_init_info
*surf_info
,
1379 const struct isl_tile_info
*tile_info
)
1381 if (tile_info
->tiling
!= ISL_TILING_LINEAR
) {
1382 /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches must
1383 * be 512B-aligned. CCS is only support on Y tilings.
1385 * Only consider 512B alignment when :
1386 * - AUX is not explicitly disabled
1387 * - the caller has specified no pitch
1389 * isl_surf_get_ccs_surf() will check that the main surface alignment
1390 * matches CCS expectations.
1392 if (ISL_DEV_GEN(dev
) >= 12 &&
1393 isl_format_supports_ccs_e(dev
->info
, surf_info
->format
) &&
1394 tile_info
->tiling
!= ISL_TILING_X
&&
1395 !(surf_info
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
) &&
1396 surf_info
->row_pitch_B
== 0) {
1397 return isl_align(tile_info
->phys_extent_B
.width
, 512);
1400 return tile_info
->phys_extent_B
.width
;
1403 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1404 * RENDER_SURFACE_STATE Surface Pitch (p349):
1406 * - For linear render target surfaces and surfaces accessed with the
1407 * typed data port messages, the pitch must be a multiple of the
1408 * element size for non-YUV surface formats. Pitch must be
1409 * a multiple of 2 * element size for YUV surface formats.
1411 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1412 * ignore because isl doesn't do buffers.]
1414 * - For other linear surfaces, the pitch can be any multiple of
1417 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1418 const uint32_t bs
= fmtl
->bpb
/ 8;
1421 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1422 if (isl_format_is_yuv(surf_info
->format
)) {
1431 /* From the Broadwell PRM >> Volume 2c: Command Reference: Registers >>
1432 * PRI_STRIDE Stride (p1254):
1434 * "When using linear memory, this must be at least 64 byte aligned."
1436 if (surf_info
->usage
& ISL_SURF_USAGE_DISPLAY_BIT
)
1437 alignment
= isl_align(alignment
, 64);
1443 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1444 const struct isl_surf_init_info
*info
,
1445 const struct isl_extent2d
*phys_total_el
,
1446 uint32_t alignment_B
)
1448 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1449 const uint32_t bs
= fmtl
->bpb
/ 8;
1451 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1455 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1456 const struct isl_surf_init_info
*surf_info
,
1457 const struct isl_tile_info
*tile_info
,
1458 const struct isl_extent2d
*phys_total_el
,
1459 uint32_t alignment_B
)
1461 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1463 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1465 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1466 const uint32_t total_w_tl
=
1467 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1468 tile_info
->logical_extent_el
.width
);
1470 /* In some cases the alignment of the pitch might be > to the tile size
1471 * (for example Gen12 CCS requires 512B alignment while the tile's width
1472 * can be 128B), so align the row pitch to the alignment.
1474 assert(alignment_B
>= tile_info
->phys_extent_B
.width
);
1475 return isl_align(total_w_tl
* tile_info
->phys_extent_B
.width
, alignment_B
);
1479 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1480 const struct isl_surf_init_info
*surf_info
,
1481 const struct isl_tile_info
*tile_info
,
1482 const struct isl_extent2d
*phys_total_el
,
1483 uint32_t alignment_B
)
1485 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1486 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1489 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1490 phys_total_el
, alignment_B
);
1495 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1496 * size is `bits` bits?
1498 * Hardware pitch fields are offset by 1. For example, if the size of
1499 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1500 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1501 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1504 pitch_in_range(uint32_t n
, uint32_t bits
)
1507 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1511 isl_calc_row_pitch(const struct isl_device
*dev
,
1512 const struct isl_surf_init_info
*surf_info
,
1513 const struct isl_tile_info
*tile_info
,
1514 enum isl_dim_layout dim_layout
,
1515 const struct isl_extent2d
*phys_total_el
,
1516 uint32_t *out_row_pitch_B
)
1518 uint32_t alignment_B
=
1519 isl_calc_row_pitch_alignment(dev
, surf_info
, tile_info
);
1521 const uint32_t min_row_pitch_B
=
1522 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1525 if (surf_info
->row_pitch_B
!= 0) {
1526 if (surf_info
->row_pitch_B
< min_row_pitch_B
)
1529 if (surf_info
->row_pitch_B
% alignment_B
!= 0)
1533 const uint32_t row_pitch_B
=
1534 surf_info
->row_pitch_B
!= 0 ? surf_info
->row_pitch_B
: min_row_pitch_B
;
1536 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1538 if (row_pitch_B
== 0)
1541 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1542 /* SurfacePitch is ignored for this layout. */
1546 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1547 ISL_SURF_USAGE_TEXTURE_BIT
|
1548 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1549 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1552 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1553 ISL_SURF_USAGE_MCS_BIT
)) &&
1554 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1557 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1558 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1561 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1562 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1565 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1566 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1567 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1569 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1570 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1574 *out_row_pitch_B
= row_pitch_B
;
1579 isl_surf_init_s(const struct isl_device
*dev
,
1580 struct isl_surf
*surf
,
1581 const struct isl_surf_init_info
*restrict info
)
1583 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1585 const struct isl_extent4d logical_level0_px
= {
1589 .a
= info
->array_len
,
1592 enum isl_tiling tiling
;
1593 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1596 struct isl_tile_info tile_info
;
1597 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1599 const enum isl_dim_layout dim_layout
=
1600 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1602 enum isl_msaa_layout msaa_layout
;
1603 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1606 struct isl_extent3d image_align_el
;
1607 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1610 struct isl_extent3d image_align_sa
=
1611 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1613 struct isl_extent4d phys_level0_sa
;
1614 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1617 enum isl_array_pitch_span array_pitch_span
=
1618 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1620 uint32_t array_pitch_el_rows
;
1621 struct isl_extent2d phys_total_el
;
1622 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1623 dim_layout
, msaa_layout
,
1624 &image_align_sa
, &phys_level0_sa
,
1625 array_pitch_span
, &array_pitch_el_rows
,
1628 uint32_t row_pitch_B
;
1629 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1630 &phys_total_el
, &row_pitch_B
))
1633 uint32_t base_alignment_B
;
1635 if (tiling
== ISL_TILING_LINEAR
) {
1636 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1638 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1640 * "The Base Address for linear render target surfaces and surfaces
1641 * accessed with the typed surface read/write data port messages must
1642 * be element-size aligned, for non-YUV surface formats, or a
1643 * multiple of 2 element-sizes for YUV surface formats. Other linear
1644 * surfaces have no alignment requirements (byte alignment is
1647 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1648 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1649 if (isl_format_is_yuv(info
->format
)) {
1650 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1652 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1655 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1657 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1659 * "For Linear memory, this field specifies the stride in chunks of
1660 * 64 bytes (1 cache line)."
1662 if (isl_surf_usage_is_display(info
->usage
))
1663 base_alignment_B
= MAX(base_alignment_B
, 64);
1665 const uint32_t total_h_tl
=
1666 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1668 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1670 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1671 tile_info
.phys_extent_B
.height
;
1672 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1673 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1675 /* The diagram in the Bspec section Memory Compression - Gen12, shows
1676 * that the CCS is indexed in 256B chunks. However, the
1677 * PLANE_AUX_DIST::Auxiliary Surface Distance field is in units of 4K
1678 * pages. We currently don't assign the usage field like we do for main
1679 * surfaces, so just use 4K for now.
1681 if (tiling
== ISL_TILING_GEN12_CCS
)
1682 base_alignment_B
= MAX(base_alignment_B
, 4096);
1684 /* Gen12+ requires that images be 64K-aligned if they're going to used
1685 * with CCS. This is because the Aux translation table maps main
1686 * surface addresses to aux addresses at a 64K (in the main surface)
1687 * granularity. Because we don't know for sure in ISL if a surface will
1688 * use CCS, we have to guess based on the DISABLE_AUX usage bit. The
1689 * one thing we do know is that we haven't enable CCS on linear images
1690 * yet so we can avoid the extra alignment there.
1692 if (ISL_DEV_GEN(dev
) >= 12 &&
1693 !(info
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)) {
1694 base_alignment_B
= MAX(base_alignment_B
, 64 * 1024);
1698 if (ISL_DEV_GEN(dev
) < 9) {
1699 /* From the Broadwell PRM Vol 5, Surface Layout:
1701 * "In addition to restrictions on maximum height, width, and depth,
1702 * surfaces are also restricted to a maximum size in bytes. This
1703 * maximum is 2 GB for all products and all surface types."
1705 * This comment is applicable to all Pre-gen9 platforms.
1707 if (size_B
> (uint64_t) 1 << 31)
1709 } else if (ISL_DEV_GEN(dev
) < 11) {
1710 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1711 * "In addition to restrictions on maximum height, width, and depth,
1712 * surfaces are also restricted to a maximum size of 2^38 bytes.
1713 * All pixels within the surface must be contained within 2^38 bytes
1714 * of the base address."
1716 if (size_B
> (uint64_t) 1 << 38)
1719 /* gen11+ platforms raised this limit to 2^44 bytes. */
1720 if (size_B
> (uint64_t) 1 << 44)
1724 *surf
= (struct isl_surf
) {
1726 .dim_layout
= dim_layout
,
1727 .msaa_layout
= msaa_layout
,
1729 .format
= info
->format
,
1731 .levels
= info
->levels
,
1732 .samples
= info
->samples
,
1734 .image_alignment_el
= image_align_el
,
1735 .logical_level0_px
= logical_level0_px
,
1736 .phys_level0_sa
= phys_level0_sa
,
1739 .alignment_B
= base_alignment_B
,
1740 .row_pitch_B
= row_pitch_B
,
1741 .array_pitch_el_rows
= array_pitch_el_rows
,
1742 .array_pitch_span
= array_pitch_span
,
1744 .usage
= info
->usage
,
1751 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1752 struct isl_tile_info
*tile_info
)
1754 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1755 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1759 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1760 const struct isl_surf
*surf
,
1761 struct isl_surf
*hiz_surf
)
1763 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1765 if (!isl_surf_usage_is_depth(surf
->usage
))
1768 /* HiZ only works with Y-tiled depth buffers */
1769 if (!isl_tiling_is_any_y(surf
->tiling
))
1772 /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
1773 switch (surf
->format
) {
1774 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1775 if (isl_surf_usage_is_depth_and_stencil(surf
->usage
)) {
1776 assert(ISL_DEV_GEN(dev
) == 5);
1777 unreachable("This should work, but is untested");
1780 case ISL_FORMAT_R16_UNORM
:
1781 case ISL_FORMAT_R32_FLOAT
:
1783 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1784 if (ISL_DEV_GEN(dev
) == 5) {
1785 assert(isl_surf_usage_is_depth_and_stencil(surf
->usage
));
1786 unreachable("This should work, but is untested");
1793 /* Multisampled depth is always interleaved */
1794 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1795 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1797 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1799 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1800 * Target View Extent, and Depth Coordinate Offset X/Y of the
1801 * hierarchical depth buffer are inherited from the depth buffer. The
1802 * height and width of the hierarchical depth buffer that must be
1803 * allocated are computed by the following formulas, where HZ is the
1804 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1805 * Z_Width, and Z_Depth values given in these formulas are those present
1806 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1808 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1809 * being applied to the table below if Number of Multisamples is set to
1810 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1811 * Z_Width must be multiplied by 4 before being applied to the table
1812 * below if Number of Multisamples is set to NUMSAMPLES_8."
1814 * In the Sky Lake PRM, the second paragraph is replaced with this:
1816 * "The Z_Height and Z_Width values must equal those present in
1817 * 3DSTATE_DEPTH_BUFFER incremented by one."
1819 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1820 * block corresponds to a region of 8x4 samples in the primary depth
1821 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1822 * a region of 8x4 pixels in the primary depth surface regardless of the
1823 * number of samples. The dimensions of a HiZ block in both pixels and
1824 * samples are given in the table below:
1826 * | SNB - BDW | SKL+
1827 * ------+-----------+-------------
1828 * 1x | 8 x 4 sa | 8 x 4 sa
1829 * MSAA | 8 x 4 px | 8 x 4 px
1830 * ------+-----------+-------------
1831 * 2x | 8 x 4 sa | 16 x 4 sa
1832 * MSAA | 4 x 4 px | 8 x 4 px
1833 * ------+-----------+-------------
1834 * 4x | 8 x 4 sa | 16 x 8 sa
1835 * MSAA | 4 x 2 px | 8 x 4 px
1836 * ------+-----------+-------------
1837 * 8x | 8 x 4 sa | 32 x 8 sa
1838 * MSAA | 2 x 2 px | 8 x 4 px
1839 * ------+-----------+-------------
1840 * 16x | N/A | 32 x 16 sa
1841 * MSAA | N/A | 8 x 4 px
1842 * ------+-----------+-------------
1844 * There are a number of different ways that this discrepency could be
1845 * handled. The way we have chosen is to simply make MSAA HiZ have the
1846 * same number of samples as the parent surface pre-Sky Lake and always be
1847 * single-sampled on Sky Lake and above. Since the block sizes of
1848 * compressed formats are given in samples, this neatly handles everything
1849 * without the need for additional HiZ formats with different block sizes
1852 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1854 return isl_surf_init(dev
, hiz_surf
,
1856 .format
= ISL_FORMAT_HIZ
,
1857 .width
= surf
->logical_level0_px
.width
,
1858 .height
= surf
->logical_level0_px
.height
,
1859 .depth
= surf
->logical_level0_px
.depth
,
1860 .levels
= surf
->levels
,
1861 .array_len
= surf
->logical_level0_px
.array_len
,
1863 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1864 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1868 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1869 const struct isl_surf
*surf
,
1870 struct isl_surf
*mcs_surf
)
1872 /* It must be multisampled with an array layout */
1873 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_ARRAY
)
1876 if (mcs_surf
->size_B
> 0)
1879 /* The following are true of all multisampled surfaces */
1880 assert(surf
->samples
> 1);
1881 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1882 assert(surf
->levels
== 1);
1883 assert(surf
->logical_level0_px
.depth
== 1);
1885 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
1887 * This field must be set to 0 for all SINT MSRTs when all RT channels
1890 * In practice this means that we have to disable MCS for all signed
1891 * integer MSAA buffers. The alternative, to disable MCS only when one
1892 * of the render target channels is disabled, is impractical because it
1893 * would require converting between CMS and UMS MSAA layouts on the fly,
1894 * which is expensive.
1896 if (ISL_DEV_GEN(dev
) == 7 && isl_format_has_sint_channel(surf
->format
))
1899 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1900 * bits which means the maximum pitch of a compression surface is 512
1901 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1902 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1903 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1904 * and 8x, we have enough room for the full 16k supported by the hardware.
1906 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1909 enum isl_format mcs_format
;
1910 switch (surf
->samples
) {
1911 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1912 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1913 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1914 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1916 unreachable("Invalid sample count");
1919 return isl_surf_init(dev
, mcs_surf
,
1920 .dim
= ISL_SURF_DIM_2D
,
1921 .format
= mcs_format
,
1922 .width
= surf
->logical_level0_px
.width
,
1923 .height
= surf
->logical_level0_px
.height
,
1926 .array_len
= surf
->logical_level0_px
.array_len
,
1927 .samples
= 1, /* MCS surfaces are really single-sampled */
1928 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1929 .tiling_flags
= ISL_TILING_Y0_BIT
);
1933 isl_surf_supports_ccs(const struct isl_device
*dev
,
1934 const struct isl_surf
*surf
)
1936 /* CCS support does not exist prior to Gen7 */
1937 if (ISL_DEV_GEN(dev
) <= 6)
1940 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1943 if (isl_format_is_compressed(surf
->format
))
1946 if (!isl_is_pow2(isl_format_get_layout(surf
->format
)->bpb
))
1949 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
1950 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
1952 * - Support is limited to tiled render targets.
1954 * From the Skylake documentation, it is made clear that X-tiling is no
1957 * - MCS and Lossless compression is supported for
1958 * TiledY/TileYs/TileYf non-MSRTs only.
1960 * From the BSpec (44930) for Gen12:
1962 * Linear CCS is only allowed for Untyped Buffers but only via HDC
1963 * Data-Port messages.
1965 * We never use untyped messages on surfaces created by ISL on Gen9+ so
1966 * this means linear is out on Gen12+ as well.
1968 if (surf
->tiling
== ISL_TILING_LINEAR
)
1971 if (ISL_DEV_GEN(dev
) >= 12) {
1972 if (isl_surf_usage_is_stencil(surf
->usage
) && surf
->samples
> 1)
1975 /* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if
1976 * it has HiZ. If not for GEN:BUG:1406512483 "deprecate compression
1977 * enable states", D16 would be supported. Supporting D16 requires being
1978 * able to specify that the control surface is present and
1979 * simultaneously disabling compression. The above bug makes it so that
1980 * it's not possible to specify this configuration.
1982 * Note: ISL Doesn't currently support depth CCS without HiZ at all.
1984 if (isl_surf_usage_is_depth(surf
->usage
) &&
1985 surf
->format
== ISL_FORMAT_R16_UNORM
) {
1989 /* On Gen12, 8BPP surfaces cannot be compressed if any level is not
1990 * 32Bx4row-aligned. For now, just reject the cases where alignment
1993 if (isl_format_get_layout(surf
->format
)->bpb
== 8 && surf
->levels
>= 3) {
1994 isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
1995 "disabled, but support for more levels is possible.",
1996 __FILE__
, __func__
);
2000 /* On Gen12, all CCS-compressed surface pitches must be multiples of
2003 if (surf
->row_pitch_B
% 512 != 0)
2006 /* According to GEN:BUG:1406738321, 3D textures need a blit to a new
2007 * surface in order to perform a resolve. For now, just disable CCS.
2009 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2010 isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
2011 " is available.", __FILE__
, __func__
);
2015 /* GEN:BUG:1207137018
2017 * TODO: implement following workaround currently covered by the
2018 * restriction above. If following conditions are met:
2020 * - RENDER_SURFACE_STATE.Surface Type == 3D
2021 * - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE
2022 * - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS
2024 * Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip
2025 * that larger than those present in the surface (i.e. 15)
2028 /* TODO: Handle the other tiling formats */
2029 if (surf
->tiling
!= ISL_TILING_Y0
)
2032 /* ISL_DEV_GEN(dev) < 12 */
2033 if (surf
->samples
> 1)
2036 /* CCS is only for color images on Gen7-11 */
2037 if (isl_surf_usage_is_depth_or_stencil(surf
->usage
))
2040 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
2041 * work for 3D textures until gen9 where the layout of 3D textures
2042 * changes to match 2D array textures.
2044 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
2047 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
2048 * Non-MultiSampler Render Target Restrictions):
2050 * "Support is for non-mip-mapped and non-array surface types only."
2052 * This restriction is lifted on gen8+. Technically, it may be possible
2053 * to create a CCS for an arrayed or mipmapped image and only enable
2054 * CCS_D when rendering to the base slice. However, there is no
2055 * documentation tell us what the hardware would do in that case or what
2056 * it does if you walk off the bases slice. (Does it ignore CCS or does
2057 * it start scribbling over random memory?) We play it safe and just
2058 * follow the docs and don't allow CCS_D for arrayed or mip-mapped
2061 if (ISL_DEV_GEN(dev
) <= 7 &&
2062 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
2065 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
2066 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
2068 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
2069 * 64bpp, and 128bpp.
2071 if (isl_format_get_layout(surf
->format
)->bpb
< 32)
2074 /* From the Skylake documentation, it is made clear that X-tiling is no
2077 * - MCS and Lossless compression is supported for
2078 * TiledY/TileYs/TileYf non-MSRTs only.
2080 if (ISL_DEV_GEN(dev
) >= 9 && !isl_tiling_is_any_y(surf
->tiling
))
2088 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
2089 const struct isl_surf
*surf
,
2090 struct isl_surf
*aux_surf
,
2091 struct isl_surf
*extra_aux_surf
,
2092 uint32_t row_pitch_B
)
2096 /* An uninitialized surface is needed to get a CCS surface. */
2097 if (aux_surf
->size_B
> 0 &&
2098 (extra_aux_surf
== NULL
|| extra_aux_surf
->size_B
> 0)) {
2102 /* A surface can't have two CCS surfaces. */
2103 if (aux_surf
->usage
& ISL_SURF_USAGE_CCS_BIT
)
2106 if (!isl_surf_supports_ccs(dev
, surf
))
2109 if (ISL_DEV_GEN(dev
) >= 12) {
2110 enum isl_format ccs_format
;
2111 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2112 case 8: ccs_format
= ISL_FORMAT_GEN12_CCS_8BPP_Y0
; break;
2113 case 16: ccs_format
= ISL_FORMAT_GEN12_CCS_16BPP_Y0
; break;
2114 case 32: ccs_format
= ISL_FORMAT_GEN12_CCS_32BPP_Y0
; break;
2115 case 64: ccs_format
= ISL_FORMAT_GEN12_CCS_64BPP_Y0
; break;
2116 case 128: ccs_format
= ISL_FORMAT_GEN12_CCS_128BPP_Y0
; break;
2121 /* On Gen12, the CCS is a scaled-down version of the main surface. We
2122 * model this as the CCS compressing a 2D-view of the entire surface.
2124 struct isl_surf
*ccs_surf
=
2125 aux_surf
->size_B
> 0 ? extra_aux_surf
: aux_surf
;
2127 isl_surf_init(dev
, ccs_surf
,
2128 .dim
= ISL_SURF_DIM_2D
,
2129 .format
= ccs_format
,
2130 .width
= isl_surf_get_row_pitch_el(surf
),
2131 .height
= surf
->size_B
/ surf
->row_pitch_B
,
2136 .row_pitch_B
= row_pitch_B
,
2137 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2138 .tiling_flags
= ISL_TILING_GEN12_CCS_BIT
);
2139 assert(!ok
|| ccs_surf
->size_B
== surf
->size_B
/ 256);
2142 enum isl_format ccs_format
;
2143 if (ISL_DEV_GEN(dev
) >= 9) {
2144 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2145 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
2146 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
2147 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
2148 default: unreachable("Unsupported CCS format");
2151 } else if (surf
->tiling
== ISL_TILING_Y0
) {
2152 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2153 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
2154 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
2155 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
2156 default: unreachable("Unsupported CCS format");
2158 } else if (surf
->tiling
== ISL_TILING_X
) {
2159 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2160 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
2161 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
2162 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
2163 default: unreachable("Unsupported CCS format");
2166 unreachable("Invalid tiling format");
2169 return isl_surf_init(dev
, aux_surf
,
2171 .format
= ccs_format
,
2172 .width
= surf
->logical_level0_px
.width
,
2173 .height
= surf
->logical_level0_px
.height
,
2174 .depth
= surf
->logical_level0_px
.depth
,
2175 .levels
= surf
->levels
,
2176 .array_len
= surf
->logical_level0_px
.array_len
,
2178 .row_pitch_B
= row_pitch_B
,
2179 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2180 .tiling_flags
= ISL_TILING_CCS_BIT
);
2184 #define isl_genX_call(dev, func, ...) \
2185 switch (ISL_DEV_GEN(dev)) { \
2187 /* G45 surface state is the same as gen5 */ \
2188 if (ISL_DEV_IS_G4X(dev)) { \
2189 isl_gen5_##func(__VA_ARGS__); \
2191 isl_gen4_##func(__VA_ARGS__); \
2195 isl_gen5_##func(__VA_ARGS__); \
2198 isl_gen6_##func(__VA_ARGS__); \
2201 if (ISL_DEV_IS_HASWELL(dev)) { \
2202 isl_gen75_##func(__VA_ARGS__); \
2204 isl_gen7_##func(__VA_ARGS__); \
2208 isl_gen8_##func(__VA_ARGS__); \
2211 isl_gen9_##func(__VA_ARGS__); \
2214 isl_gen10_##func(__VA_ARGS__); \
2217 isl_gen11_##func(__VA_ARGS__); \
2220 isl_gen12_##func(__VA_ARGS__); \
2223 assert(!"Unknown hardware generation"); \
2227 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
2228 const struct isl_surf_fill_state_info
*restrict info
)
2231 isl_surf_usage_flags_t _base_usage
=
2232 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
2233 ISL_SURF_USAGE_TEXTURE_BIT
|
2234 ISL_SURF_USAGE_STORAGE_BIT
);
2235 /* They may only specify one of the above bits at a time */
2236 assert(__builtin_popcount(_base_usage
) == 1);
2237 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
2238 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
2241 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
2242 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2243 info
->surf
->logical_level0_px
.depth
);
2245 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2246 info
->surf
->logical_level0_px
.array_len
);
2249 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
2253 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
2254 const struct isl_buffer_fill_state_info
*restrict info
)
2256 isl_genX_call(dev
, buffer_fill_state_s
, dev
, state
, info
);
2260 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
2261 struct isl_extent3d size
)
2263 isl_genX_call(dev
, null_fill_state
, state
, size
);
2267 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
2268 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
2270 if (info
->depth_surf
&& info
->stencil_surf
) {
2271 if (!dev
->info
->has_hiz_and_separate_stencil
) {
2272 assert(info
->depth_surf
== info
->stencil_surf
);
2273 assert(info
->depth_address
== info
->stencil_address
);
2275 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
2278 if (info
->depth_surf
) {
2279 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
2280 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
2281 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2282 info
->depth_surf
->logical_level0_px
.depth
);
2284 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2285 info
->depth_surf
->logical_level0_px
.array_len
);
2289 if (info
->stencil_surf
) {
2290 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
2291 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
2292 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2293 info
->stencil_surf
->logical_level0_px
.depth
);
2295 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2296 info
->stencil_surf
->logical_level0_px
.array_len
);
2300 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
2304 * A variant of isl_surf_get_image_offset_sa() specific to
2305 * ISL_DIM_LAYOUT_GEN4_2D.
2308 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
2309 uint32_t level
, uint32_t logical_array_layer
,
2310 uint32_t *x_offset_sa
,
2311 uint32_t *y_offset_sa
)
2313 assert(level
< surf
->levels
);
2314 if (surf
->dim
== ISL_SURF_DIM_3D
)
2315 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2317 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2319 const struct isl_extent3d image_align_sa
=
2320 isl_surf_get_image_alignment_sa(surf
);
2322 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2323 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2325 const uint32_t phys_layer
= logical_array_layer
*
2326 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2329 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2331 for (uint32_t l
= 0; l
< level
; ++l
) {
2333 uint32_t W
= isl_minify(W0
, l
);
2334 x
+= isl_align_npot(W
, image_align_sa
.w
);
2336 uint32_t H
= isl_minify(H0
, l
);
2337 y
+= isl_align_npot(H
, image_align_sa
.h
);
2346 * A variant of isl_surf_get_image_offset_sa() specific to
2347 * ISL_DIM_LAYOUT_GEN4_3D.
2350 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2351 uint32_t level
, uint32_t logical_z_offset_px
,
2352 uint32_t *x_offset_sa
,
2353 uint32_t *y_offset_sa
)
2355 assert(level
< surf
->levels
);
2356 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2357 assert(surf
->phys_level0_sa
.array_len
== 1);
2358 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2360 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2361 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2362 assert(surf
->phys_level0_sa
.array_len
== 6);
2363 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2366 const struct isl_extent3d image_align_sa
=
2367 isl_surf_get_image_alignment_sa(surf
);
2369 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2370 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2371 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2372 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2377 for (uint32_t l
= 0; l
< level
; ++l
) {
2378 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2379 const uint32_t level_d
=
2380 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2382 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2384 y
+= level_h
* max_layers_vert
;
2387 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2388 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2389 const uint32_t level_d
=
2390 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2393 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2395 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2396 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2403 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2405 uint32_t logical_array_layer
,
2406 uint32_t *x_offset_sa
,
2407 uint32_t *y_offset_sa
)
2409 assert(level
< surf
->levels
);
2410 assert(surf
->logical_level0_px
.depth
== 1);
2411 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2413 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2415 const struct isl_extent3d image_align_sa
=
2416 isl_surf_get_image_alignment_sa(surf
);
2418 struct isl_tile_info tile_info
;
2419 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2420 const struct isl_extent2d tile_extent_sa
= {
2421 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2422 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2424 /* Tile size is a multiple of image alignment */
2425 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2426 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2428 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2429 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2431 /* Each image has the same height as LOD0 because the hardware thinks
2432 * everything is LOD0
2434 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2436 /* Quick sanity check for consistency */
2437 if (surf
->phys_level0_sa
.array_len
> 1)
2438 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2440 uint32_t x
= 0, y
= 0;
2441 for (uint32_t l
= 0; l
< level
; ++l
) {
2442 const uint32_t W
= isl_minify(W0
, l
);
2444 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2445 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2455 y
+= H
* logical_array_layer
;
2462 * A variant of isl_surf_get_image_offset_sa() specific to
2463 * ISL_DIM_LAYOUT_GEN9_1D.
2466 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2467 uint32_t level
, uint32_t layer
,
2468 uint32_t *x_offset_sa
,
2469 uint32_t *y_offset_sa
)
2471 assert(level
< surf
->levels
);
2472 assert(layer
< surf
->phys_level0_sa
.array_len
);
2473 assert(surf
->phys_level0_sa
.height
== 1);
2474 assert(surf
->phys_level0_sa
.depth
== 1);
2475 assert(surf
->samples
== 1);
2477 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2478 const struct isl_extent3d image_align_sa
=
2479 isl_surf_get_image_alignment_sa(surf
);
2483 for (uint32_t l
= 0; l
< level
; ++l
) {
2484 uint32_t W
= isl_minify(W0
, l
);
2485 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2491 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2495 * Calculate the offset, in units of surface samples, to a subimage in the
2498 * @invariant level < surface levels
2499 * @invariant logical_array_layer < logical array length of surface
2500 * @invariant logical_z_offset_px < logical depth of surface at level
2503 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2505 uint32_t logical_array_layer
,
2506 uint32_t logical_z_offset_px
,
2507 uint32_t *x_offset_sa
,
2508 uint32_t *y_offset_sa
)
2510 assert(level
< surf
->levels
);
2511 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2512 assert(logical_z_offset_px
2513 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2515 switch (surf
->dim_layout
) {
2516 case ISL_DIM_LAYOUT_GEN9_1D
:
2517 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2518 x_offset_sa
, y_offset_sa
);
2520 case ISL_DIM_LAYOUT_GEN4_2D
:
2521 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2522 + logical_z_offset_px
,
2523 x_offset_sa
, y_offset_sa
);
2525 case ISL_DIM_LAYOUT_GEN4_3D
:
2526 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2527 logical_z_offset_px
,
2528 x_offset_sa
, y_offset_sa
);
2530 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2531 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2532 logical_z_offset_px
,
2533 x_offset_sa
, y_offset_sa
);
2537 unreachable("not reached");
2542 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2544 uint32_t logical_array_layer
,
2545 uint32_t logical_z_offset_px
,
2546 uint32_t *x_offset_el
,
2547 uint32_t *y_offset_el
)
2549 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2551 assert(level
< surf
->levels
);
2552 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2553 assert(logical_z_offset_px
2554 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2556 uint32_t x_offset_sa
, y_offset_sa
;
2557 isl_surf_get_image_offset_sa(surf
, level
,
2558 logical_array_layer
,
2559 logical_z_offset_px
,
2563 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2564 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2568 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2570 uint32_t logical_array_layer
,
2571 uint32_t logical_z_offset_px
,
2573 uint32_t *x_offset_sa
,
2574 uint32_t *y_offset_sa
)
2576 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2578 uint32_t total_x_offset_el
, total_y_offset_el
;
2579 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2580 logical_z_offset_px
,
2582 &total_y_offset_el
);
2584 uint32_t x_offset_el
, y_offset_el
;
2585 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2594 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2596 assert(x_offset_el
== 0);
2600 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2602 assert(y_offset_el
== 0);
2607 isl_surf_get_image_range_B_tile(const struct isl_surf
*surf
,
2609 uint32_t logical_array_layer
,
2610 uint32_t logical_z_offset_px
,
2611 uint32_t *start_tile_B
,
2612 uint32_t *end_tile_B
)
2614 uint32_t start_x_offset_el
, start_y_offset_el
;
2615 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2616 logical_z_offset_px
,
2618 &start_y_offset_el
);
2620 /* Compute the size of the subimage in surface elements */
2621 const uint32_t subimage_w_sa
= isl_minify(surf
->phys_level0_sa
.w
, level
);
2622 const uint32_t subimage_h_sa
= isl_minify(surf
->phys_level0_sa
.h
, level
);
2623 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2624 const uint32_t subimage_w_el
= isl_align_div_npot(subimage_w_sa
, fmtl
->bw
);
2625 const uint32_t subimage_h_el
= isl_align_div_npot(subimage_h_sa
, fmtl
->bh
);
2627 /* Find the last pixel */
2628 uint32_t end_x_offset_el
= start_x_offset_el
+ subimage_w_el
- 1;
2629 uint32_t end_y_offset_el
= start_y_offset_el
+ subimage_h_el
- 1;
2631 UNUSED
uint32_t x_offset_el
, y_offset_el
;
2632 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2640 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2648 /* We want the range we return to be exclusive but the tile containing the
2649 * last pixel (what we just calculated) is inclusive. Add one.
2653 assert(*end_tile_B
<= surf
->size_B
);
2657 isl_surf_get_image_surf(const struct isl_device
*dev
,
2658 const struct isl_surf
*surf
,
2660 uint32_t logical_array_layer
,
2661 uint32_t logical_z_offset_px
,
2662 struct isl_surf
*image_surf
,
2664 uint32_t *x_offset_sa
,
2665 uint32_t *y_offset_sa
)
2667 isl_surf_get_image_offset_B_tile_sa(surf
,
2669 logical_array_layer
,
2670 logical_z_offset_px
,
2675 /* Even for cube maps there will be only single face, therefore drop the
2676 * corresponding flag if present.
2678 const isl_surf_usage_flags_t usage
=
2679 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2682 ok
= isl_surf_init(dev
, image_surf
,
2683 .dim
= ISL_SURF_DIM_2D
,
2684 .format
= surf
->format
,
2685 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2686 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2690 .samples
= surf
->samples
,
2691 .row_pitch_B
= surf
->row_pitch_B
,
2693 .tiling_flags
= (1 << surf
->tiling
));
2698 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2700 uint32_t row_pitch_B
,
2701 uint32_t total_x_offset_el
,
2702 uint32_t total_y_offset_el
,
2703 uint32_t *base_address_offset
,
2704 uint32_t *x_offset_el
,
2705 uint32_t *y_offset_el
)
2707 if (tiling
== ISL_TILING_LINEAR
) {
2708 assert(bpb
% 8 == 0);
2709 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2710 total_x_offset_el
* (bpb
/ 8);
2716 struct isl_tile_info tile_info
;
2717 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2719 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2721 /* For non-power-of-two formats, we need the address to be both tile and
2722 * element-aligned. The easiest way to achieve this is to work with a tile
2723 * that is three times as wide as the regular tile.
2725 * The tile info returned by get_tile_info has a logical size that is an
2726 * integer number of tile_info.format_bpb size elements. To scale the
2727 * tile, we scale up the physical width and then treat the logical tile
2728 * size as if it has bpb size elements.
2730 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2731 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2733 /* Compute the offset into the tile */
2734 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2735 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2737 /* Compute the offset of the tile in units of whole tiles */
2738 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2739 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2741 *base_address_offset
=
2742 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2743 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2747 isl_surf_get_depth_format(const struct isl_device
*dev
,
2748 const struct isl_surf
*surf
)
2750 /* Support for separate stencil buffers began in gen5. Support for
2751 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2752 * those that supported separate and interleaved stencil, were gen5 and
2755 * For a list of all available formats, see the Sandybridge PRM >> Volume
2756 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2760 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2762 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2765 assert(ISL_DEV_GEN(dev
) < 7);
2767 switch (surf
->format
) {
2769 unreachable("bad isl depth format");
2770 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2771 assert(ISL_DEV_GEN(dev
) < 7);
2772 return 0; /* D32_FLOAT_S8X24_UINT */
2773 case ISL_FORMAT_R32_FLOAT
:
2774 assert(!has_stencil
);
2775 return 1; /* D32_FLOAT */
2776 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2778 assert(ISL_DEV_GEN(dev
) < 7);
2779 return 2; /* D24_UNORM_S8_UINT */
2781 assert(ISL_DEV_GEN(dev
) >= 5);
2782 return 3; /* D24_UNORM_X8_UINT */
2784 case ISL_FORMAT_R16_UNORM
:
2785 assert(!has_stencil
);
2786 return 5; /* D16_UNORM */
2791 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2792 struct isl_swizzle swizzle
)
2794 if (devinfo
->is_haswell
) {
2795 /* From the Haswell PRM,
2796 * RENDER_SURFACE_STATE::Shader Channel Select Red
2798 * "The Shader channel selects also define which shader channels are
2799 * written to which surface channel. If the Shader channel select is
2800 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2801 * shader channel select is SCS_RED it is written to the surface red
2802 * channel and so on. If more than one shader channel select is set
2803 * to the same surface channel only the first shader channel in RGBA
2804 * order will be written."
2807 } else if (devinfo
->gen
<= 7) {
2808 /* Ivy Bridge and early doesn't have any swizzling */
2809 return isl_swizzle_is_identity(swizzle
);
2811 /* From the Sky Lake PRM Vol. 2d,
2812 * RENDER_SURFACE_STATE::Shader Channel Select Red
2814 * "For Render Target, Red, Green and Blue Shader Channel Selects
2815 * MUST be such that only valid components can be swapped i.e. only
2816 * change the order of components in the pixel. Any other values for
2817 * these Shader Channel Select fields are not valid for Render
2818 * Targets. This also means that there MUST not be multiple shader
2819 * channels mapped to the same RT channel."
2821 * From the Sky Lake PRM Vol. 2d,
2822 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2824 * "For Render Target, this field MUST be programmed to
2825 * value = SCS_ALPHA."
2827 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2828 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2829 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2830 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2831 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2832 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2833 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2834 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2835 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2836 swizzle
.r
!= swizzle
.g
&&
2837 swizzle
.r
!= swizzle
.b
&&
2838 swizzle
.g
!= swizzle
.b
&&
2839 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2843 static enum isl_channel_select
2844 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2847 case ISL_CHANNEL_SELECT_ZERO
:
2848 case ISL_CHANNEL_SELECT_ONE
:
2850 case ISL_CHANNEL_SELECT_RED
:
2852 case ISL_CHANNEL_SELECT_GREEN
:
2854 case ISL_CHANNEL_SELECT_BLUE
:
2856 case ISL_CHANNEL_SELECT_ALPHA
:
2859 unreachable("Invalid swizzle component");
2864 * Returns the single swizzle that is equivalent to applying the two given
2865 * swizzles in sequence.
2868 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2870 return (struct isl_swizzle
) {
2871 .r
= swizzle_select(first
.r
, second
),
2872 .g
= swizzle_select(first
.g
, second
),
2873 .b
= swizzle_select(first
.b
, second
),
2874 .a
= swizzle_select(first
.a
, second
),
2879 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2882 isl_swizzle_invert(struct isl_swizzle swizzle
)
2884 /* Default to zero for channels which do not show up in the swizzle */
2885 enum isl_channel_select chans
[4] = {
2886 ISL_CHANNEL_SELECT_ZERO
,
2887 ISL_CHANNEL_SELECT_ZERO
,
2888 ISL_CHANNEL_SELECT_ZERO
,
2889 ISL_CHANNEL_SELECT_ZERO
,
2892 /* We go in ABGR order so that, if there are any duplicates, the first one
2893 * is taken if you look at it in RGBA order. This is what Haswell hardware
2894 * does for render target swizzles.
2896 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2897 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2898 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2899 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2900 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2901 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2902 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2903 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2905 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };
2908 /** Applies an inverse swizzle to a color value */
2909 union isl_color_value
2910 isl_color_value_swizzle_inv(union isl_color_value src
,
2911 struct isl_swizzle swizzle
)
2913 union isl_color_value dst
= { .u32
= { 0, } };
2915 /* We assign colors in ABGR order so that the first one will be taken in
2916 * RGBA precedence order. According to the PRM docs for shader channel
2917 * select, this matches Haswell hardware behavior.
2919 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2920 dst
.u32
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[3];
2921 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2922 dst
.u32
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[2];
2923 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2924 dst
.u32
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[1];
2925 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2926 dst
.u32
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = src
.u32
[0];
2932 isl_format_get_aux_map_encoding(enum isl_format format
)
2935 case ISL_FORMAT_R32G32B32A32_FLOAT
: return 0x11;
2936 case ISL_FORMAT_R32G32B32X32_FLOAT
: return 0x11;
2937 case ISL_FORMAT_R32G32B32A32_SINT
: return 0x12;
2938 case ISL_FORMAT_R32G32B32A32_UINT
: return 0x13;
2939 case ISL_FORMAT_R16G16B16A16_UNORM
: return 0x14;
2940 case ISL_FORMAT_R16G16B16A16_SNORM
: return 0x15;
2941 case ISL_FORMAT_R16G16B16A16_SINT
: return 0x16;
2942 case ISL_FORMAT_R16G16B16A16_UINT
: return 0x17;
2943 case ISL_FORMAT_R16G16B16A16_FLOAT
: return 0x10;
2944 case ISL_FORMAT_R16G16B16X16_FLOAT
: return 0x10;
2945 case ISL_FORMAT_R32G32_FLOAT
: return 0x11;
2946 case ISL_FORMAT_R32G32_SINT
: return 0x12;
2947 case ISL_FORMAT_R32G32_UINT
: return 0x13;
2948 case ISL_FORMAT_B8G8R8A8_UNORM
: return 0xA;
2949 case ISL_FORMAT_B8G8R8X8_UNORM
: return 0xA;
2950 case ISL_FORMAT_B8G8R8A8_UNORM_SRGB
: return 0xA;
2951 case ISL_FORMAT_B8G8R8X8_UNORM_SRGB
: return 0xA;
2952 case ISL_FORMAT_R10G10B10A2_UNORM
: return 0x18;
2953 case ISL_FORMAT_R10G10B10A2_UNORM_SRGB
: return 0x18;
2954 case ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM
: return 0x19;
2955 case ISL_FORMAT_R10G10B10A2_UINT
: return 0x1A;
2956 case ISL_FORMAT_R8G8B8A8_UNORM
: return 0xA;
2957 case ISL_FORMAT_R8G8B8A8_UNORM_SRGB
: return 0xA;
2958 case ISL_FORMAT_R8G8B8A8_SNORM
: return 0x1B;
2959 case ISL_FORMAT_R8G8B8A8_SINT
: return 0x1C;
2960 case ISL_FORMAT_R8G8B8A8_UINT
: return 0x1D;
2961 case ISL_FORMAT_R16G16_UNORM
: return 0x14;
2962 case ISL_FORMAT_R16G16_SNORM
: return 0x15;
2963 case ISL_FORMAT_R16G16_SINT
: return 0x16;
2964 case ISL_FORMAT_R16G16_UINT
: return 0x17;
2965 case ISL_FORMAT_R16G16_FLOAT
: return 0x10;
2966 case ISL_FORMAT_B10G10R10A2_UNORM
: return 0x18;
2967 case ISL_FORMAT_B10G10R10A2_UNORM_SRGB
: return 0x18;
2968 case ISL_FORMAT_R11G11B10_FLOAT
: return 0x1E;
2969 case ISL_FORMAT_R32_SINT
: return 0x12;
2970 case ISL_FORMAT_R32_UINT
: return 0x13;
2971 case ISL_FORMAT_R32_FLOAT
: return 0x11;
2972 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
: return 0x11;
2973 case ISL_FORMAT_B5G6R5_UNORM
: return 0xA;
2974 case ISL_FORMAT_B5G6R5_UNORM_SRGB
: return 0xA;
2975 case ISL_FORMAT_B5G5R5A1_UNORM
: return 0xA;
2976 case ISL_FORMAT_B5G5R5A1_UNORM_SRGB
: return 0xA;
2977 case ISL_FORMAT_B4G4R4A4_UNORM
: return 0xA;
2978 case ISL_FORMAT_B4G4R4A4_UNORM_SRGB
: return 0xA;
2979 case ISL_FORMAT_R8G8_UNORM
: return 0xA;
2980 case ISL_FORMAT_R8G8_SNORM
: return 0x1B;
2981 case ISL_FORMAT_R8G8_SINT
: return 0x1C;
2982 case ISL_FORMAT_R8G8_UINT
: return 0x1D;
2983 case ISL_FORMAT_R16_UNORM
: return 0x14;
2984 case ISL_FORMAT_R16_SNORM
: return 0x15;
2985 case ISL_FORMAT_R16_SINT
: return 0x16;
2986 case ISL_FORMAT_R16_UINT
: return 0x17;
2987 case ISL_FORMAT_R16_FLOAT
: return 0x10;
2988 case ISL_FORMAT_B5G5R5X1_UNORM
: return 0xA;
2989 case ISL_FORMAT_B5G5R5X1_UNORM_SRGB
: return 0xA;
2990 case ISL_FORMAT_A1B5G5R5_UNORM
: return 0xA;
2991 case ISL_FORMAT_A4B4G4R4_UNORM
: return 0xA;
2992 case ISL_FORMAT_R8_UNORM
: return 0xA;
2993 case ISL_FORMAT_R8_SNORM
: return 0x1B;
2994 case ISL_FORMAT_R8_SINT
: return 0x1C;
2995 case ISL_FORMAT_R8_UINT
: return 0x1D;
2996 case ISL_FORMAT_A8_UNORM
: return 0xA;
2998 unreachable("Unsupported aux-map format!");