2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
52 isl_device_init(struct isl_device
*dev
,
53 const struct gen_device_info
*info
,
54 bool has_bit6_swizzling
)
57 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
58 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
60 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
61 * device properties at buildtime. Verify that the macros with the device
62 * properties chosen during runtime.
64 ISL_DEV_GEN_SANITIZE(dev
);
65 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
67 /* Did we break hiz or stencil? */
68 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
69 assert(info
->has_hiz_and_separate_stencil
);
70 if (info
->must_use_separate_stencil
)
71 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
74 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
76 dev
->ss
.clear_value_size
=
77 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
78 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
79 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
80 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
82 dev
->ss
.clear_value_offset
=
83 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
85 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
87 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
89 /* The "Auxiliary Surface Base Address" field starts a bit higher up
90 * because the bottom 12 bits are used for other things. Round down to
91 * the nearest dword before.
93 dev
->ss
.aux_addr_offset
=
94 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
96 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
97 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
98 dev
->ds
.depth_offset
=
99 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
101 if (dev
->use_separate_stencil
) {
102 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
103 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
104 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
106 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
107 dev
->ds
.stencil_offset
=
108 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
109 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
111 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
113 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
114 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
115 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
117 dev
->ds
.stencil_offset
= 0;
118 dev
->ds
.hiz_offset
= 0;
123 * @brief Query the set of multisamples supported by the device.
125 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
128 isl_sample_count_mask_t ATTRIBUTE_CONST
129 isl_device_get_sample_counts(struct isl_device
*dev
)
131 if (ISL_DEV_GEN(dev
) >= 9) {
132 return ISL_SAMPLE_COUNT_1_BIT
|
133 ISL_SAMPLE_COUNT_2_BIT
|
134 ISL_SAMPLE_COUNT_4_BIT
|
135 ISL_SAMPLE_COUNT_8_BIT
|
136 ISL_SAMPLE_COUNT_16_BIT
;
137 } else if (ISL_DEV_GEN(dev
) >= 8) {
138 return ISL_SAMPLE_COUNT_1_BIT
|
139 ISL_SAMPLE_COUNT_2_BIT
|
140 ISL_SAMPLE_COUNT_4_BIT
|
141 ISL_SAMPLE_COUNT_8_BIT
;
142 } else if (ISL_DEV_GEN(dev
) >= 7) {
143 return ISL_SAMPLE_COUNT_1_BIT
|
144 ISL_SAMPLE_COUNT_4_BIT
|
145 ISL_SAMPLE_COUNT_8_BIT
;
146 } else if (ISL_DEV_GEN(dev
) >= 6) {
147 return ISL_SAMPLE_COUNT_1_BIT
|
148 ISL_SAMPLE_COUNT_4_BIT
;
150 return ISL_SAMPLE_COUNT_1_BIT
;
155 * @param[out] info is written only on success
158 isl_tiling_get_info(enum isl_tiling tiling
,
160 struct isl_tile_info
*tile_info
)
162 const uint32_t bs
= format_bpb
/ 8;
163 struct isl_extent2d logical_el
, phys_B
;
165 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
166 /* It is possible to have non-power-of-two formats in a tiled buffer.
167 * The easiest way to handle this is to treat the tile as if it is three
168 * times as wide. This way no pixel will ever cross a tile boundary.
169 * This really only works on legacy X and Y tiling formats.
171 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
172 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
173 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
178 case ISL_TILING_LINEAR
:
180 logical_el
= isl_extent2d(1, 1);
181 phys_B
= isl_extent2d(bs
, 1);
186 logical_el
= isl_extent2d(512 / bs
, 8);
187 phys_B
= isl_extent2d(512, 8);
192 logical_el
= isl_extent2d(128 / bs
, 32);
193 phys_B
= isl_extent2d(128, 32);
198 logical_el
= isl_extent2d(64, 64);
199 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
201 * "If the surface is a stencil buffer (and thus has Tile Mode set
202 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
203 * computed based on width, as the stencil buffer is stored with two
206 * This, together with the fact that stencil buffers are referred to as
207 * being Y-tiled in the PRMs for older hardware implies that the
208 * physical size of a W-tile is actually the same as for a Y-tile.
210 phys_B
= isl_extent2d(128, 32);
214 case ISL_TILING_Ys
: {
215 bool is_Ys
= tiling
== ISL_TILING_Ys
;
218 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
219 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
221 logical_el
= isl_extent2d(width
/ bs
, height
);
222 phys_B
= isl_extent2d(width
, height
);
227 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
228 * 128bpb format. The tiling has the same physical dimensions as
229 * Y-tiling but actually has two HiZ columns per Y-tiled column.
232 logical_el
= isl_extent2d(16, 16);
233 phys_B
= isl_extent2d(128, 32);
237 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
238 * have a block size of 1 or 2 bits per block and each CCS element
239 * corresponds to one cache-line pair in the main surface. From the Sky
240 * Lake PRM Vol. 12 in the section on planes:
242 * "The Color Control Surface (CCS) contains the compression status
243 * of the cache-line pairs. The compression state of the cache-line
244 * pair is specified by 2 bits in the CCS. Each CCS cache-line
245 * represents an area on the main surface of 16x16 sets of 128 byte
246 * Y-tiled cache-line-pairs. CCS is always Y tiled."
248 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
249 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
250 * that yields total tile area of 128x128 cache-line pairs or CCS
251 * elements. On older hardware, each CCS element is 1 bit and the tile
252 * is 128x256 elements.
254 assert(format_bpb
== 1 || format_bpb
== 2);
255 logical_el
= isl_extent2d(128, 256 / format_bpb
);
256 phys_B
= isl_extent2d(128, 32);
260 unreachable("not reached");
263 *tile_info
= (struct isl_tile_info
) {
265 .format_bpb
= format_bpb
,
266 .logical_extent_el
= logical_el
,
267 .phys_extent_B
= phys_B
,
272 isl_color_value_is_zero_one(union isl_color_value value
,
273 enum isl_format format
)
275 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
277 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
278 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
281 if (isl_format_has_int_channel(format
)) {
282 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
283 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
284 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
285 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
287 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
288 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
289 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
290 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
293 #undef RETURN_FALSE_IF_NOT_0_1
299 * @param[out] tiling is set only on success
302 isl_surf_choose_tiling(const struct isl_device
*dev
,
303 const struct isl_surf_init_info
*restrict info
,
304 enum isl_tiling
*tiling
)
306 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
308 /* HiZ surfaces always use the HiZ tiling */
309 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
310 assert(info
->format
== ISL_FORMAT_HIZ
);
311 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
312 *tiling
= ISL_TILING_HIZ
;
316 /* CCS surfaces always use the CCS tiling */
317 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
318 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
319 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
320 *tiling
= ISL_TILING_CCS
;
324 if (ISL_DEV_GEN(dev
) >= 6) {
325 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
327 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
330 #define CHOOSE(__tiling) \
332 if (tiling_flags & (1u << (__tiling))) { \
333 *tiling = (__tiling); \
338 /* Of the tiling modes remaining, choose the one that offers the best
342 if (info
->dim
== ISL_SURF_DIM_1D
) {
343 /* Prefer linear for 1D surfaces because they do not benefit from
344 * tiling. To the contrary, tiling leads to wasted memory and poor
345 * memory locality due to the swizzling and alignment restrictions
346 * required in tiled surfaces.
348 CHOOSE(ISL_TILING_LINEAR
);
351 CHOOSE(ISL_TILING_Ys
);
352 CHOOSE(ISL_TILING_Yf
);
353 CHOOSE(ISL_TILING_Y0
);
354 CHOOSE(ISL_TILING_X
);
355 CHOOSE(ISL_TILING_W
);
356 CHOOSE(ISL_TILING_LINEAR
);
360 /* No tiling mode accomodates the inputs. */
365 isl_choose_msaa_layout(const struct isl_device
*dev
,
366 const struct isl_surf_init_info
*info
,
367 enum isl_tiling tiling
,
368 enum isl_msaa_layout
*msaa_layout
)
370 if (ISL_DEV_GEN(dev
) >= 8) {
371 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
372 } else if (ISL_DEV_GEN(dev
) >= 7) {
373 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
374 } else if (ISL_DEV_GEN(dev
) >= 6) {
375 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
377 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
382 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
384 assert(isl_is_pow2(samples
));
386 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
389 * If the surface is multisampled and it is a depth or stencil surface
390 * or Multisampled Surface StorageFormat in SURFACE_STATE is
391 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
394 return (struct isl_extent2d
) {
395 .width
= 1 << ((ffs(samples
) - 0) / 2),
396 .height
= 1 << ((ffs(samples
) - 1) / 2),
401 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
402 uint32_t *width
, uint32_t *height
)
404 const struct isl_extent2d px_size_sa
=
405 isl_get_interleaved_msaa_px_size_sa(samples
);
408 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
410 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
413 static enum isl_array_pitch_span
414 isl_choose_array_pitch_span(const struct isl_device
*dev
,
415 const struct isl_surf_init_info
*restrict info
,
416 enum isl_dim_layout dim_layout
,
417 const struct isl_extent4d
*phys_level0_sa
)
419 switch (dim_layout
) {
420 case ISL_DIM_LAYOUT_GEN9_1D
:
421 case ISL_DIM_LAYOUT_GEN4_2D
:
422 if (ISL_DEV_GEN(dev
) >= 8) {
423 /* QPitch becomes programmable in Broadwell. So choose the
424 * most compact QPitch possible in order to conserve memory.
426 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
427 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
429 * - Software must ensure that this field is set to a value
430 * sufficiently large such that the array slices in the surface
431 * do not overlap. Refer to the Memory Data Formats section for
432 * information on how surfaces are stored in memory.
434 * - This field specifies the distance in rows between array
435 * slices. It is used only in the following cases:
437 * - Surface Array is enabled OR
438 * - Number of Mulitsamples is not NUMSAMPLES_1 and
439 * Multisampled Surface Storage Format set to MSFMT_MSS OR
440 * - Surface Type is SURFTYPE_CUBE
442 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
443 } else if (ISL_DEV_GEN(dev
) >= 7) {
444 /* Note that Ivybridge introduces
445 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
446 * driver more control over the QPitch.
449 if (phys_level0_sa
->array_len
== 1) {
450 /* The hardware will never use the QPitch. So choose the most
451 * compact QPitch possible in order to conserve memory.
453 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
456 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
457 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
458 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
459 * Section 6.18.4.7: Surface Arrays (p112):
461 * If Surface Array Spacing is set to ARYSPC_FULL (note that
462 * the depth buffer and stencil buffer have an implied value of
465 return ISL_ARRAY_PITCH_SPAN_FULL
;
468 if (info
->levels
== 1) {
469 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
472 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
475 return ISL_ARRAY_PITCH_SPAN_FULL
;
476 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
477 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
478 isl_surf_usage_is_stencil(info
->usage
)) {
479 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
480 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
482 * The separate stencil buffer does not support mip mapping, thus
483 * the storage for LODs other than LOD 0 is not needed.
485 assert(info
->levels
== 1);
486 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
488 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
489 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
490 isl_surf_usage_is_stencil(info
->usage
)) {
491 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
492 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
494 * The separate stencil buffer does not support mip mapping,
495 * thus the storage for LODs other than LOD 0 is not needed.
497 assert(info
->levels
== 1);
498 assert(phys_level0_sa
->array_len
== 1);
499 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
502 if (phys_level0_sa
->array_len
== 1) {
503 /* The hardware will never use the QPitch. So choose the most
504 * compact QPitch possible in order to conserve memory.
506 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
509 return ISL_ARRAY_PITCH_SPAN_FULL
;
512 case ISL_DIM_LAYOUT_GEN4_3D
:
513 /* The hardware will never use the QPitch. So choose the most
514 * compact QPitch possible in order to conserve memory.
516 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
518 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
519 /* Each array image in the gen6 stencil of HiZ surface is compact in the
520 * sense that every LOD is a compact array of the same size as LOD0.
522 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
525 unreachable("bad isl_dim_layout");
526 return ISL_ARRAY_PITCH_SPAN_FULL
;
530 isl_choose_image_alignment_el(const struct isl_device
*dev
,
531 const struct isl_surf_init_info
*restrict info
,
532 enum isl_tiling tiling
,
533 enum isl_dim_layout dim_layout
,
534 enum isl_msaa_layout msaa_layout
,
535 struct isl_extent3d
*image_align_el
)
537 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
538 if (fmtl
->txc
== ISL_TXC_MCS
) {
539 assert(tiling
== ISL_TILING_Y0
);
542 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
544 * Height, width, and layout of MCS buffer in this case must match with
545 * Render Target height, width, and layout. MCS buffer is tiledY.
547 * To avoid wasting memory, choose the smallest alignment possible:
548 * HALIGN_4 and VALIGN_4.
550 *image_align_el
= isl_extent3d(4, 4, 1);
552 } else if (info
->format
== ISL_FORMAT_HIZ
) {
553 assert(ISL_DEV_GEN(dev
) >= 6);
554 if (ISL_DEV_GEN(dev
) == 6) {
555 /* HiZ surfaces on Sandy Bridge are packed tightly. */
556 *image_align_el
= isl_extent3d(1, 1, 1);
558 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
559 * primary surface which works out to 2x2 HiZ elments.
561 *image_align_el
= isl_extent3d(2, 2, 1);
566 if (ISL_DEV_GEN(dev
) >= 9) {
567 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
568 msaa_layout
, image_align_el
);
569 } else if (ISL_DEV_GEN(dev
) >= 8) {
570 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
571 msaa_layout
, image_align_el
);
572 } else if (ISL_DEV_GEN(dev
) >= 7) {
573 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
574 msaa_layout
, image_align_el
);
575 } else if (ISL_DEV_GEN(dev
) >= 6) {
576 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
577 msaa_layout
, image_align_el
);
579 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
580 msaa_layout
, image_align_el
);
584 static enum isl_dim_layout
585 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
586 enum isl_surf_dim logical_dim
,
587 enum isl_tiling tiling
,
588 isl_surf_usage_flags_t usage
)
590 /* Sandy bridge needs a special layout for HiZ and stencil. */
591 if (ISL_DEV_GEN(dev
) == 6 &&
592 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
593 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
595 if (ISL_DEV_GEN(dev
) >= 9) {
596 switch (logical_dim
) {
597 case ISL_SURF_DIM_1D
:
598 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
600 * One-dimensional surfaces use a tiling mode of linear.
601 * Technically, they are not tiled resources, but the Tiled
602 * Resource Mode field in RENDER_SURFACE_STATE is still used to
603 * indicate the alignment requirements for this linear surface
604 * (See 1D Alignment requirements for how 4K and 64KB Tiled
605 * Resource Modes impact alignment). Alternatively, a 1D surface
606 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
609 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
610 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
612 if (tiling
== ISL_TILING_LINEAR
)
613 return ISL_DIM_LAYOUT_GEN9_1D
;
615 return ISL_DIM_LAYOUT_GEN4_2D
;
616 case ISL_SURF_DIM_2D
:
617 case ISL_SURF_DIM_3D
:
618 return ISL_DIM_LAYOUT_GEN4_2D
;
621 switch (logical_dim
) {
622 case ISL_SURF_DIM_1D
:
623 case ISL_SURF_DIM_2D
:
624 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
626 * The cube face textures are stored in the same way as 3D surfaces
627 * are stored (see section 6.17.5 for details). For cube surfaces,
628 * however, the depth is equal to the number of faces (always 6) and
629 * is not reduced for each MIP.
631 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
632 return ISL_DIM_LAYOUT_GEN4_3D
;
634 return ISL_DIM_LAYOUT_GEN4_2D
;
635 case ISL_SURF_DIM_3D
:
636 return ISL_DIM_LAYOUT_GEN4_3D
;
640 unreachable("bad isl_surf_dim");
641 return ISL_DIM_LAYOUT_GEN4_2D
;
645 * Calculate the physical extent of the surface's first level, in units of
646 * surface samples. The result is aligned to the format's compression block.
649 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
650 const struct isl_surf_init_info
*restrict info
,
651 enum isl_dim_layout dim_layout
,
652 enum isl_tiling tiling
,
653 enum isl_msaa_layout msaa_layout
,
654 struct isl_extent4d
*phys_level0_sa
)
656 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
658 if (isl_format_is_yuv(info
->format
))
659 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
662 case ISL_SURF_DIM_1D
:
663 assert(info
->height
== 1);
664 assert(info
->depth
== 1);
665 assert(info
->samples
== 1);
667 switch (dim_layout
) {
668 case ISL_DIM_LAYOUT_GEN4_3D
:
669 unreachable("bad isl_dim_layout");
671 case ISL_DIM_LAYOUT_GEN9_1D
:
672 case ISL_DIM_LAYOUT_GEN4_2D
:
673 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
674 *phys_level0_sa
= (struct isl_extent4d
) {
675 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
678 .a
= info
->array_len
,
684 case ISL_SURF_DIM_2D
:
685 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
686 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
688 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
689 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
691 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
692 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
694 switch (msaa_layout
) {
695 case ISL_MSAA_LAYOUT_NONE
:
696 assert(info
->depth
== 1);
697 assert(info
->samples
== 1);
699 *phys_level0_sa
= (struct isl_extent4d
) {
700 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
701 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
703 .a
= info
->array_len
,
707 case ISL_MSAA_LAYOUT_ARRAY
:
708 assert(info
->depth
== 1);
709 assert(info
->levels
== 1);
710 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
711 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
713 *phys_level0_sa
= (struct isl_extent4d
) {
717 .a
= info
->array_len
* info
->samples
,
721 case ISL_MSAA_LAYOUT_INTERLEAVED
:
722 assert(info
->depth
== 1);
723 assert(info
->levels
== 1);
724 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
726 *phys_level0_sa
= (struct isl_extent4d
) {
730 .a
= info
->array_len
,
733 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
737 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
738 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
743 case ISL_SURF_DIM_3D
:
744 assert(info
->array_len
== 1);
745 assert(info
->samples
== 1);
748 isl_finishme("%s:%s: compression block with depth > 1",
752 switch (dim_layout
) {
753 case ISL_DIM_LAYOUT_GEN9_1D
:
754 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
755 unreachable("bad isl_dim_layout");
757 case ISL_DIM_LAYOUT_GEN4_2D
:
758 assert(ISL_DEV_GEN(dev
) >= 9);
760 *phys_level0_sa
= (struct isl_extent4d
) {
761 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
762 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
768 case ISL_DIM_LAYOUT_GEN4_3D
:
769 assert(ISL_DEV_GEN(dev
) < 9);
770 *phys_level0_sa
= (struct isl_extent4d
) {
771 .w
= isl_align(info
->width
, fmtl
->bw
),
772 .h
= isl_align(info
->height
, fmtl
->bh
),
783 * Calculate the pitch between physical array slices, in units of rows of
787 isl_calc_array_pitch_el_rows_gen4_2d(
788 const struct isl_device
*dev
,
789 const struct isl_surf_init_info
*restrict info
,
790 const struct isl_tile_info
*tile_info
,
791 const struct isl_extent3d
*image_align_sa
,
792 const struct isl_extent4d
*phys_level0_sa
,
793 enum isl_array_pitch_span array_pitch_span
,
794 const struct isl_extent2d
*phys_slice0_sa
)
796 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
797 uint32_t pitch_sa_rows
= 0;
799 switch (array_pitch_span
) {
800 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
801 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
803 case ISL_ARRAY_PITCH_SPAN_FULL
: {
804 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
805 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
806 * Surfaces >> Surface Arrays.
808 uint32_t H0_sa
= phys_level0_sa
->h
;
809 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
811 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
812 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
815 if (ISL_DEV_GEN(dev
) >= 7) {
816 /* The QPitch equation changed slightly in Ivybridge. */
822 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
824 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
825 (info
->height
% 4 == 1)) {
826 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
827 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
829 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
830 * the value calculated in the equation above , for every
831 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
833 * XXX(chadv): Is the errata natural corollary of the physical
834 * layout of interleaved samples?
839 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
844 assert(pitch_sa_rows
% fmtl
->bh
== 0);
845 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
847 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
849 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
851 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
852 * layout with these alignments in the RT space: Horizontal
853 * Alignment = 128 and Vertical Alignment = 64."
855 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
857 * "For non-multisampled render target's CCS auxiliary surface,
858 * QPitch must be computed with Horizontal Alignment = 128 and
859 * Surface Vertical Alignment = 256. These alignments are only for
860 * CCS buffer and not for associated render target."
862 * The first restriction is already handled by isl_choose_image_alignment_el
863 * but the second restriction, which is an extension of the first, only
864 * applies to qpitch and must be applied here.
866 assert(fmtl
->bh
== 4);
867 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
870 if (ISL_DEV_GEN(dev
) >= 9 &&
871 info
->dim
== ISL_SURF_DIM_3D
&&
872 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
873 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
875 * Tile Mode != Linear: This field must be set to an integer multiple
878 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
881 return pitch_el_rows
;
885 * A variant of isl_calc_phys_slice0_extent_sa() specific to
886 * ISL_DIM_LAYOUT_GEN4_2D.
889 isl_calc_phys_slice0_extent_sa_gen4_2d(
890 const struct isl_device
*dev
,
891 const struct isl_surf_init_info
*restrict info
,
892 enum isl_msaa_layout msaa_layout
,
893 const struct isl_extent3d
*image_align_sa
,
894 const struct isl_extent4d
*phys_level0_sa
,
895 struct isl_extent2d
*phys_slice0_sa
)
897 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
899 assert(phys_level0_sa
->depth
== 1);
901 if (info
->levels
== 1) {
902 /* Do not pad the surface to the image alignment. Instead, pad it only
903 * to the pixel format's block alignment.
905 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
906 * cycles on the below mipmap layout caluclations. Reducing the
907 * alignment here is safe because we later align the row pitch and array
908 * pitch to the tile boundary. It is safe even for
909 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
910 * to accomodate the interleaved samples.
912 * For linear surfaces, reducing the alignment here permits us to later
913 * choose an arbitrary, non-aligned row pitch. If the surface backs
914 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
915 * VkBufferImageCopy::bufferRowLength.
917 *phys_slice0_sa
= (struct isl_extent2d
) {
918 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
919 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
924 uint32_t slice_top_w
= 0;
925 uint32_t slice_bottom_w
= 0;
926 uint32_t slice_left_h
= 0;
927 uint32_t slice_right_h
= 0;
929 uint32_t W0
= phys_level0_sa
->w
;
930 uint32_t H0
= phys_level0_sa
->h
;
932 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
933 uint32_t W
= isl_minify(W0
, l
);
934 uint32_t H
= isl_minify(H0
, l
);
936 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
937 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
954 *phys_slice0_sa
= (struct isl_extent2d
) {
955 .w
= MAX(slice_top_w
, slice_bottom_w
),
956 .h
= MAX(slice_left_h
, slice_right_h
),
961 isl_calc_phys_total_extent_el_gen4_2d(
962 const struct isl_device
*dev
,
963 const struct isl_surf_init_info
*restrict info
,
964 const struct isl_tile_info
*tile_info
,
965 enum isl_msaa_layout msaa_layout
,
966 const struct isl_extent3d
*image_align_sa
,
967 const struct isl_extent4d
*phys_level0_sa
,
968 enum isl_array_pitch_span array_pitch_span
,
969 uint32_t *array_pitch_el_rows
,
970 struct isl_extent2d
*total_extent_el
)
972 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
974 struct isl_extent2d phys_slice0_sa
;
975 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
976 image_align_sa
, phys_level0_sa
,
978 *array_pitch_el_rows
=
979 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
980 image_align_sa
, phys_level0_sa
,
983 *total_extent_el
= (struct isl_extent2d
) {
984 .w
= isl_assert_div(phys_slice0_sa
.w
, fmtl
->bw
),
985 .h
= *array_pitch_el_rows
* phys_level0_sa
->array_len
,
990 * A variant of isl_calc_phys_slice0_extent_sa() specific to
991 * ISL_DIM_LAYOUT_GEN4_3D.
994 isl_calc_phys_total_extent_el_gen4_3d(
995 const struct isl_device
*dev
,
996 const struct isl_surf_init_info
*restrict info
,
997 const struct isl_extent3d
*image_align_sa
,
998 const struct isl_extent4d
*phys_level0_sa
,
999 uint32_t *array_pitch_el_rows
,
1000 struct isl_extent2d
*phys_total_el
)
1002 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1004 assert(info
->samples
== 1);
1006 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1007 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1009 * The cube face textures are stored in the same way as 3D surfaces
1010 * are stored (see section 6.17.5 for details). For cube surfaces,
1011 * however, the depth is equal to the number of faces (always 6) and
1012 * is not reduced for each MIP.
1014 assert(ISL_DEV_GEN(dev
) == 4);
1015 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1016 assert(phys_level0_sa
->array_len
== 6);
1018 assert(phys_level0_sa
->array_len
== 1);
1021 uint32_t total_w
= 0;
1022 uint32_t total_h
= 0;
1024 uint32_t W0
= phys_level0_sa
->w
;
1025 uint32_t H0
= phys_level0_sa
->h
;
1026 uint32_t D0
= phys_level0_sa
->d
;
1027 uint32_t A0
= phys_level0_sa
->a
;
1029 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1030 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1031 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1032 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1034 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1035 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1037 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1038 total_h
+= level_h
* max_layers_vert
;
1041 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1042 * different number of horizontal and vertical layers. We have to set it
1043 * to something, so at least make it true for LOD0.
1045 *array_pitch_el_rows
=
1046 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1047 *phys_total_el
= (struct isl_extent2d
) {
1048 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1049 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1054 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1055 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1058 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1059 const struct isl_device
*dev
,
1060 const struct isl_surf_init_info
*restrict info
,
1061 const struct isl_tile_info
*tile_info
,
1062 const struct isl_extent3d
*image_align_sa
,
1063 const struct isl_extent4d
*phys_level0_sa
,
1064 uint32_t *array_pitch_el_rows
,
1065 struct isl_extent2d
*phys_total_el
)
1067 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1069 const struct isl_extent2d tile_extent_sa
= {
1070 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1071 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1073 /* Tile size is a multiple of image alignment */
1074 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1075 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1077 const uint32_t W0
= phys_level0_sa
->w
;
1078 const uint32_t H0
= phys_level0_sa
->h
;
1080 /* Each image has the same height as LOD0 because the hardware thinks
1081 * everything is LOD0
1083 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1085 uint32_t total_top_w
= 0;
1086 uint32_t total_bottom_w
= 0;
1087 uint32_t total_h
= 0;
1089 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1090 const uint32_t W
= isl_minify(W0
, l
);
1092 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1093 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1098 } else if (l
== 1) {
1102 total_bottom_w
+= w
;
1106 *array_pitch_el_rows
=
1107 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1108 *phys_total_el
= (struct isl_extent2d
) {
1109 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1110 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1115 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1116 * ISL_DIM_LAYOUT_GEN9_1D.
1119 isl_calc_phys_total_extent_el_gen9_1d(
1120 const struct isl_device
*dev
,
1121 const struct isl_surf_init_info
*restrict info
,
1122 const struct isl_extent3d
*image_align_sa
,
1123 const struct isl_extent4d
*phys_level0_sa
,
1124 uint32_t *array_pitch_el_rows
,
1125 struct isl_extent2d
*phys_total_el
)
1127 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1129 assert(phys_level0_sa
->height
/ fmtl
->bh
== 1);
1130 assert(phys_level0_sa
->depth
== 1);
1131 assert(info
->samples
== 1);
1132 assert(image_align_sa
->w
>= fmtl
->bw
);
1134 uint32_t slice_w
= 0;
1135 const uint32_t W0
= phys_level0_sa
->w
;
1137 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1138 uint32_t W
= isl_minify(W0
, l
);
1139 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1144 *array_pitch_el_rows
= 1;
1145 *phys_total_el
= (struct isl_extent2d
) {
1146 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1147 .h
= phys_level0_sa
->array_len
,
1152 * Calculate the two-dimensional total physical extent of the surface, in
1153 * units of surface elements.
1156 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1157 const struct isl_surf_init_info
*restrict info
,
1158 const struct isl_tile_info
*tile_info
,
1159 enum isl_dim_layout dim_layout
,
1160 enum isl_msaa_layout msaa_layout
,
1161 const struct isl_extent3d
*image_align_sa
,
1162 const struct isl_extent4d
*phys_level0_sa
,
1163 enum isl_array_pitch_span array_pitch_span
,
1164 uint32_t *array_pitch_el_rows
,
1165 struct isl_extent2d
*total_extent_el
)
1167 switch (dim_layout
) {
1168 case ISL_DIM_LAYOUT_GEN9_1D
:
1169 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1170 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1171 image_align_sa
, phys_level0_sa
,
1172 array_pitch_el_rows
,
1175 case ISL_DIM_LAYOUT_GEN4_2D
:
1176 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1177 image_align_sa
, phys_level0_sa
,
1179 array_pitch_el_rows
,
1182 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1183 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1184 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1187 array_pitch_el_rows
,
1190 case ISL_DIM_LAYOUT_GEN4_3D
:
1191 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1192 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1193 image_align_sa
, phys_level0_sa
,
1194 array_pitch_el_rows
,
1201 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1202 const struct isl_tile_info
*tile_info
)
1204 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1205 return tile_info
->phys_extent_B
.width
;
1207 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1208 * RENDER_SURFACE_STATE Surface Pitch (p349):
1210 * - For linear render target surfaces and surfaces accessed with the
1211 * typed data port messages, the pitch must be a multiple of the
1212 * element size for non-YUV surface formats. Pitch must be
1213 * a multiple of 2 * element size for YUV surface formats.
1215 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1216 * ignore because isl doesn't do buffers.]
1218 * - For other linear surfaces, the pitch can be any multiple of
1221 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1222 const uint32_t bs
= fmtl
->bpb
/ 8;
1224 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1225 if (isl_format_is_yuv(surf_info
->format
)) {
1236 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1237 const struct isl_surf_init_info
*info
,
1238 const struct isl_extent2d
*phys_total_el
,
1241 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1242 const uint32_t bs
= fmtl
->bpb
/ 8;
1244 return isl_align_npot(bs
* phys_total_el
->w
, alignment
);
1248 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1249 const struct isl_surf_init_info
*surf_info
,
1250 const struct isl_tile_info
*tile_info
,
1251 const struct isl_extent2d
*phys_total_el
,
1254 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1256 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1258 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1259 const uint32_t total_w_tl
=
1260 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1261 tile_info
->logical_extent_el
.width
);
1263 assert(alignment
== tile_info
->phys_extent_B
.width
);
1264 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1268 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1269 const struct isl_surf_init_info
*surf_info
,
1270 const struct isl_tile_info
*tile_info
,
1271 const struct isl_extent2d
*phys_total_el
,
1274 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1275 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1278 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1279 phys_total_el
, alignment
);
1284 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1285 * size is `bits` bits?
1287 * Hardware pitch fields are offset by 1. For example, if the size of
1288 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1289 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1290 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1293 pitch_in_range(uint32_t n
, uint32_t bits
)
1296 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1300 isl_calc_row_pitch(const struct isl_device
*dev
,
1301 const struct isl_surf_init_info
*surf_info
,
1302 const struct isl_tile_info
*tile_info
,
1303 enum isl_dim_layout dim_layout
,
1304 const struct isl_extent2d
*phys_total_el
,
1305 uint32_t *out_row_pitch
)
1307 uint32_t alignment
=
1308 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1310 /* If pitch isn't given and it can be chosen freely, align it by cache line
1311 * allowing one to use blit engine on the surface.
1313 if (surf_info
->row_pitch
== 0 && tile_info
->tiling
== ISL_TILING_LINEAR
) {
1314 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
1316 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
1317 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
1318 * enabled), this address must be 4KB-aligned. When Tiling is not
1319 * enabled, this address should be CL (64byte) aligned."
1321 alignment
= MAX2(alignment
, 64);
1324 const uint32_t min_row_pitch
=
1325 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1328 uint32_t row_pitch
= min_row_pitch
;
1330 if (surf_info
->row_pitch
!= 0) {
1331 row_pitch
= surf_info
->row_pitch
;
1333 if (row_pitch
< min_row_pitch
)
1336 if (row_pitch
% alignment
!= 0)
1340 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1345 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1346 /* SurfacePitch is ignored for this layout. */
1350 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1351 ISL_SURF_USAGE_TEXTURE_BIT
|
1352 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1353 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1356 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1357 ISL_SURF_USAGE_MCS_BIT
)) &&
1358 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1361 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1362 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1365 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1366 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1369 if (surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
1370 isl_finishme("validate row pitch of stencil surfaces");
1373 *out_row_pitch
= row_pitch
;
1378 * Calculate and apply any padding required for the surface.
1380 * @param[inout] total_h_el is updated with the new height
1381 * @param[out] pad_bytes is overwritten with additional padding requirements.
1384 isl_apply_surface_padding(const struct isl_device
*dev
,
1385 const struct isl_surf_init_info
*restrict info
,
1386 const struct isl_tile_info
*tile_info
,
1387 uint32_t *total_h_el
,
1388 uint32_t *pad_bytes
)
1390 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1394 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1395 * Formats >> Surface Padding Requirements >> Render Target and Media
1398 * The data port accesses data (pixels) outside of the surface if they
1399 * are contained in the same cache request as pixels that are within the
1400 * surface. These pixels will not be returned by the requesting message,
1401 * however if these pixels lie outside of defined pages in the GTT,
1402 * a GTT error will result when the cache request is processed. In
1403 * order to avoid these GTT errors, “padding” at the bottom of the
1404 * surface is sometimes necessary.
1406 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1407 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1409 * ... Lots of padding requirements, all listed separately below.
1412 /* We can safely ignore the first padding requirement, quoted below,
1413 * because isl doesn't do buffers.
1415 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1416 * requirements are different. A buffer must be padded to the next
1417 * multiple of 256 array elements, with an additional 16 bytes added
1418 * beyond that to account for the L1 cache line.
1422 * - For compressed textures [...], padding at the bottom of the surface
1423 * is to an even compressed row.
1425 if (isl_format_is_compressed(info
->format
))
1426 *total_h_el
= isl_align(*total_h_el
, 2);
1429 * - For cube surfaces, an additional two rows of padding are required
1430 * at the bottom of the surface.
1432 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1436 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1437 * additional padding is required. These surfaces require an extra row
1438 * plus 16 bytes of padding at the bottom in addition to the general
1439 * padding requirements.
1441 if (isl_format_is_yuv(info
->format
) &&
1442 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1448 * - For linear surfaces, additional padding of 64 bytes is required at
1449 * the bottom of the surface. This is in addition to the padding
1452 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1455 /* The below text weakens, not strengthens, the padding requirements for
1456 * linear surfaces. Therefore we can safely ignore it.
1458 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1459 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1460 * padding requirement is to the next aligned 64-byte boundary beyond
1461 * the end of the surface. The rest of the padding requirements
1462 * documented above do not apply to these surfaces.
1466 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1467 * height % 4 != 0, the surface must be padded with
1468 * 4-(height % 4)*Surface Pitch # of bytes.
1470 if (ISL_DEV_GEN(dev
) >= 9 &&
1471 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1472 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1473 *total_h_el
= isl_align(*total_h_el
, 4);
1477 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1478 * to 4 times the Surface Pitch # of bytes
1480 if (ISL_DEV_GEN(dev
) >= 9 &&
1481 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1482 info
->dim
== ISL_SURF_DIM_1D
) {
1488 isl_surf_init_s(const struct isl_device
*dev
,
1489 struct isl_surf
*surf
,
1490 const struct isl_surf_init_info
*restrict info
)
1492 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1494 const struct isl_extent4d logical_level0_px
= {
1498 .a
= info
->array_len
,
1501 enum isl_tiling tiling
;
1502 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1505 struct isl_tile_info tile_info
;
1506 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1508 const enum isl_dim_layout dim_layout
=
1509 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1511 enum isl_msaa_layout msaa_layout
;
1512 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1515 struct isl_extent3d image_align_el
;
1516 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1519 struct isl_extent3d image_align_sa
=
1520 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1522 struct isl_extent4d phys_level0_sa
;
1523 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1525 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1526 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1528 enum isl_array_pitch_span array_pitch_span
=
1529 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1531 uint32_t array_pitch_el_rows
;
1532 struct isl_extent2d phys_total_el
;
1533 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1534 dim_layout
, msaa_layout
,
1535 &image_align_sa
, &phys_level0_sa
,
1536 array_pitch_span
, &array_pitch_el_rows
,
1539 uint32_t padded_h_el
= phys_total_el
.h
;
1541 isl_apply_surface_padding(dev
, info
, &tile_info
, &padded_h_el
, &pad_bytes
);
1544 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1545 &phys_total_el
, &row_pitch
))
1548 uint32_t base_alignment
;
1550 if (tiling
== ISL_TILING_LINEAR
) {
1551 size
= (uint64_t) row_pitch
* padded_h_el
+ pad_bytes
;
1553 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1555 * "The Base Address for linear render target surfaces and surfaces
1556 * accessed with the typed surface read/write data port messages must
1557 * be element-size aligned, for non-YUV surface formats, or a
1558 * multiple of 2 element-sizes for YUV surface formats. Other linear
1559 * surfaces have no alignment requirements (byte alignment is
1562 base_alignment
= MAX(1, info
->min_alignment
);
1563 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1564 if (isl_format_is_yuv(info
->format
)) {
1565 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1567 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1570 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1572 padded_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1573 const uint32_t total_h_tl
=
1574 isl_align_div(padded_h_el
, tile_info
.logical_extent_el
.height
);
1576 size
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1578 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1579 tile_info
.phys_extent_B
.height
;
1580 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1581 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1584 if (ISL_DEV_GEN(dev
) < 9) {
1585 /* From the Broadwell PRM Vol 5, Surface Layout:
1587 * "In addition to restrictions on maximum height, width, and depth,
1588 * surfaces are also restricted to a maximum size in bytes. This
1589 * maximum is 2 GB for all products and all surface types."
1591 * This comment is applicable to all Pre-gen9 platforms.
1593 if (size
> (uint64_t) 1 << 31)
1596 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1597 * "In addition to restrictions on maximum height, width, and depth,
1598 * surfaces are also restricted to a maximum size of 2^38 bytes.
1599 * All pixels within the surface must be contained within 2^38 bytes
1600 * of the base address."
1602 if (size
> (uint64_t) 1 << 38)
1606 *surf
= (struct isl_surf
) {
1608 .dim_layout
= dim_layout
,
1609 .msaa_layout
= msaa_layout
,
1611 .format
= info
->format
,
1613 .levels
= info
->levels
,
1614 .samples
= info
->samples
,
1616 .image_alignment_el
= image_align_el
,
1617 .logical_level0_px
= logical_level0_px
,
1618 .phys_level0_sa
= phys_level0_sa
,
1621 .alignment
= base_alignment
,
1622 .row_pitch
= row_pitch
,
1623 .array_pitch_el_rows
= array_pitch_el_rows
,
1624 .array_pitch_span
= array_pitch_span
,
1626 .usage
= info
->usage
,
1633 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1634 struct isl_tile_info
*tile_info
)
1636 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1637 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1641 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1642 const struct isl_surf
*surf
,
1643 struct isl_surf
*hiz_surf
)
1645 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1647 /* Multisampled depth is always interleaved */
1648 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1649 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1651 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1653 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1654 * Target View Extent, and Depth Coordinate Offset X/Y of the
1655 * hierarchical depth buffer are inherited from the depth buffer. The
1656 * height and width of the hierarchical depth buffer that must be
1657 * allocated are computed by the following formulas, where HZ is the
1658 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1659 * Z_Width, and Z_Depth values given in these formulas are those present
1660 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1662 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1663 * being applied to the table below if Number of Multisamples is set to
1664 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1665 * Z_Width must be multiplied by 4 before being applied to the table
1666 * below if Number of Multisamples is set to NUMSAMPLES_8."
1668 * In the Sky Lake PRM, the second paragraph is replaced with this:
1670 * "The Z_Height and Z_Width values must equal those present in
1671 * 3DSTATE_DEPTH_BUFFER incremented by one."
1673 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1674 * block corresponds to a region of 8x4 samples in the primary depth
1675 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1676 * a region of 8x4 pixels in the primary depth surface regardless of the
1677 * number of samples. The dimensions of a HiZ block in both pixels and
1678 * samples are given in the table below:
1680 * | SNB - BDW | SKL+
1681 * ------+-----------+-------------
1682 * 1x | 8 x 4 sa | 8 x 4 sa
1683 * MSAA | 8 x 4 px | 8 x 4 px
1684 * ------+-----------+-------------
1685 * 2x | 8 x 4 sa | 16 x 4 sa
1686 * MSAA | 4 x 4 px | 8 x 4 px
1687 * ------+-----------+-------------
1688 * 4x | 8 x 4 sa | 16 x 8 sa
1689 * MSAA | 4 x 2 px | 8 x 4 px
1690 * ------+-----------+-------------
1691 * 8x | 8 x 4 sa | 32 x 8 sa
1692 * MSAA | 2 x 2 px | 8 x 4 px
1693 * ------+-----------+-------------
1694 * 16x | N/A | 32 x 16 sa
1695 * MSAA | N/A | 8 x 4 px
1696 * ------+-----------+-------------
1698 * There are a number of different ways that this discrepency could be
1699 * handled. The way we have chosen is to simply make MSAA HiZ have the
1700 * same number of samples as the parent surface pre-Sky Lake and always be
1701 * single-sampled on Sky Lake and above. Since the block sizes of
1702 * compressed formats are given in samples, this neatly handles everything
1703 * without the need for additional HiZ formats with different block sizes
1706 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1708 return isl_surf_init(dev
, hiz_surf
,
1710 .format
= ISL_FORMAT_HIZ
,
1711 .width
= surf
->logical_level0_px
.width
,
1712 .height
= surf
->logical_level0_px
.height
,
1713 .depth
= surf
->logical_level0_px
.depth
,
1714 .levels
= surf
->levels
,
1715 .array_len
= surf
->logical_level0_px
.array_len
,
1717 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1718 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1722 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1723 const struct isl_surf
*surf
,
1724 struct isl_surf
*mcs_surf
)
1726 /* It must be multisampled with an array layout */
1727 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1729 /* The following are true of all multisampled surfaces */
1730 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1731 assert(surf
->levels
== 1);
1732 assert(surf
->logical_level0_px
.depth
== 1);
1734 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1735 * bits which means the maximum pitch of a compression surface is 512
1736 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1737 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1738 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1739 * and 8x, we have enough room for the full 16k supported by the hardware.
1741 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1744 enum isl_format mcs_format
;
1745 switch (surf
->samples
) {
1746 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1747 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1748 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1749 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1751 unreachable("Invalid sample count");
1754 return isl_surf_init(dev
, mcs_surf
,
1755 .dim
= ISL_SURF_DIM_2D
,
1756 .format
= mcs_format
,
1757 .width
= surf
->logical_level0_px
.width
,
1758 .height
= surf
->logical_level0_px
.height
,
1761 .array_len
= surf
->logical_level0_px
.array_len
,
1762 .samples
= 1, /* MCS surfaces are really single-sampled */
1763 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1764 .tiling_flags
= ISL_TILING_Y0_BIT
);
1768 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1769 const struct isl_surf
*surf
,
1770 struct isl_surf
*ccs_surf
,
1773 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1774 assert(ISL_DEV_GEN(dev
) >= 7);
1776 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1779 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1780 * work for 3D textures until gen9 where the layout of 3D textures changes
1781 * to match 2D array textures.
1783 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1786 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1787 * Non-MultiSampler Render Target Restrictions):
1789 * "Support is for non-mip-mapped and non-array surface types only."
1791 * This restriction is lifted on gen8+. Technically, it may be possible to
1792 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1793 * when rendering to the base slice. However, there is no documentation
1794 * tell us what the hardware would do in that case or what it does if you
1795 * walk off the bases slice. (Does it ignore CCS or does it start
1796 * scribbling over random memory?) We play it safe and just follow the
1797 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1799 if (ISL_DEV_GEN(dev
) <= 7 &&
1800 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1803 if (isl_format_is_compressed(surf
->format
))
1806 /* TODO: More conditions where it can fail. */
1808 enum isl_format ccs_format
;
1809 if (ISL_DEV_GEN(dev
) >= 9) {
1810 if (!isl_tiling_is_any_y(surf
->tiling
))
1813 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1814 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1815 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1816 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1820 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1821 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1822 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1823 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1824 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1828 } else if (surf
->tiling
== ISL_TILING_X
) {
1829 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1830 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1831 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1832 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1840 return isl_surf_init(dev
, ccs_surf
,
1842 .format
= ccs_format
,
1843 .width
= surf
->logical_level0_px
.width
,
1844 .height
= surf
->logical_level0_px
.height
,
1845 .depth
= surf
->logical_level0_px
.depth
,
1846 .levels
= surf
->levels
,
1847 .array_len
= surf
->logical_level0_px
.array_len
,
1849 .row_pitch
= row_pitch
,
1850 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1851 .tiling_flags
= ISL_TILING_CCS_BIT
);
1855 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1856 const struct isl_surf_fill_state_info
*restrict info
)
1859 isl_surf_usage_flags_t _base_usage
=
1860 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1861 ISL_SURF_USAGE_TEXTURE_BIT
|
1862 ISL_SURF_USAGE_STORAGE_BIT
);
1863 /* They may only specify one of the above bits at a time */
1864 assert(__builtin_popcount(_base_usage
) == 1);
1865 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1866 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1869 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1870 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1871 info
->surf
->logical_level0_px
.depth
);
1873 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1874 info
->surf
->logical_level0_px
.array_len
);
1877 switch (ISL_DEV_GEN(dev
)) {
1879 if (ISL_DEV_IS_G4X(dev
)) {
1880 /* G45 surface state is the same as gen5 */
1881 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1883 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1887 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1890 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1893 if (ISL_DEV_IS_HASWELL(dev
)) {
1894 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1896 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1900 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1903 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1906 isl_gen10_surf_fill_state_s(dev
, state
, info
);
1909 assert(!"Cannot fill surface state for this gen");
1914 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1915 const struct isl_buffer_fill_state_info
*restrict info
)
1917 switch (ISL_DEV_GEN(dev
)) {
1920 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1921 isl_gen5_buffer_fill_state_s(state
, info
);
1924 isl_gen6_buffer_fill_state_s(state
, info
);
1927 if (ISL_DEV_IS_HASWELL(dev
)) {
1928 isl_gen75_buffer_fill_state_s(state
, info
);
1930 isl_gen7_buffer_fill_state_s(state
, info
);
1934 isl_gen8_buffer_fill_state_s(state
, info
);
1937 isl_gen9_buffer_fill_state_s(state
, info
);
1940 isl_gen10_buffer_fill_state_s(state
, info
);
1943 assert(!"Cannot fill surface state for this gen");
1948 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1949 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1951 if (info
->depth_surf
&& info
->stencil_surf
) {
1952 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1953 assert(info
->depth_surf
== info
->stencil_surf
);
1954 assert(info
->depth_address
== info
->stencil_address
);
1956 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1959 if (info
->depth_surf
) {
1960 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1961 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1962 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1963 info
->depth_surf
->logical_level0_px
.depth
);
1965 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1966 info
->depth_surf
->logical_level0_px
.array_len
);
1970 if (info
->stencil_surf
) {
1971 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1972 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1973 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1974 info
->stencil_surf
->logical_level0_px
.depth
);
1976 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1977 info
->stencil_surf
->logical_level0_px
.array_len
);
1981 switch (ISL_DEV_GEN(dev
)) {
1983 if (ISL_DEV_IS_G4X(dev
)) {
1984 /* G45 surface state is the same as gen5 */
1985 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1987 isl_gen4_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1991 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1994 isl_gen6_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1997 if (ISL_DEV_IS_HASWELL(dev
)) {
1998 isl_gen75_emit_depth_stencil_hiz_s(dev
, batch
, info
);
2000 isl_gen7_emit_depth_stencil_hiz_s(dev
, batch
, info
);
2004 isl_gen8_emit_depth_stencil_hiz_s(dev
, batch
, info
);
2007 isl_gen9_emit_depth_stencil_hiz_s(dev
, batch
, info
);
2010 isl_gen10_emit_depth_stencil_hiz_s(dev
, batch
, info
);
2013 assert(!"Cannot fill surface state for this gen");
2018 * A variant of isl_surf_get_image_offset_sa() specific to
2019 * ISL_DIM_LAYOUT_GEN4_2D.
2022 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
2023 uint32_t level
, uint32_t logical_array_layer
,
2024 uint32_t *x_offset_sa
,
2025 uint32_t *y_offset_sa
)
2027 assert(level
< surf
->levels
);
2028 if (surf
->dim
== ISL_SURF_DIM_3D
)
2029 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2031 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2033 const struct isl_extent3d image_align_sa
=
2034 isl_surf_get_image_alignment_sa(surf
);
2036 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2037 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2039 const uint32_t phys_layer
= logical_array_layer
*
2040 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2043 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2045 for (uint32_t l
= 0; l
< level
; ++l
) {
2047 uint32_t W
= isl_minify(W0
, l
);
2048 x
+= isl_align_npot(W
, image_align_sa
.w
);
2050 uint32_t H
= isl_minify(H0
, l
);
2051 y
+= isl_align_npot(H
, image_align_sa
.h
);
2060 * A variant of isl_surf_get_image_offset_sa() specific to
2061 * ISL_DIM_LAYOUT_GEN4_3D.
2064 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2065 uint32_t level
, uint32_t logical_z_offset_px
,
2066 uint32_t *x_offset_sa
,
2067 uint32_t *y_offset_sa
)
2069 assert(level
< surf
->levels
);
2070 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2071 assert(surf
->phys_level0_sa
.array_len
== 1);
2072 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2074 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2075 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2076 assert(surf
->phys_level0_sa
.array_len
== 6);
2077 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2080 const struct isl_extent3d image_align_sa
=
2081 isl_surf_get_image_alignment_sa(surf
);
2083 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2084 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2085 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2086 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2091 for (uint32_t l
= 0; l
< level
; ++l
) {
2092 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2093 const uint32_t level_d
=
2094 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2096 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2098 y
+= level_h
* max_layers_vert
;
2101 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2102 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2103 const uint32_t level_d
=
2104 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2107 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2109 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2110 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2117 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2119 uint32_t logical_array_layer
,
2120 uint32_t *x_offset_sa
,
2121 uint32_t *y_offset_sa
)
2123 assert(level
< surf
->levels
);
2124 assert(surf
->logical_level0_px
.depth
== 1);
2125 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2127 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2129 const struct isl_extent3d image_align_sa
=
2130 isl_surf_get_image_alignment_sa(surf
);
2132 struct isl_tile_info tile_info
;
2133 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2134 const struct isl_extent2d tile_extent_sa
= {
2135 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2136 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2138 /* Tile size is a multiple of image alignment */
2139 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2140 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2142 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2143 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2145 /* Each image has the same height as LOD0 because the hardware thinks
2146 * everything is LOD0
2148 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2150 /* Quick sanity check for consistency */
2151 if (surf
->phys_level0_sa
.array_len
> 1)
2152 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2154 uint32_t x
= 0, y
= 0;
2155 for (uint32_t l
= 0; l
< level
; ++l
) {
2156 const uint32_t W
= isl_minify(W0
, l
);
2158 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2159 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2169 y
+= H
* logical_array_layer
;
2176 * A variant of isl_surf_get_image_offset_sa() specific to
2177 * ISL_DIM_LAYOUT_GEN9_1D.
2180 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2181 uint32_t level
, uint32_t layer
,
2182 uint32_t *x_offset_sa
,
2183 uint32_t *y_offset_sa
)
2185 assert(level
< surf
->levels
);
2186 assert(layer
< surf
->phys_level0_sa
.array_len
);
2187 assert(surf
->phys_level0_sa
.height
== 1);
2188 assert(surf
->phys_level0_sa
.depth
== 1);
2189 assert(surf
->samples
== 1);
2191 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2192 const struct isl_extent3d image_align_sa
=
2193 isl_surf_get_image_alignment_sa(surf
);
2197 for (uint32_t l
= 0; l
< level
; ++l
) {
2198 uint32_t W
= isl_minify(W0
, l
);
2199 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2205 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2209 * Calculate the offset, in units of surface samples, to a subimage in the
2212 * @invariant level < surface levels
2213 * @invariant logical_array_layer < logical array length of surface
2214 * @invariant logical_z_offset_px < logical depth of surface at level
2217 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2219 uint32_t logical_array_layer
,
2220 uint32_t logical_z_offset_px
,
2221 uint32_t *x_offset_sa
,
2222 uint32_t *y_offset_sa
)
2224 assert(level
< surf
->levels
);
2225 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2226 assert(logical_z_offset_px
2227 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2229 switch (surf
->dim_layout
) {
2230 case ISL_DIM_LAYOUT_GEN9_1D
:
2231 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2232 x_offset_sa
, y_offset_sa
);
2234 case ISL_DIM_LAYOUT_GEN4_2D
:
2235 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2236 + logical_z_offset_px
,
2237 x_offset_sa
, y_offset_sa
);
2239 case ISL_DIM_LAYOUT_GEN4_3D
:
2240 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2241 logical_z_offset_px
,
2242 x_offset_sa
, y_offset_sa
);
2244 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2245 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2246 logical_z_offset_px
,
2247 x_offset_sa
, y_offset_sa
);
2251 unreachable("not reached");
2256 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2258 uint32_t logical_array_layer
,
2259 uint32_t logical_z_offset_px
,
2260 uint32_t *x_offset_el
,
2261 uint32_t *y_offset_el
)
2263 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2265 assert(level
< surf
->levels
);
2266 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2267 assert(logical_z_offset_px
2268 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2270 uint32_t x_offset_sa
, y_offset_sa
;
2271 isl_surf_get_image_offset_sa(surf
, level
,
2272 logical_array_layer
,
2273 logical_z_offset_px
,
2277 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2278 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2282 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2284 uint32_t logical_array_layer
,
2285 uint32_t logical_z_offset_px
,
2287 uint32_t *x_offset_sa
,
2288 uint32_t *y_offset_sa
)
2290 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2292 uint32_t total_x_offset_el
, total_y_offset_el
;
2293 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2294 logical_z_offset_px
,
2296 &total_y_offset_el
);
2298 uint32_t x_offset_el
, y_offset_el
;
2299 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2308 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2310 assert(x_offset_el
== 0);
2314 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2316 assert(y_offset_el
== 0);
2321 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2324 uint32_t total_x_offset_el
,
2325 uint32_t total_y_offset_el
,
2326 uint32_t *base_address_offset
,
2327 uint32_t *x_offset_el
,
2328 uint32_t *y_offset_el
)
2330 if (tiling
== ISL_TILING_LINEAR
) {
2331 assert(bpb
% 8 == 0);
2332 *base_address_offset
= total_y_offset_el
* row_pitch
+
2333 total_x_offset_el
* (bpb
/ 8);
2339 struct isl_tile_info tile_info
;
2340 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2342 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
2344 /* For non-power-of-two formats, we need the address to be both tile and
2345 * element-aligned. The easiest way to achieve this is to work with a tile
2346 * that is three times as wide as the regular tile.
2348 * The tile info returned by get_tile_info has a logical size that is an
2349 * integer number of tile_info.format_bpb size elements. To scale the
2350 * tile, we scale up the physical width and then treat the logical tile
2351 * size as if it has bpb size elements.
2353 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2354 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2356 /* Compute the offset into the tile */
2357 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2358 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2360 /* Compute the offset of the tile in units of whole tiles */
2361 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2362 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2364 *base_address_offset
=
2365 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
2366 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2370 isl_surf_get_depth_format(const struct isl_device
*dev
,
2371 const struct isl_surf
*surf
)
2373 /* Support for separate stencil buffers began in gen5. Support for
2374 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2375 * those that supported separate and interleaved stencil, were gen5 and
2378 * For a list of all available formats, see the Sandybridge PRM >> Volume
2379 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2383 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2385 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2388 assert(ISL_DEV_GEN(dev
) < 7);
2390 switch (surf
->format
) {
2392 unreachable("bad isl depth format");
2393 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2394 assert(ISL_DEV_GEN(dev
) < 7);
2395 return 0; /* D32_FLOAT_S8X24_UINT */
2396 case ISL_FORMAT_R32_FLOAT
:
2397 assert(!has_stencil
);
2398 return 1; /* D32_FLOAT */
2399 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2401 assert(ISL_DEV_GEN(dev
) < 7);
2402 return 2; /* D24_UNORM_S8_UINT */
2404 assert(ISL_DEV_GEN(dev
) >= 5);
2405 return 3; /* D24_UNORM_X8_UINT */
2407 case ISL_FORMAT_R16_UNORM
:
2408 assert(!has_stencil
);
2409 return 5; /* D16_UNORM */