2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
52 isl_device_init(struct isl_device
*dev
,
53 const struct gen_device_info
*info
,
54 bool has_bit6_swizzling
)
57 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
58 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
60 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
61 * device properties at buildtime. Verify that the macros with the device
62 * properties chosen during runtime.
64 ISL_DEV_GEN_SANITIZE(dev
);
65 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
67 /* Did we break hiz or stencil? */
68 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
69 assert(info
->has_hiz_and_separate_stencil
);
70 if (info
->must_use_separate_stencil
)
71 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
74 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
76 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
78 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
80 /* The "Auxiliary Surface Base Address" field starts a bit higher up
81 * because the bottom 12 bits are used for other things. Round down to
82 * the nearest dword before.
84 dev
->ss
.aux_addr_offset
=
85 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
89 * @brief Query the set of multisamples supported by the device.
91 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
94 isl_sample_count_mask_t ATTRIBUTE_CONST
95 isl_device_get_sample_counts(struct isl_device
*dev
)
97 if (ISL_DEV_GEN(dev
) >= 9) {
98 return ISL_SAMPLE_COUNT_1_BIT
|
99 ISL_SAMPLE_COUNT_2_BIT
|
100 ISL_SAMPLE_COUNT_4_BIT
|
101 ISL_SAMPLE_COUNT_8_BIT
|
102 ISL_SAMPLE_COUNT_16_BIT
;
103 } else if (ISL_DEV_GEN(dev
) >= 8) {
104 return ISL_SAMPLE_COUNT_1_BIT
|
105 ISL_SAMPLE_COUNT_2_BIT
|
106 ISL_SAMPLE_COUNT_4_BIT
|
107 ISL_SAMPLE_COUNT_8_BIT
;
108 } else if (ISL_DEV_GEN(dev
) >= 7) {
109 return ISL_SAMPLE_COUNT_1_BIT
|
110 ISL_SAMPLE_COUNT_4_BIT
|
111 ISL_SAMPLE_COUNT_8_BIT
;
112 } else if (ISL_DEV_GEN(dev
) >= 6) {
113 return ISL_SAMPLE_COUNT_1_BIT
|
114 ISL_SAMPLE_COUNT_4_BIT
;
116 return ISL_SAMPLE_COUNT_1_BIT
;
121 * @param[out] info is written only on success
124 isl_tiling_get_info(const struct isl_device
*dev
,
125 enum isl_tiling tiling
,
127 struct isl_tile_info
*tile_info
)
129 const uint32_t bs
= format_bpb
/ 8;
130 struct isl_extent2d logical_el
, phys_B
;
132 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
133 /* It is possible to have non-power-of-two formats in a tiled buffer.
134 * The easiest way to handle this is to treat the tile as if it is three
135 * times as wide. This way no pixel will ever cross a tile boundary.
136 * This really only works on legacy X and Y tiling formats.
138 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
139 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
140 return isl_tiling_get_info(dev
, tiling
, format_bpb
/ 3, tile_info
);
144 case ISL_TILING_LINEAR
:
146 logical_el
= isl_extent2d(1, 1);
147 phys_B
= isl_extent2d(bs
, 1);
152 logical_el
= isl_extent2d(512 / bs
, 8);
153 phys_B
= isl_extent2d(512, 8);
158 logical_el
= isl_extent2d(128 / bs
, 32);
159 phys_B
= isl_extent2d(128, 32);
164 logical_el
= isl_extent2d(64, 64);
165 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
167 * "If the surface is a stencil buffer (and thus has Tile Mode set
168 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
169 * computed based on width, as the stencil buffer is stored with two
172 * This, together with the fact that stencil buffers are referred to as
173 * being Y-tiled in the PRMs for older hardware implies that the
174 * physical size of a W-tile is actually the same as for a Y-tile.
176 phys_B
= isl_extent2d(128, 32);
180 case ISL_TILING_Ys
: {
181 if (ISL_DEV_GEN(dev
) < 9)
184 if (!isl_is_pow2(bs
))
187 bool is_Ys
= tiling
== ISL_TILING_Ys
;
190 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
191 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
193 logical_el
= isl_extent2d(width
/ bs
, height
);
194 phys_B
= isl_extent2d(width
, height
);
199 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
200 * 128bpb format. The tiling has the same physical dimensions as
201 * Y-tiling but actually has two HiZ columns per Y-tiled column.
204 logical_el
= isl_extent2d(16, 16);
205 phys_B
= isl_extent2d(128, 32);
209 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
210 * have a block size of 1 or 2 bits per block and each CCS element
211 * corresponds to one cache-line pair in the main surface. From the Sky
212 * Lake PRM Vol. 12 in the section on planes:
214 * "The Color Control Surface (CCS) contains the compression status
215 * of the cache-line pairs. The compression state of the cache-line
216 * pair is specified by 2 bits in the CCS. Each CCS cache-line
217 * represents an area on the main surface of 16x16 sets of 128 byte
218 * Y-tiled cache-line-pairs. CCS is always Y tiled."
220 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
221 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
222 * that yields total tile area of 128x128 cache-line pairs or CCS
223 * elements. On older hardware, each CCS element is 1 bit and the tile
224 * is 128x256 elements.
226 assert(format_bpb
== 1 || format_bpb
== 2);
227 logical_el
= isl_extent2d(128, 256 / format_bpb
);
228 phys_B
= isl_extent2d(128, 32);
232 unreachable("not reached");
235 *tile_info
= (struct isl_tile_info
) {
237 .format_bpb
= format_bpb
,
238 .logical_extent_el
= logical_el
,
239 .phys_extent_B
= phys_B
,
246 * @param[out] tiling is set only on success
249 isl_surf_choose_tiling(const struct isl_device
*dev
,
250 const struct isl_surf_init_info
*restrict info
,
251 enum isl_tiling
*tiling
)
253 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
255 /* HiZ surfaces always use the HiZ tiling */
256 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
257 assert(info
->format
== ISL_FORMAT_HIZ
);
258 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
259 *tiling
= ISL_TILING_HIZ
;
263 /* CCS surfaces always use the CCS tiling */
264 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
265 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
266 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
267 *tiling
= ISL_TILING_CCS
;
271 if (ISL_DEV_GEN(dev
) >= 6) {
272 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
274 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
275 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
278 #define CHOOSE(__tiling) \
280 if (tiling_flags & (1u << (__tiling))) { \
281 *tiling = (__tiling); \
286 /* Of the tiling modes remaining, choose the one that offers the best
290 if (info
->dim
== ISL_SURF_DIM_1D
) {
291 /* Prefer linear for 1D surfaces because they do not benefit from
292 * tiling. To the contrary, tiling leads to wasted memory and poor
293 * memory locality due to the swizzling and alignment restrictions
294 * required in tiled surfaces.
296 CHOOSE(ISL_TILING_LINEAR
);
299 CHOOSE(ISL_TILING_Ys
);
300 CHOOSE(ISL_TILING_Yf
);
301 CHOOSE(ISL_TILING_Y0
);
302 CHOOSE(ISL_TILING_X
);
303 CHOOSE(ISL_TILING_W
);
304 CHOOSE(ISL_TILING_LINEAR
);
308 /* No tiling mode accomodates the inputs. */
313 isl_choose_msaa_layout(const struct isl_device
*dev
,
314 const struct isl_surf_init_info
*info
,
315 enum isl_tiling tiling
,
316 enum isl_msaa_layout
*msaa_layout
)
318 if (ISL_DEV_GEN(dev
) >= 8) {
319 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
320 } else if (ISL_DEV_GEN(dev
) >= 7) {
321 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
322 } else if (ISL_DEV_GEN(dev
) >= 6) {
323 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
325 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
330 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
332 assert(isl_is_pow2(samples
));
334 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
337 * If the surface is multisampled and it is a depth or stencil surface
338 * or Multisampled Surface StorageFormat in SURFACE_STATE is
339 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
342 return (struct isl_extent2d
) {
343 .width
= 1 << ((ffs(samples
) - 0) / 2),
344 .height
= 1 << ((ffs(samples
) - 1) / 2),
349 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
350 uint32_t *width
, uint32_t *height
)
352 const struct isl_extent2d px_size_sa
=
353 isl_get_interleaved_msaa_px_size_sa(samples
);
356 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
358 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
361 static enum isl_array_pitch_span
362 isl_choose_array_pitch_span(const struct isl_device
*dev
,
363 const struct isl_surf_init_info
*restrict info
,
364 enum isl_dim_layout dim_layout
,
365 const struct isl_extent4d
*phys_level0_sa
)
367 switch (dim_layout
) {
368 case ISL_DIM_LAYOUT_GEN9_1D
:
369 case ISL_DIM_LAYOUT_GEN4_2D
:
370 if (ISL_DEV_GEN(dev
) >= 8) {
371 /* QPitch becomes programmable in Broadwell. So choose the
372 * most compact QPitch possible in order to conserve memory.
374 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
375 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
377 * - Software must ensure that this field is set to a value
378 * sufficiently large such that the array slices in the surface
379 * do not overlap. Refer to the Memory Data Formats section for
380 * information on how surfaces are stored in memory.
382 * - This field specifies the distance in rows between array
383 * slices. It is used only in the following cases:
385 * - Surface Array is enabled OR
386 * - Number of Mulitsamples is not NUMSAMPLES_1 and
387 * Multisampled Surface Storage Format set to MSFMT_MSS OR
388 * - Surface Type is SURFTYPE_CUBE
390 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
391 } else if (ISL_DEV_GEN(dev
) >= 7) {
392 /* Note that Ivybridge introduces
393 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
394 * driver more control over the QPitch.
397 if (phys_level0_sa
->array_len
== 1) {
398 /* The hardware will never use the QPitch. So choose the most
399 * compact QPitch possible in order to conserve memory.
401 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
404 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
405 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
406 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
407 * Section 6.18.4.7: Surface Arrays (p112):
409 * If Surface Array Spacing is set to ARYSPC_FULL (note that
410 * the depth buffer and stencil buffer have an implied value of
413 return ISL_ARRAY_PITCH_SPAN_FULL
;
416 if (info
->levels
== 1) {
417 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
420 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
423 return ISL_ARRAY_PITCH_SPAN_FULL
;
424 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
425 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
426 isl_surf_usage_is_stencil(info
->usage
)) {
427 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
428 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
430 * The separate stencil buffer does not support mip mapping, thus
431 * the storage for LODs other than LOD 0 is not needed.
433 assert(info
->levels
== 1);
434 assert(phys_level0_sa
->array_len
== 1);
435 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
437 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
438 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
439 isl_surf_usage_is_stencil(info
->usage
)) {
440 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
441 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
443 * The separate stencil buffer does not support mip mapping,
444 * thus the storage for LODs other than LOD 0 is not needed.
446 assert(info
->levels
== 1);
447 assert(phys_level0_sa
->array_len
== 1);
448 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
451 if (phys_level0_sa
->array_len
== 1) {
452 /* The hardware will never use the QPitch. So choose the most
453 * compact QPitch possible in order to conserve memory.
455 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
458 return ISL_ARRAY_PITCH_SPAN_FULL
;
461 case ISL_DIM_LAYOUT_GEN4_3D
:
462 /* The hardware will never use the QPitch. So choose the most
463 * compact QPitch possible in order to conserve memory.
465 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
468 unreachable("bad isl_dim_layout");
469 return ISL_ARRAY_PITCH_SPAN_FULL
;
473 isl_choose_image_alignment_el(const struct isl_device
*dev
,
474 const struct isl_surf_init_info
*restrict info
,
475 enum isl_tiling tiling
,
476 enum isl_dim_layout dim_layout
,
477 enum isl_msaa_layout msaa_layout
,
478 struct isl_extent3d
*image_align_el
)
480 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
481 if (fmtl
->txc
== ISL_TXC_MCS
) {
482 assert(tiling
== ISL_TILING_Y0
);
485 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
487 * Height, width, and layout of MCS buffer in this case must match with
488 * Render Target height, width, and layout. MCS buffer is tiledY.
490 * To avoid wasting memory, choose the smallest alignment possible:
491 * HALIGN_4 and VALIGN_4.
493 *image_align_el
= isl_extent3d(4, 4, 1);
495 } else if (info
->format
== ISL_FORMAT_HIZ
) {
496 assert(ISL_DEV_GEN(dev
) >= 6);
497 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
498 * which works out to 2x2 HiZ elments.
500 *image_align_el
= isl_extent3d(2, 2, 1);
504 if (ISL_DEV_GEN(dev
) >= 9) {
505 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
506 msaa_layout
, image_align_el
);
507 } else if (ISL_DEV_GEN(dev
) >= 8) {
508 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
509 msaa_layout
, image_align_el
);
510 } else if (ISL_DEV_GEN(dev
) >= 7) {
511 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
512 msaa_layout
, image_align_el
);
513 } else if (ISL_DEV_GEN(dev
) >= 6) {
514 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
515 msaa_layout
, image_align_el
);
517 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
518 msaa_layout
, image_align_el
);
522 static enum isl_dim_layout
523 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
524 enum isl_surf_dim logical_dim
,
525 enum isl_tiling tiling
)
527 if (ISL_DEV_GEN(dev
) >= 9) {
528 switch (logical_dim
) {
529 case ISL_SURF_DIM_1D
:
530 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
532 * One-dimensional surfaces use a tiling mode of linear.
533 * Technically, they are not tiled resources, but the Tiled
534 * Resource Mode field in RENDER_SURFACE_STATE is still used to
535 * indicate the alignment requirements for this linear surface
536 * (See 1D Alignment requirements for how 4K and 64KB Tiled
537 * Resource Modes impact alignment). Alternatively, a 1D surface
538 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
541 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
542 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
544 if (tiling
== ISL_TILING_LINEAR
)
545 return ISL_DIM_LAYOUT_GEN9_1D
;
547 return ISL_DIM_LAYOUT_GEN4_2D
;
548 case ISL_SURF_DIM_2D
:
549 case ISL_SURF_DIM_3D
:
550 return ISL_DIM_LAYOUT_GEN4_2D
;
553 switch (logical_dim
) {
554 case ISL_SURF_DIM_1D
:
555 case ISL_SURF_DIM_2D
:
556 return ISL_DIM_LAYOUT_GEN4_2D
;
557 case ISL_SURF_DIM_3D
:
558 return ISL_DIM_LAYOUT_GEN4_3D
;
562 unreachable("bad isl_surf_dim");
563 return ISL_DIM_LAYOUT_GEN4_2D
;
567 * Calculate the physical extent of the surface's first level, in units of
568 * surface samples. The result is aligned to the format's compression block.
571 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
572 const struct isl_surf_init_info
*restrict info
,
573 enum isl_dim_layout dim_layout
,
574 enum isl_tiling tiling
,
575 enum isl_msaa_layout msaa_layout
,
576 struct isl_extent4d
*phys_level0_sa
)
578 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
580 if (isl_format_is_yuv(info
->format
))
581 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
584 case ISL_SURF_DIM_1D
:
585 assert(info
->height
== 1);
586 assert(info
->depth
== 1);
587 assert(info
->samples
== 1);
589 switch (dim_layout
) {
590 case ISL_DIM_LAYOUT_GEN4_3D
:
591 unreachable("bad isl_dim_layout");
593 case ISL_DIM_LAYOUT_GEN9_1D
:
594 case ISL_DIM_LAYOUT_GEN4_2D
:
595 *phys_level0_sa
= (struct isl_extent4d
) {
596 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
599 .a
= info
->array_len
,
605 case ISL_SURF_DIM_2D
:
606 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
608 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
609 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
611 switch (msaa_layout
) {
612 case ISL_MSAA_LAYOUT_NONE
:
613 assert(info
->depth
== 1);
614 assert(info
->samples
== 1);
616 *phys_level0_sa
= (struct isl_extent4d
) {
617 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
618 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
620 .a
= info
->array_len
,
624 case ISL_MSAA_LAYOUT_ARRAY
:
625 assert(info
->depth
== 1);
626 assert(info
->levels
== 1);
627 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
628 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
630 *phys_level0_sa
= (struct isl_extent4d
) {
634 .a
= info
->array_len
* info
->samples
,
638 case ISL_MSAA_LAYOUT_INTERLEAVED
:
639 assert(info
->depth
== 1);
640 assert(info
->levels
== 1);
641 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
643 *phys_level0_sa
= (struct isl_extent4d
) {
647 .a
= info
->array_len
,
650 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
654 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
655 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
660 case ISL_SURF_DIM_3D
:
661 assert(info
->array_len
== 1);
662 assert(info
->samples
== 1);
665 isl_finishme("%s:%s: compression block with depth > 1",
669 switch (dim_layout
) {
670 case ISL_DIM_LAYOUT_GEN9_1D
:
671 unreachable("bad isl_dim_layout");
673 case ISL_DIM_LAYOUT_GEN4_2D
:
674 assert(ISL_DEV_GEN(dev
) >= 9);
676 *phys_level0_sa
= (struct isl_extent4d
) {
677 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
678 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
684 case ISL_DIM_LAYOUT_GEN4_3D
:
685 assert(ISL_DEV_GEN(dev
) < 9);
686 *phys_level0_sa
= (struct isl_extent4d
) {
687 .w
= isl_align(info
->width
, fmtl
->bw
),
688 .h
= isl_align(info
->height
, fmtl
->bh
),
699 * A variant of isl_calc_phys_slice0_extent_sa() specific to
700 * ISL_DIM_LAYOUT_GEN4_2D.
703 isl_calc_phys_slice0_extent_sa_gen4_2d(
704 const struct isl_device
*dev
,
705 const struct isl_surf_init_info
*restrict info
,
706 enum isl_msaa_layout msaa_layout
,
707 const struct isl_extent3d
*image_align_sa
,
708 const struct isl_extent4d
*phys_level0_sa
,
709 struct isl_extent2d
*phys_slice0_sa
)
711 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
713 assert(phys_level0_sa
->depth
== 1);
715 if (info
->levels
== 1) {
716 /* Do not pad the surface to the image alignment. Instead, pad it only
717 * to the pixel format's block alignment.
719 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
720 * cycles on the below mipmap layout caluclations. Reducing the
721 * alignment here is safe because we later align the row pitch and array
722 * pitch to the tile boundary. It is safe even for
723 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
724 * to accomodate the interleaved samples.
726 * For linear surfaces, reducing the alignment here permits us to later
727 * choose an arbitrary, non-aligned row pitch. If the surface backs
728 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
729 * VkBufferImageCopy::bufferRowLength.
731 *phys_slice0_sa
= (struct isl_extent2d
) {
732 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
733 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
738 uint32_t slice_top_w
= 0;
739 uint32_t slice_bottom_w
= 0;
740 uint32_t slice_left_h
= 0;
741 uint32_t slice_right_h
= 0;
743 uint32_t W0
= phys_level0_sa
->w
;
744 uint32_t H0
= phys_level0_sa
->h
;
746 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
747 uint32_t W
= isl_minify(W0
, l
);
748 uint32_t H
= isl_minify(H0
, l
);
750 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
751 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
768 *phys_slice0_sa
= (struct isl_extent2d
) {
769 .w
= MAX(slice_top_w
, slice_bottom_w
),
770 .h
= MAX(slice_left_h
, slice_right_h
),
775 * A variant of isl_calc_phys_slice0_extent_sa() specific to
776 * ISL_DIM_LAYOUT_GEN4_3D.
779 isl_calc_phys_slice0_extent_sa_gen4_3d(
780 const struct isl_device
*dev
,
781 const struct isl_surf_init_info
*restrict info
,
782 const struct isl_extent3d
*image_align_sa
,
783 const struct isl_extent4d
*phys_level0_sa
,
784 struct isl_extent2d
*phys_slice0_sa
)
786 assert(info
->samples
== 1);
787 assert(phys_level0_sa
->array_len
== 1);
789 uint32_t slice_w
= 0;
790 uint32_t slice_h
= 0;
792 uint32_t W0
= phys_level0_sa
->w
;
793 uint32_t H0
= phys_level0_sa
->h
;
794 uint32_t D0
= phys_level0_sa
->d
;
796 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
797 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
798 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
799 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
801 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
802 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
804 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
805 slice_h
+= level_h
* max_layers_vert
;
808 *phys_slice0_sa
= (struct isl_extent2d
) {
815 * A variant of isl_calc_phys_slice0_extent_sa() specific to
816 * ISL_DIM_LAYOUT_GEN9_1D.
819 isl_calc_phys_slice0_extent_sa_gen9_1d(
820 const struct isl_device
*dev
,
821 const struct isl_surf_init_info
*restrict info
,
822 const struct isl_extent3d
*image_align_sa
,
823 const struct isl_extent4d
*phys_level0_sa
,
824 struct isl_extent2d
*phys_slice0_sa
)
826 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
828 assert(phys_level0_sa
->height
== 1);
829 assert(phys_level0_sa
->depth
== 1);
830 assert(info
->samples
== 1);
831 assert(image_align_sa
->w
>= fmtl
->bw
);
833 uint32_t slice_w
= 0;
834 const uint32_t W0
= phys_level0_sa
->w
;
836 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
837 uint32_t W
= isl_minify(W0
, l
);
838 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
843 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
847 * Calculate the physical extent of the surface's first array slice, in units
848 * of surface samples. If the surface is multi-leveled, then the result will
849 * be aligned to \a image_align_sa.
852 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
853 const struct isl_surf_init_info
*restrict info
,
854 enum isl_dim_layout dim_layout
,
855 enum isl_msaa_layout msaa_layout
,
856 const struct isl_extent3d
*image_align_sa
,
857 const struct isl_extent4d
*phys_level0_sa
,
858 struct isl_extent2d
*phys_slice0_sa
)
860 switch (dim_layout
) {
861 case ISL_DIM_LAYOUT_GEN9_1D
:
862 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
863 image_align_sa
, phys_level0_sa
,
866 case ISL_DIM_LAYOUT_GEN4_2D
:
867 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
868 image_align_sa
, phys_level0_sa
,
871 case ISL_DIM_LAYOUT_GEN4_3D
:
872 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
873 phys_level0_sa
, phys_slice0_sa
);
879 * Calculate the pitch between physical array slices, in units of rows of
883 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
884 const struct isl_surf_init_info
*restrict info
,
885 const struct isl_tile_info
*tile_info
,
886 enum isl_dim_layout dim_layout
,
887 enum isl_array_pitch_span array_pitch_span
,
888 const struct isl_extent3d
*image_align_sa
,
889 const struct isl_extent4d
*phys_level0_sa
,
890 const struct isl_extent2d
*phys_slice0_sa
)
892 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
893 uint32_t pitch_sa_rows
= 0;
895 switch (dim_layout
) {
896 case ISL_DIM_LAYOUT_GEN9_1D
:
897 /* Each row is an array slice */
900 case ISL_DIM_LAYOUT_GEN4_2D
:
901 switch (array_pitch_span
) {
902 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
903 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
905 case ISL_ARRAY_PITCH_SPAN_FULL
: {
906 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
907 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
908 * Surfaces >> Surface Arrays.
910 uint32_t H0_sa
= phys_level0_sa
->h
;
911 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
913 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
914 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
917 if (ISL_DEV_GEN(dev
) >= 7) {
918 /* The QPitch equation changed slightly in Ivybridge. */
924 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
926 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
927 (info
->height
% 4 == 1)) {
928 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
929 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
931 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
932 * the value calculated in the equation above , for every
933 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
935 * XXX(chadv): Is the errata natural corollary of the physical
936 * layout of interleaved samples?
941 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
946 case ISL_DIM_LAYOUT_GEN4_3D
:
947 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
948 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
951 unreachable("bad isl_dim_layout");
955 assert(pitch_sa_rows
% fmtl
->bh
== 0);
956 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
958 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
960 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
962 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
963 * layout with these alignments in the RT space: Horizontal
964 * Alignment = 128 and Vertical Alignment = 64."
966 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
968 * "For non-multisampled render target's CCS auxiliary surface,
969 * QPitch must be computed with Horizontal Alignment = 128 and
970 * Surface Vertical Alignment = 256. These alignments are only for
971 * CCS buffer and not for associated render target."
973 * The first restriction is already handled by isl_choose_image_alignment_el
974 * but the second restriction, which is an extension of the first, only
975 * applies to qpitch and must be applied here.
977 assert(fmtl
->bh
== 4);
978 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
981 if (ISL_DEV_GEN(dev
) >= 9 &&
982 info
->dim
== ISL_SURF_DIM_3D
&&
983 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
984 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
986 * Tile Mode != Linear: This field must be set to an integer multiple
989 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
992 return pitch_el_rows
;
996 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
997 const struct isl_tile_info
*tile_info
)
999 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1000 return tile_info
->phys_extent_B
.width
;
1002 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1003 * RENDER_SURFACE_STATE Surface Pitch (p349):
1005 * - For linear render target surfaces and surfaces accessed with the
1006 * typed data port messages, the pitch must be a multiple of the
1007 * element size for non-YUV surface formats. Pitch must be
1008 * a multiple of 2 * element size for YUV surface formats.
1010 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1011 * ignore because isl doesn't do buffers.]
1013 * - For other linear surfaces, the pitch can be any multiple of
1016 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1017 const uint32_t bs
= fmtl
->bpb
/ 8;
1019 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1020 if (isl_format_is_yuv(surf_info
->format
)) {
1031 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1032 const struct isl_surf_init_info
*info
,
1033 const struct isl_extent2d
*phys_slice0_sa
,
1036 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1037 const uint32_t bs
= fmtl
->bpb
/ 8;
1039 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1041 return isl_align_npot(bs
* (phys_slice0_sa
->w
/ fmtl
->bw
), alignment
);
1045 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1046 const struct isl_surf_init_info
*surf_info
,
1047 const struct isl_tile_info
*tile_info
,
1048 const struct isl_extent2d
*phys_slice0_sa
,
1051 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1053 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1054 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1056 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1057 const uint32_t total_w_el
= phys_slice0_sa
->width
/ fmtl
->bw
;
1058 const uint32_t total_w_tl
=
1059 isl_align_div(total_w_el
* tile_el_scale
,
1060 tile_info
->logical_extent_el
.width
);
1062 assert(alignment
== tile_info
->phys_extent_B
.width
);
1063 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1067 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1068 const struct isl_surf_init_info
*surf_info
,
1069 const struct isl_tile_info
*tile_info
,
1070 const struct isl_extent2d
*phys_slice0_sa
,
1073 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1074 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_slice0_sa
,
1077 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1078 phys_slice0_sa
, alignment
);
1083 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1084 * size is `bits` bits?
1086 * Hardware pitch fields are offset by 1. For example, if the size of
1087 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1088 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1089 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1092 pitch_in_range(uint32_t n
, uint32_t bits
)
1095 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1099 isl_calc_row_pitch(const struct isl_device
*dev
,
1100 const struct isl_surf_init_info
*surf_info
,
1101 const struct isl_tile_info
*tile_info
,
1102 enum isl_dim_layout dim_layout
,
1103 const struct isl_extent2d
*phys_slice0_sa
,
1104 uint32_t *out_row_pitch
)
1106 const uint32_t alignment
=
1107 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1109 const uint32_t min_row_pitch
=
1110 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_slice0_sa
,
1113 uint32_t row_pitch
= min_row_pitch
;
1115 if (surf_info
->row_pitch
!= 0) {
1116 row_pitch
= surf_info
->row_pitch
;
1118 if (row_pitch
< min_row_pitch
)
1121 if (row_pitch
% alignment
!= 0)
1125 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1130 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1131 /* SurfacePitch is ignored for this layout. */
1135 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1136 ISL_SURF_USAGE_TEXTURE_BIT
|
1137 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1138 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1141 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1142 ISL_SURF_USAGE_MCS_BIT
)) &&
1143 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1146 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1147 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1150 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1151 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1154 if (surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
1155 isl_finishme("validate row pitch of stencil surfaces");
1158 *out_row_pitch
= row_pitch
;
1163 * Calculate and apply any padding required for the surface.
1165 * @param[inout] total_h_el is updated with the new height
1166 * @param[out] pad_bytes is overwritten with additional padding requirements.
1169 isl_apply_surface_padding(const struct isl_device
*dev
,
1170 const struct isl_surf_init_info
*restrict info
,
1171 const struct isl_tile_info
*tile_info
,
1172 uint32_t *total_h_el
,
1173 uint32_t *pad_bytes
)
1175 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1179 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1180 * Formats >> Surface Padding Requirements >> Render Target and Media
1183 * The data port accesses data (pixels) outside of the surface if they
1184 * are contained in the same cache request as pixels that are within the
1185 * surface. These pixels will not be returned by the requesting message,
1186 * however if these pixels lie outside of defined pages in the GTT,
1187 * a GTT error will result when the cache request is processed. In
1188 * order to avoid these GTT errors, “padding” at the bottom of the
1189 * surface is sometimes necessary.
1191 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1192 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1194 * ... Lots of padding requirements, all listed separately below.
1197 /* We can safely ignore the first padding requirement, quoted below,
1198 * because isl doesn't do buffers.
1200 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1201 * requirements are different. A buffer must be padded to the next
1202 * multiple of 256 array elements, with an additional 16 bytes added
1203 * beyond that to account for the L1 cache line.
1207 * - For compressed textures [...], padding at the bottom of the surface
1208 * is to an even compressed row.
1210 if (isl_format_is_compressed(info
->format
))
1211 *total_h_el
= isl_align(*total_h_el
, 2);
1214 * - For cube surfaces, an additional two rows of padding are required
1215 * at the bottom of the surface.
1217 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1221 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1222 * additional padding is required. These surfaces require an extra row
1223 * plus 16 bytes of padding at the bottom in addition to the general
1224 * padding requirements.
1226 if (isl_format_is_yuv(info
->format
) &&
1227 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1233 * - For linear surfaces, additional padding of 64 bytes is required at
1234 * the bottom of the surface. This is in addition to the padding
1237 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1240 /* The below text weakens, not strengthens, the padding requirements for
1241 * linear surfaces. Therefore we can safely ignore it.
1243 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1244 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1245 * padding requirement is to the next aligned 64-byte boundary beyond
1246 * the end of the surface. The rest of the padding requirements
1247 * documented above do not apply to these surfaces.
1251 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1252 * height % 4 != 0, the surface must be padded with
1253 * 4-(height % 4)*Surface Pitch # of bytes.
1255 if (ISL_DEV_GEN(dev
) >= 9 &&
1256 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1257 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1258 *total_h_el
= isl_align(*total_h_el
, 4);
1262 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1263 * to 4 times the Surface Pitch # of bytes
1265 if (ISL_DEV_GEN(dev
) >= 9 &&
1266 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1267 info
->dim
== ISL_SURF_DIM_1D
) {
1273 isl_surf_init_s(const struct isl_device
*dev
,
1274 struct isl_surf
*surf
,
1275 const struct isl_surf_init_info
*restrict info
)
1277 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1279 const struct isl_extent4d logical_level0_px
= {
1283 .a
= info
->array_len
,
1286 enum isl_tiling tiling
;
1287 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1290 struct isl_tile_info tile_info
;
1291 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1294 const enum isl_dim_layout dim_layout
=
1295 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1297 enum isl_msaa_layout msaa_layout
;
1298 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1301 struct isl_extent3d image_align_el
;
1302 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1305 struct isl_extent3d image_align_sa
=
1306 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1308 struct isl_extent4d phys_level0_sa
;
1309 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1311 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1312 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1314 enum isl_array_pitch_span array_pitch_span
=
1315 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1317 struct isl_extent2d phys_slice0_sa
;
1318 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1319 &image_align_sa
, &phys_level0_sa
,
1321 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1322 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1324 const uint32_t array_pitch_el_rows
=
1325 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1326 array_pitch_span
, &image_align_sa
,
1327 &phys_level0_sa
, &phys_slice0_sa
);
1329 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1332 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1335 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1336 &phys_slice0_sa
, &row_pitch
))
1339 uint32_t size
, base_alignment
;
1340 if (tiling
== ISL_TILING_LINEAR
) {
1341 size
= row_pitch
* total_h_el
+ pad_bytes
;
1343 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1345 * "The Base Address for linear render target surfaces and surfaces
1346 * accessed with the typed surface read/write data port messages must
1347 * be element-size aligned, for non-YUV surface formats, or a
1348 * multiple of 2 element-sizes for YUV surface formats. Other linear
1349 * surfaces have no alignment requirements (byte alignment is
1352 base_alignment
= MAX(1, info
->min_alignment
);
1353 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1354 if (isl_format_is_yuv(info
->format
)) {
1355 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1357 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1360 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1362 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1363 const uint32_t total_h_tl
=
1364 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1366 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1368 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1369 tile_info
.phys_extent_B
.height
;
1370 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1371 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1374 *surf
= (struct isl_surf
) {
1376 .dim_layout
= dim_layout
,
1377 .msaa_layout
= msaa_layout
,
1379 .format
= info
->format
,
1381 .levels
= info
->levels
,
1382 .samples
= info
->samples
,
1384 .image_alignment_el
= image_align_el
,
1385 .logical_level0_px
= logical_level0_px
,
1386 .phys_level0_sa
= phys_level0_sa
,
1389 .alignment
= base_alignment
,
1390 .row_pitch
= row_pitch
,
1391 .array_pitch_el_rows
= array_pitch_el_rows
,
1392 .array_pitch_span
= array_pitch_span
,
1394 .usage
= info
->usage
,
1401 isl_surf_get_tile_info(const struct isl_device
*dev
,
1402 const struct isl_surf
*surf
,
1403 struct isl_tile_info
*tile_info
)
1405 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1406 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1410 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1411 const struct isl_surf
*surf
,
1412 struct isl_surf
*hiz_surf
)
1414 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1416 /* Multisampled depth is always interleaved */
1417 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1418 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1420 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1422 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1423 * Target View Extent, and Depth Coordinate Offset X/Y of the
1424 * hierarchical depth buffer are inherited from the depth buffer. The
1425 * height and width of the hierarchical depth buffer that must be
1426 * allocated are computed by the following formulas, where HZ is the
1427 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1428 * Z_Width, and Z_Depth values given in these formulas are those present
1429 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1431 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1432 * being applied to the table below if Number of Multisamples is set to
1433 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1434 * Z_Width must be multiplied by 4 before being applied to the table
1435 * below if Number of Multisamples is set to NUMSAMPLES_8."
1437 * In the Sky Lake PRM, the second paragraph is replaced with this:
1439 * "The Z_Height and Z_Width values must equal those present in
1440 * 3DSTATE_DEPTH_BUFFER incremented by one."
1442 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1443 * block corresponds to a region of 8x4 samples in the primary depth
1444 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1445 * a region of 8x4 pixels in the primary depth surface regardless of the
1446 * number of samples. The dimensions of a HiZ block in both pixels and
1447 * samples are given in the table below:
1449 * | SNB - BDW | SKL+
1450 * ------+-----------+-------------
1451 * 1x | 8 x 4 sa | 8 x 4 sa
1452 * MSAA | 8 x 4 px | 8 x 4 px
1453 * ------+-----------+-------------
1454 * 2x | 8 x 4 sa | 16 x 4 sa
1455 * MSAA | 4 x 4 px | 8 x 4 px
1456 * ------+-----------+-------------
1457 * 4x | 8 x 4 sa | 16 x 8 sa
1458 * MSAA | 4 x 2 px | 8 x 4 px
1459 * ------+-----------+-------------
1460 * 8x | 8 x 4 sa | 32 x 8 sa
1461 * MSAA | 2 x 2 px | 8 x 4 px
1462 * ------+-----------+-------------
1463 * 16x | N/A | 32 x 16 sa
1464 * MSAA | N/A | 8 x 4 px
1465 * ------+-----------+-------------
1467 * There are a number of different ways that this discrepency could be
1468 * handled. The way we have chosen is to simply make MSAA HiZ have the
1469 * same number of samples as the parent surface pre-Sky Lake and always be
1470 * single-sampled on Sky Lake and above. Since the block sizes of
1471 * compressed formats are given in samples, this neatly handles everything
1472 * without the need for additional HiZ formats with different block sizes
1475 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1477 return isl_surf_init(dev
, hiz_surf
,
1479 .format
= ISL_FORMAT_HIZ
,
1480 .width
= surf
->logical_level0_px
.width
,
1481 .height
= surf
->logical_level0_px
.height
,
1482 .depth
= surf
->logical_level0_px
.depth
,
1483 .levels
= surf
->levels
,
1484 .array_len
= surf
->logical_level0_px
.array_len
,
1486 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1487 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1491 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1492 const struct isl_surf
*surf
,
1493 struct isl_surf
*mcs_surf
)
1495 /* It must be multisampled with an array layout */
1496 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1498 /* The following are true of all multisampled surfaces */
1499 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1500 assert(surf
->levels
== 1);
1501 assert(surf
->logical_level0_px
.depth
== 1);
1503 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1504 * bits which means the maximum pitch of a compression surface is 512
1505 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1506 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1507 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1508 * and 8x, we have enough room for the full 16k supported by the hardware.
1510 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1513 enum isl_format mcs_format
;
1514 switch (surf
->samples
) {
1515 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1516 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1517 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1518 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1520 unreachable("Invalid sample count");
1523 return isl_surf_init(dev
, mcs_surf
,
1524 .dim
= ISL_SURF_DIM_2D
,
1525 .format
= mcs_format
,
1526 .width
= surf
->logical_level0_px
.width
,
1527 .height
= surf
->logical_level0_px
.height
,
1530 .array_len
= surf
->logical_level0_px
.array_len
,
1531 .samples
= 1, /* MCS surfaces are really single-sampled */
1532 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1533 .tiling_flags
= ISL_TILING_Y0_BIT
);
1537 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1538 const struct isl_surf
*surf
,
1539 struct isl_surf
*ccs_surf
)
1541 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1542 assert(ISL_DEV_GEN(dev
) >= 7);
1544 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1547 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1550 if (isl_format_is_compressed(surf
->format
))
1553 /* TODO: More conditions where it can fail. */
1555 enum isl_format ccs_format
;
1556 if (ISL_DEV_GEN(dev
) >= 9) {
1557 if (!isl_tiling_is_any_y(surf
->tiling
))
1560 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1561 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1562 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1563 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1567 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1568 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1569 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1570 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1571 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1575 } else if (surf
->tiling
== ISL_TILING_X
) {
1576 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1577 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1578 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1579 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1587 return isl_surf_init(dev
, ccs_surf
,
1589 .format
= ccs_format
,
1590 .width
= surf
->logical_level0_px
.width
,
1591 .height
= surf
->logical_level0_px
.height
,
1592 .depth
= surf
->logical_level0_px
.depth
,
1593 .levels
= surf
->levels
,
1594 .array_len
= surf
->logical_level0_px
.array_len
,
1596 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1597 .tiling_flags
= ISL_TILING_CCS_BIT
);
1601 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1602 const struct isl_surf_fill_state_info
*restrict info
)
1605 isl_surf_usage_flags_t _base_usage
=
1606 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1607 ISL_SURF_USAGE_TEXTURE_BIT
|
1608 ISL_SURF_USAGE_STORAGE_BIT
);
1609 /* They may only specify one of the above bits at a time */
1610 assert(__builtin_popcount(_base_usage
) == 1);
1611 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1612 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1615 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1616 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1617 info
->surf
->logical_level0_px
.depth
);
1619 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1620 info
->surf
->logical_level0_px
.array_len
);
1623 switch (ISL_DEV_GEN(dev
)) {
1625 if (ISL_DEV_IS_G4X(dev
)) {
1626 /* G45 surface state is the same as gen5 */
1627 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1629 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1633 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1636 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1639 if (ISL_DEV_IS_HASWELL(dev
)) {
1640 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1642 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1646 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1649 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1652 assert(!"Cannot fill surface state for this gen");
1657 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1658 const struct isl_buffer_fill_state_info
*restrict info
)
1660 switch (ISL_DEV_GEN(dev
)) {
1663 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1664 isl_gen5_buffer_fill_state_s(state
, info
);
1667 isl_gen6_buffer_fill_state_s(state
, info
);
1670 if (ISL_DEV_IS_HASWELL(dev
)) {
1671 isl_gen75_buffer_fill_state_s(state
, info
);
1673 isl_gen7_buffer_fill_state_s(state
, info
);
1677 isl_gen8_buffer_fill_state_s(state
, info
);
1680 isl_gen9_buffer_fill_state_s(state
, info
);
1683 assert(!"Cannot fill surface state for this gen");
1688 * A variant of isl_surf_get_image_offset_sa() specific to
1689 * ISL_DIM_LAYOUT_GEN4_2D.
1692 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1693 uint32_t level
, uint32_t logical_array_layer
,
1694 uint32_t *x_offset_sa
,
1695 uint32_t *y_offset_sa
)
1697 assert(level
< surf
->levels
);
1698 if (surf
->dim
== ISL_SURF_DIM_3D
)
1699 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1701 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1703 const struct isl_extent3d image_align_sa
=
1704 isl_surf_get_image_alignment_sa(surf
);
1706 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1707 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1709 const uint32_t phys_layer
= logical_array_layer
*
1710 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1713 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1715 for (uint32_t l
= 0; l
< level
; ++l
) {
1717 uint32_t W
= isl_minify(W0
, l
);
1718 x
+= isl_align_npot(W
, image_align_sa
.w
);
1720 uint32_t H
= isl_minify(H0
, l
);
1721 y
+= isl_align_npot(H
, image_align_sa
.h
);
1730 * A variant of isl_surf_get_image_offset_sa() specific to
1731 * ISL_DIM_LAYOUT_GEN4_3D.
1734 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1735 uint32_t level
, uint32_t logical_z_offset_px
,
1736 uint32_t *x_offset_sa
,
1737 uint32_t *y_offset_sa
)
1739 assert(level
< surf
->levels
);
1740 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1741 assert(surf
->phys_level0_sa
.array_len
== 1);
1743 const struct isl_extent3d image_align_sa
=
1744 isl_surf_get_image_alignment_sa(surf
);
1746 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1747 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1748 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1753 for (uint32_t l
= 0; l
< level
; ++l
) {
1754 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1755 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1756 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1758 y
+= level_h
* max_layers_vert
;
1761 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1762 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1763 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1765 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1767 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1768 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1775 * A variant of isl_surf_get_image_offset_sa() specific to
1776 * ISL_DIM_LAYOUT_GEN9_1D.
1779 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1780 uint32_t level
, uint32_t layer
,
1781 uint32_t *x_offset_sa
,
1782 uint32_t *y_offset_sa
)
1784 assert(level
< surf
->levels
);
1785 assert(layer
< surf
->phys_level0_sa
.array_len
);
1786 assert(surf
->phys_level0_sa
.height
== 1);
1787 assert(surf
->phys_level0_sa
.depth
== 1);
1788 assert(surf
->samples
== 1);
1790 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1791 const struct isl_extent3d image_align_sa
=
1792 isl_surf_get_image_alignment_sa(surf
);
1796 for (uint32_t l
= 0; l
< level
; ++l
) {
1797 uint32_t W
= isl_minify(W0
, l
);
1798 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1804 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1808 * Calculate the offset, in units of surface samples, to a subimage in the
1811 * @invariant level < surface levels
1812 * @invariant logical_array_layer < logical array length of surface
1813 * @invariant logical_z_offset_px < logical depth of surface at level
1816 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1818 uint32_t logical_array_layer
,
1819 uint32_t logical_z_offset_px
,
1820 uint32_t *x_offset_sa
,
1821 uint32_t *y_offset_sa
)
1823 assert(level
< surf
->levels
);
1824 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1825 assert(logical_z_offset_px
1826 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1828 switch (surf
->dim_layout
) {
1829 case ISL_DIM_LAYOUT_GEN9_1D
:
1830 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1831 x_offset_sa
, y_offset_sa
);
1833 case ISL_DIM_LAYOUT_GEN4_2D
:
1834 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1835 + logical_z_offset_px
,
1836 x_offset_sa
, y_offset_sa
);
1838 case ISL_DIM_LAYOUT_GEN4_3D
:
1839 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1840 x_offset_sa
, y_offset_sa
);
1844 unreachable("not reached");
1849 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1851 uint32_t logical_array_layer
,
1852 uint32_t logical_z_offset_px
,
1853 uint32_t *x_offset_el
,
1854 uint32_t *y_offset_el
)
1856 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1858 assert(level
< surf
->levels
);
1859 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1860 assert(logical_z_offset_px
1861 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1863 uint32_t x_offset_sa
, y_offset_sa
;
1864 isl_surf_get_image_offset_sa(surf
, level
,
1865 logical_array_layer
,
1866 logical_z_offset_px
,
1870 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1871 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1875 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1876 enum isl_tiling tiling
,
1879 uint32_t total_x_offset_el
,
1880 uint32_t total_y_offset_el
,
1881 uint32_t *base_address_offset
,
1882 uint32_t *x_offset_el
,
1883 uint32_t *y_offset_el
)
1885 if (tiling
== ISL_TILING_LINEAR
) {
1886 *base_address_offset
= total_y_offset_el
* row_pitch
+
1887 total_x_offset_el
* bs
;
1893 const uint32_t bpb
= bs
* 8;
1895 struct isl_tile_info tile_info
;
1896 isl_tiling_get_info(dev
, tiling
, bpb
, &tile_info
);
1898 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1900 /* For non-power-of-two formats, we need the address to be both tile and
1901 * element-aligned. The easiest way to achieve this is to work with a tile
1902 * that is three times as wide as the regular tile.
1904 * The tile info returned by get_tile_info has a logical size that is an
1905 * integer number of tile_info.format_bpb size elements. To scale the
1906 * tile, we scale up the physical width and then treat the logical tile
1907 * size as if it has bpb size elements.
1909 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
1910 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
1912 /* Compute the offset into the tile */
1913 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1914 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1916 /* Compute the offset of the tile in units of whole tiles */
1917 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1918 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1920 *base_address_offset
=
1921 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1922 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1926 isl_surf_get_depth_format(const struct isl_device
*dev
,
1927 const struct isl_surf
*surf
)
1929 /* Support for separate stencil buffers began in gen5. Support for
1930 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1931 * those that supported separate and interleaved stencil, were gen5 and
1934 * For a list of all available formats, see the Sandybridge PRM >> Volume
1935 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1939 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1941 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1944 assert(ISL_DEV_GEN(dev
) < 7);
1946 switch (surf
->format
) {
1948 unreachable("bad isl depth format");
1949 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1950 assert(ISL_DEV_GEN(dev
) < 7);
1951 return 0; /* D32_FLOAT_S8X24_UINT */
1952 case ISL_FORMAT_R32_FLOAT
:
1953 assert(!has_stencil
);
1954 return 1; /* D32_FLOAT */
1955 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1957 assert(ISL_DEV_GEN(dev
) < 7);
1958 return 2; /* D24_UNORM_S8_UINT */
1960 assert(ISL_DEV_GEN(dev
) >= 5);
1961 return 3; /* D24_UNORM_X8_UINT */
1963 case ISL_FORMAT_R16_UNORM
:
1964 assert(!has_stencil
);
1965 return 5; /* D16_UNORM */