2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct brw_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_bpb
/ 8;
114 struct isl_extent2d logical_el
, phys_B
;
117 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
120 case ISL_TILING_LINEAR
:
121 logical_el
= isl_extent2d(1, 1);
122 phys_B
= isl_extent2d(bs
, 1);
126 logical_el
= isl_extent2d(512 / bs
, 8);
127 phys_B
= isl_extent2d(512, 8);
131 logical_el
= isl_extent2d(128 / bs
, 32);
132 phys_B
= isl_extent2d(128, 32);
137 logical_el
= isl_extent2d(64, 64);
138 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
140 * "If the surface is a stencil buffer (and thus has Tile Mode set
141 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
142 * computed based on width, as the stencil buffer is stored with two
145 * This, together with the fact that stencil buffers are referred to as
146 * being Y-tiled in the PRMs for older hardware implies that the
147 * physical size of a W-tile is actually the same as for a Y-tile.
149 phys_B
= isl_extent2d(128, 32);
153 case ISL_TILING_Ys
: {
154 if (ISL_DEV_GEN(dev
) < 9)
157 if (!isl_is_pow2(bs
))
160 bool is_Ys
= tiling
== ISL_TILING_Ys
;
162 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
163 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
165 logical_el
= isl_extent2d(width
/ bs
, height
);
166 phys_B
= isl_extent2d(width
, height
);
171 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
172 * 128bpb format. The tiling has the same physical dimensions as
173 * Y-tiling but actually has two HiZ columns per Y-tiled column.
176 logical_el
= isl_extent2d(16, 16);
177 phys_B
= isl_extent2d(128, 32);
181 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
182 * have a block size of 1 or 2 bits per block and each CCS element
183 * corresponds to one cache-line pair in the main surface. From the Sky
184 * Lake PRM Vol. 12 in the section on planes:
186 * "The Color Control Surface (CCS) contains the compression status
187 * of the cache-line pairs. The compression state of the cache-line
188 * pair is specified by 2 bits in the CCS. Each CCS cache-line
189 * represents an area on the main surface of 16x16 sets of 128 byte
190 * Y-tiled cache-line-pairs. CCS is always Y tiled."
192 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
193 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
194 * that yields total tile area of 128x128 cache-line pairs or CCS
195 * elements. On older hardware, each CCS element is 1 bit and the tile
196 * is 128x256 elements.
198 assert(format_bpb
== 1 || format_bpb
== 2);
199 logical_el
= isl_extent2d(128, 256 / format_bpb
);
200 phys_B
= isl_extent2d(128, 32);
204 unreachable("not reached");
207 *tile_info
= (struct isl_tile_info
) {
209 .logical_extent_el
= logical_el
,
210 .phys_extent_B
= phys_B
,
217 * @param[out] tiling is set only on success
220 isl_surf_choose_tiling(const struct isl_device
*dev
,
221 const struct isl_surf_init_info
*restrict info
,
222 enum isl_tiling
*tiling
)
224 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
226 if (ISL_DEV_GEN(dev
) >= 7) {
227 gen7_filter_tiling(dev
, info
, &tiling_flags
);
229 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
230 gen7_filter_tiling(dev
, info
, &tiling_flags
);
233 #define CHOOSE(__tiling) \
235 if (tiling_flags & (1u << (__tiling))) { \
236 *tiling = (__tiling); \
241 /* Of the tiling modes remaining, choose the one that offers the best
245 if (info
->dim
== ISL_SURF_DIM_1D
) {
246 /* Prefer linear for 1D surfaces because they do not benefit from
247 * tiling. To the contrary, tiling leads to wasted memory and poor
248 * memory locality due to the swizzling and alignment restrictions
249 * required in tiled surfaces.
251 CHOOSE(ISL_TILING_LINEAR
);
254 CHOOSE(ISL_TILING_CCS
);
255 CHOOSE(ISL_TILING_HIZ
);
256 CHOOSE(ISL_TILING_Ys
);
257 CHOOSE(ISL_TILING_Yf
);
258 CHOOSE(ISL_TILING_Y0
);
259 CHOOSE(ISL_TILING_X
);
260 CHOOSE(ISL_TILING_W
);
261 CHOOSE(ISL_TILING_LINEAR
);
265 /* No tiling mode accomodates the inputs. */
270 isl_choose_msaa_layout(const struct isl_device
*dev
,
271 const struct isl_surf_init_info
*info
,
272 enum isl_tiling tiling
,
273 enum isl_msaa_layout
*msaa_layout
)
275 if (ISL_DEV_GEN(dev
) >= 8) {
276 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
277 } else if (ISL_DEV_GEN(dev
) >= 7) {
278 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
279 } else if (ISL_DEV_GEN(dev
) >= 6) {
280 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
282 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
287 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
288 uint32_t *width
, uint32_t *height
)
290 assert(isl_is_pow2(samples
));
292 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
295 * If the surface is multisampled and it is a depth or stencil surface
296 * or Multisampled Surface StorageFormat in SURFACE_STATE is
297 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
301 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
303 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
306 static enum isl_array_pitch_span
307 isl_choose_array_pitch_span(const struct isl_device
*dev
,
308 const struct isl_surf_init_info
*restrict info
,
309 enum isl_dim_layout dim_layout
,
310 const struct isl_extent4d
*phys_level0_sa
)
312 switch (dim_layout
) {
313 case ISL_DIM_LAYOUT_GEN9_1D
:
314 case ISL_DIM_LAYOUT_GEN4_2D
:
315 if (ISL_DEV_GEN(dev
) >= 8) {
316 /* QPitch becomes programmable in Broadwell. So choose the
317 * most compact QPitch possible in order to conserve memory.
319 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
320 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
322 * - Software must ensure that this field is set to a value
323 * sufficiently large such that the array slices in the surface
324 * do not overlap. Refer to the Memory Data Formats section for
325 * information on how surfaces are stored in memory.
327 * - This field specifies the distance in rows between array
328 * slices. It is used only in the following cases:
330 * - Surface Array is enabled OR
331 * - Number of Mulitsamples is not NUMSAMPLES_1 and
332 * Multisampled Surface Storage Format set to MSFMT_MSS OR
333 * - Surface Type is SURFTYPE_CUBE
335 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
336 } else if (ISL_DEV_GEN(dev
) >= 7) {
337 /* Note that Ivybridge introduces
338 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
339 * driver more control over the QPitch.
342 if (phys_level0_sa
->array_len
== 1) {
343 /* The hardware will never use the QPitch. So choose the most
344 * compact QPitch possible in order to conserve memory.
346 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
349 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
350 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
351 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
352 * Section 6.18.4.7: Surface Arrays (p112):
354 * If Surface Array Spacing is set to ARYSPC_FULL (note that
355 * the depth buffer and stencil buffer have an implied value of
358 return ISL_ARRAY_PITCH_SPAN_FULL
;
361 if (info
->levels
== 1) {
362 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
365 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
368 return ISL_ARRAY_PITCH_SPAN_FULL
;
369 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
370 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
371 isl_surf_usage_is_stencil(info
->usage
)) {
372 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
373 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
375 * The separate stencil buffer does not support mip mapping, thus
376 * the storage for LODs other than LOD 0 is not needed.
378 assert(info
->levels
== 1);
379 assert(phys_level0_sa
->array_len
== 1);
380 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
382 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
383 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
384 isl_surf_usage_is_stencil(info
->usage
)) {
385 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
386 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
388 * The separate stencil buffer does not support mip mapping,
389 * thus the storage for LODs other than LOD 0 is not needed.
391 assert(info
->levels
== 1);
392 assert(phys_level0_sa
->array_len
== 1);
393 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
396 if (phys_level0_sa
->array_len
== 1) {
397 /* The hardware will never use the QPitch. So choose the most
398 * compact QPitch possible in order to conserve memory.
400 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
403 return ISL_ARRAY_PITCH_SPAN_FULL
;
406 case ISL_DIM_LAYOUT_GEN4_3D
:
407 /* The hardware will never use the QPitch. So choose the most
408 * compact QPitch possible in order to conserve memory.
410 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
413 unreachable("bad isl_dim_layout");
414 return ISL_ARRAY_PITCH_SPAN_FULL
;
418 isl_choose_image_alignment_el(const struct isl_device
*dev
,
419 const struct isl_surf_init_info
*restrict info
,
420 enum isl_tiling tiling
,
421 enum isl_msaa_layout msaa_layout
,
422 struct isl_extent3d
*image_align_el
)
424 if (info
->format
== ISL_FORMAT_HIZ
) {
425 assert(ISL_DEV_GEN(dev
) >= 6);
426 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
427 * which works out to 2x2 HiZ elments.
429 *image_align_el
= isl_extent3d(2, 2, 1);
433 if (ISL_DEV_GEN(dev
) >= 9) {
434 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
436 } else if (ISL_DEV_GEN(dev
) >= 8) {
437 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
439 } else if (ISL_DEV_GEN(dev
) >= 7) {
440 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
442 } else if (ISL_DEV_GEN(dev
) >= 6) {
443 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
446 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
451 static enum isl_dim_layout
452 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
453 enum isl_surf_dim logical_dim
)
455 if (ISL_DEV_GEN(dev
) >= 9) {
456 switch (logical_dim
) {
457 case ISL_SURF_DIM_1D
:
458 return ISL_DIM_LAYOUT_GEN9_1D
;
459 case ISL_SURF_DIM_2D
:
460 case ISL_SURF_DIM_3D
:
461 return ISL_DIM_LAYOUT_GEN4_2D
;
464 switch (logical_dim
) {
465 case ISL_SURF_DIM_1D
:
466 case ISL_SURF_DIM_2D
:
467 return ISL_DIM_LAYOUT_GEN4_2D
;
468 case ISL_SURF_DIM_3D
:
469 return ISL_DIM_LAYOUT_GEN4_3D
;
473 unreachable("bad isl_surf_dim");
474 return ISL_DIM_LAYOUT_GEN4_2D
;
478 * Calculate the physical extent of the surface's first level, in units of
479 * surface samples. The result is aligned to the format's compression block.
482 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
483 const struct isl_surf_init_info
*restrict info
,
484 enum isl_dim_layout dim_layout
,
485 enum isl_tiling tiling
,
486 enum isl_msaa_layout msaa_layout
,
487 struct isl_extent4d
*phys_level0_sa
)
489 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
491 if (isl_format_is_yuv(info
->format
))
492 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
495 case ISL_SURF_DIM_1D
:
496 assert(info
->height
== 1);
497 assert(info
->depth
== 1);
498 assert(info
->samples
== 1);
499 assert(!isl_format_is_compressed(info
->format
));
501 switch (dim_layout
) {
502 case ISL_DIM_LAYOUT_GEN4_3D
:
503 unreachable("bad isl_dim_layout");
505 case ISL_DIM_LAYOUT_GEN9_1D
:
506 case ISL_DIM_LAYOUT_GEN4_2D
:
507 *phys_level0_sa
= (struct isl_extent4d
) {
511 .a
= info
->array_len
,
517 case ISL_SURF_DIM_2D
:
518 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
520 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
521 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
523 switch (msaa_layout
) {
524 case ISL_MSAA_LAYOUT_NONE
:
525 assert(info
->depth
== 1);
526 assert(info
->samples
== 1);
528 *phys_level0_sa
= (struct isl_extent4d
) {
529 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
530 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
532 .a
= info
->array_len
,
536 case ISL_MSAA_LAYOUT_ARRAY
:
537 assert(info
->depth
== 1);
538 assert(info
->array_len
== 1);
539 assert(!isl_format_is_compressed(info
->format
));
541 *phys_level0_sa
= (struct isl_extent4d
) {
549 case ISL_MSAA_LAYOUT_INTERLEAVED
:
550 assert(info
->depth
== 1);
551 assert(info
->array_len
== 1);
552 assert(!isl_format_is_compressed(info
->format
));
554 *phys_level0_sa
= (struct isl_extent4d
) {
561 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
568 case ISL_SURF_DIM_3D
:
569 assert(info
->array_len
== 1);
570 assert(info
->samples
== 1);
573 isl_finishme("%s:%s: compression block with depth > 1",
577 switch (dim_layout
) {
578 case ISL_DIM_LAYOUT_GEN9_1D
:
579 unreachable("bad isl_dim_layout");
581 case ISL_DIM_LAYOUT_GEN4_2D
:
582 assert(ISL_DEV_GEN(dev
) >= 9);
584 *phys_level0_sa
= (struct isl_extent4d
) {
585 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
586 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
592 case ISL_DIM_LAYOUT_GEN4_3D
:
593 assert(ISL_DEV_GEN(dev
) < 9);
594 *phys_level0_sa
= (struct isl_extent4d
) {
595 .w
= isl_align(info
->width
, fmtl
->bw
),
596 .h
= isl_align(info
->height
, fmtl
->bh
),
607 * A variant of isl_calc_phys_slice0_extent_sa() specific to
608 * ISL_DIM_LAYOUT_GEN4_2D.
611 isl_calc_phys_slice0_extent_sa_gen4_2d(
612 const struct isl_device
*dev
,
613 const struct isl_surf_init_info
*restrict info
,
614 enum isl_msaa_layout msaa_layout
,
615 const struct isl_extent3d
*image_align_sa
,
616 const struct isl_extent4d
*phys_level0_sa
,
617 struct isl_extent2d
*phys_slice0_sa
)
619 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
621 assert(phys_level0_sa
->depth
== 1);
623 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
624 /* Do not pad the surface to the image alignment. Instead, pad it only
625 * to the pixel format's block alignment.
627 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
628 * cycles on the below mipmap layout caluclations. Reducing the
629 * alignment here is safe because we later align the row pitch and array
630 * pitch to the tile boundary. It is safe even for
631 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
632 * to accomodate the interleaved samples.
634 * For linear surfaces, reducing the alignment here permits us to later
635 * choose an arbitrary, non-aligned row pitch. If the surface backs
636 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
637 * VkBufferImageCopy::bufferRowLength.
639 *phys_slice0_sa
= (struct isl_extent2d
) {
640 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
641 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
646 uint32_t slice_top_w
= 0;
647 uint32_t slice_bottom_w
= 0;
648 uint32_t slice_left_h
= 0;
649 uint32_t slice_right_h
= 0;
651 uint32_t W0
= phys_level0_sa
->w
;
652 uint32_t H0
= phys_level0_sa
->h
;
654 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
655 uint32_t W
= isl_minify(W0
, l
);
656 uint32_t H
= isl_minify(H0
, l
);
658 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
659 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
662 * If the surface is multisampled and it is a depth or stencil
663 * surface or Multisampled Surface StorageFormat in
664 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
665 * adjusted as follows before proceeding: [...]
667 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
670 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
671 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
688 *phys_slice0_sa
= (struct isl_extent2d
) {
689 .w
= MAX(slice_top_w
, slice_bottom_w
),
690 .h
= MAX(slice_left_h
, slice_right_h
),
695 * A variant of isl_calc_phys_slice0_extent_sa() specific to
696 * ISL_DIM_LAYOUT_GEN4_3D.
699 isl_calc_phys_slice0_extent_sa_gen4_3d(
700 const struct isl_device
*dev
,
701 const struct isl_surf_init_info
*restrict info
,
702 const struct isl_extent3d
*image_align_sa
,
703 const struct isl_extent4d
*phys_level0_sa
,
704 struct isl_extent2d
*phys_slice0_sa
)
706 assert(info
->samples
== 1);
707 assert(phys_level0_sa
->array_len
== 1);
709 uint32_t slice_w
= 0;
710 uint32_t slice_h
= 0;
712 uint32_t W0
= phys_level0_sa
->w
;
713 uint32_t H0
= phys_level0_sa
->h
;
714 uint32_t D0
= phys_level0_sa
->d
;
716 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
717 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
718 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
719 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
721 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
722 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
724 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
725 slice_h
+= level_h
* max_layers_vert
;
728 *phys_slice0_sa
= (struct isl_extent2d
) {
735 * A variant of isl_calc_phys_slice0_extent_sa() specific to
736 * ISL_DIM_LAYOUT_GEN9_1D.
739 isl_calc_phys_slice0_extent_sa_gen9_1d(
740 const struct isl_device
*dev
,
741 const struct isl_surf_init_info
*restrict info
,
742 const struct isl_extent3d
*image_align_sa
,
743 const struct isl_extent4d
*phys_level0_sa
,
744 struct isl_extent2d
*phys_slice0_sa
)
746 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
748 assert(phys_level0_sa
->height
== 1);
749 assert(phys_level0_sa
->depth
== 1);
750 assert(info
->samples
== 1);
751 assert(image_align_sa
->w
>= fmtl
->bw
);
753 uint32_t slice_w
= 0;
754 const uint32_t W0
= phys_level0_sa
->w
;
756 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
757 uint32_t W
= isl_minify(W0
, l
);
758 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
763 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
767 * Calculate the physical extent of the surface's first array slice, in units
768 * of surface samples. If the surface is multi-leveled, then the result will
769 * be aligned to \a image_align_sa.
772 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
773 const struct isl_surf_init_info
*restrict info
,
774 enum isl_dim_layout dim_layout
,
775 enum isl_msaa_layout msaa_layout
,
776 const struct isl_extent3d
*image_align_sa
,
777 const struct isl_extent4d
*phys_level0_sa
,
778 struct isl_extent2d
*phys_slice0_sa
)
780 switch (dim_layout
) {
781 case ISL_DIM_LAYOUT_GEN9_1D
:
782 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
783 image_align_sa
, phys_level0_sa
,
786 case ISL_DIM_LAYOUT_GEN4_2D
:
787 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
788 image_align_sa
, phys_level0_sa
,
791 case ISL_DIM_LAYOUT_GEN4_3D
:
792 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
793 phys_level0_sa
, phys_slice0_sa
);
799 * Calculate the pitch between physical array slices, in units of rows of
803 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
804 const struct isl_surf_init_info
*restrict info
,
805 const struct isl_tile_info
*tile_info
,
806 enum isl_dim_layout dim_layout
,
807 enum isl_array_pitch_span array_pitch_span
,
808 const struct isl_extent3d
*image_align_sa
,
809 const struct isl_extent4d
*phys_level0_sa
,
810 const struct isl_extent2d
*phys_slice0_sa
)
812 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
813 uint32_t pitch_sa_rows
= 0;
815 switch (dim_layout
) {
816 case ISL_DIM_LAYOUT_GEN9_1D
:
817 /* Each row is an array slice */
820 case ISL_DIM_LAYOUT_GEN4_2D
:
821 switch (array_pitch_span
) {
822 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
823 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
825 case ISL_ARRAY_PITCH_SPAN_FULL
: {
826 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
827 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
828 * Surfaces >> Surface Arrays.
830 uint32_t H0_sa
= phys_level0_sa
->h
;
831 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
833 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
834 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
837 if (ISL_DEV_GEN(dev
) >= 7) {
838 /* The QPitch equation changed slightly in Ivybridge. */
844 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
846 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
847 (info
->height
% 4 == 1)) {
848 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
849 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
851 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
852 * the value calculated in the equation above , for every
853 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
855 * XXX(chadv): Is the errata natural corollary of the physical
856 * layout of interleaved samples?
861 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
866 case ISL_DIM_LAYOUT_GEN4_3D
:
867 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
868 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
871 unreachable("bad isl_dim_layout");
875 assert(pitch_sa_rows
% fmtl
->bh
== 0);
876 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
878 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
880 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
882 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
883 * layout with these alignments in the RT space: Horizontal
884 * Alignment = 128 and Vertical Alignment = 64."
886 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
888 * "For non-multisampled render target's CCS auxiliary surface,
889 * QPitch must be computed with Horizontal Alignment = 128 and
890 * Surface Vertical Alignment = 256. These alignments are only for
891 * CCS buffer and not for associated render target."
893 * The first restriction is already handled by isl_choose_image_alignment_el
894 * but the second restriction, which is an extension of the first, only
895 * applies to qpitch and must be applied here.
897 assert(fmtl
->bh
== 4);
898 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
901 if (ISL_DEV_GEN(dev
) >= 9 &&
902 info
->dim
== ISL_SURF_DIM_3D
&&
903 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
904 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
906 * Tile Mode != Linear: This field must be set to an integer multiple
909 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
912 return pitch_el_rows
;
916 * Calculate the pitch of each surface row, in bytes.
919 isl_calc_linear_row_pitch(const struct isl_device
*dev
,
920 const struct isl_surf_init_info
*restrict info
,
921 const struct isl_extent2d
*phys_slice0_sa
)
923 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
925 uint32_t row_pitch
= info
->min_pitch
;
927 /* First, align the surface to a cache line boundary, as the PRM explains
930 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
931 * Formats >> Surface Padding Requirements >> Render Target and Media
934 * The data port accesses data (pixels) outside of the surface if they
935 * are contained in the same cache request as pixels that are within the
936 * surface. These pixels will not be returned by the requesting message,
937 * however if these pixels lie outside of defined pages in the GTT,
938 * a GTT error will result when the cache request is processed. In order
939 * to avoid these GTT errors, “padding” at the bottom of the surface is
940 * sometimes necessary.
942 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
943 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
945 * The sampling engine accesses texels outside of the surface if they
946 * are contained in the same cache line as texels that are within the
947 * surface. These texels will not participate in any calculation
948 * performed by the sampling engine and will not affect the result of
949 * any sampling engine operation, however if these texels lie outside of
950 * defined pages in the GTT, a GTT error will result when the cache line
951 * is accessed. In order to avoid these GTT errors, “padding” at the
952 * bottom and right side of a sampling engine surface is sometimes
955 * It is possible that a cache line will straddle a page boundary if the
956 * base address or pitch is not aligned. All pages included in the cache
957 * lines that are part of the surface must map to valid GTT entries to
958 * avoid errors. To determine the necessary padding on the bottom and
959 * right side of the surface, refer to the table in Alignment Unit Size
960 * section for the i and j parameters for the surface format in use. The
961 * surface must then be extended to the next multiple of the alignment
962 * unit size in each dimension, and all texels contained in this
963 * extended surface must have valid GTT entries.
965 * For example, suppose the surface size is 15 texels by 10 texels and
966 * the alignment parameters are i=4 and j=2. In this case, the extended
967 * surface would be 16 by 10. Note that these calculations are done in
968 * texels, and must be converted to bytes based on the surface format
969 * being used to determine whether additional pages need to be defined.
971 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
972 const uint32_t bs
= fmtl
->bpb
/ 8;
973 row_pitch
= MAX(row_pitch
, bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
975 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
976 * RENDER_SURFACE_STATE Surface Pitch (p349):
978 * - For linear render target surfaces and surfaces accessed with the
979 * typed data port messages, the pitch must be a multiple of the
980 * element size for non-YUV surface formats. Pitch must be
981 * a multiple of 2 * element size for YUV surface formats.
983 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
984 * ignore because isl doesn't do buffers.]
986 * - For other linear surfaces, the pitch can be any multiple of
989 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
990 if (isl_format_is_yuv(info
->format
)) {
991 row_pitch
= isl_align_npot(row_pitch
, 2 * bs
);
993 row_pitch
= isl_align_npot(row_pitch
, bs
);
1001 * Calculate and apply any padding required for the surface.
1003 * @param[inout] total_h_el is updated with the new height
1004 * @param[out] pad_bytes is overwritten with additional padding requirements.
1007 isl_apply_surface_padding(const struct isl_device
*dev
,
1008 const struct isl_surf_init_info
*restrict info
,
1009 const struct isl_tile_info
*tile_info
,
1010 uint32_t *total_h_el
,
1011 uint32_t *pad_bytes
)
1013 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1017 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1018 * Formats >> Surface Padding Requirements >> Render Target and Media
1021 * The data port accesses data (pixels) outside of the surface if they
1022 * are contained in the same cache request as pixels that are within the
1023 * surface. These pixels will not be returned by the requesting message,
1024 * however if these pixels lie outside of defined pages in the GTT,
1025 * a GTT error will result when the cache request is processed. In
1026 * order to avoid these GTT errors, “padding” at the bottom of the
1027 * surface is sometimes necessary.
1029 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1030 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1032 * ... Lots of padding requirements, all listed separately below.
1035 /* We can safely ignore the first padding requirement, quoted below,
1036 * because isl doesn't do buffers.
1038 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1039 * requirements are different. A buffer must be padded to the next
1040 * multiple of 256 array elements, with an additional 16 bytes added
1041 * beyond that to account for the L1 cache line.
1045 * - For compressed textures [...], padding at the bottom of the surface
1046 * is to an even compressed row.
1048 if (isl_format_is_compressed(info
->format
))
1049 *total_h_el
= isl_align(*total_h_el
, 2);
1052 * - For cube surfaces, an additional two rows of padding are required
1053 * at the bottom of the surface.
1055 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1059 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1060 * additional padding is required. These surfaces require an extra row
1061 * plus 16 bytes of padding at the bottom in addition to the general
1062 * padding requirements.
1064 if (isl_format_is_yuv(info
->format
) &&
1065 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1071 * - For linear surfaces, additional padding of 64 bytes is required at
1072 * the bottom of the surface. This is in addition to the padding
1075 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1078 /* The below text weakens, not strengthens, the padding requirements for
1079 * linear surfaces. Therefore we can safely ignore it.
1081 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1082 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1083 * padding requirement is to the next aligned 64-byte boundary beyond
1084 * the end of the surface. The rest of the padding requirements
1085 * documented above do not apply to these surfaces.
1089 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1090 * height % 4 != 0, the surface must be padded with
1091 * 4-(height % 4)*Surface Pitch # of bytes.
1093 if (ISL_DEV_GEN(dev
) >= 9 &&
1094 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1095 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1096 *total_h_el
= isl_align(*total_h_el
, 4);
1100 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1101 * to 4 times the Surface Pitch # of bytes
1103 if (ISL_DEV_GEN(dev
) >= 9 &&
1104 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1105 info
->dim
== ISL_SURF_DIM_1D
) {
1111 isl_surf_init_s(const struct isl_device
*dev
,
1112 struct isl_surf
*surf
,
1113 const struct isl_surf_init_info
*restrict info
)
1115 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1117 const struct isl_extent4d logical_level0_px
= {
1121 .a
= info
->array_len
,
1124 enum isl_dim_layout dim_layout
=
1125 isl_surf_choose_dim_layout(dev
, info
->dim
);
1127 enum isl_tiling tiling
;
1128 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1131 struct isl_tile_info tile_info
;
1132 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1135 enum isl_msaa_layout msaa_layout
;
1136 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1139 struct isl_extent3d image_align_el
;
1140 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1143 struct isl_extent3d image_align_sa
=
1144 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1146 struct isl_extent4d phys_level0_sa
;
1147 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1149 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1150 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1152 enum isl_array_pitch_span array_pitch_span
=
1153 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1155 struct isl_extent2d phys_slice0_sa
;
1156 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1157 &image_align_sa
, &phys_level0_sa
,
1159 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1160 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1162 const uint32_t array_pitch_el_rows
=
1163 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1164 array_pitch_span
, &image_align_sa
,
1165 &phys_level0_sa
, &phys_slice0_sa
);
1167 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1170 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1172 uint32_t row_pitch
, size
, base_alignment
;
1173 if (tiling
== ISL_TILING_LINEAR
) {
1174 row_pitch
= isl_calc_linear_row_pitch(dev
, info
, &phys_slice0_sa
);
1175 size
= row_pitch
* total_h_el
+ pad_bytes
;
1177 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1179 * "The Base Address for linear render target surfaces and surfaces
1180 * accessed with the typed surface read/write data port messages must
1181 * be element-size aligned, for non-YUV surface formats, or a
1182 * multiple of 2 element-sizes for YUV surface formats. Other linear
1183 * surfaces have no alignment requirements (byte alignment is
1186 base_alignment
= MAX(1, info
->min_alignment
);
1187 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1188 if (isl_format_is_yuv(info
->format
)) {
1189 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1191 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1195 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1196 const uint32_t total_w_el
= phys_slice0_sa
.width
/ fmtl
->bw
;
1197 const uint32_t total_w_tl
=
1198 isl_align_div(total_w_el
, tile_info
.logical_extent_el
.width
);
1200 row_pitch
= total_w_tl
* tile_info
.phys_extent_B
.width
;
1201 if (row_pitch
< info
->min_pitch
) {
1202 row_pitch
= isl_align(info
->min_pitch
, tile_info
.phys_extent_B
.width
);
1205 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1206 const uint32_t total_h_tl
=
1207 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1209 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1211 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1212 tile_info
.phys_extent_B
.height
;
1213 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1214 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1217 *surf
= (struct isl_surf
) {
1219 .dim_layout
= dim_layout
,
1220 .msaa_layout
= msaa_layout
,
1222 .format
= info
->format
,
1224 .levels
= info
->levels
,
1225 .samples
= info
->samples
,
1227 .image_alignment_el
= image_align_el
,
1228 .logical_level0_px
= logical_level0_px
,
1229 .phys_level0_sa
= phys_level0_sa
,
1232 .alignment
= base_alignment
,
1233 .row_pitch
= row_pitch
,
1234 .array_pitch_el_rows
= array_pitch_el_rows
,
1235 .array_pitch_span
= array_pitch_span
,
1237 .usage
= info
->usage
,
1244 isl_surf_get_tile_info(const struct isl_device
*dev
,
1245 const struct isl_surf
*surf
,
1246 struct isl_tile_info
*tile_info
)
1248 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1249 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1253 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1254 const struct isl_surf_fill_state_info
*restrict info
)
1257 isl_surf_usage_flags_t _base_usage
=
1258 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1259 ISL_SURF_USAGE_TEXTURE_BIT
|
1260 ISL_SURF_USAGE_STORAGE_BIT
);
1261 /* They may only specify one of the above bits at a time */
1262 assert(__builtin_popcount(_base_usage
) == 1);
1263 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1264 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1267 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1268 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1269 info
->surf
->logical_level0_px
.depth
);
1271 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1272 info
->surf
->logical_level0_px
.array_len
);
1275 switch (ISL_DEV_GEN(dev
)) {
1277 if (ISL_DEV_IS_HASWELL(dev
)) {
1278 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1280 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1284 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1287 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1290 assert(!"Cannot fill surface state for this gen");
1295 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1296 const struct isl_buffer_fill_state_info
*restrict info
)
1298 switch (ISL_DEV_GEN(dev
)) {
1300 if (ISL_DEV_IS_HASWELL(dev
)) {
1301 isl_gen75_buffer_fill_state_s(state
, info
);
1303 isl_gen7_buffer_fill_state_s(state
, info
);
1307 isl_gen8_buffer_fill_state_s(state
, info
);
1310 isl_gen9_buffer_fill_state_s(state
, info
);
1313 assert(!"Cannot fill surface state for this gen");
1318 * A variant of isl_surf_get_image_offset_sa() specific to
1319 * ISL_DIM_LAYOUT_GEN4_2D.
1322 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1323 uint32_t level
, uint32_t layer
,
1324 uint32_t *x_offset_sa
,
1325 uint32_t *y_offset_sa
)
1327 assert(level
< surf
->levels
);
1328 assert(layer
< surf
->phys_level0_sa
.array_len
);
1329 assert(surf
->phys_level0_sa
.depth
== 1);
1331 const struct isl_extent3d image_align_sa
=
1332 isl_surf_get_image_alignment_sa(surf
);
1334 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1335 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1338 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1340 for (uint32_t l
= 0; l
< level
; ++l
) {
1342 uint32_t W
= isl_minify(W0
, l
);
1344 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1345 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1347 x
+= isl_align_npot(W
, image_align_sa
.w
);
1349 uint32_t H
= isl_minify(H0
, l
);
1351 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1352 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1354 y
+= isl_align_npot(H
, image_align_sa
.h
);
1363 * A variant of isl_surf_get_image_offset_sa() specific to
1364 * ISL_DIM_LAYOUT_GEN4_3D.
1367 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1368 uint32_t level
, uint32_t logical_z_offset_px
,
1369 uint32_t *x_offset_sa
,
1370 uint32_t *y_offset_sa
)
1372 assert(level
< surf
->levels
);
1373 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1374 assert(surf
->phys_level0_sa
.array_len
== 1);
1376 const struct isl_extent3d image_align_sa
=
1377 isl_surf_get_image_alignment_sa(surf
);
1379 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1380 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1381 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1386 for (uint32_t l
= 0; l
< level
; ++l
) {
1387 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1388 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1389 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1391 y
+= level_h
* max_layers_vert
;
1394 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1395 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1396 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1398 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1400 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1401 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1408 * A variant of isl_surf_get_image_offset_sa() specific to
1409 * ISL_DIM_LAYOUT_GEN9_1D.
1412 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1413 uint32_t level
, uint32_t layer
,
1414 uint32_t *x_offset_sa
,
1415 uint32_t *y_offset_sa
)
1417 assert(level
< surf
->levels
);
1418 assert(layer
< surf
->phys_level0_sa
.array_len
);
1419 assert(surf
->phys_level0_sa
.height
== 1);
1420 assert(surf
->phys_level0_sa
.depth
== 1);
1421 assert(surf
->samples
== 1);
1423 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1424 const struct isl_extent3d image_align_sa
=
1425 isl_surf_get_image_alignment_sa(surf
);
1429 for (uint32_t l
= 0; l
< level
; ++l
) {
1430 uint32_t W
= isl_minify(W0
, l
);
1431 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1437 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1441 * Calculate the offset, in units of surface samples, to a subimage in the
1444 * @invariant level < surface levels
1445 * @invariant logical_array_layer < logical array length of surface
1446 * @invariant logical_z_offset_px < logical depth of surface at level
1449 get_image_offset_sa(const struct isl_surf
*surf
,
1451 uint32_t logical_array_layer
,
1452 uint32_t logical_z_offset_px
,
1453 uint32_t *x_offset_sa
,
1454 uint32_t *y_offset_sa
)
1456 assert(level
< surf
->levels
);
1457 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1458 assert(logical_z_offset_px
1459 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1461 switch (surf
->dim_layout
) {
1462 case ISL_DIM_LAYOUT_GEN9_1D
:
1463 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1464 x_offset_sa
, y_offset_sa
);
1466 case ISL_DIM_LAYOUT_GEN4_2D
:
1467 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1468 + logical_z_offset_px
,
1469 x_offset_sa
, y_offset_sa
);
1471 case ISL_DIM_LAYOUT_GEN4_3D
:
1472 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1473 x_offset_sa
, y_offset_sa
);
1477 unreachable("not reached");
1482 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1484 uint32_t logical_array_layer
,
1485 uint32_t logical_z_offset_px
,
1486 uint32_t *x_offset_el
,
1487 uint32_t *y_offset_el
)
1489 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1491 assert(level
< surf
->levels
);
1492 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1493 assert(logical_z_offset_px
1494 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1496 uint32_t x_offset_sa
, y_offset_sa
;
1497 get_image_offset_sa(surf
, level
,
1498 logical_array_layer
,
1499 logical_z_offset_px
,
1503 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1504 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1508 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1509 enum isl_tiling tiling
,
1512 uint32_t total_x_offset_el
,
1513 uint32_t total_y_offset_el
,
1514 uint32_t *base_address_offset
,
1515 uint32_t *x_offset_el
,
1516 uint32_t *y_offset_el
)
1518 /* This function only really works for power-of-two surfaces. In
1519 * theory, we could make it work for non-power-of-two surfaces by going
1520 * to the left until we find a block that is bs-aligned. The Vulkan
1521 * driver doesn't use non-power-of-two tiled surfaces so we'll leave
1522 * this unimplemented for now.
1524 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
1526 if (tiling
== ISL_TILING_LINEAR
) {
1527 *base_address_offset
= total_y_offset_el
* row_pitch
+
1528 total_x_offset_el
* bs
;
1534 struct isl_tile_info tile_info
;
1535 isl_tiling_get_info(dev
, tiling
, bs
* 8, &tile_info
);
1537 /* Compute the offset into the tile */
1538 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1539 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1541 /* Compute the offset of the tile in units of whole tiles */
1542 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1543 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1545 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1546 *base_address_offset
=
1547 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1548 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1552 isl_surf_get_depth_format(const struct isl_device
*dev
,
1553 const struct isl_surf
*surf
)
1555 /* Support for separate stencil buffers began in gen5. Support for
1556 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1557 * those that supported separate and interleaved stencil, were gen5 and
1560 * For a list of all available formats, see the Sandybridge PRM >> Volume
1561 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1565 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1567 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1570 assert(ISL_DEV_GEN(dev
) < 7);
1572 switch (surf
->format
) {
1574 unreachable("bad isl depth format");
1575 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1576 assert(ISL_DEV_GEN(dev
) < 7);
1577 return 0; /* D32_FLOAT_S8X24_UINT */
1578 case ISL_FORMAT_R32_FLOAT
:
1579 assert(!has_stencil
);
1580 return 1; /* D32_FLOAT */
1581 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1583 assert(ISL_DEV_GEN(dev
) < 7);
1584 return 2; /* D24_UNORM_S8_UINT */
1586 assert(ISL_DEV_GEN(dev
) >= 5);
1587 return 3; /* D24_UNORM_X8_UINT */
1589 case ISL_FORMAT_R16_UNORM
:
1590 assert(!has_stencil
);
1591 return 5; /* D16_UNORM */