2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
36 #include "isl_gen12.h"
40 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
41 uint32_t yt1
, uint32_t yt2
,
42 char *dst
, const char *src
,
43 uint32_t dst_pitch
, int32_t src_pitch
,
45 enum isl_tiling tiling
,
46 isl_memcpy_type copy_type
)
49 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
50 _isl_memcpy_linear_to_tiled_sse41(
51 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
57 _isl_memcpy_linear_to_tiled(
58 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
63 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
64 uint32_t yt1
, uint32_t yt2
,
65 char *dst
, const char *src
,
66 int32_t dst_pitch
, uint32_t src_pitch
,
68 enum isl_tiling tiling
,
69 isl_memcpy_type copy_type
)
72 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
73 _isl_memcpy_tiled_to_linear_sse41(
74 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
80 _isl_memcpy_tiled_to_linear(
81 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
85 void PRINTFLIKE(3, 4) UNUSED
86 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
92 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
95 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
99 isl_device_setup_mocs(struct isl_device
*dev
)
101 if (dev
->info
->gen
>= 12) {
102 /* TODO: Set PTE to MOCS 61 when the kernel is ready */
103 /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
104 dev
->mocs
.external
= 3 << 1;
105 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
106 dev
->mocs
.internal
= 2 << 1;
107 } else if (dev
->info
->gen
>= 9) {
108 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
109 dev
->mocs
.external
= 1 << 1;
110 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
111 dev
->mocs
.internal
= 2 << 1;
112 } else if (dev
->info
->gen
>= 8) {
113 /* MEMORY_OBJECT_CONTROL_STATE:
114 * .MemoryTypeLLCeLLCCacheabilityControl = UCwithFenceifcoherentcycle,
115 * .TargetCache = L3DefertoPATforLLCeLLCselection,
118 dev
->mocs
.external
= 0x18;
119 /* MEMORY_OBJECT_CONTROL_STATE:
120 * .MemoryTypeLLCeLLCCacheabilityControl = WB,
121 * .TargetCache = L3DefertoPATforLLCeLLCselection,
124 dev
->mocs
.internal
= 0x78;
125 } else if (dev
->info
->gen
>= 7) {
126 if (dev
->info
->is_haswell
) {
127 /* MEMORY_OBJECT_CONTROL_STATE:
128 * .LLCeLLCCacheabilityControlLLCCC = 0,
129 * .L3CacheabilityControlL3CC = 1,
131 dev
->mocs
.internal
= 1;
132 dev
->mocs
.external
= 1;
134 /* MEMORY_OBJECT_CONTROL_STATE:
135 * .GraphicsDataTypeGFDT = 0,
136 * .LLCCacheabilityControlLLCCC = 0,
137 * .L3CacheabilityControlL3CC = 1,
139 dev
->mocs
.internal
= 1;
140 dev
->mocs
.external
= 1;
143 dev
->mocs
.internal
= 0;
144 dev
->mocs
.external
= 0;
149 isl_device_init(struct isl_device
*dev
,
150 const struct gen_device_info
*info
,
151 bool has_bit6_swizzling
)
153 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
154 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
157 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
158 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
160 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
161 * device properties at buildtime. Verify that the macros with the device
162 * properties chosen during runtime.
164 ISL_DEV_GEN_SANITIZE(dev
);
165 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
167 /* Did we break hiz or stencil? */
168 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
169 assert(info
->has_hiz_and_separate_stencil
);
170 if (info
->must_use_separate_stencil
)
171 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
173 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
174 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
176 dev
->ss
.clear_color_state_size
=
177 isl_align(CLEAR_COLOR_length(info
) * 4, 64);
178 dev
->ss
.clear_color_state_offset
=
179 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
181 dev
->ss
.clear_value_size
=
182 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
183 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
184 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
185 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
187 dev
->ss
.clear_value_offset
=
188 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
190 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
191 dev
->ss
.addr_offset
=
192 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
194 /* The "Auxiliary Surface Base Address" field starts a bit higher up
195 * because the bottom 12 bits are used for other things. Round down to
196 * the nearest dword before.
198 dev
->ss
.aux_addr_offset
=
199 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
201 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
202 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
203 dev
->ds
.depth_offset
=
204 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
206 if (dev
->use_separate_stencil
) {
207 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
208 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
209 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
211 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
212 dev
->ds
.stencil_offset
=
213 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
214 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
216 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
218 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
219 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
220 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
222 dev
->ds
.stencil_offset
= 0;
223 dev
->ds
.hiz_offset
= 0;
226 isl_device_setup_mocs(dev
);
230 * @brief Query the set of multisamples supported by the device.
232 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
235 isl_sample_count_mask_t ATTRIBUTE_CONST
236 isl_device_get_sample_counts(struct isl_device
*dev
)
238 if (ISL_DEV_GEN(dev
) >= 9) {
239 return ISL_SAMPLE_COUNT_1_BIT
|
240 ISL_SAMPLE_COUNT_2_BIT
|
241 ISL_SAMPLE_COUNT_4_BIT
|
242 ISL_SAMPLE_COUNT_8_BIT
|
243 ISL_SAMPLE_COUNT_16_BIT
;
244 } else if (ISL_DEV_GEN(dev
) >= 8) {
245 return ISL_SAMPLE_COUNT_1_BIT
|
246 ISL_SAMPLE_COUNT_2_BIT
|
247 ISL_SAMPLE_COUNT_4_BIT
|
248 ISL_SAMPLE_COUNT_8_BIT
;
249 } else if (ISL_DEV_GEN(dev
) >= 7) {
250 return ISL_SAMPLE_COUNT_1_BIT
|
251 ISL_SAMPLE_COUNT_4_BIT
|
252 ISL_SAMPLE_COUNT_8_BIT
;
253 } else if (ISL_DEV_GEN(dev
) >= 6) {
254 return ISL_SAMPLE_COUNT_1_BIT
|
255 ISL_SAMPLE_COUNT_4_BIT
;
257 return ISL_SAMPLE_COUNT_1_BIT
;
262 * @param[out] info is written only on success
265 isl_tiling_get_info(enum isl_tiling tiling
,
267 struct isl_tile_info
*tile_info
)
269 const uint32_t bs
= format_bpb
/ 8;
270 struct isl_extent2d logical_el
, phys_B
;
272 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
273 /* It is possible to have non-power-of-two formats in a tiled buffer.
274 * The easiest way to handle this is to treat the tile as if it is three
275 * times as wide. This way no pixel will ever cross a tile boundary.
276 * This really only works on legacy X and Y tiling formats.
278 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
279 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
280 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
285 case ISL_TILING_LINEAR
:
287 logical_el
= isl_extent2d(1, 1);
288 phys_B
= isl_extent2d(bs
, 1);
293 logical_el
= isl_extent2d(512 / bs
, 8);
294 phys_B
= isl_extent2d(512, 8);
299 logical_el
= isl_extent2d(128 / bs
, 32);
300 phys_B
= isl_extent2d(128, 32);
305 logical_el
= isl_extent2d(64, 64);
306 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
308 * "If the surface is a stencil buffer (and thus has Tile Mode set
309 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
310 * computed based on width, as the stencil buffer is stored with two
313 * This, together with the fact that stencil buffers are referred to as
314 * being Y-tiled in the PRMs for older hardware implies that the
315 * physical size of a W-tile is actually the same as for a Y-tile.
317 phys_B
= isl_extent2d(128, 32);
321 case ISL_TILING_Ys
: {
322 bool is_Ys
= tiling
== ISL_TILING_Ys
;
325 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
326 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
328 logical_el
= isl_extent2d(width
/ bs
, height
);
329 phys_B
= isl_extent2d(width
, height
);
334 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
335 * 128bpb format. The tiling has the same physical dimensions as
336 * Y-tiling but actually has two HiZ columns per Y-tiled column.
339 logical_el
= isl_extent2d(16, 16);
340 phys_B
= isl_extent2d(128, 32);
344 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
345 * have a block size of 1 or 2 bits per block and each CCS element
346 * corresponds to one cache-line pair in the main surface. From the Sky
347 * Lake PRM Vol. 12 in the section on planes:
349 * "The Color Control Surface (CCS) contains the compression status
350 * of the cache-line pairs. The compression state of the cache-line
351 * pair is specified by 2 bits in the CCS. Each CCS cache-line
352 * represents an area on the main surface of 16x16 sets of 128 byte
353 * Y-tiled cache-line-pairs. CCS is always Y tiled."
355 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
356 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
357 * that yields total tile area of 128x128 cache-line pairs or CCS
358 * elements. On older hardware, each CCS element is 1 bit and the tile
359 * is 128x256 elements.
361 assert(format_bpb
== 1 || format_bpb
== 2);
362 logical_el
= isl_extent2d(128, 256 / format_bpb
);
363 phys_B
= isl_extent2d(128, 32);
366 case ISL_TILING_GEN12_CCS
:
367 /* From the Bspec, Gen Graphics > Gen12 > Memory Data Formats > Memory
368 * Compression > Memory Compression - Gen12:
370 * 4 bits of auxiliary plane data are required for 2 cachelines of
371 * main surface data. This results in a single cacheline of auxiliary
372 * plane data mapping to 4 4K pages of main surface data for the 4K
373 * pages (tile Y ) and 1 64K Tile Ys page.
375 * The Y-tiled pairing bit of 9 shown in the table below that Bspec
376 * section expresses that the 2 cachelines of main surface data are
377 * horizontally adjacent.
379 * TODO: Handle Ys, Yf and their pairing bits.
381 * Therefore, each CCS cacheline represents a 512Bx32 row area and each
382 * element represents a 32Bx4 row area.
384 assert(format_bpb
== 4);
385 logical_el
= isl_extent2d(16, 8);
386 phys_B
= isl_extent2d(64, 1);
390 unreachable("not reached");
393 *tile_info
= (struct isl_tile_info
) {
395 .format_bpb
= format_bpb
,
396 .logical_extent_el
= logical_el
,
397 .phys_extent_B
= phys_B
,
402 isl_color_value_is_zero(union isl_color_value value
,
403 enum isl_format format
)
405 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
407 #define RETURN_FALSE_IF_NOT_0(c, i) \
408 if (fmtl->channels.c.bits && value.u32[i] != 0) \
411 RETURN_FALSE_IF_NOT_0(r
, 0);
412 RETURN_FALSE_IF_NOT_0(g
, 1);
413 RETURN_FALSE_IF_NOT_0(b
, 2);
414 RETURN_FALSE_IF_NOT_0(a
, 3);
416 #undef RETURN_FALSE_IF_NOT_0
422 isl_color_value_is_zero_one(union isl_color_value value
,
423 enum isl_format format
)
425 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
427 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
428 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
431 if (isl_format_has_int_channel(format
)) {
432 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
433 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
434 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
435 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
437 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
438 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
439 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
440 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
443 #undef RETURN_FALSE_IF_NOT_0_1
449 * @param[out] tiling is set only on success
452 isl_surf_choose_tiling(const struct isl_device
*dev
,
453 const struct isl_surf_init_info
*restrict info
,
454 enum isl_tiling
*tiling
)
456 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
458 /* HiZ surfaces always use the HiZ tiling */
459 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
460 assert(info
->format
== ISL_FORMAT_HIZ
);
461 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
462 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
466 /* CCS surfaces always use the CCS tiling */
467 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
468 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
469 UNUSED
bool ivb_ccs
= ISL_DEV_GEN(dev
) < 12 &&
470 tiling_flags
== ISL_TILING_CCS_BIT
;
471 UNUSED
bool tgl_ccs
= ISL_DEV_GEN(dev
) >= 12 &&
472 tiling_flags
== ISL_TILING_GEN12_CCS_BIT
;
473 assert(ivb_ccs
!= tgl_ccs
);
474 *tiling
= isl_tiling_flag_to_enum(tiling_flags
);
478 if (ISL_DEV_GEN(dev
) >= 6) {
479 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
481 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
484 #define CHOOSE(__tiling) \
486 if (tiling_flags & (1u << (__tiling))) { \
487 *tiling = (__tiling); \
492 /* Of the tiling modes remaining, choose the one that offers the best
496 if (info
->dim
== ISL_SURF_DIM_1D
) {
497 /* Prefer linear for 1D surfaces because they do not benefit from
498 * tiling. To the contrary, tiling leads to wasted memory and poor
499 * memory locality due to the swizzling and alignment restrictions
500 * required in tiled surfaces.
502 CHOOSE(ISL_TILING_LINEAR
);
505 CHOOSE(ISL_TILING_Ys
);
506 CHOOSE(ISL_TILING_Yf
);
507 CHOOSE(ISL_TILING_Y0
);
508 CHOOSE(ISL_TILING_X
);
509 CHOOSE(ISL_TILING_W
);
510 CHOOSE(ISL_TILING_LINEAR
);
514 /* No tiling mode accomodates the inputs. */
519 isl_choose_msaa_layout(const struct isl_device
*dev
,
520 const struct isl_surf_init_info
*info
,
521 enum isl_tiling tiling
,
522 enum isl_msaa_layout
*msaa_layout
)
524 if (ISL_DEV_GEN(dev
) >= 8) {
525 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
526 } else if (ISL_DEV_GEN(dev
) >= 7) {
527 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
528 } else if (ISL_DEV_GEN(dev
) >= 6) {
529 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
531 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
536 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
538 assert(isl_is_pow2(samples
));
540 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
543 * If the surface is multisampled and it is a depth or stencil surface
544 * or Multisampled Surface StorageFormat in SURFACE_STATE is
545 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
548 return (struct isl_extent2d
) {
549 .width
= 1 << ((ffs(samples
) - 0) / 2),
550 .height
= 1 << ((ffs(samples
) - 1) / 2),
555 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
556 uint32_t *width
, uint32_t *height
)
558 const struct isl_extent2d px_size_sa
=
559 isl_get_interleaved_msaa_px_size_sa(samples
);
562 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
564 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
567 static enum isl_array_pitch_span
568 isl_choose_array_pitch_span(const struct isl_device
*dev
,
569 const struct isl_surf_init_info
*restrict info
,
570 enum isl_dim_layout dim_layout
,
571 const struct isl_extent4d
*phys_level0_sa
)
573 switch (dim_layout
) {
574 case ISL_DIM_LAYOUT_GEN9_1D
:
575 case ISL_DIM_LAYOUT_GEN4_2D
:
576 if (ISL_DEV_GEN(dev
) >= 8) {
577 /* QPitch becomes programmable in Broadwell. So choose the
578 * most compact QPitch possible in order to conserve memory.
580 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
581 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
583 * - Software must ensure that this field is set to a value
584 * sufficiently large such that the array slices in the surface
585 * do not overlap. Refer to the Memory Data Formats section for
586 * information on how surfaces are stored in memory.
588 * - This field specifies the distance in rows between array
589 * slices. It is used only in the following cases:
591 * - Surface Array is enabled OR
592 * - Number of Mulitsamples is not NUMSAMPLES_1 and
593 * Multisampled Surface Storage Format set to MSFMT_MSS OR
594 * - Surface Type is SURFTYPE_CUBE
596 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
597 } else if (ISL_DEV_GEN(dev
) >= 7) {
598 /* Note that Ivybridge introduces
599 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
600 * driver more control over the QPitch.
603 if (phys_level0_sa
->array_len
== 1) {
604 /* The hardware will never use the QPitch. So choose the most
605 * compact QPitch possible in order to conserve memory.
607 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
610 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
611 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
612 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
613 * Section 6.18.4.7: Surface Arrays (p112):
615 * If Surface Array Spacing is set to ARYSPC_FULL (note that
616 * the depth buffer and stencil buffer have an implied value of
619 return ISL_ARRAY_PITCH_SPAN_FULL
;
622 if (info
->levels
== 1) {
623 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
626 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
629 return ISL_ARRAY_PITCH_SPAN_FULL
;
630 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
631 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
632 isl_surf_usage_is_stencil(info
->usage
)) {
633 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
634 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
636 * The separate stencil buffer does not support mip mapping, thus
637 * the storage for LODs other than LOD 0 is not needed.
639 assert(info
->levels
== 1);
640 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
642 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
643 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
644 isl_surf_usage_is_stencil(info
->usage
)) {
645 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
646 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
648 * The separate stencil buffer does not support mip mapping,
649 * thus the storage for LODs other than LOD 0 is not needed.
651 assert(info
->levels
== 1);
652 assert(phys_level0_sa
->array_len
== 1);
653 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
656 if (phys_level0_sa
->array_len
== 1) {
657 /* The hardware will never use the QPitch. So choose the most
658 * compact QPitch possible in order to conserve memory.
660 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
663 return ISL_ARRAY_PITCH_SPAN_FULL
;
666 case ISL_DIM_LAYOUT_GEN4_3D
:
667 /* The hardware will never use the QPitch. So choose the most
668 * compact QPitch possible in order to conserve memory.
670 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
672 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
673 /* Each array image in the gen6 stencil of HiZ surface is compact in the
674 * sense that every LOD is a compact array of the same size as LOD0.
676 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
679 unreachable("bad isl_dim_layout");
680 return ISL_ARRAY_PITCH_SPAN_FULL
;
684 isl_choose_image_alignment_el(const struct isl_device
*dev
,
685 const struct isl_surf_init_info
*restrict info
,
686 enum isl_tiling tiling
,
687 enum isl_dim_layout dim_layout
,
688 enum isl_msaa_layout msaa_layout
,
689 struct isl_extent3d
*image_align_el
)
691 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
692 if (fmtl
->txc
== ISL_TXC_MCS
) {
693 assert(tiling
== ISL_TILING_Y0
);
696 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
698 * Height, width, and layout of MCS buffer in this case must match with
699 * Render Target height, width, and layout. MCS buffer is tiledY.
701 * To avoid wasting memory, choose the smallest alignment possible:
702 * HALIGN_4 and VALIGN_4.
704 *image_align_el
= isl_extent3d(4, 4, 1);
706 } else if (info
->format
== ISL_FORMAT_HIZ
) {
707 assert(ISL_DEV_GEN(dev
) >= 6);
708 if (ISL_DEV_GEN(dev
) == 6) {
709 /* HiZ surfaces on Sandy Bridge are packed tightly. */
710 *image_align_el
= isl_extent3d(1, 1, 1);
711 } else if (ISL_DEV_GEN(dev
) < 12) {
712 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
713 * primary surface which works out to 2x2 HiZ elments.
715 *image_align_el
= isl_extent3d(2, 2, 1);
717 /* On gen12+, HiZ surfaces are always aligned to 16x16 pixels in the
718 * primary surface which works out to 2x4 HiZ elments.
721 *image_align_el
= isl_extent3d(2, 4, 1);
726 if (ISL_DEV_GEN(dev
) >= 12) {
727 isl_gen12_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
728 msaa_layout
, image_align_el
);
729 } else if (ISL_DEV_GEN(dev
) >= 9) {
730 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
731 msaa_layout
, image_align_el
);
732 } else if (ISL_DEV_GEN(dev
) >= 8) {
733 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
734 msaa_layout
, image_align_el
);
735 } else if (ISL_DEV_GEN(dev
) >= 7) {
736 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
737 msaa_layout
, image_align_el
);
738 } else if (ISL_DEV_GEN(dev
) >= 6) {
739 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
740 msaa_layout
, image_align_el
);
742 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
743 msaa_layout
, image_align_el
);
747 static enum isl_dim_layout
748 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
749 enum isl_surf_dim logical_dim
,
750 enum isl_tiling tiling
,
751 isl_surf_usage_flags_t usage
)
753 /* Sandy bridge needs a special layout for HiZ and stencil. */
754 if (ISL_DEV_GEN(dev
) == 6 &&
755 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
756 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
758 if (ISL_DEV_GEN(dev
) >= 9) {
759 switch (logical_dim
) {
760 case ISL_SURF_DIM_1D
:
761 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
763 * One-dimensional surfaces use a tiling mode of linear.
764 * Technically, they are not tiled resources, but the Tiled
765 * Resource Mode field in RENDER_SURFACE_STATE is still used to
766 * indicate the alignment requirements for this linear surface
767 * (See 1D Alignment requirements for how 4K and 64KB Tiled
768 * Resource Modes impact alignment). Alternatively, a 1D surface
769 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
772 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
773 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
775 if (tiling
== ISL_TILING_LINEAR
)
776 return ISL_DIM_LAYOUT_GEN9_1D
;
778 return ISL_DIM_LAYOUT_GEN4_2D
;
779 case ISL_SURF_DIM_2D
:
780 case ISL_SURF_DIM_3D
:
781 return ISL_DIM_LAYOUT_GEN4_2D
;
784 switch (logical_dim
) {
785 case ISL_SURF_DIM_1D
:
786 case ISL_SURF_DIM_2D
:
787 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
789 * The cube face textures are stored in the same way as 3D surfaces
790 * are stored (see section 6.17.5 for details). For cube surfaces,
791 * however, the depth is equal to the number of faces (always 6) and
792 * is not reduced for each MIP.
794 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
795 return ISL_DIM_LAYOUT_GEN4_3D
;
797 return ISL_DIM_LAYOUT_GEN4_2D
;
798 case ISL_SURF_DIM_3D
:
799 return ISL_DIM_LAYOUT_GEN4_3D
;
803 unreachable("bad isl_surf_dim");
804 return ISL_DIM_LAYOUT_GEN4_2D
;
808 * Calculate the physical extent of the surface's first level, in units of
812 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
813 const struct isl_surf_init_info
*restrict info
,
814 enum isl_dim_layout dim_layout
,
815 enum isl_tiling tiling
,
816 enum isl_msaa_layout msaa_layout
,
817 struct isl_extent4d
*phys_level0_sa
)
819 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
821 if (isl_format_is_yuv(info
->format
))
822 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
825 case ISL_SURF_DIM_1D
:
826 assert(info
->height
== 1);
827 assert(info
->depth
== 1);
828 assert(info
->samples
== 1);
830 switch (dim_layout
) {
831 case ISL_DIM_LAYOUT_GEN4_3D
:
832 unreachable("bad isl_dim_layout");
834 case ISL_DIM_LAYOUT_GEN9_1D
:
835 case ISL_DIM_LAYOUT_GEN4_2D
:
836 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
837 *phys_level0_sa
= (struct isl_extent4d
) {
841 .a
= info
->array_len
,
847 case ISL_SURF_DIM_2D
:
848 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
849 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
851 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
852 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
854 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
855 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
857 switch (msaa_layout
) {
858 case ISL_MSAA_LAYOUT_NONE
:
859 assert(info
->depth
== 1);
860 assert(info
->samples
== 1);
862 *phys_level0_sa
= (struct isl_extent4d
) {
866 .a
= info
->array_len
,
870 case ISL_MSAA_LAYOUT_ARRAY
:
871 assert(info
->depth
== 1);
872 assert(info
->levels
== 1);
873 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
874 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
876 *phys_level0_sa
= (struct isl_extent4d
) {
880 .a
= info
->array_len
* info
->samples
,
884 case ISL_MSAA_LAYOUT_INTERLEAVED
:
885 assert(info
->depth
== 1);
886 assert(info
->levels
== 1);
887 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
889 *phys_level0_sa
= (struct isl_extent4d
) {
893 .a
= info
->array_len
,
896 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
903 case ISL_SURF_DIM_3D
:
904 assert(info
->array_len
== 1);
905 assert(info
->samples
== 1);
908 isl_finishme("%s:%s: compression block with depth > 1",
912 switch (dim_layout
) {
913 case ISL_DIM_LAYOUT_GEN9_1D
:
914 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
915 unreachable("bad isl_dim_layout");
917 case ISL_DIM_LAYOUT_GEN4_2D
:
918 assert(ISL_DEV_GEN(dev
) >= 9);
920 *phys_level0_sa
= (struct isl_extent4d
) {
928 case ISL_DIM_LAYOUT_GEN4_3D
:
929 assert(ISL_DEV_GEN(dev
) < 9);
930 *phys_level0_sa
= (struct isl_extent4d
) {
943 * Calculate the pitch between physical array slices, in units of rows of
947 isl_calc_array_pitch_el_rows_gen4_2d(
948 const struct isl_device
*dev
,
949 const struct isl_surf_init_info
*restrict info
,
950 const struct isl_tile_info
*tile_info
,
951 const struct isl_extent3d
*image_align_sa
,
952 const struct isl_extent4d
*phys_level0_sa
,
953 enum isl_array_pitch_span array_pitch_span
,
954 const struct isl_extent2d
*phys_slice0_sa
)
956 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
957 uint32_t pitch_sa_rows
= 0;
959 switch (array_pitch_span
) {
960 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
961 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
963 case ISL_ARRAY_PITCH_SPAN_FULL
: {
964 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
965 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
966 * Surfaces >> Surface Arrays.
968 uint32_t H0_sa
= phys_level0_sa
->h
;
969 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
971 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
972 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
975 if (ISL_DEV_GEN(dev
) >= 7) {
976 /* The QPitch equation changed slightly in Ivybridge. */
982 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
984 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
985 (info
->height
% 4 == 1)) {
986 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
987 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
989 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
990 * the value calculated in the equation above , for every
991 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
993 * XXX(chadv): Is the errata natural corollary of the physical
994 * layout of interleaved samples?
999 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
1004 assert(pitch_sa_rows
% fmtl
->bh
== 0);
1005 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
1007 if (ISL_DEV_GEN(dev
) >= 9 && ISL_DEV_GEN(dev
) <= 11 &&
1008 fmtl
->txc
== ISL_TXC_CCS
) {
1010 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
1012 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
1013 * layout with these alignments in the RT space: Horizontal
1014 * Alignment = 128 and Vertical Alignment = 64."
1016 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
1018 * "For non-multisampled render target's CCS auxiliary surface,
1019 * QPitch must be computed with Horizontal Alignment = 128 and
1020 * Surface Vertical Alignment = 256. These alignments are only for
1021 * CCS buffer and not for associated render target."
1023 * The first restriction is already handled by isl_choose_image_alignment_el
1024 * but the second restriction, which is an extension of the first, only
1025 * applies to qpitch and must be applied here.
1027 * The second restriction disappears on Gen12.
1029 assert(fmtl
->bh
== 4);
1030 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
1033 if (ISL_DEV_GEN(dev
) >= 9 &&
1034 info
->dim
== ISL_SURF_DIM_3D
&&
1035 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
1036 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
1038 * Tile Mode != Linear: This field must be set to an integer multiple
1039 * of the tile height
1041 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
1044 return pitch_el_rows
;
1048 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1049 * ISL_DIM_LAYOUT_GEN4_2D.
1052 isl_calc_phys_slice0_extent_sa_gen4_2d(
1053 const struct isl_device
*dev
,
1054 const struct isl_surf_init_info
*restrict info
,
1055 enum isl_msaa_layout msaa_layout
,
1056 const struct isl_extent3d
*image_align_sa
,
1057 const struct isl_extent4d
*phys_level0_sa
,
1058 struct isl_extent2d
*phys_slice0_sa
)
1060 assert(phys_level0_sa
->depth
== 1);
1062 if (info
->levels
== 1) {
1063 /* Do not pad the surface to the image alignment.
1065 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
1066 * cycles on the below mipmap layout caluclations. Reducing the
1067 * alignment here is safe because we later align the row pitch and array
1068 * pitch to the tile boundary. It is safe even for
1069 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
1070 * to accomodate the interleaved samples.
1072 * For linear surfaces, reducing the alignment here permits us to later
1073 * choose an arbitrary, non-aligned row pitch. If the surface backs
1074 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
1075 * VkBufferImageCopy::bufferRowLength.
1077 *phys_slice0_sa
= (struct isl_extent2d
) {
1078 .w
= phys_level0_sa
->w
,
1079 .h
= phys_level0_sa
->h
,
1084 uint32_t slice_top_w
= 0;
1085 uint32_t slice_bottom_w
= 0;
1086 uint32_t slice_left_h
= 0;
1087 uint32_t slice_right_h
= 0;
1089 uint32_t W0
= phys_level0_sa
->w
;
1090 uint32_t H0
= phys_level0_sa
->h
;
1092 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1093 uint32_t W
= isl_minify(W0
, l
);
1094 uint32_t H
= isl_minify(H0
, l
);
1096 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1097 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1103 } else if (l
== 1) {
1106 } else if (l
== 2) {
1107 slice_bottom_w
+= w
;
1114 *phys_slice0_sa
= (struct isl_extent2d
) {
1115 .w
= MAX(slice_top_w
, slice_bottom_w
),
1116 .h
= MAX(slice_left_h
, slice_right_h
),
1121 isl_calc_phys_total_extent_el_gen4_2d(
1122 const struct isl_device
*dev
,
1123 const struct isl_surf_init_info
*restrict info
,
1124 const struct isl_tile_info
*tile_info
,
1125 enum isl_msaa_layout msaa_layout
,
1126 const struct isl_extent3d
*image_align_sa
,
1127 const struct isl_extent4d
*phys_level0_sa
,
1128 enum isl_array_pitch_span array_pitch_span
,
1129 uint32_t *array_pitch_el_rows
,
1130 struct isl_extent2d
*total_extent_el
)
1132 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1134 struct isl_extent2d phys_slice0_sa
;
1135 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1136 image_align_sa
, phys_level0_sa
,
1138 *array_pitch_el_rows
=
1139 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1140 image_align_sa
, phys_level0_sa
,
1143 *total_extent_el
= (struct isl_extent2d
) {
1144 .w
= isl_align_div_npot(phys_slice0_sa
.w
, fmtl
->bw
),
1145 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1146 isl_align_div_npot(phys_slice0_sa
.h
, fmtl
->bh
),
1151 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1152 * ISL_DIM_LAYOUT_GEN4_3D.
1155 isl_calc_phys_total_extent_el_gen4_3d(
1156 const struct isl_device
*dev
,
1157 const struct isl_surf_init_info
*restrict info
,
1158 const struct isl_extent3d
*image_align_sa
,
1159 const struct isl_extent4d
*phys_level0_sa
,
1160 uint32_t *array_pitch_el_rows
,
1161 struct isl_extent2d
*phys_total_el
)
1163 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1165 assert(info
->samples
== 1);
1167 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1168 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1170 * The cube face textures are stored in the same way as 3D surfaces
1171 * are stored (see section 6.17.5 for details). For cube surfaces,
1172 * however, the depth is equal to the number of faces (always 6) and
1173 * is not reduced for each MIP.
1175 assert(ISL_DEV_GEN(dev
) == 4);
1176 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1177 assert(phys_level0_sa
->array_len
== 6);
1179 assert(phys_level0_sa
->array_len
== 1);
1182 uint32_t total_w
= 0;
1183 uint32_t total_h
= 0;
1185 uint32_t W0
= phys_level0_sa
->w
;
1186 uint32_t H0
= phys_level0_sa
->h
;
1187 uint32_t D0
= phys_level0_sa
->d
;
1188 uint32_t A0
= phys_level0_sa
->a
;
1190 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1191 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1192 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1193 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1195 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1196 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1198 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1199 total_h
+= level_h
* max_layers_vert
;
1202 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1203 * different number of horizontal and vertical layers. We have to set it
1204 * to something, so at least make it true for LOD0.
1206 *array_pitch_el_rows
=
1207 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1208 *phys_total_el
= (struct isl_extent2d
) {
1209 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1210 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1215 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1216 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1219 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1220 const struct isl_device
*dev
,
1221 const struct isl_surf_init_info
*restrict info
,
1222 const struct isl_tile_info
*tile_info
,
1223 const struct isl_extent3d
*image_align_sa
,
1224 const struct isl_extent4d
*phys_level0_sa
,
1225 uint32_t *array_pitch_el_rows
,
1226 struct isl_extent2d
*phys_total_el
)
1228 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1230 const struct isl_extent2d tile_extent_sa
= {
1231 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1232 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1234 /* Tile size is a multiple of image alignment */
1235 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1236 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1238 const uint32_t W0
= phys_level0_sa
->w
;
1239 const uint32_t H0
= phys_level0_sa
->h
;
1241 /* Each image has the same height as LOD0 because the hardware thinks
1242 * everything is LOD0
1244 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1246 uint32_t total_top_w
= 0;
1247 uint32_t total_bottom_w
= 0;
1248 uint32_t total_h
= 0;
1250 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1251 const uint32_t W
= isl_minify(W0
, l
);
1253 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1254 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1259 } else if (l
== 1) {
1263 total_bottom_w
+= w
;
1267 *array_pitch_el_rows
=
1268 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1269 *phys_total_el
= (struct isl_extent2d
) {
1270 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1271 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1276 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1277 * ISL_DIM_LAYOUT_GEN9_1D.
1280 isl_calc_phys_total_extent_el_gen9_1d(
1281 const struct isl_device
*dev
,
1282 const struct isl_surf_init_info
*restrict info
,
1283 const struct isl_extent3d
*image_align_sa
,
1284 const struct isl_extent4d
*phys_level0_sa
,
1285 uint32_t *array_pitch_el_rows
,
1286 struct isl_extent2d
*phys_total_el
)
1288 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1290 assert(phys_level0_sa
->height
== 1);
1291 assert(phys_level0_sa
->depth
== 1);
1292 assert(info
->samples
== 1);
1293 assert(image_align_sa
->w
>= fmtl
->bw
);
1295 uint32_t slice_w
= 0;
1296 const uint32_t W0
= phys_level0_sa
->w
;
1298 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1299 uint32_t W
= isl_minify(W0
, l
);
1300 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1305 *array_pitch_el_rows
= 1;
1306 *phys_total_el
= (struct isl_extent2d
) {
1307 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1308 .h
= phys_level0_sa
->array_len
,
1313 * Calculate the two-dimensional total physical extent of the surface, in
1314 * units of surface elements.
1317 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1318 const struct isl_surf_init_info
*restrict info
,
1319 const struct isl_tile_info
*tile_info
,
1320 enum isl_dim_layout dim_layout
,
1321 enum isl_msaa_layout msaa_layout
,
1322 const struct isl_extent3d
*image_align_sa
,
1323 const struct isl_extent4d
*phys_level0_sa
,
1324 enum isl_array_pitch_span array_pitch_span
,
1325 uint32_t *array_pitch_el_rows
,
1326 struct isl_extent2d
*total_extent_el
)
1328 switch (dim_layout
) {
1329 case ISL_DIM_LAYOUT_GEN9_1D
:
1330 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1331 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1332 image_align_sa
, phys_level0_sa
,
1333 array_pitch_el_rows
,
1336 case ISL_DIM_LAYOUT_GEN4_2D
:
1337 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1338 image_align_sa
, phys_level0_sa
,
1340 array_pitch_el_rows
,
1343 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1344 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1345 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1348 array_pitch_el_rows
,
1351 case ISL_DIM_LAYOUT_GEN4_3D
:
1352 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1353 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1354 image_align_sa
, phys_level0_sa
,
1355 array_pitch_el_rows
,
1360 unreachable("invalid value for dim_layout");
1364 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1365 const struct isl_tile_info
*tile_info
)
1367 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1368 return tile_info
->phys_extent_B
.width
;
1370 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1371 * RENDER_SURFACE_STATE Surface Pitch (p349):
1373 * - For linear render target surfaces and surfaces accessed with the
1374 * typed data port messages, the pitch must be a multiple of the
1375 * element size for non-YUV surface formats. Pitch must be
1376 * a multiple of 2 * element size for YUV surface formats.
1378 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1379 * ignore because isl doesn't do buffers.]
1381 * - For other linear surfaces, the pitch can be any multiple of
1384 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1385 const uint32_t bs
= fmtl
->bpb
/ 8;
1387 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1388 if (isl_format_is_yuv(surf_info
->format
)) {
1399 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1400 const struct isl_surf_init_info
*info
,
1401 const struct isl_extent2d
*phys_total_el
,
1402 uint32_t alignment_B
)
1404 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1405 const uint32_t bs
= fmtl
->bpb
/ 8;
1407 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1411 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1412 const struct isl_surf_init_info
*surf_info
,
1413 const struct isl_tile_info
*tile_info
,
1414 const struct isl_extent2d
*phys_total_el
,
1415 uint32_t alignment_B
)
1417 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1419 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1421 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1422 const uint32_t total_w_tl
=
1423 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1424 tile_info
->logical_extent_el
.width
);
1426 assert(alignment_B
== tile_info
->phys_extent_B
.width
);
1427 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1431 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1432 const struct isl_surf_init_info
*surf_info
,
1433 const struct isl_tile_info
*tile_info
,
1434 const struct isl_extent2d
*phys_total_el
,
1435 uint32_t alignment_B
)
1437 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1438 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1441 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1442 phys_total_el
, alignment_B
);
1447 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1448 * size is `bits` bits?
1450 * Hardware pitch fields are offset by 1. For example, if the size of
1451 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1452 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1453 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1456 pitch_in_range(uint32_t n
, uint32_t bits
)
1459 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1463 isl_calc_row_pitch(const struct isl_device
*dev
,
1464 const struct isl_surf_init_info
*surf_info
,
1465 const struct isl_tile_info
*tile_info
,
1466 enum isl_dim_layout dim_layout
,
1467 const struct isl_extent2d
*phys_total_el
,
1468 uint32_t *out_row_pitch_B
)
1470 uint32_t alignment_B
=
1471 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1473 const uint32_t min_row_pitch_B
=
1474 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1477 if (surf_info
->row_pitch_B
!= 0) {
1478 if (surf_info
->row_pitch_B
< min_row_pitch_B
)
1481 if (surf_info
->row_pitch_B
% alignment_B
!= 0)
1485 const uint32_t row_pitch_B
=
1486 surf_info
->row_pitch_B
!= 0 ?
1487 surf_info
->row_pitch_B
:
1488 /* According to BSpec: 44930, Gen12's CCS-compressed surface pitches
1489 * must be 512B-aligned.
1491 ISL_DEV_GEN(dev
) >= 12 &&
1492 isl_format_supports_ccs_e(dev
->info
, surf_info
->format
) ?
1493 isl_align(min_row_pitch_B
, 512) :
1497 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1499 if (row_pitch_B
== 0)
1502 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1503 /* SurfacePitch is ignored for this layout. */
1507 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1508 ISL_SURF_USAGE_TEXTURE_BIT
|
1509 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1510 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1513 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1514 ISL_SURF_USAGE_MCS_BIT
)) &&
1515 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1518 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1519 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1522 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1523 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1526 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1527 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1528 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1530 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1531 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1535 *out_row_pitch_B
= row_pitch_B
;
1540 isl_surf_init_s(const struct isl_device
*dev
,
1541 struct isl_surf
*surf
,
1542 const struct isl_surf_init_info
*restrict info
)
1544 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1546 const struct isl_extent4d logical_level0_px
= {
1550 .a
= info
->array_len
,
1553 enum isl_tiling tiling
;
1554 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1557 struct isl_tile_info tile_info
;
1558 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1560 const enum isl_dim_layout dim_layout
=
1561 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1563 enum isl_msaa_layout msaa_layout
;
1564 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1567 struct isl_extent3d image_align_el
;
1568 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1571 struct isl_extent3d image_align_sa
=
1572 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1574 struct isl_extent4d phys_level0_sa
;
1575 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1578 enum isl_array_pitch_span array_pitch_span
=
1579 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1581 uint32_t array_pitch_el_rows
;
1582 struct isl_extent2d phys_total_el
;
1583 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1584 dim_layout
, msaa_layout
,
1585 &image_align_sa
, &phys_level0_sa
,
1586 array_pitch_span
, &array_pitch_el_rows
,
1589 uint32_t row_pitch_B
;
1590 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1591 &phys_total_el
, &row_pitch_B
))
1594 uint32_t base_alignment_B
;
1596 if (tiling
== ISL_TILING_LINEAR
) {
1597 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1599 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1601 * "The Base Address for linear render target surfaces and surfaces
1602 * accessed with the typed surface read/write data port messages must
1603 * be element-size aligned, for non-YUV surface formats, or a
1604 * multiple of 2 element-sizes for YUV surface formats. Other linear
1605 * surfaces have no alignment requirements (byte alignment is
1608 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1609 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1610 if (isl_format_is_yuv(info
->format
)) {
1611 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1613 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1616 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1618 /* From the Skylake PRM Vol 2c, PLANE_STRIDE::Stride:
1620 * "For Linear memory, this field specifies the stride in chunks of
1621 * 64 bytes (1 cache line)."
1623 if (isl_surf_usage_is_display(info
->usage
))
1624 base_alignment_B
= MAX(base_alignment_B
, 64);
1626 const uint32_t total_h_tl
=
1627 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1629 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1631 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1632 tile_info
.phys_extent_B
.height
;
1633 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1634 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1636 /* The diagram in the Bspec section Memory Compression - Gen12, shows
1637 * that the CCS is indexed in 256B chunks. However, the
1638 * PLANE_AUX_DIST::Auxiliary Surface Distance field is in units of 4K
1639 * pages. We currently don't assign the usage field like we do for main
1640 * surfaces, so just use 4K for now.
1642 if (tiling
== ISL_TILING_GEN12_CCS
)
1643 base_alignment_B
= MAX(base_alignment_B
, 4096);
1646 if (ISL_DEV_GEN(dev
) >= 12) {
1647 base_alignment_B
= MAX(base_alignment_B
, 64 * 1024);
1650 if (ISL_DEV_GEN(dev
) < 9) {
1651 /* From the Broadwell PRM Vol 5, Surface Layout:
1653 * "In addition to restrictions on maximum height, width, and depth,
1654 * surfaces are also restricted to a maximum size in bytes. This
1655 * maximum is 2 GB for all products and all surface types."
1657 * This comment is applicable to all Pre-gen9 platforms.
1659 if (size_B
> (uint64_t) 1 << 31)
1661 } else if (ISL_DEV_GEN(dev
) < 11) {
1662 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1663 * "In addition to restrictions on maximum height, width, and depth,
1664 * surfaces are also restricted to a maximum size of 2^38 bytes.
1665 * All pixels within the surface must be contained within 2^38 bytes
1666 * of the base address."
1668 if (size_B
> (uint64_t) 1 << 38)
1671 /* gen11+ platforms raised this limit to 2^44 bytes. */
1672 if (size_B
> (uint64_t) 1 << 44)
1676 *surf
= (struct isl_surf
) {
1678 .dim_layout
= dim_layout
,
1679 .msaa_layout
= msaa_layout
,
1681 .format
= info
->format
,
1683 .levels
= info
->levels
,
1684 .samples
= info
->samples
,
1686 .image_alignment_el
= image_align_el
,
1687 .logical_level0_px
= logical_level0_px
,
1688 .phys_level0_sa
= phys_level0_sa
,
1691 .alignment_B
= base_alignment_B
,
1692 .row_pitch_B
= row_pitch_B
,
1693 .array_pitch_el_rows
= array_pitch_el_rows
,
1694 .array_pitch_span
= array_pitch_span
,
1696 .usage
= info
->usage
,
1703 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1704 struct isl_tile_info
*tile_info
)
1706 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1707 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1711 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1712 const struct isl_surf
*surf
,
1713 struct isl_surf
*hiz_surf
)
1715 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1717 if (!isl_surf_usage_is_depth(surf
->usage
))
1720 /* HiZ only works with Y-tiled depth buffers */
1721 if (!isl_tiling_is_any_y(surf
->tiling
))
1724 /* On SNB+, compressed depth buffers cannot be interleaved with stencil. */
1725 switch (surf
->format
) {
1726 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1727 if (isl_surf_usage_is_depth_and_stencil(surf
->usage
)) {
1728 assert(ISL_DEV_GEN(dev
) == 5);
1729 unreachable("This should work, but is untested");
1732 case ISL_FORMAT_R16_UNORM
:
1733 case ISL_FORMAT_R32_FLOAT
:
1735 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1736 if (ISL_DEV_GEN(dev
) == 5) {
1737 assert(isl_surf_usage_is_depth_and_stencil(surf
->usage
));
1738 unreachable("This should work, but is untested");
1745 /* Multisampled depth is always interleaved */
1746 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1747 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1749 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1751 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1752 * Target View Extent, and Depth Coordinate Offset X/Y of the
1753 * hierarchical depth buffer are inherited from the depth buffer. The
1754 * height and width of the hierarchical depth buffer that must be
1755 * allocated are computed by the following formulas, where HZ is the
1756 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1757 * Z_Width, and Z_Depth values given in these formulas are those present
1758 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1760 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1761 * being applied to the table below if Number of Multisamples is set to
1762 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1763 * Z_Width must be multiplied by 4 before being applied to the table
1764 * below if Number of Multisamples is set to NUMSAMPLES_8."
1766 * In the Sky Lake PRM, the second paragraph is replaced with this:
1768 * "The Z_Height and Z_Width values must equal those present in
1769 * 3DSTATE_DEPTH_BUFFER incremented by one."
1771 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1772 * block corresponds to a region of 8x4 samples in the primary depth
1773 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1774 * a region of 8x4 pixels in the primary depth surface regardless of the
1775 * number of samples. The dimensions of a HiZ block in both pixels and
1776 * samples are given in the table below:
1778 * | SNB - BDW | SKL+
1779 * ------+-----------+-------------
1780 * 1x | 8 x 4 sa | 8 x 4 sa
1781 * MSAA | 8 x 4 px | 8 x 4 px
1782 * ------+-----------+-------------
1783 * 2x | 8 x 4 sa | 16 x 4 sa
1784 * MSAA | 4 x 4 px | 8 x 4 px
1785 * ------+-----------+-------------
1786 * 4x | 8 x 4 sa | 16 x 8 sa
1787 * MSAA | 4 x 2 px | 8 x 4 px
1788 * ------+-----------+-------------
1789 * 8x | 8 x 4 sa | 32 x 8 sa
1790 * MSAA | 2 x 2 px | 8 x 4 px
1791 * ------+-----------+-------------
1792 * 16x | N/A | 32 x 16 sa
1793 * MSAA | N/A | 8 x 4 px
1794 * ------+-----------+-------------
1796 * There are a number of different ways that this discrepency could be
1797 * handled. The way we have chosen is to simply make MSAA HiZ have the
1798 * same number of samples as the parent surface pre-Sky Lake and always be
1799 * single-sampled on Sky Lake and above. Since the block sizes of
1800 * compressed formats are given in samples, this neatly handles everything
1801 * without the need for additional HiZ formats with different block sizes
1804 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1806 return isl_surf_init(dev
, hiz_surf
,
1808 .format
= ISL_FORMAT_HIZ
,
1809 .width
= surf
->logical_level0_px
.width
,
1810 .height
= surf
->logical_level0_px
.height
,
1811 .depth
= surf
->logical_level0_px
.depth
,
1812 .levels
= surf
->levels
,
1813 .array_len
= surf
->logical_level0_px
.array_len
,
1815 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1816 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1820 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1821 const struct isl_surf
*surf
,
1822 struct isl_surf
*mcs_surf
)
1824 /* It must be multisampled with an array layout */
1825 if (surf
->msaa_layout
!= ISL_MSAA_LAYOUT_ARRAY
)
1828 if (mcs_surf
->size_B
> 0)
1831 /* The following are true of all multisampled surfaces */
1832 assert(surf
->samples
> 1);
1833 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1834 assert(surf
->levels
== 1);
1835 assert(surf
->logical_level0_px
.depth
== 1);
1837 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
1839 * This field must be set to 0 for all SINT MSRTs when all RT channels
1842 * In practice this means that we have to disable MCS for all signed
1843 * integer MSAA buffers. The alternative, to disable MCS only when one
1844 * of the render target channels is disabled, is impractical because it
1845 * would require converting between CMS and UMS MSAA layouts on the fly,
1846 * which is expensive.
1848 if (ISL_DEV_GEN(dev
) == 7 && isl_format_has_sint_channel(surf
->format
))
1851 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1852 * bits which means the maximum pitch of a compression surface is 512
1853 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1854 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1855 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1856 * and 8x, we have enough room for the full 16k supported by the hardware.
1858 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1861 enum isl_format mcs_format
;
1862 switch (surf
->samples
) {
1863 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1864 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1865 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1866 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1868 unreachable("Invalid sample count");
1871 return isl_surf_init(dev
, mcs_surf
,
1872 .dim
= ISL_SURF_DIM_2D
,
1873 .format
= mcs_format
,
1874 .width
= surf
->logical_level0_px
.width
,
1875 .height
= surf
->logical_level0_px
.height
,
1878 .array_len
= surf
->logical_level0_px
.array_len
,
1879 .samples
= 1, /* MCS surfaces are really single-sampled */
1880 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1881 .tiling_flags
= ISL_TILING_Y0_BIT
);
1885 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1886 const struct isl_surf
*surf
,
1887 struct isl_surf
*aux_surf
,
1888 struct isl_surf
*extra_aux_surf
,
1889 uint32_t row_pitch_B
)
1893 /* An uninitialized surface is needed to get a CCS surface. */
1894 if (aux_surf
->size_B
> 0 &&
1895 (extra_aux_surf
== NULL
|| extra_aux_surf
->size_B
> 0)) {
1899 /* A surface can't have two CCS surfaces. */
1900 if (aux_surf
->usage
& ISL_SURF_USAGE_CCS_BIT
)
1903 if (ISL_DEV_GEN(dev
) < 12 && surf
->samples
> 1)
1906 /* CCS support does not exist prior to Gen7 */
1907 if (ISL_DEV_GEN(dev
) <= 6)
1910 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1913 /* Allow CCS for single-sampled stencil buffers Gen12+. */
1914 if (isl_surf_usage_is_stencil(surf
->usage
) &&
1915 (ISL_DEV_GEN(dev
) < 12 || surf
->samples
> 1))
1918 /* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if it
1919 * has HiZ. If not for GEN:BUG:1406512483 "deprecate compression enable
1920 * states", D16 would be supported. Supporting D16 requires being able to
1921 * specify that the control surface is present and simultaneously disabling
1922 * compression. The above bug makes it so that it's not possible to specify
1923 * this configuration.
1925 if (isl_surf_usage_is_depth(surf
->usage
) && (aux_surf
->size_B
== 0 ||
1926 ISL_DEV_GEN(dev
) < 12 || surf
->format
== ISL_FORMAT_R16_UNORM
)) {
1930 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1931 * work for 3D textures until gen9 where the layout of 3D textures changes
1932 * to match 2D array textures.
1934 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1937 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1938 * Non-MultiSampler Render Target Restrictions):
1940 * "Support is for non-mip-mapped and non-array surface types only."
1942 * This restriction is lifted on gen8+. Technically, it may be possible to
1943 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1944 * when rendering to the base slice. However, there is no documentation
1945 * tell us what the hardware would do in that case or what it does if you
1946 * walk off the bases slice. (Does it ignore CCS or does it start
1947 * scribbling over random memory?) We play it safe and just follow the
1948 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1950 if (ISL_DEV_GEN(dev
) <= 7 &&
1951 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1954 /* On Gen12, 8BPP surfaces cannot be compressed if any level is not
1955 * 32Bx4row-aligned. For now, just reject the cases where alignment
1958 if (ISL_DEV_GEN(dev
) >= 12 &&
1959 isl_format_get_layout(surf
->format
)->bpb
== 8 && surf
->levels
>= 3) {
1960 isl_finishme("%s:%s: CCS for 8BPP textures with 3+ miplevels is "
1961 "disabled, but support for more levels is possible.",
1962 __FILE__
, __func__
);
1966 /* On Gen12, all CCS-compressed surface pitches must be multiples of 512B.
1968 if (ISL_DEV_GEN(dev
) >= 12 && surf
->row_pitch_B
% 512 != 0)
1971 if (isl_format_is_compressed(surf
->format
))
1974 /* According to GEN:BUG:1406738321, 3D textures need a blit to a new
1975 * surface in order to perform a resolve. For now, just disable CCS.
1977 if (ISL_DEV_GEN(dev
) >= 12 && surf
->dim
== ISL_SURF_DIM_3D
) {
1978 isl_finishme("%s:%s: CCS for 3D textures is disabled, but a workaround"
1979 " is available.", __FILE__
, __func__
);
1983 /* GEN:BUG:1207137018
1985 * TODO: implement following workaround currently covered by the restriction
1986 * above. If following conditions are met:
1988 * - RENDER_SURFACE_STATE.Surface Type == 3D
1989 * - RENDER_SURFACE_STATE.Auxiliary Surface Mode != AUX_NONE
1990 * - RENDER_SURFACE_STATE.Tiled ResourceMode is TYF or TYS
1992 * Set the value of RENDER_SURFACE_STATE.Mip Tail Start LOD to a mip that
1993 * larger than those present in the surface (i.e. 15)
1996 /* TODO: More conditions where it can fail. */
1998 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
1999 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
2001 * - Support is limited to tiled render targets.
2002 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
2003 * 64bpp, and 128bpp.
2005 * From the Skylake documentation, it is made clear that X-tiling is no
2008 * - MCS and Lossless compression is supported for
2009 * TiledY/TileYs/TileYf non-MSRTs only.
2011 enum isl_format ccs_format
;
2012 if (ISL_DEV_GEN(dev
) >= 12) {
2013 /* TODO: Handle the other tiling formats */
2014 if (surf
->tiling
!= ISL_TILING_Y0
)
2017 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2018 case 8: ccs_format
= ISL_FORMAT_GEN12_CCS_8BPP_Y0
; break;
2019 case 16: ccs_format
= ISL_FORMAT_GEN12_CCS_16BPP_Y0
; break;
2020 case 32: ccs_format
= ISL_FORMAT_GEN12_CCS_32BPP_Y0
; break;
2021 case 64: ccs_format
= ISL_FORMAT_GEN12_CCS_64BPP_Y0
; break;
2022 case 128: ccs_format
= ISL_FORMAT_GEN12_CCS_128BPP_Y0
; break;
2026 } else if (ISL_DEV_GEN(dev
) >= 9) {
2027 if (!isl_tiling_is_any_y(surf
->tiling
))
2030 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2031 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
2032 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
2033 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
2037 } else if (surf
->tiling
== ISL_TILING_Y0
) {
2038 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2039 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
2040 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
2041 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
2045 } else if (surf
->tiling
== ISL_TILING_X
) {
2046 switch (isl_format_get_layout(surf
->format
)->bpb
) {
2047 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
2048 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
2049 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
2057 if (ISL_DEV_GEN(dev
) >= 12) {
2058 /* On Gen12, the CCS is a scaled-down version of the main surface. We
2059 * model this as the CCS compressing a 2D-view of the entire surface.
2061 struct isl_surf
*ccs_surf
=
2062 aux_surf
->size_B
> 0 ? extra_aux_surf
: aux_surf
;
2064 isl_surf_init(dev
, ccs_surf
,
2065 .dim
= ISL_SURF_DIM_2D
,
2066 .format
= ccs_format
,
2067 .width
= isl_surf_get_row_pitch_el(surf
),
2068 .height
= surf
->size_B
/ surf
->row_pitch_B
,
2073 .row_pitch_B
= row_pitch_B
,
2074 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2075 .tiling_flags
= ISL_TILING_GEN12_CCS_BIT
);
2076 assert(!ok
|| ccs_surf
->size_B
== surf
->size_B
/ 256);
2079 return isl_surf_init(dev
, aux_surf
,
2081 .format
= ccs_format
,
2082 .width
= surf
->logical_level0_px
.width
,
2083 .height
= surf
->logical_level0_px
.height
,
2084 .depth
= surf
->logical_level0_px
.depth
,
2085 .levels
= surf
->levels
,
2086 .array_len
= surf
->logical_level0_px
.array_len
,
2088 .row_pitch_B
= row_pitch_B
,
2089 .usage
= ISL_SURF_USAGE_CCS_BIT
,
2090 .tiling_flags
= ISL_TILING_CCS_BIT
);
2094 #define isl_genX_call(dev, func, ...) \
2095 switch (ISL_DEV_GEN(dev)) { \
2097 /* G45 surface state is the same as gen5 */ \
2098 if (ISL_DEV_IS_G4X(dev)) { \
2099 isl_gen5_##func(__VA_ARGS__); \
2101 isl_gen4_##func(__VA_ARGS__); \
2105 isl_gen5_##func(__VA_ARGS__); \
2108 isl_gen6_##func(__VA_ARGS__); \
2111 if (ISL_DEV_IS_HASWELL(dev)) { \
2112 isl_gen75_##func(__VA_ARGS__); \
2114 isl_gen7_##func(__VA_ARGS__); \
2118 isl_gen8_##func(__VA_ARGS__); \
2121 isl_gen9_##func(__VA_ARGS__); \
2124 isl_gen10_##func(__VA_ARGS__); \
2127 isl_gen11_##func(__VA_ARGS__); \
2130 isl_gen12_##func(__VA_ARGS__); \
2133 assert(!"Unknown hardware generation"); \
2137 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
2138 const struct isl_surf_fill_state_info
*restrict info
)
2141 isl_surf_usage_flags_t _base_usage
=
2142 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
2143 ISL_SURF_USAGE_TEXTURE_BIT
|
2144 ISL_SURF_USAGE_STORAGE_BIT
);
2145 /* They may only specify one of the above bits at a time */
2146 assert(__builtin_popcount(_base_usage
) == 1);
2147 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
2148 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
2151 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
2152 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2153 info
->surf
->logical_level0_px
.depth
);
2155 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2156 info
->surf
->logical_level0_px
.array_len
);
2159 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
2163 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
2164 const struct isl_buffer_fill_state_info
*restrict info
)
2166 isl_genX_call(dev
, buffer_fill_state_s
, dev
, state
, info
);
2170 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
2171 struct isl_extent3d size
)
2173 isl_genX_call(dev
, null_fill_state
, state
, size
);
2177 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
2178 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
2180 if (info
->depth_surf
&& info
->stencil_surf
) {
2181 if (!dev
->info
->has_hiz_and_separate_stencil
) {
2182 assert(info
->depth_surf
== info
->stencil_surf
);
2183 assert(info
->depth_address
== info
->stencil_address
);
2185 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
2188 if (info
->depth_surf
) {
2189 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
2190 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
2191 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2192 info
->depth_surf
->logical_level0_px
.depth
);
2194 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2195 info
->depth_surf
->logical_level0_px
.array_len
);
2199 if (info
->stencil_surf
) {
2200 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
2201 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
2202 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2203 info
->stencil_surf
->logical_level0_px
.depth
);
2205 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
2206 info
->stencil_surf
->logical_level0_px
.array_len
);
2210 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
2214 * A variant of isl_surf_get_image_offset_sa() specific to
2215 * ISL_DIM_LAYOUT_GEN4_2D.
2218 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
2219 uint32_t level
, uint32_t logical_array_layer
,
2220 uint32_t *x_offset_sa
,
2221 uint32_t *y_offset_sa
)
2223 assert(level
< surf
->levels
);
2224 if (surf
->dim
== ISL_SURF_DIM_3D
)
2225 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
2227 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2229 const struct isl_extent3d image_align_sa
=
2230 isl_surf_get_image_alignment_sa(surf
);
2232 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2233 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2235 const uint32_t phys_layer
= logical_array_layer
*
2236 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
2239 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2241 for (uint32_t l
= 0; l
< level
; ++l
) {
2243 uint32_t W
= isl_minify(W0
, l
);
2244 x
+= isl_align_npot(W
, image_align_sa
.w
);
2246 uint32_t H
= isl_minify(H0
, l
);
2247 y
+= isl_align_npot(H
, image_align_sa
.h
);
2256 * A variant of isl_surf_get_image_offset_sa() specific to
2257 * ISL_DIM_LAYOUT_GEN4_3D.
2260 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
2261 uint32_t level
, uint32_t logical_z_offset_px
,
2262 uint32_t *x_offset_sa
,
2263 uint32_t *y_offset_sa
)
2265 assert(level
< surf
->levels
);
2266 if (surf
->dim
== ISL_SURF_DIM_3D
) {
2267 assert(surf
->phys_level0_sa
.array_len
== 1);
2268 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
2270 assert(surf
->dim
== ISL_SURF_DIM_2D
);
2271 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
2272 assert(surf
->phys_level0_sa
.array_len
== 6);
2273 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2276 const struct isl_extent3d image_align_sa
=
2277 isl_surf_get_image_alignment_sa(surf
);
2279 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2280 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2281 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2282 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2287 for (uint32_t l
= 0; l
< level
; ++l
) {
2288 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2289 const uint32_t level_d
=
2290 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2292 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2294 y
+= level_h
* max_layers_vert
;
2297 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2298 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2299 const uint32_t level_d
=
2300 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2303 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2305 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2306 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2313 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2315 uint32_t logical_array_layer
,
2316 uint32_t *x_offset_sa
,
2317 uint32_t *y_offset_sa
)
2319 assert(level
< surf
->levels
);
2320 assert(surf
->logical_level0_px
.depth
== 1);
2321 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2323 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2325 const struct isl_extent3d image_align_sa
=
2326 isl_surf_get_image_alignment_sa(surf
);
2328 struct isl_tile_info tile_info
;
2329 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2330 const struct isl_extent2d tile_extent_sa
= {
2331 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2332 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2334 /* Tile size is a multiple of image alignment */
2335 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2336 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2338 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2339 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2341 /* Each image has the same height as LOD0 because the hardware thinks
2342 * everything is LOD0
2344 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2346 /* Quick sanity check for consistency */
2347 if (surf
->phys_level0_sa
.array_len
> 1)
2348 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2350 uint32_t x
= 0, y
= 0;
2351 for (uint32_t l
= 0; l
< level
; ++l
) {
2352 const uint32_t W
= isl_minify(W0
, l
);
2354 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2355 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2365 y
+= H
* logical_array_layer
;
2372 * A variant of isl_surf_get_image_offset_sa() specific to
2373 * ISL_DIM_LAYOUT_GEN9_1D.
2376 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2377 uint32_t level
, uint32_t layer
,
2378 uint32_t *x_offset_sa
,
2379 uint32_t *y_offset_sa
)
2381 assert(level
< surf
->levels
);
2382 assert(layer
< surf
->phys_level0_sa
.array_len
);
2383 assert(surf
->phys_level0_sa
.height
== 1);
2384 assert(surf
->phys_level0_sa
.depth
== 1);
2385 assert(surf
->samples
== 1);
2387 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2388 const struct isl_extent3d image_align_sa
=
2389 isl_surf_get_image_alignment_sa(surf
);
2393 for (uint32_t l
= 0; l
< level
; ++l
) {
2394 uint32_t W
= isl_minify(W0
, l
);
2395 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2401 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2405 * Calculate the offset, in units of surface samples, to a subimage in the
2408 * @invariant level < surface levels
2409 * @invariant logical_array_layer < logical array length of surface
2410 * @invariant logical_z_offset_px < logical depth of surface at level
2413 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2415 uint32_t logical_array_layer
,
2416 uint32_t logical_z_offset_px
,
2417 uint32_t *x_offset_sa
,
2418 uint32_t *y_offset_sa
)
2420 assert(level
< surf
->levels
);
2421 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2422 assert(logical_z_offset_px
2423 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2425 switch (surf
->dim_layout
) {
2426 case ISL_DIM_LAYOUT_GEN9_1D
:
2427 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2428 x_offset_sa
, y_offset_sa
);
2430 case ISL_DIM_LAYOUT_GEN4_2D
:
2431 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2432 + logical_z_offset_px
,
2433 x_offset_sa
, y_offset_sa
);
2435 case ISL_DIM_LAYOUT_GEN4_3D
:
2436 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2437 logical_z_offset_px
,
2438 x_offset_sa
, y_offset_sa
);
2440 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2441 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2442 logical_z_offset_px
,
2443 x_offset_sa
, y_offset_sa
);
2447 unreachable("not reached");
2452 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2454 uint32_t logical_array_layer
,
2455 uint32_t logical_z_offset_px
,
2456 uint32_t *x_offset_el
,
2457 uint32_t *y_offset_el
)
2459 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2461 assert(level
< surf
->levels
);
2462 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2463 assert(logical_z_offset_px
2464 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2466 uint32_t x_offset_sa
, y_offset_sa
;
2467 isl_surf_get_image_offset_sa(surf
, level
,
2468 logical_array_layer
,
2469 logical_z_offset_px
,
2473 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2474 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2478 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2480 uint32_t logical_array_layer
,
2481 uint32_t logical_z_offset_px
,
2483 uint32_t *x_offset_sa
,
2484 uint32_t *y_offset_sa
)
2486 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2488 uint32_t total_x_offset_el
, total_y_offset_el
;
2489 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2490 logical_z_offset_px
,
2492 &total_y_offset_el
);
2494 uint32_t x_offset_el
, y_offset_el
;
2495 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2504 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2506 assert(x_offset_el
== 0);
2510 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2512 assert(y_offset_el
== 0);
2517 isl_surf_get_image_surf(const struct isl_device
*dev
,
2518 const struct isl_surf
*surf
,
2520 uint32_t logical_array_layer
,
2521 uint32_t logical_z_offset_px
,
2522 struct isl_surf
*image_surf
,
2524 uint32_t *x_offset_sa
,
2525 uint32_t *y_offset_sa
)
2527 isl_surf_get_image_offset_B_tile_sa(surf
,
2529 logical_array_layer
,
2530 logical_z_offset_px
,
2535 /* Even for cube maps there will be only single face, therefore drop the
2536 * corresponding flag if present.
2538 const isl_surf_usage_flags_t usage
=
2539 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2542 ok
= isl_surf_init(dev
, image_surf
,
2543 .dim
= ISL_SURF_DIM_2D
,
2544 .format
= surf
->format
,
2545 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2546 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2550 .samples
= surf
->samples
,
2551 .row_pitch_B
= surf
->row_pitch_B
,
2553 .tiling_flags
= (1 << surf
->tiling
));
2558 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2560 uint32_t row_pitch_B
,
2561 uint32_t total_x_offset_el
,
2562 uint32_t total_y_offset_el
,
2563 uint32_t *base_address_offset
,
2564 uint32_t *x_offset_el
,
2565 uint32_t *y_offset_el
)
2567 if (tiling
== ISL_TILING_LINEAR
) {
2568 assert(bpb
% 8 == 0);
2569 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2570 total_x_offset_el
* (bpb
/ 8);
2576 struct isl_tile_info tile_info
;
2577 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2579 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2581 /* For non-power-of-two formats, we need the address to be both tile and
2582 * element-aligned. The easiest way to achieve this is to work with a tile
2583 * that is three times as wide as the regular tile.
2585 * The tile info returned by get_tile_info has a logical size that is an
2586 * integer number of tile_info.format_bpb size elements. To scale the
2587 * tile, we scale up the physical width and then treat the logical tile
2588 * size as if it has bpb size elements.
2590 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2591 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2593 /* Compute the offset into the tile */
2594 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2595 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2597 /* Compute the offset of the tile in units of whole tiles */
2598 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2599 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2601 *base_address_offset
=
2602 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2603 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2607 isl_surf_get_depth_format(const struct isl_device
*dev
,
2608 const struct isl_surf
*surf
)
2610 /* Support for separate stencil buffers began in gen5. Support for
2611 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2612 * those that supported separate and interleaved stencil, were gen5 and
2615 * For a list of all available formats, see the Sandybridge PRM >> Volume
2616 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2620 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2622 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2625 assert(ISL_DEV_GEN(dev
) < 7);
2627 switch (surf
->format
) {
2629 unreachable("bad isl depth format");
2630 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2631 assert(ISL_DEV_GEN(dev
) < 7);
2632 return 0; /* D32_FLOAT_S8X24_UINT */
2633 case ISL_FORMAT_R32_FLOAT
:
2634 assert(!has_stencil
);
2635 return 1; /* D32_FLOAT */
2636 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2638 assert(ISL_DEV_GEN(dev
) < 7);
2639 return 2; /* D24_UNORM_S8_UINT */
2641 assert(ISL_DEV_GEN(dev
) >= 5);
2642 return 3; /* D24_UNORM_X8_UINT */
2644 case ISL_FORMAT_R16_UNORM
:
2645 assert(!has_stencil
);
2646 return 5; /* D16_UNORM */
2651 isl_surf_supports_hiz_ccs_wt(const struct gen_device_info
*dev
,
2652 const struct isl_surf
*surf
,
2653 enum isl_aux_usage aux_usage
)
2655 return aux_usage
== ISL_AUX_USAGE_HIZ_CCS
&&
2656 surf
->samples
== 1 &&
2657 surf
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
;
2661 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2662 struct isl_swizzle swizzle
)
2664 if (devinfo
->is_haswell
) {
2665 /* From the Haswell PRM,
2666 * RENDER_SURFACE_STATE::Shader Channel Select Red
2668 * "The Shader channel selects also define which shader channels are
2669 * written to which surface channel. If the Shader channel select is
2670 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2671 * shader channel select is SCS_RED it is written to the surface red
2672 * channel and so on. If more than one shader channel select is set
2673 * to the same surface channel only the first shader channel in RGBA
2674 * order will be written."
2677 } else if (devinfo
->gen
<= 7) {
2678 /* Ivy Bridge and early doesn't have any swizzling */
2679 return isl_swizzle_is_identity(swizzle
);
2681 /* From the Sky Lake PRM Vol. 2d,
2682 * RENDER_SURFACE_STATE::Shader Channel Select Red
2684 * "For Render Target, Red, Green and Blue Shader Channel Selects
2685 * MUST be such that only valid components can be swapped i.e. only
2686 * change the order of components in the pixel. Any other values for
2687 * these Shader Channel Select fields are not valid for Render
2688 * Targets. This also means that there MUST not be multiple shader
2689 * channels mapped to the same RT channel."
2691 * From the Sky Lake PRM Vol. 2d,
2692 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2694 * "For Render Target, this field MUST be programmed to
2695 * value = SCS_ALPHA."
2697 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2698 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2699 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2700 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2701 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2702 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2703 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2704 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2705 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2706 swizzle
.r
!= swizzle
.g
&&
2707 swizzle
.r
!= swizzle
.b
&&
2708 swizzle
.g
!= swizzle
.b
&&
2709 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2713 static enum isl_channel_select
2714 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2717 case ISL_CHANNEL_SELECT_ZERO
:
2718 case ISL_CHANNEL_SELECT_ONE
:
2720 case ISL_CHANNEL_SELECT_RED
:
2722 case ISL_CHANNEL_SELECT_GREEN
:
2724 case ISL_CHANNEL_SELECT_BLUE
:
2726 case ISL_CHANNEL_SELECT_ALPHA
:
2729 unreachable("Invalid swizzle component");
2734 * Returns the single swizzle that is equivalent to applying the two given
2735 * swizzles in sequence.
2738 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2740 return (struct isl_swizzle
) {
2741 .r
= swizzle_select(first
.r
, second
),
2742 .g
= swizzle_select(first
.g
, second
),
2743 .b
= swizzle_select(first
.b
, second
),
2744 .a
= swizzle_select(first
.a
, second
),
2749 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2752 isl_swizzle_invert(struct isl_swizzle swizzle
)
2754 /* Default to zero for channels which do not show up in the swizzle */
2755 enum isl_channel_select chans
[4] = {
2756 ISL_CHANNEL_SELECT_ZERO
,
2757 ISL_CHANNEL_SELECT_ZERO
,
2758 ISL_CHANNEL_SELECT_ZERO
,
2759 ISL_CHANNEL_SELECT_ZERO
,
2762 /* We go in ABGR order so that, if there are any duplicates, the first one
2763 * is taken if you look at it in RGBA order. This is what Haswell hardware
2764 * does for render target swizzles.
2766 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2767 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2768 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2769 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2770 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2771 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2772 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2773 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2775 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };