2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct brw_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_bpb
/ 8;
114 struct isl_extent2d logical_el
, phys_B
;
116 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(format_bpb
));
119 case ISL_TILING_LINEAR
:
121 logical_el
= isl_extent2d(1, 1);
122 phys_B
= isl_extent2d(bs
, 1);
127 logical_el
= isl_extent2d(512 / bs
, 8);
128 phys_B
= isl_extent2d(512, 8);
133 logical_el
= isl_extent2d(128 / bs
, 32);
134 phys_B
= isl_extent2d(128, 32);
139 logical_el
= isl_extent2d(64, 64);
140 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
142 * "If the surface is a stencil buffer (and thus has Tile Mode set
143 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
144 * computed based on width, as the stencil buffer is stored with two
147 * This, together with the fact that stencil buffers are referred to as
148 * being Y-tiled in the PRMs for older hardware implies that the
149 * physical size of a W-tile is actually the same as for a Y-tile.
151 phys_B
= isl_extent2d(128, 32);
155 case ISL_TILING_Ys
: {
156 if (ISL_DEV_GEN(dev
) < 9)
159 if (!isl_is_pow2(bs
))
162 bool is_Ys
= tiling
== ISL_TILING_Ys
;
165 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
166 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
168 logical_el
= isl_extent2d(width
/ bs
, height
);
169 phys_B
= isl_extent2d(width
, height
);
174 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
175 * 128bpb format. The tiling has the same physical dimensions as
176 * Y-tiling but actually has two HiZ columns per Y-tiled column.
179 logical_el
= isl_extent2d(16, 16);
180 phys_B
= isl_extent2d(128, 32);
184 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
185 * have a block size of 1 or 2 bits per block and each CCS element
186 * corresponds to one cache-line pair in the main surface. From the Sky
187 * Lake PRM Vol. 12 in the section on planes:
189 * "The Color Control Surface (CCS) contains the compression status
190 * of the cache-line pairs. The compression state of the cache-line
191 * pair is specified by 2 bits in the CCS. Each CCS cache-line
192 * represents an area on the main surface of 16x16 sets of 128 byte
193 * Y-tiled cache-line-pairs. CCS is always Y tiled."
195 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
196 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
197 * that yields total tile area of 128x128 cache-line pairs or CCS
198 * elements. On older hardware, each CCS element is 1 bit and the tile
199 * is 128x256 elements.
201 assert(format_bpb
== 1 || format_bpb
== 2);
202 logical_el
= isl_extent2d(128, 256 / format_bpb
);
203 phys_B
= isl_extent2d(128, 32);
207 unreachable("not reached");
210 *tile_info
= (struct isl_tile_info
) {
212 .logical_extent_el
= logical_el
,
213 .phys_extent_B
= phys_B
,
220 * @param[out] tiling is set only on success
223 isl_surf_choose_tiling(const struct isl_device
*dev
,
224 const struct isl_surf_init_info
*restrict info
,
225 enum isl_tiling
*tiling
)
227 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
229 if (ISL_DEV_GEN(dev
) >= 7) {
230 gen7_filter_tiling(dev
, info
, &tiling_flags
);
232 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
233 gen7_filter_tiling(dev
, info
, &tiling_flags
);
236 #define CHOOSE(__tiling) \
238 if (tiling_flags & (1u << (__tiling))) { \
239 *tiling = (__tiling); \
244 /* Of the tiling modes remaining, choose the one that offers the best
248 if (info
->dim
== ISL_SURF_DIM_1D
) {
249 /* Prefer linear for 1D surfaces because they do not benefit from
250 * tiling. To the contrary, tiling leads to wasted memory and poor
251 * memory locality due to the swizzling and alignment restrictions
252 * required in tiled surfaces.
254 CHOOSE(ISL_TILING_LINEAR
);
257 CHOOSE(ISL_TILING_CCS
);
258 CHOOSE(ISL_TILING_HIZ
);
259 CHOOSE(ISL_TILING_Ys
);
260 CHOOSE(ISL_TILING_Yf
);
261 CHOOSE(ISL_TILING_Y0
);
262 CHOOSE(ISL_TILING_X
);
263 CHOOSE(ISL_TILING_W
);
264 CHOOSE(ISL_TILING_LINEAR
);
268 /* No tiling mode accomodates the inputs. */
273 isl_choose_msaa_layout(const struct isl_device
*dev
,
274 const struct isl_surf_init_info
*info
,
275 enum isl_tiling tiling
,
276 enum isl_msaa_layout
*msaa_layout
)
278 if (ISL_DEV_GEN(dev
) >= 8) {
279 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
280 } else if (ISL_DEV_GEN(dev
) >= 7) {
281 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
282 } else if (ISL_DEV_GEN(dev
) >= 6) {
283 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
285 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
290 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
291 uint32_t *width
, uint32_t *height
)
293 assert(isl_is_pow2(samples
));
295 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
298 * If the surface is multisampled and it is a depth or stencil surface
299 * or Multisampled Surface StorageFormat in SURFACE_STATE is
300 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
304 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
306 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
309 static enum isl_array_pitch_span
310 isl_choose_array_pitch_span(const struct isl_device
*dev
,
311 const struct isl_surf_init_info
*restrict info
,
312 enum isl_dim_layout dim_layout
,
313 const struct isl_extent4d
*phys_level0_sa
)
315 switch (dim_layout
) {
316 case ISL_DIM_LAYOUT_GEN9_1D
:
317 case ISL_DIM_LAYOUT_GEN4_2D
:
318 if (ISL_DEV_GEN(dev
) >= 8) {
319 /* QPitch becomes programmable in Broadwell. So choose the
320 * most compact QPitch possible in order to conserve memory.
322 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
323 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
325 * - Software must ensure that this field is set to a value
326 * sufficiently large such that the array slices in the surface
327 * do not overlap. Refer to the Memory Data Formats section for
328 * information on how surfaces are stored in memory.
330 * - This field specifies the distance in rows between array
331 * slices. It is used only in the following cases:
333 * - Surface Array is enabled OR
334 * - Number of Mulitsamples is not NUMSAMPLES_1 and
335 * Multisampled Surface Storage Format set to MSFMT_MSS OR
336 * - Surface Type is SURFTYPE_CUBE
338 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
339 } else if (ISL_DEV_GEN(dev
) >= 7) {
340 /* Note that Ivybridge introduces
341 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
342 * driver more control over the QPitch.
345 if (phys_level0_sa
->array_len
== 1) {
346 /* The hardware will never use the QPitch. So choose the most
347 * compact QPitch possible in order to conserve memory.
349 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
352 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
353 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
354 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
355 * Section 6.18.4.7: Surface Arrays (p112):
357 * If Surface Array Spacing is set to ARYSPC_FULL (note that
358 * the depth buffer and stencil buffer have an implied value of
361 return ISL_ARRAY_PITCH_SPAN_FULL
;
364 if (info
->levels
== 1) {
365 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
368 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
371 return ISL_ARRAY_PITCH_SPAN_FULL
;
372 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
373 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
374 isl_surf_usage_is_stencil(info
->usage
)) {
375 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
376 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
378 * The separate stencil buffer does not support mip mapping, thus
379 * the storage for LODs other than LOD 0 is not needed.
381 assert(info
->levels
== 1);
382 assert(phys_level0_sa
->array_len
== 1);
383 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
385 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
386 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
387 isl_surf_usage_is_stencil(info
->usage
)) {
388 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
389 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
391 * The separate stencil buffer does not support mip mapping,
392 * thus the storage for LODs other than LOD 0 is not needed.
394 assert(info
->levels
== 1);
395 assert(phys_level0_sa
->array_len
== 1);
396 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
399 if (phys_level0_sa
->array_len
== 1) {
400 /* The hardware will never use the QPitch. So choose the most
401 * compact QPitch possible in order to conserve memory.
403 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
406 return ISL_ARRAY_PITCH_SPAN_FULL
;
409 case ISL_DIM_LAYOUT_GEN4_3D
:
410 /* The hardware will never use the QPitch. So choose the most
411 * compact QPitch possible in order to conserve memory.
413 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
416 unreachable("bad isl_dim_layout");
417 return ISL_ARRAY_PITCH_SPAN_FULL
;
421 isl_choose_image_alignment_el(const struct isl_device
*dev
,
422 const struct isl_surf_init_info
*restrict info
,
423 enum isl_tiling tiling
,
424 enum isl_msaa_layout msaa_layout
,
425 struct isl_extent3d
*image_align_el
)
427 if (info
->format
== ISL_FORMAT_HIZ
) {
428 assert(ISL_DEV_GEN(dev
) >= 6);
429 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
430 * which works out to 2x2 HiZ elments.
432 *image_align_el
= isl_extent3d(2, 2, 1);
436 if (ISL_DEV_GEN(dev
) >= 9) {
437 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
439 } else if (ISL_DEV_GEN(dev
) >= 8) {
440 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
442 } else if (ISL_DEV_GEN(dev
) >= 7) {
443 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
445 } else if (ISL_DEV_GEN(dev
) >= 6) {
446 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
449 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
454 static enum isl_dim_layout
455 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
456 enum isl_surf_dim logical_dim
)
458 if (ISL_DEV_GEN(dev
) >= 9) {
459 switch (logical_dim
) {
460 case ISL_SURF_DIM_1D
:
461 return ISL_DIM_LAYOUT_GEN9_1D
;
462 case ISL_SURF_DIM_2D
:
463 case ISL_SURF_DIM_3D
:
464 return ISL_DIM_LAYOUT_GEN4_2D
;
467 switch (logical_dim
) {
468 case ISL_SURF_DIM_1D
:
469 case ISL_SURF_DIM_2D
:
470 return ISL_DIM_LAYOUT_GEN4_2D
;
471 case ISL_SURF_DIM_3D
:
472 return ISL_DIM_LAYOUT_GEN4_3D
;
476 unreachable("bad isl_surf_dim");
477 return ISL_DIM_LAYOUT_GEN4_2D
;
481 * Calculate the physical extent of the surface's first level, in units of
482 * surface samples. The result is aligned to the format's compression block.
485 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
486 const struct isl_surf_init_info
*restrict info
,
487 enum isl_dim_layout dim_layout
,
488 enum isl_tiling tiling
,
489 enum isl_msaa_layout msaa_layout
,
490 struct isl_extent4d
*phys_level0_sa
)
492 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
494 if (isl_format_is_yuv(info
->format
))
495 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
498 case ISL_SURF_DIM_1D
:
499 assert(info
->height
== 1);
500 assert(info
->depth
== 1);
501 assert(info
->samples
== 1);
502 assert(!isl_format_is_compressed(info
->format
));
504 switch (dim_layout
) {
505 case ISL_DIM_LAYOUT_GEN4_3D
:
506 unreachable("bad isl_dim_layout");
508 case ISL_DIM_LAYOUT_GEN9_1D
:
509 case ISL_DIM_LAYOUT_GEN4_2D
:
510 *phys_level0_sa
= (struct isl_extent4d
) {
514 .a
= info
->array_len
,
520 case ISL_SURF_DIM_2D
:
521 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
523 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
524 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
526 switch (msaa_layout
) {
527 case ISL_MSAA_LAYOUT_NONE
:
528 assert(info
->depth
== 1);
529 assert(info
->samples
== 1);
531 *phys_level0_sa
= (struct isl_extent4d
) {
532 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
533 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
535 .a
= info
->array_len
,
539 case ISL_MSAA_LAYOUT_ARRAY
:
540 assert(info
->depth
== 1);
541 assert(info
->array_len
== 1);
542 assert(!isl_format_is_compressed(info
->format
));
544 *phys_level0_sa
= (struct isl_extent4d
) {
552 case ISL_MSAA_LAYOUT_INTERLEAVED
:
553 assert(info
->depth
== 1);
554 assert(info
->array_len
== 1);
555 assert(!isl_format_is_compressed(info
->format
));
557 *phys_level0_sa
= (struct isl_extent4d
) {
564 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
571 case ISL_SURF_DIM_3D
:
572 assert(info
->array_len
== 1);
573 assert(info
->samples
== 1);
576 isl_finishme("%s:%s: compression block with depth > 1",
580 switch (dim_layout
) {
581 case ISL_DIM_LAYOUT_GEN9_1D
:
582 unreachable("bad isl_dim_layout");
584 case ISL_DIM_LAYOUT_GEN4_2D
:
585 assert(ISL_DEV_GEN(dev
) >= 9);
587 *phys_level0_sa
= (struct isl_extent4d
) {
588 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
589 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
595 case ISL_DIM_LAYOUT_GEN4_3D
:
596 assert(ISL_DEV_GEN(dev
) < 9);
597 *phys_level0_sa
= (struct isl_extent4d
) {
598 .w
= isl_align(info
->width
, fmtl
->bw
),
599 .h
= isl_align(info
->height
, fmtl
->bh
),
610 * A variant of isl_calc_phys_slice0_extent_sa() specific to
611 * ISL_DIM_LAYOUT_GEN4_2D.
614 isl_calc_phys_slice0_extent_sa_gen4_2d(
615 const struct isl_device
*dev
,
616 const struct isl_surf_init_info
*restrict info
,
617 enum isl_msaa_layout msaa_layout
,
618 const struct isl_extent3d
*image_align_sa
,
619 const struct isl_extent4d
*phys_level0_sa
,
620 struct isl_extent2d
*phys_slice0_sa
)
622 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
624 assert(phys_level0_sa
->depth
== 1);
626 if (info
->levels
== 1) {
627 /* Do not pad the surface to the image alignment. Instead, pad it only
628 * to the pixel format's block alignment.
630 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
631 * cycles on the below mipmap layout caluclations. Reducing the
632 * alignment here is safe because we later align the row pitch and array
633 * pitch to the tile boundary. It is safe even for
634 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
635 * to accomodate the interleaved samples.
637 * For linear surfaces, reducing the alignment here permits us to later
638 * choose an arbitrary, non-aligned row pitch. If the surface backs
639 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
640 * VkBufferImageCopy::bufferRowLength.
642 *phys_slice0_sa
= (struct isl_extent2d
) {
643 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
644 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
649 uint32_t slice_top_w
= 0;
650 uint32_t slice_bottom_w
= 0;
651 uint32_t slice_left_h
= 0;
652 uint32_t slice_right_h
= 0;
654 uint32_t W0
= phys_level0_sa
->w
;
655 uint32_t H0
= phys_level0_sa
->h
;
657 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
658 uint32_t W
= isl_minify(W0
, l
);
659 uint32_t H
= isl_minify(H0
, l
);
661 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
662 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
679 *phys_slice0_sa
= (struct isl_extent2d
) {
680 .w
= MAX(slice_top_w
, slice_bottom_w
),
681 .h
= MAX(slice_left_h
, slice_right_h
),
686 * A variant of isl_calc_phys_slice0_extent_sa() specific to
687 * ISL_DIM_LAYOUT_GEN4_3D.
690 isl_calc_phys_slice0_extent_sa_gen4_3d(
691 const struct isl_device
*dev
,
692 const struct isl_surf_init_info
*restrict info
,
693 const struct isl_extent3d
*image_align_sa
,
694 const struct isl_extent4d
*phys_level0_sa
,
695 struct isl_extent2d
*phys_slice0_sa
)
697 assert(info
->samples
== 1);
698 assert(phys_level0_sa
->array_len
== 1);
700 uint32_t slice_w
= 0;
701 uint32_t slice_h
= 0;
703 uint32_t W0
= phys_level0_sa
->w
;
704 uint32_t H0
= phys_level0_sa
->h
;
705 uint32_t D0
= phys_level0_sa
->d
;
707 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
708 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
709 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
710 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
712 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
713 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
715 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
716 slice_h
+= level_h
* max_layers_vert
;
719 *phys_slice0_sa
= (struct isl_extent2d
) {
726 * A variant of isl_calc_phys_slice0_extent_sa() specific to
727 * ISL_DIM_LAYOUT_GEN9_1D.
730 isl_calc_phys_slice0_extent_sa_gen9_1d(
731 const struct isl_device
*dev
,
732 const struct isl_surf_init_info
*restrict info
,
733 const struct isl_extent3d
*image_align_sa
,
734 const struct isl_extent4d
*phys_level0_sa
,
735 struct isl_extent2d
*phys_slice0_sa
)
737 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
739 assert(phys_level0_sa
->height
== 1);
740 assert(phys_level0_sa
->depth
== 1);
741 assert(info
->samples
== 1);
742 assert(image_align_sa
->w
>= fmtl
->bw
);
744 uint32_t slice_w
= 0;
745 const uint32_t W0
= phys_level0_sa
->w
;
747 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
748 uint32_t W
= isl_minify(W0
, l
);
749 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
754 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
758 * Calculate the physical extent of the surface's first array slice, in units
759 * of surface samples. If the surface is multi-leveled, then the result will
760 * be aligned to \a image_align_sa.
763 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
764 const struct isl_surf_init_info
*restrict info
,
765 enum isl_dim_layout dim_layout
,
766 enum isl_msaa_layout msaa_layout
,
767 const struct isl_extent3d
*image_align_sa
,
768 const struct isl_extent4d
*phys_level0_sa
,
769 struct isl_extent2d
*phys_slice0_sa
)
771 switch (dim_layout
) {
772 case ISL_DIM_LAYOUT_GEN9_1D
:
773 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
774 image_align_sa
, phys_level0_sa
,
777 case ISL_DIM_LAYOUT_GEN4_2D
:
778 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
779 image_align_sa
, phys_level0_sa
,
782 case ISL_DIM_LAYOUT_GEN4_3D
:
783 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
784 phys_level0_sa
, phys_slice0_sa
);
790 * Calculate the pitch between physical array slices, in units of rows of
794 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
795 const struct isl_surf_init_info
*restrict info
,
796 const struct isl_tile_info
*tile_info
,
797 enum isl_dim_layout dim_layout
,
798 enum isl_array_pitch_span array_pitch_span
,
799 const struct isl_extent3d
*image_align_sa
,
800 const struct isl_extent4d
*phys_level0_sa
,
801 const struct isl_extent2d
*phys_slice0_sa
)
803 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
804 uint32_t pitch_sa_rows
= 0;
806 switch (dim_layout
) {
807 case ISL_DIM_LAYOUT_GEN9_1D
:
808 /* Each row is an array slice */
811 case ISL_DIM_LAYOUT_GEN4_2D
:
812 switch (array_pitch_span
) {
813 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
814 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
816 case ISL_ARRAY_PITCH_SPAN_FULL
: {
817 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
818 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
819 * Surfaces >> Surface Arrays.
821 uint32_t H0_sa
= phys_level0_sa
->h
;
822 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
824 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
825 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
828 if (ISL_DEV_GEN(dev
) >= 7) {
829 /* The QPitch equation changed slightly in Ivybridge. */
835 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
837 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
838 (info
->height
% 4 == 1)) {
839 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
840 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
842 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
843 * the value calculated in the equation above , for every
844 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
846 * XXX(chadv): Is the errata natural corollary of the physical
847 * layout of interleaved samples?
852 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
857 case ISL_DIM_LAYOUT_GEN4_3D
:
858 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
859 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
862 unreachable("bad isl_dim_layout");
866 assert(pitch_sa_rows
% fmtl
->bh
== 0);
867 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
869 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
871 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
873 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
874 * layout with these alignments in the RT space: Horizontal
875 * Alignment = 128 and Vertical Alignment = 64."
877 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
879 * "For non-multisampled render target's CCS auxiliary surface,
880 * QPitch must be computed with Horizontal Alignment = 128 and
881 * Surface Vertical Alignment = 256. These alignments are only for
882 * CCS buffer and not for associated render target."
884 * The first restriction is already handled by isl_choose_image_alignment_el
885 * but the second restriction, which is an extension of the first, only
886 * applies to qpitch and must be applied here.
888 assert(fmtl
->bh
== 4);
889 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
892 if (ISL_DEV_GEN(dev
) >= 9 &&
893 info
->dim
== ISL_SURF_DIM_3D
&&
894 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
895 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
897 * Tile Mode != Linear: This field must be set to an integer multiple
900 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
903 return pitch_el_rows
;
907 * Calculate the pitch of each surface row, in bytes.
910 isl_calc_linear_row_pitch(const struct isl_device
*dev
,
911 const struct isl_surf_init_info
*restrict info
,
912 const struct isl_extent2d
*phys_slice0_sa
)
914 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
916 uint32_t row_pitch
= info
->min_pitch
;
918 /* First, align the surface to a cache line boundary, as the PRM explains
921 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
922 * Formats >> Surface Padding Requirements >> Render Target and Media
925 * The data port accesses data (pixels) outside of the surface if they
926 * are contained in the same cache request as pixels that are within the
927 * surface. These pixels will not be returned by the requesting message,
928 * however if these pixels lie outside of defined pages in the GTT,
929 * a GTT error will result when the cache request is processed. In order
930 * to avoid these GTT errors, “padding” at the bottom of the surface is
931 * sometimes necessary.
933 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
934 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
936 * The sampling engine accesses texels outside of the surface if they
937 * are contained in the same cache line as texels that are within the
938 * surface. These texels will not participate in any calculation
939 * performed by the sampling engine and will not affect the result of
940 * any sampling engine operation, however if these texels lie outside of
941 * defined pages in the GTT, a GTT error will result when the cache line
942 * is accessed. In order to avoid these GTT errors, “padding” at the
943 * bottom and right side of a sampling engine surface is sometimes
946 * It is possible that a cache line will straddle a page boundary if the
947 * base address or pitch is not aligned. All pages included in the cache
948 * lines that are part of the surface must map to valid GTT entries to
949 * avoid errors. To determine the necessary padding on the bottom and
950 * right side of the surface, refer to the table in Alignment Unit Size
951 * section for the i and j parameters for the surface format in use. The
952 * surface must then be extended to the next multiple of the alignment
953 * unit size in each dimension, and all texels contained in this
954 * extended surface must have valid GTT entries.
956 * For example, suppose the surface size is 15 texels by 10 texels and
957 * the alignment parameters are i=4 and j=2. In this case, the extended
958 * surface would be 16 by 10. Note that these calculations are done in
959 * texels, and must be converted to bytes based on the surface format
960 * being used to determine whether additional pages need to be defined.
962 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
963 const uint32_t bs
= fmtl
->bpb
/ 8;
964 row_pitch
= MAX(row_pitch
, bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
966 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
967 * RENDER_SURFACE_STATE Surface Pitch (p349):
969 * - For linear render target surfaces and surfaces accessed with the
970 * typed data port messages, the pitch must be a multiple of the
971 * element size for non-YUV surface formats. Pitch must be
972 * a multiple of 2 * element size for YUV surface formats.
974 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
975 * ignore because isl doesn't do buffers.]
977 * - For other linear surfaces, the pitch can be any multiple of
980 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
981 if (isl_format_is_yuv(info
->format
)) {
982 row_pitch
= isl_align_npot(row_pitch
, 2 * bs
);
984 row_pitch
= isl_align_npot(row_pitch
, bs
);
992 * Calculate and apply any padding required for the surface.
994 * @param[inout] total_h_el is updated with the new height
995 * @param[out] pad_bytes is overwritten with additional padding requirements.
998 isl_apply_surface_padding(const struct isl_device
*dev
,
999 const struct isl_surf_init_info
*restrict info
,
1000 const struct isl_tile_info
*tile_info
,
1001 uint32_t *total_h_el
,
1002 uint32_t *pad_bytes
)
1004 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1008 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1009 * Formats >> Surface Padding Requirements >> Render Target and Media
1012 * The data port accesses data (pixels) outside of the surface if they
1013 * are contained in the same cache request as pixels that are within the
1014 * surface. These pixels will not be returned by the requesting message,
1015 * however if these pixels lie outside of defined pages in the GTT,
1016 * a GTT error will result when the cache request is processed. In
1017 * order to avoid these GTT errors, “padding” at the bottom of the
1018 * surface is sometimes necessary.
1020 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1021 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1023 * ... Lots of padding requirements, all listed separately below.
1026 /* We can safely ignore the first padding requirement, quoted below,
1027 * because isl doesn't do buffers.
1029 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1030 * requirements are different. A buffer must be padded to the next
1031 * multiple of 256 array elements, with an additional 16 bytes added
1032 * beyond that to account for the L1 cache line.
1036 * - For compressed textures [...], padding at the bottom of the surface
1037 * is to an even compressed row.
1039 if (isl_format_is_compressed(info
->format
))
1040 *total_h_el
= isl_align(*total_h_el
, 2);
1043 * - For cube surfaces, an additional two rows of padding are required
1044 * at the bottom of the surface.
1046 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1050 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1051 * additional padding is required. These surfaces require an extra row
1052 * plus 16 bytes of padding at the bottom in addition to the general
1053 * padding requirements.
1055 if (isl_format_is_yuv(info
->format
) &&
1056 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1062 * - For linear surfaces, additional padding of 64 bytes is required at
1063 * the bottom of the surface. This is in addition to the padding
1066 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1069 /* The below text weakens, not strengthens, the padding requirements for
1070 * linear surfaces. Therefore we can safely ignore it.
1072 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1073 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1074 * padding requirement is to the next aligned 64-byte boundary beyond
1075 * the end of the surface. The rest of the padding requirements
1076 * documented above do not apply to these surfaces.
1080 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1081 * height % 4 != 0, the surface must be padded with
1082 * 4-(height % 4)*Surface Pitch # of bytes.
1084 if (ISL_DEV_GEN(dev
) >= 9 &&
1085 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1086 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1087 *total_h_el
= isl_align(*total_h_el
, 4);
1091 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1092 * to 4 times the Surface Pitch # of bytes
1094 if (ISL_DEV_GEN(dev
) >= 9 &&
1095 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1096 info
->dim
== ISL_SURF_DIM_1D
) {
1102 isl_surf_init_s(const struct isl_device
*dev
,
1103 struct isl_surf
*surf
,
1104 const struct isl_surf_init_info
*restrict info
)
1106 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1108 const struct isl_extent4d logical_level0_px
= {
1112 .a
= info
->array_len
,
1115 enum isl_dim_layout dim_layout
=
1116 isl_surf_choose_dim_layout(dev
, info
->dim
);
1118 enum isl_tiling tiling
;
1119 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1122 struct isl_tile_info tile_info
;
1123 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1126 enum isl_msaa_layout msaa_layout
;
1127 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1130 struct isl_extent3d image_align_el
;
1131 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1134 struct isl_extent3d image_align_sa
=
1135 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1137 struct isl_extent4d phys_level0_sa
;
1138 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1140 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1141 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1143 enum isl_array_pitch_span array_pitch_span
=
1144 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1146 struct isl_extent2d phys_slice0_sa
;
1147 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1148 &image_align_sa
, &phys_level0_sa
,
1150 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1151 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1153 const uint32_t array_pitch_el_rows
=
1154 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1155 array_pitch_span
, &image_align_sa
,
1156 &phys_level0_sa
, &phys_slice0_sa
);
1158 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1161 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1163 uint32_t row_pitch
, size
, base_alignment
;
1164 if (tiling
== ISL_TILING_LINEAR
) {
1165 row_pitch
= isl_calc_linear_row_pitch(dev
, info
, &phys_slice0_sa
);
1166 size
= row_pitch
* total_h_el
+ pad_bytes
;
1168 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1170 * "The Base Address for linear render target surfaces and surfaces
1171 * accessed with the typed surface read/write data port messages must
1172 * be element-size aligned, for non-YUV surface formats, or a
1173 * multiple of 2 element-sizes for YUV surface formats. Other linear
1174 * surfaces have no alignment requirements (byte alignment is
1177 base_alignment
= MAX(1, info
->min_alignment
);
1178 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1179 if (isl_format_is_yuv(info
->format
)) {
1180 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1182 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1186 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1187 const uint32_t total_w_el
= phys_slice0_sa
.width
/ fmtl
->bw
;
1188 const uint32_t total_w_tl
=
1189 isl_align_div(total_w_el
, tile_info
.logical_extent_el
.width
);
1191 row_pitch
= total_w_tl
* tile_info
.phys_extent_B
.width
;
1192 if (row_pitch
< info
->min_pitch
) {
1193 row_pitch
= isl_align(info
->min_pitch
, tile_info
.phys_extent_B
.width
);
1196 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1197 const uint32_t total_h_tl
=
1198 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1200 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1202 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1203 tile_info
.phys_extent_B
.height
;
1204 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1205 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1208 *surf
= (struct isl_surf
) {
1210 .dim_layout
= dim_layout
,
1211 .msaa_layout
= msaa_layout
,
1213 .format
= info
->format
,
1215 .levels
= info
->levels
,
1216 .samples
= info
->samples
,
1218 .image_alignment_el
= image_align_el
,
1219 .logical_level0_px
= logical_level0_px
,
1220 .phys_level0_sa
= phys_level0_sa
,
1223 .alignment
= base_alignment
,
1224 .row_pitch
= row_pitch
,
1225 .array_pitch_el_rows
= array_pitch_el_rows
,
1226 .array_pitch_span
= array_pitch_span
,
1228 .usage
= info
->usage
,
1235 isl_surf_get_tile_info(const struct isl_device
*dev
,
1236 const struct isl_surf
*surf
,
1237 struct isl_tile_info
*tile_info
)
1239 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1240 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1244 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1245 const struct isl_surf_fill_state_info
*restrict info
)
1248 isl_surf_usage_flags_t _base_usage
=
1249 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1250 ISL_SURF_USAGE_TEXTURE_BIT
|
1251 ISL_SURF_USAGE_STORAGE_BIT
);
1252 /* They may only specify one of the above bits at a time */
1253 assert(__builtin_popcount(_base_usage
) == 1);
1254 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1255 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1258 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1259 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1260 info
->surf
->logical_level0_px
.depth
);
1262 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1263 info
->surf
->logical_level0_px
.array_len
);
1266 switch (ISL_DEV_GEN(dev
)) {
1268 if (ISL_DEV_IS_G4X(dev
)) {
1269 /* G45 surface state is the same as gen5 */
1270 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1272 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1276 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1279 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1282 if (ISL_DEV_IS_HASWELL(dev
)) {
1283 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1285 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1289 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1292 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1295 assert(!"Cannot fill surface state for this gen");
1300 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1301 const struct isl_buffer_fill_state_info
*restrict info
)
1303 switch (ISL_DEV_GEN(dev
)) {
1306 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1307 isl_gen5_buffer_fill_state_s(state
, info
);
1310 isl_gen6_buffer_fill_state_s(state
, info
);
1313 if (ISL_DEV_IS_HASWELL(dev
)) {
1314 isl_gen75_buffer_fill_state_s(state
, info
);
1316 isl_gen7_buffer_fill_state_s(state
, info
);
1320 isl_gen8_buffer_fill_state_s(state
, info
);
1323 isl_gen9_buffer_fill_state_s(state
, info
);
1326 assert(!"Cannot fill surface state for this gen");
1331 * A variant of isl_surf_get_image_offset_sa() specific to
1332 * ISL_DIM_LAYOUT_GEN4_2D.
1335 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1336 uint32_t level
, uint32_t logical_array_layer
,
1337 uint32_t *x_offset_sa
,
1338 uint32_t *y_offset_sa
)
1340 assert(level
< surf
->levels
);
1341 if (surf
->dim
== ISL_SURF_DIM_3D
)
1342 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1344 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1346 const struct isl_extent3d image_align_sa
=
1347 isl_surf_get_image_alignment_sa(surf
);
1349 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1350 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1352 const uint32_t phys_layer
= logical_array_layer
*
1353 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1356 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1358 for (uint32_t l
= 0; l
< level
; ++l
) {
1360 uint32_t W
= isl_minify(W0
, l
);
1361 x
+= isl_align_npot(W
, image_align_sa
.w
);
1363 uint32_t H
= isl_minify(H0
, l
);
1364 y
+= isl_align_npot(H
, image_align_sa
.h
);
1373 * A variant of isl_surf_get_image_offset_sa() specific to
1374 * ISL_DIM_LAYOUT_GEN4_3D.
1377 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1378 uint32_t level
, uint32_t logical_z_offset_px
,
1379 uint32_t *x_offset_sa
,
1380 uint32_t *y_offset_sa
)
1382 assert(level
< surf
->levels
);
1383 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1384 assert(surf
->phys_level0_sa
.array_len
== 1);
1386 const struct isl_extent3d image_align_sa
=
1387 isl_surf_get_image_alignment_sa(surf
);
1389 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1390 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1391 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1396 for (uint32_t l
= 0; l
< level
; ++l
) {
1397 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1398 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1399 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1401 y
+= level_h
* max_layers_vert
;
1404 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1405 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1406 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1408 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1410 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1411 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1418 * A variant of isl_surf_get_image_offset_sa() specific to
1419 * ISL_DIM_LAYOUT_GEN9_1D.
1422 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1423 uint32_t level
, uint32_t layer
,
1424 uint32_t *x_offset_sa
,
1425 uint32_t *y_offset_sa
)
1427 assert(level
< surf
->levels
);
1428 assert(layer
< surf
->phys_level0_sa
.array_len
);
1429 assert(surf
->phys_level0_sa
.height
== 1);
1430 assert(surf
->phys_level0_sa
.depth
== 1);
1431 assert(surf
->samples
== 1);
1433 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1434 const struct isl_extent3d image_align_sa
=
1435 isl_surf_get_image_alignment_sa(surf
);
1439 for (uint32_t l
= 0; l
< level
; ++l
) {
1440 uint32_t W
= isl_minify(W0
, l
);
1441 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1447 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1451 * Calculate the offset, in units of surface samples, to a subimage in the
1454 * @invariant level < surface levels
1455 * @invariant logical_array_layer < logical array length of surface
1456 * @invariant logical_z_offset_px < logical depth of surface at level
1459 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1461 uint32_t logical_array_layer
,
1462 uint32_t logical_z_offset_px
,
1463 uint32_t *x_offset_sa
,
1464 uint32_t *y_offset_sa
)
1466 assert(level
< surf
->levels
);
1467 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1468 assert(logical_z_offset_px
1469 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1471 switch (surf
->dim_layout
) {
1472 case ISL_DIM_LAYOUT_GEN9_1D
:
1473 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1474 x_offset_sa
, y_offset_sa
);
1476 case ISL_DIM_LAYOUT_GEN4_2D
:
1477 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1478 + logical_z_offset_px
,
1479 x_offset_sa
, y_offset_sa
);
1481 case ISL_DIM_LAYOUT_GEN4_3D
:
1482 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1483 x_offset_sa
, y_offset_sa
);
1487 unreachable("not reached");
1492 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1494 uint32_t logical_array_layer
,
1495 uint32_t logical_z_offset_px
,
1496 uint32_t *x_offset_el
,
1497 uint32_t *y_offset_el
)
1499 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1501 assert(level
< surf
->levels
);
1502 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1503 assert(logical_z_offset_px
1504 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1506 uint32_t x_offset_sa
, y_offset_sa
;
1507 isl_surf_get_image_offset_sa(surf
, level
,
1508 logical_array_layer
,
1509 logical_z_offset_px
,
1513 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1514 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1518 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1519 enum isl_tiling tiling
,
1522 uint32_t total_x_offset_el
,
1523 uint32_t total_y_offset_el
,
1524 uint32_t *base_address_offset
,
1525 uint32_t *x_offset_el
,
1526 uint32_t *y_offset_el
)
1528 /* This function only really works for power-of-two surfaces. In
1529 * theory, we could make it work for non-power-of-two surfaces by going
1530 * to the left until we find a block that is bs-aligned. The Vulkan
1531 * driver doesn't use non-power-of-two tiled surfaces so we'll leave
1532 * this unimplemented for now.
1534 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
1536 if (tiling
== ISL_TILING_LINEAR
) {
1537 *base_address_offset
= total_y_offset_el
* row_pitch
+
1538 total_x_offset_el
* bs
;
1544 struct isl_tile_info tile_info
;
1545 isl_tiling_get_info(dev
, tiling
, bs
* 8, &tile_info
);
1547 /* Compute the offset into the tile */
1548 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1549 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1551 /* Compute the offset of the tile in units of whole tiles */
1552 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1553 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1555 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1556 *base_address_offset
=
1557 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1558 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1562 isl_surf_get_depth_format(const struct isl_device
*dev
,
1563 const struct isl_surf
*surf
)
1565 /* Support for separate stencil buffers began in gen5. Support for
1566 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1567 * those that supported separate and interleaved stencil, were gen5 and
1570 * For a list of all available formats, see the Sandybridge PRM >> Volume
1571 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1575 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1577 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1580 assert(ISL_DEV_GEN(dev
) < 7);
1582 switch (surf
->format
) {
1584 unreachable("bad isl depth format");
1585 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1586 assert(ISL_DEV_GEN(dev
) < 7);
1587 return 0; /* D32_FLOAT_S8X24_UINT */
1588 case ISL_FORMAT_R32_FLOAT
:
1589 assert(!has_stencil
);
1590 return 1; /* D32_FLOAT */
1591 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1593 assert(ISL_DEV_GEN(dev
) < 7);
1594 return 2; /* D24_UNORM_S8_UINT */
1596 assert(ISL_DEV_GEN(dev
) >= 5);
1597 return 3; /* D24_UNORM_X8_UINT */
1599 case ISL_FORMAT_R16_UNORM
:
1600 assert(!has_stencil
);
1601 return 5; /* D16_UNORM */