2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
38 void PRINTFLIKE(3, 4) UNUSED
39 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
45 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
48 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
52 isl_device_init(struct isl_device
*dev
,
53 const struct gen_device_info
*info
,
54 bool has_bit6_swizzling
)
57 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
58 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
60 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
61 * device properties at buildtime. Verify that the macros with the device
62 * properties chosen during runtime.
64 ISL_DEV_GEN_SANITIZE(dev
);
65 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
67 /* Did we break hiz or stencil? */
68 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
69 assert(info
->has_hiz_and_separate_stencil
);
70 if (info
->must_use_separate_stencil
)
71 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
74 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
76 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
78 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
80 /* The "Auxiliary Surface Base Address" field starts a bit higher up
81 * because the bottom 12 bits are used for other things. Round down to
82 * the nearest dword before.
84 dev
->ss
.aux_addr_offset
=
85 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
87 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
88 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
89 dev
->ds
.depth_offset
=
90 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
92 if (dev
->use_separate_stencil
) {
93 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
94 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
95 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
97 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
98 dev
->ds
.stencil_offset
=
99 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
100 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
102 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
104 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
105 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
106 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
108 dev
->ds
.stencil_offset
= 0;
109 dev
->ds
.hiz_offset
= 0;
114 * @brief Query the set of multisamples supported by the device.
116 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
119 isl_sample_count_mask_t ATTRIBUTE_CONST
120 isl_device_get_sample_counts(struct isl_device
*dev
)
122 if (ISL_DEV_GEN(dev
) >= 9) {
123 return ISL_SAMPLE_COUNT_1_BIT
|
124 ISL_SAMPLE_COUNT_2_BIT
|
125 ISL_SAMPLE_COUNT_4_BIT
|
126 ISL_SAMPLE_COUNT_8_BIT
|
127 ISL_SAMPLE_COUNT_16_BIT
;
128 } else if (ISL_DEV_GEN(dev
) >= 8) {
129 return ISL_SAMPLE_COUNT_1_BIT
|
130 ISL_SAMPLE_COUNT_2_BIT
|
131 ISL_SAMPLE_COUNT_4_BIT
|
132 ISL_SAMPLE_COUNT_8_BIT
;
133 } else if (ISL_DEV_GEN(dev
) >= 7) {
134 return ISL_SAMPLE_COUNT_1_BIT
|
135 ISL_SAMPLE_COUNT_4_BIT
|
136 ISL_SAMPLE_COUNT_8_BIT
;
137 } else if (ISL_DEV_GEN(dev
) >= 6) {
138 return ISL_SAMPLE_COUNT_1_BIT
|
139 ISL_SAMPLE_COUNT_4_BIT
;
141 return ISL_SAMPLE_COUNT_1_BIT
;
146 * @param[out] info is written only on success
149 isl_tiling_get_info(enum isl_tiling tiling
,
151 struct isl_tile_info
*tile_info
)
153 const uint32_t bs
= format_bpb
/ 8;
154 struct isl_extent2d logical_el
, phys_B
;
156 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
157 /* It is possible to have non-power-of-two formats in a tiled buffer.
158 * The easiest way to handle this is to treat the tile as if it is three
159 * times as wide. This way no pixel will ever cross a tile boundary.
160 * This really only works on legacy X and Y tiling formats.
162 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
163 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
164 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
169 case ISL_TILING_LINEAR
:
171 logical_el
= isl_extent2d(1, 1);
172 phys_B
= isl_extent2d(bs
, 1);
177 logical_el
= isl_extent2d(512 / bs
, 8);
178 phys_B
= isl_extent2d(512, 8);
183 logical_el
= isl_extent2d(128 / bs
, 32);
184 phys_B
= isl_extent2d(128, 32);
189 logical_el
= isl_extent2d(64, 64);
190 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
192 * "If the surface is a stencil buffer (and thus has Tile Mode set
193 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
194 * computed based on width, as the stencil buffer is stored with two
197 * This, together with the fact that stencil buffers are referred to as
198 * being Y-tiled in the PRMs for older hardware implies that the
199 * physical size of a W-tile is actually the same as for a Y-tile.
201 phys_B
= isl_extent2d(128, 32);
205 case ISL_TILING_Ys
: {
206 bool is_Ys
= tiling
== ISL_TILING_Ys
;
209 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
210 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
212 logical_el
= isl_extent2d(width
/ bs
, height
);
213 phys_B
= isl_extent2d(width
, height
);
218 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
219 * 128bpb format. The tiling has the same physical dimensions as
220 * Y-tiling but actually has two HiZ columns per Y-tiled column.
223 logical_el
= isl_extent2d(16, 16);
224 phys_B
= isl_extent2d(128, 32);
228 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
229 * have a block size of 1 or 2 bits per block and each CCS element
230 * corresponds to one cache-line pair in the main surface. From the Sky
231 * Lake PRM Vol. 12 in the section on planes:
233 * "The Color Control Surface (CCS) contains the compression status
234 * of the cache-line pairs. The compression state of the cache-line
235 * pair is specified by 2 bits in the CCS. Each CCS cache-line
236 * represents an area on the main surface of 16x16 sets of 128 byte
237 * Y-tiled cache-line-pairs. CCS is always Y tiled."
239 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
240 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
241 * that yields total tile area of 128x128 cache-line pairs or CCS
242 * elements. On older hardware, each CCS element is 1 bit and the tile
243 * is 128x256 elements.
245 assert(format_bpb
== 1 || format_bpb
== 2);
246 logical_el
= isl_extent2d(128, 256 / format_bpb
);
247 phys_B
= isl_extent2d(128, 32);
251 unreachable("not reached");
254 *tile_info
= (struct isl_tile_info
) {
256 .format_bpb
= format_bpb
,
257 .logical_extent_el
= logical_el
,
258 .phys_extent_B
= phys_B
,
263 * @param[out] tiling is set only on success
266 isl_surf_choose_tiling(const struct isl_device
*dev
,
267 const struct isl_surf_init_info
*restrict info
,
268 enum isl_tiling
*tiling
)
270 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
272 /* HiZ surfaces always use the HiZ tiling */
273 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
274 assert(info
->format
== ISL_FORMAT_HIZ
);
275 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
276 *tiling
= ISL_TILING_HIZ
;
280 /* CCS surfaces always use the CCS tiling */
281 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
282 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
283 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
284 *tiling
= ISL_TILING_CCS
;
288 if (ISL_DEV_GEN(dev
) >= 6) {
289 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
291 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
294 #define CHOOSE(__tiling) \
296 if (tiling_flags & (1u << (__tiling))) { \
297 *tiling = (__tiling); \
302 /* Of the tiling modes remaining, choose the one that offers the best
306 if (info
->dim
== ISL_SURF_DIM_1D
) {
307 /* Prefer linear for 1D surfaces because they do not benefit from
308 * tiling. To the contrary, tiling leads to wasted memory and poor
309 * memory locality due to the swizzling and alignment restrictions
310 * required in tiled surfaces.
312 CHOOSE(ISL_TILING_LINEAR
);
315 CHOOSE(ISL_TILING_Ys
);
316 CHOOSE(ISL_TILING_Yf
);
317 CHOOSE(ISL_TILING_Y0
);
318 CHOOSE(ISL_TILING_X
);
319 CHOOSE(ISL_TILING_W
);
320 CHOOSE(ISL_TILING_LINEAR
);
324 /* No tiling mode accomodates the inputs. */
329 isl_choose_msaa_layout(const struct isl_device
*dev
,
330 const struct isl_surf_init_info
*info
,
331 enum isl_tiling tiling
,
332 enum isl_msaa_layout
*msaa_layout
)
334 if (ISL_DEV_GEN(dev
) >= 8) {
335 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
336 } else if (ISL_DEV_GEN(dev
) >= 7) {
337 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
338 } else if (ISL_DEV_GEN(dev
) >= 6) {
339 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
341 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
346 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
348 assert(isl_is_pow2(samples
));
350 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
353 * If the surface is multisampled and it is a depth or stencil surface
354 * or Multisampled Surface StorageFormat in SURFACE_STATE is
355 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
358 return (struct isl_extent2d
) {
359 .width
= 1 << ((ffs(samples
) - 0) / 2),
360 .height
= 1 << ((ffs(samples
) - 1) / 2),
365 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
366 uint32_t *width
, uint32_t *height
)
368 const struct isl_extent2d px_size_sa
=
369 isl_get_interleaved_msaa_px_size_sa(samples
);
372 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
374 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
377 static enum isl_array_pitch_span
378 isl_choose_array_pitch_span(const struct isl_device
*dev
,
379 const struct isl_surf_init_info
*restrict info
,
380 enum isl_dim_layout dim_layout
,
381 const struct isl_extent4d
*phys_level0_sa
)
383 switch (dim_layout
) {
384 case ISL_DIM_LAYOUT_GEN9_1D
:
385 case ISL_DIM_LAYOUT_GEN4_2D
:
386 if (ISL_DEV_GEN(dev
) >= 8) {
387 /* QPitch becomes programmable in Broadwell. So choose the
388 * most compact QPitch possible in order to conserve memory.
390 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
391 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
393 * - Software must ensure that this field is set to a value
394 * sufficiently large such that the array slices in the surface
395 * do not overlap. Refer to the Memory Data Formats section for
396 * information on how surfaces are stored in memory.
398 * - This field specifies the distance in rows between array
399 * slices. It is used only in the following cases:
401 * - Surface Array is enabled OR
402 * - Number of Mulitsamples is not NUMSAMPLES_1 and
403 * Multisampled Surface Storage Format set to MSFMT_MSS OR
404 * - Surface Type is SURFTYPE_CUBE
406 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
407 } else if (ISL_DEV_GEN(dev
) >= 7) {
408 /* Note that Ivybridge introduces
409 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
410 * driver more control over the QPitch.
413 if (phys_level0_sa
->array_len
== 1) {
414 /* The hardware will never use the QPitch. So choose the most
415 * compact QPitch possible in order to conserve memory.
417 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
420 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
421 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
422 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
423 * Section 6.18.4.7: Surface Arrays (p112):
425 * If Surface Array Spacing is set to ARYSPC_FULL (note that
426 * the depth buffer and stencil buffer have an implied value of
429 return ISL_ARRAY_PITCH_SPAN_FULL
;
432 if (info
->levels
== 1) {
433 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
436 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
439 return ISL_ARRAY_PITCH_SPAN_FULL
;
440 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
441 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
442 isl_surf_usage_is_stencil(info
->usage
)) {
443 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
444 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
446 * The separate stencil buffer does not support mip mapping, thus
447 * the storage for LODs other than LOD 0 is not needed.
449 assert(info
->levels
== 1);
450 assert(phys_level0_sa
->array_len
== 1);
451 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
453 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
454 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
455 isl_surf_usage_is_stencil(info
->usage
)) {
456 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
457 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
459 * The separate stencil buffer does not support mip mapping,
460 * thus the storage for LODs other than LOD 0 is not needed.
462 assert(info
->levels
== 1);
463 assert(phys_level0_sa
->array_len
== 1);
464 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
467 if (phys_level0_sa
->array_len
== 1) {
468 /* The hardware will never use the QPitch. So choose the most
469 * compact QPitch possible in order to conserve memory.
471 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
474 return ISL_ARRAY_PITCH_SPAN_FULL
;
477 case ISL_DIM_LAYOUT_GEN4_3D
:
478 /* The hardware will never use the QPitch. So choose the most
479 * compact QPitch possible in order to conserve memory.
481 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
484 unreachable("bad isl_dim_layout");
485 return ISL_ARRAY_PITCH_SPAN_FULL
;
489 isl_choose_image_alignment_el(const struct isl_device
*dev
,
490 const struct isl_surf_init_info
*restrict info
,
491 enum isl_tiling tiling
,
492 enum isl_dim_layout dim_layout
,
493 enum isl_msaa_layout msaa_layout
,
494 struct isl_extent3d
*image_align_el
)
496 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
497 if (fmtl
->txc
== ISL_TXC_MCS
) {
498 assert(tiling
== ISL_TILING_Y0
);
501 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
503 * Height, width, and layout of MCS buffer in this case must match with
504 * Render Target height, width, and layout. MCS buffer is tiledY.
506 * To avoid wasting memory, choose the smallest alignment possible:
507 * HALIGN_4 and VALIGN_4.
509 *image_align_el
= isl_extent3d(4, 4, 1);
511 } else if (info
->format
== ISL_FORMAT_HIZ
) {
512 assert(ISL_DEV_GEN(dev
) >= 6);
513 /* HiZ surfaces are always aligned to 16x8 pixels in the primary surface
514 * which works out to 2x2 HiZ elments.
516 *image_align_el
= isl_extent3d(2, 2, 1);
520 if (ISL_DEV_GEN(dev
) >= 9) {
521 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
522 msaa_layout
, image_align_el
);
523 } else if (ISL_DEV_GEN(dev
) >= 8) {
524 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
525 msaa_layout
, image_align_el
);
526 } else if (ISL_DEV_GEN(dev
) >= 7) {
527 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
528 msaa_layout
, image_align_el
);
529 } else if (ISL_DEV_GEN(dev
) >= 6) {
530 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
531 msaa_layout
, image_align_el
);
533 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
534 msaa_layout
, image_align_el
);
538 static enum isl_dim_layout
539 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
540 enum isl_surf_dim logical_dim
,
541 enum isl_tiling tiling
)
543 if (ISL_DEV_GEN(dev
) >= 9) {
544 switch (logical_dim
) {
545 case ISL_SURF_DIM_1D
:
546 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
548 * One-dimensional surfaces use a tiling mode of linear.
549 * Technically, they are not tiled resources, but the Tiled
550 * Resource Mode field in RENDER_SURFACE_STATE is still used to
551 * indicate the alignment requirements for this linear surface
552 * (See 1D Alignment requirements for how 4K and 64KB Tiled
553 * Resource Modes impact alignment). Alternatively, a 1D surface
554 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
557 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
558 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
560 if (tiling
== ISL_TILING_LINEAR
)
561 return ISL_DIM_LAYOUT_GEN9_1D
;
563 return ISL_DIM_LAYOUT_GEN4_2D
;
564 case ISL_SURF_DIM_2D
:
565 case ISL_SURF_DIM_3D
:
566 return ISL_DIM_LAYOUT_GEN4_2D
;
569 switch (logical_dim
) {
570 case ISL_SURF_DIM_1D
:
571 case ISL_SURF_DIM_2D
:
572 return ISL_DIM_LAYOUT_GEN4_2D
;
573 case ISL_SURF_DIM_3D
:
574 return ISL_DIM_LAYOUT_GEN4_3D
;
578 unreachable("bad isl_surf_dim");
579 return ISL_DIM_LAYOUT_GEN4_2D
;
583 * Calculate the physical extent of the surface's first level, in units of
584 * surface samples. The result is aligned to the format's compression block.
587 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
588 const struct isl_surf_init_info
*restrict info
,
589 enum isl_dim_layout dim_layout
,
590 enum isl_tiling tiling
,
591 enum isl_msaa_layout msaa_layout
,
592 struct isl_extent4d
*phys_level0_sa
)
594 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
596 if (isl_format_is_yuv(info
->format
))
597 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
600 case ISL_SURF_DIM_1D
:
601 assert(info
->height
== 1);
602 assert(info
->depth
== 1);
603 assert(info
->samples
== 1);
605 switch (dim_layout
) {
606 case ISL_DIM_LAYOUT_GEN4_3D
:
607 unreachable("bad isl_dim_layout");
609 case ISL_DIM_LAYOUT_GEN9_1D
:
610 case ISL_DIM_LAYOUT_GEN4_2D
:
611 *phys_level0_sa
= (struct isl_extent4d
) {
612 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
615 .a
= info
->array_len
,
621 case ISL_SURF_DIM_2D
:
622 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
624 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
625 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
627 switch (msaa_layout
) {
628 case ISL_MSAA_LAYOUT_NONE
:
629 assert(info
->depth
== 1);
630 assert(info
->samples
== 1);
632 *phys_level0_sa
= (struct isl_extent4d
) {
633 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
634 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
636 .a
= info
->array_len
,
640 case ISL_MSAA_LAYOUT_ARRAY
:
641 assert(info
->depth
== 1);
642 assert(info
->levels
== 1);
643 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
644 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
646 *phys_level0_sa
= (struct isl_extent4d
) {
650 .a
= info
->array_len
* info
->samples
,
654 case ISL_MSAA_LAYOUT_INTERLEAVED
:
655 assert(info
->depth
== 1);
656 assert(info
->levels
== 1);
657 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
659 *phys_level0_sa
= (struct isl_extent4d
) {
663 .a
= info
->array_len
,
666 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
670 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
671 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
676 case ISL_SURF_DIM_3D
:
677 assert(info
->array_len
== 1);
678 assert(info
->samples
== 1);
681 isl_finishme("%s:%s: compression block with depth > 1",
685 switch (dim_layout
) {
686 case ISL_DIM_LAYOUT_GEN9_1D
:
687 unreachable("bad isl_dim_layout");
689 case ISL_DIM_LAYOUT_GEN4_2D
:
690 assert(ISL_DEV_GEN(dev
) >= 9);
692 *phys_level0_sa
= (struct isl_extent4d
) {
693 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
694 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
700 case ISL_DIM_LAYOUT_GEN4_3D
:
701 assert(ISL_DEV_GEN(dev
) < 9);
702 *phys_level0_sa
= (struct isl_extent4d
) {
703 .w
= isl_align(info
->width
, fmtl
->bw
),
704 .h
= isl_align(info
->height
, fmtl
->bh
),
715 * Calculate the pitch between physical array slices, in units of rows of
719 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
720 const struct isl_surf_init_info
*restrict info
,
721 const struct isl_tile_info
*tile_info
,
722 enum isl_dim_layout dim_layout
,
723 enum isl_array_pitch_span array_pitch_span
,
724 const struct isl_extent3d
*image_align_sa
,
725 const struct isl_extent4d
*phys_level0_sa
,
726 const struct isl_extent2d
*phys_slice0_sa
)
728 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
729 uint32_t pitch_sa_rows
= 0;
731 switch (dim_layout
) {
732 case ISL_DIM_LAYOUT_GEN4_2D
:
733 break; /* Handled below */
734 case ISL_DIM_LAYOUT_GEN9_1D
:
735 /* Each row is an array slice */
737 case ISL_DIM_LAYOUT_GEN4_3D
:
738 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
739 return isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
741 unreachable("bad isl_dim_layout");
745 switch (array_pitch_span
) {
746 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
747 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
749 case ISL_ARRAY_PITCH_SPAN_FULL
: {
750 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
751 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
752 * Surfaces >> Surface Arrays.
754 uint32_t H0_sa
= phys_level0_sa
->h
;
755 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
757 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
758 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
761 if (ISL_DEV_GEN(dev
) >= 7) {
762 /* The QPitch equation changed slightly in Ivybridge. */
768 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
770 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
771 (info
->height
% 4 == 1)) {
772 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
773 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
775 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
776 * the value calculated in the equation above , for every
777 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
779 * XXX(chadv): Is the errata natural corollary of the physical
780 * layout of interleaved samples?
785 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
790 assert(pitch_sa_rows
% fmtl
->bh
== 0);
791 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
793 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
795 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
797 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
798 * layout with these alignments in the RT space: Horizontal
799 * Alignment = 128 and Vertical Alignment = 64."
801 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
803 * "For non-multisampled render target's CCS auxiliary surface,
804 * QPitch must be computed with Horizontal Alignment = 128 and
805 * Surface Vertical Alignment = 256. These alignments are only for
806 * CCS buffer and not for associated render target."
808 * The first restriction is already handled by isl_choose_image_alignment_el
809 * but the second restriction, which is an extension of the first, only
810 * applies to qpitch and must be applied here.
812 assert(fmtl
->bh
== 4);
813 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
816 if (ISL_DEV_GEN(dev
) >= 9 &&
817 info
->dim
== ISL_SURF_DIM_3D
&&
818 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
819 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
821 * Tile Mode != Linear: This field must be set to an integer multiple
824 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
827 return pitch_el_rows
;
831 * A variant of isl_calc_phys_slice0_extent_sa() specific to
832 * ISL_DIM_LAYOUT_GEN4_2D.
835 isl_calc_phys_slice0_extent_sa_gen4_2d(
836 const struct isl_device
*dev
,
837 const struct isl_surf_init_info
*restrict info
,
838 enum isl_msaa_layout msaa_layout
,
839 const struct isl_extent3d
*image_align_sa
,
840 const struct isl_extent4d
*phys_level0_sa
,
841 struct isl_extent2d
*phys_slice0_sa
)
843 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
845 assert(phys_level0_sa
->depth
== 1);
847 if (info
->levels
== 1) {
848 /* Do not pad the surface to the image alignment. Instead, pad it only
849 * to the pixel format's block alignment.
851 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
852 * cycles on the below mipmap layout caluclations. Reducing the
853 * alignment here is safe because we later align the row pitch and array
854 * pitch to the tile boundary. It is safe even for
855 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
856 * to accomodate the interleaved samples.
858 * For linear surfaces, reducing the alignment here permits us to later
859 * choose an arbitrary, non-aligned row pitch. If the surface backs
860 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
861 * VkBufferImageCopy::bufferRowLength.
863 *phys_slice0_sa
= (struct isl_extent2d
) {
864 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
865 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
870 uint32_t slice_top_w
= 0;
871 uint32_t slice_bottom_w
= 0;
872 uint32_t slice_left_h
= 0;
873 uint32_t slice_right_h
= 0;
875 uint32_t W0
= phys_level0_sa
->w
;
876 uint32_t H0
= phys_level0_sa
->h
;
878 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
879 uint32_t W
= isl_minify(W0
, l
);
880 uint32_t H
= isl_minify(H0
, l
);
882 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
883 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
900 *phys_slice0_sa
= (struct isl_extent2d
) {
901 .w
= MAX(slice_top_w
, slice_bottom_w
),
902 .h
= MAX(slice_left_h
, slice_right_h
),
907 * A variant of isl_calc_phys_slice0_extent_sa() specific to
908 * ISL_DIM_LAYOUT_GEN4_3D.
911 isl_calc_phys_slice0_extent_sa_gen4_3d(
912 const struct isl_device
*dev
,
913 const struct isl_surf_init_info
*restrict info
,
914 const struct isl_extent3d
*image_align_sa
,
915 const struct isl_extent4d
*phys_level0_sa
,
916 struct isl_extent2d
*phys_slice0_sa
)
918 assert(info
->samples
== 1);
919 assert(phys_level0_sa
->array_len
== 1);
921 uint32_t slice_w
= 0;
922 uint32_t slice_h
= 0;
924 uint32_t W0
= phys_level0_sa
->w
;
925 uint32_t H0
= phys_level0_sa
->h
;
926 uint32_t D0
= phys_level0_sa
->d
;
928 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
929 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
930 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
931 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
933 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
934 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
936 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
937 slice_h
+= level_h
* max_layers_vert
;
940 *phys_slice0_sa
= (struct isl_extent2d
) {
947 * A variant of isl_calc_phys_slice0_extent_sa() specific to
948 * ISL_DIM_LAYOUT_GEN9_1D.
951 isl_calc_phys_slice0_extent_sa_gen9_1d(
952 const struct isl_device
*dev
,
953 const struct isl_surf_init_info
*restrict info
,
954 const struct isl_extent3d
*image_align_sa
,
955 const struct isl_extent4d
*phys_level0_sa
,
956 struct isl_extent2d
*phys_slice0_sa
)
958 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
960 assert(phys_level0_sa
->height
== 1);
961 assert(phys_level0_sa
->depth
== 1);
962 assert(info
->samples
== 1);
963 assert(image_align_sa
->w
>= fmtl
->bw
);
965 uint32_t slice_w
= 0;
966 const uint32_t W0
= phys_level0_sa
->w
;
968 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
969 uint32_t W
= isl_minify(W0
, l
);
970 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
975 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
979 * Calculate the physical extent of the surface's first array slice, in units
980 * of surface samples. If the surface is multi-leveled, then the result will
981 * be aligned to \a image_align_sa.
984 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
985 const struct isl_surf_init_info
*restrict info
,
986 enum isl_dim_layout dim_layout
,
987 enum isl_msaa_layout msaa_layout
,
988 const struct isl_extent3d
*image_align_sa
,
989 const struct isl_extent4d
*phys_level0_sa
,
990 struct isl_extent2d
*phys_slice0_sa
)
992 switch (dim_layout
) {
993 case ISL_DIM_LAYOUT_GEN9_1D
:
994 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
995 image_align_sa
, phys_level0_sa
,
998 case ISL_DIM_LAYOUT_GEN4_2D
:
999 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1000 image_align_sa
, phys_level0_sa
,
1003 case ISL_DIM_LAYOUT_GEN4_3D
:
1004 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
1005 phys_level0_sa
, phys_slice0_sa
);
1011 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1012 const struct isl_tile_info
*tile_info
)
1014 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1015 return tile_info
->phys_extent_B
.width
;
1017 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1018 * RENDER_SURFACE_STATE Surface Pitch (p349):
1020 * - For linear render target surfaces and surfaces accessed with the
1021 * typed data port messages, the pitch must be a multiple of the
1022 * element size for non-YUV surface formats. Pitch must be
1023 * a multiple of 2 * element size for YUV surface formats.
1025 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1026 * ignore because isl doesn't do buffers.]
1028 * - For other linear surfaces, the pitch can be any multiple of
1031 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1032 const uint32_t bs
= fmtl
->bpb
/ 8;
1034 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1035 if (isl_format_is_yuv(surf_info
->format
)) {
1046 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1047 const struct isl_surf_init_info
*info
,
1048 const struct isl_extent2d
*phys_slice0_sa
,
1051 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1052 const uint32_t bs
= fmtl
->bpb
/ 8;
1054 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1056 return isl_align_npot(bs
* (phys_slice0_sa
->w
/ fmtl
->bw
), alignment
);
1060 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1061 const struct isl_surf_init_info
*surf_info
,
1062 const struct isl_tile_info
*tile_info
,
1063 const struct isl_extent2d
*phys_slice0_sa
,
1066 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1068 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1069 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
1071 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1072 const uint32_t total_w_el
= phys_slice0_sa
->width
/ fmtl
->bw
;
1073 const uint32_t total_w_tl
=
1074 isl_align_div(total_w_el
* tile_el_scale
,
1075 tile_info
->logical_extent_el
.width
);
1077 assert(alignment
== tile_info
->phys_extent_B
.width
);
1078 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1082 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1083 const struct isl_surf_init_info
*surf_info
,
1084 const struct isl_tile_info
*tile_info
,
1085 const struct isl_extent2d
*phys_slice0_sa
,
1088 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1089 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_slice0_sa
,
1092 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1093 phys_slice0_sa
, alignment
);
1098 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1099 * size is `bits` bits?
1101 * Hardware pitch fields are offset by 1. For example, if the size of
1102 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1103 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1104 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1107 pitch_in_range(uint32_t n
, uint32_t bits
)
1110 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1114 isl_calc_row_pitch(const struct isl_device
*dev
,
1115 const struct isl_surf_init_info
*surf_info
,
1116 const struct isl_tile_info
*tile_info
,
1117 enum isl_dim_layout dim_layout
,
1118 const struct isl_extent2d
*phys_slice0_sa
,
1119 uint32_t *out_row_pitch
)
1121 const uint32_t alignment
=
1122 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1124 const uint32_t min_row_pitch
=
1125 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_slice0_sa
,
1128 uint32_t row_pitch
= min_row_pitch
;
1130 if (surf_info
->row_pitch
!= 0) {
1131 row_pitch
= surf_info
->row_pitch
;
1133 if (row_pitch
< min_row_pitch
)
1136 if (row_pitch
% alignment
!= 0)
1140 const uint32_t row_pitch_tiles
= row_pitch
/ tile_info
->phys_extent_B
.width
;
1145 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1146 /* SurfacePitch is ignored for this layout. */
1150 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1151 ISL_SURF_USAGE_TEXTURE_BIT
|
1152 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1153 !pitch_in_range(row_pitch
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1156 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1157 ISL_SURF_USAGE_MCS_BIT
)) &&
1158 !pitch_in_range(row_pitch_tiles
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1161 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1162 !pitch_in_range(row_pitch
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1165 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1166 !pitch_in_range(row_pitch
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1169 if (surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
)
1170 isl_finishme("validate row pitch of stencil surfaces");
1173 *out_row_pitch
= row_pitch
;
1178 * Calculate and apply any padding required for the surface.
1180 * @param[inout] total_h_el is updated with the new height
1181 * @param[out] pad_bytes is overwritten with additional padding requirements.
1184 isl_apply_surface_padding(const struct isl_device
*dev
,
1185 const struct isl_surf_init_info
*restrict info
,
1186 const struct isl_tile_info
*tile_info
,
1187 uint32_t *total_h_el
,
1188 uint32_t *pad_bytes
)
1190 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1194 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1195 * Formats >> Surface Padding Requirements >> Render Target and Media
1198 * The data port accesses data (pixels) outside of the surface if they
1199 * are contained in the same cache request as pixels that are within the
1200 * surface. These pixels will not be returned by the requesting message,
1201 * however if these pixels lie outside of defined pages in the GTT,
1202 * a GTT error will result when the cache request is processed. In
1203 * order to avoid these GTT errors, “padding” at the bottom of the
1204 * surface is sometimes necessary.
1206 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
1207 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
1209 * ... Lots of padding requirements, all listed separately below.
1212 /* We can safely ignore the first padding requirement, quoted below,
1213 * because isl doesn't do buffers.
1215 * - [pre-BDW] For buffers, which have no inherent “height,” padding
1216 * requirements are different. A buffer must be padded to the next
1217 * multiple of 256 array elements, with an additional 16 bytes added
1218 * beyond that to account for the L1 cache line.
1222 * - For compressed textures [...], padding at the bottom of the surface
1223 * is to an even compressed row.
1225 if (isl_format_is_compressed(info
->format
))
1226 *total_h_el
= isl_align(*total_h_el
, 2);
1229 * - For cube surfaces, an additional two rows of padding are required
1230 * at the bottom of the surface.
1232 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
1236 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
1237 * additional padding is required. These surfaces require an extra row
1238 * plus 16 bytes of padding at the bottom in addition to the general
1239 * padding requirements.
1241 if (isl_format_is_yuv(info
->format
) &&
1242 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1248 * - For linear surfaces, additional padding of 64 bytes is required at
1249 * the bottom of the surface. This is in addition to the padding
1252 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1255 /* The below text weakens, not strengthens, the padding requirements for
1256 * linear surfaces. Therefore we can safely ignore it.
1258 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1259 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1260 * padding requirement is to the next aligned 64-byte boundary beyond
1261 * the end of the surface. The rest of the padding requirements
1262 * documented above do not apply to these surfaces.
1266 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1267 * height % 4 != 0, the surface must be padded with
1268 * 4-(height % 4)*Surface Pitch # of bytes.
1270 if (ISL_DEV_GEN(dev
) >= 9 &&
1271 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1272 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1273 *total_h_el
= isl_align(*total_h_el
, 4);
1277 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1278 * to 4 times the Surface Pitch # of bytes
1280 if (ISL_DEV_GEN(dev
) >= 9 &&
1281 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1282 info
->dim
== ISL_SURF_DIM_1D
) {
1288 isl_surf_init_s(const struct isl_device
*dev
,
1289 struct isl_surf
*surf
,
1290 const struct isl_surf_init_info
*restrict info
)
1292 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1294 const struct isl_extent4d logical_level0_px
= {
1298 .a
= info
->array_len
,
1301 enum isl_tiling tiling
;
1302 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1305 struct isl_tile_info tile_info
;
1306 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1308 const enum isl_dim_layout dim_layout
=
1309 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
);
1311 enum isl_msaa_layout msaa_layout
;
1312 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1315 struct isl_extent3d image_align_el
;
1316 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1319 struct isl_extent3d image_align_sa
=
1320 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1322 struct isl_extent4d phys_level0_sa
;
1323 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1325 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1326 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1328 enum isl_array_pitch_span array_pitch_span
=
1329 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1331 struct isl_extent2d phys_slice0_sa
;
1332 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1333 &image_align_sa
, &phys_level0_sa
,
1335 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1336 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1338 const uint32_t array_pitch_el_rows
=
1339 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1340 array_pitch_span
, &image_align_sa
,
1341 &phys_level0_sa
, &phys_slice0_sa
);
1343 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1346 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1349 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1350 &phys_slice0_sa
, &row_pitch
))
1353 uint32_t size
, base_alignment
;
1354 if (tiling
== ISL_TILING_LINEAR
) {
1355 size
= row_pitch
* total_h_el
+ pad_bytes
;
1357 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1359 * "The Base Address for linear render target surfaces and surfaces
1360 * accessed with the typed surface read/write data port messages must
1361 * be element-size aligned, for non-YUV surface formats, or a
1362 * multiple of 2 element-sizes for YUV surface formats. Other linear
1363 * surfaces have no alignment requirements (byte alignment is
1366 base_alignment
= MAX(1, info
->min_alignment
);
1367 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1368 if (isl_format_is_yuv(info
->format
)) {
1369 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1371 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1374 base_alignment
= isl_round_up_to_power_of_two(base_alignment
);
1376 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1377 const uint32_t total_h_tl
=
1378 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1380 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1382 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1383 tile_info
.phys_extent_B
.height
;
1384 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1385 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1388 *surf
= (struct isl_surf
) {
1390 .dim_layout
= dim_layout
,
1391 .msaa_layout
= msaa_layout
,
1393 .format
= info
->format
,
1395 .levels
= info
->levels
,
1396 .samples
= info
->samples
,
1398 .image_alignment_el
= image_align_el
,
1399 .logical_level0_px
= logical_level0_px
,
1400 .phys_level0_sa
= phys_level0_sa
,
1403 .alignment
= base_alignment
,
1404 .row_pitch
= row_pitch
,
1405 .array_pitch_el_rows
= array_pitch_el_rows
,
1406 .array_pitch_span
= array_pitch_span
,
1408 .usage
= info
->usage
,
1415 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1416 struct isl_tile_info
*tile_info
)
1418 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1419 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1423 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1424 const struct isl_surf
*surf
,
1425 struct isl_surf
*hiz_surf
)
1427 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1429 /* Multisampled depth is always interleaved */
1430 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1431 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1433 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1435 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1436 * Target View Extent, and Depth Coordinate Offset X/Y of the
1437 * hierarchical depth buffer are inherited from the depth buffer. The
1438 * height and width of the hierarchical depth buffer that must be
1439 * allocated are computed by the following formulas, where HZ is the
1440 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1441 * Z_Width, and Z_Depth values given in these formulas are those present
1442 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1444 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1445 * being applied to the table below if Number of Multisamples is set to
1446 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1447 * Z_Width must be multiplied by 4 before being applied to the table
1448 * below if Number of Multisamples is set to NUMSAMPLES_8."
1450 * In the Sky Lake PRM, the second paragraph is replaced with this:
1452 * "The Z_Height and Z_Width values must equal those present in
1453 * 3DSTATE_DEPTH_BUFFER incremented by one."
1455 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1456 * block corresponds to a region of 8x4 samples in the primary depth
1457 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1458 * a region of 8x4 pixels in the primary depth surface regardless of the
1459 * number of samples. The dimensions of a HiZ block in both pixels and
1460 * samples are given in the table below:
1462 * | SNB - BDW | SKL+
1463 * ------+-----------+-------------
1464 * 1x | 8 x 4 sa | 8 x 4 sa
1465 * MSAA | 8 x 4 px | 8 x 4 px
1466 * ------+-----------+-------------
1467 * 2x | 8 x 4 sa | 16 x 4 sa
1468 * MSAA | 4 x 4 px | 8 x 4 px
1469 * ------+-----------+-------------
1470 * 4x | 8 x 4 sa | 16 x 8 sa
1471 * MSAA | 4 x 2 px | 8 x 4 px
1472 * ------+-----------+-------------
1473 * 8x | 8 x 4 sa | 32 x 8 sa
1474 * MSAA | 2 x 2 px | 8 x 4 px
1475 * ------+-----------+-------------
1476 * 16x | N/A | 32 x 16 sa
1477 * MSAA | N/A | 8 x 4 px
1478 * ------+-----------+-------------
1480 * There are a number of different ways that this discrepency could be
1481 * handled. The way we have chosen is to simply make MSAA HiZ have the
1482 * same number of samples as the parent surface pre-Sky Lake and always be
1483 * single-sampled on Sky Lake and above. Since the block sizes of
1484 * compressed formats are given in samples, this neatly handles everything
1485 * without the need for additional HiZ formats with different block sizes
1488 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1490 return isl_surf_init(dev
, hiz_surf
,
1492 .format
= ISL_FORMAT_HIZ
,
1493 .width
= surf
->logical_level0_px
.width
,
1494 .height
= surf
->logical_level0_px
.height
,
1495 .depth
= surf
->logical_level0_px
.depth
,
1496 .levels
= surf
->levels
,
1497 .array_len
= surf
->logical_level0_px
.array_len
,
1499 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1500 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1504 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1505 const struct isl_surf
*surf
,
1506 struct isl_surf
*mcs_surf
)
1508 /* It must be multisampled with an array layout */
1509 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1511 /* The following are true of all multisampled surfaces */
1512 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1513 assert(surf
->levels
== 1);
1514 assert(surf
->logical_level0_px
.depth
== 1);
1516 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1517 * bits which means the maximum pitch of a compression surface is 512
1518 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1519 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1520 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1521 * and 8x, we have enough room for the full 16k supported by the hardware.
1523 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1526 enum isl_format mcs_format
;
1527 switch (surf
->samples
) {
1528 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1529 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1530 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1531 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1533 unreachable("Invalid sample count");
1536 return isl_surf_init(dev
, mcs_surf
,
1537 .dim
= ISL_SURF_DIM_2D
,
1538 .format
= mcs_format
,
1539 .width
= surf
->logical_level0_px
.width
,
1540 .height
= surf
->logical_level0_px
.height
,
1543 .array_len
= surf
->logical_level0_px
.array_len
,
1544 .samples
= 1, /* MCS surfaces are really single-sampled */
1545 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1546 .tiling_flags
= ISL_TILING_Y0_BIT
);
1550 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1551 const struct isl_surf
*surf
,
1552 struct isl_surf
*ccs_surf
)
1554 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1555 assert(ISL_DEV_GEN(dev
) >= 7);
1557 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1560 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1563 if (isl_format_is_compressed(surf
->format
))
1566 /* TODO: More conditions where it can fail. */
1568 enum isl_format ccs_format
;
1569 if (ISL_DEV_GEN(dev
) >= 9) {
1570 if (!isl_tiling_is_any_y(surf
->tiling
))
1573 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1574 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1575 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1576 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1580 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1581 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1582 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1583 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1584 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1588 } else if (surf
->tiling
== ISL_TILING_X
) {
1589 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1590 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1591 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1592 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1600 return isl_surf_init(dev
, ccs_surf
,
1602 .format
= ccs_format
,
1603 .width
= surf
->logical_level0_px
.width
,
1604 .height
= surf
->logical_level0_px
.height
,
1605 .depth
= surf
->logical_level0_px
.depth
,
1606 .levels
= surf
->levels
,
1607 .array_len
= surf
->logical_level0_px
.array_len
,
1609 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1610 .tiling_flags
= ISL_TILING_CCS_BIT
);
1614 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1615 const struct isl_surf_fill_state_info
*restrict info
)
1618 isl_surf_usage_flags_t _base_usage
=
1619 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1620 ISL_SURF_USAGE_TEXTURE_BIT
|
1621 ISL_SURF_USAGE_STORAGE_BIT
);
1622 /* They may only specify one of the above bits at a time */
1623 assert(__builtin_popcount(_base_usage
) == 1);
1624 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1625 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1628 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1629 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1630 info
->surf
->logical_level0_px
.depth
);
1632 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1633 info
->surf
->logical_level0_px
.array_len
);
1636 switch (ISL_DEV_GEN(dev
)) {
1638 if (ISL_DEV_IS_G4X(dev
)) {
1639 /* G45 surface state is the same as gen5 */
1640 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1642 isl_gen4_surf_fill_state_s(dev
, state
, info
);
1646 isl_gen5_surf_fill_state_s(dev
, state
, info
);
1649 isl_gen6_surf_fill_state_s(dev
, state
, info
);
1652 if (ISL_DEV_IS_HASWELL(dev
)) {
1653 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1655 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1659 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1662 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1665 assert(!"Cannot fill surface state for this gen");
1670 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1671 const struct isl_buffer_fill_state_info
*restrict info
)
1673 switch (ISL_DEV_GEN(dev
)) {
1676 /* Gen 4-5 are all the same when it comes to buffer surfaces */
1677 isl_gen5_buffer_fill_state_s(state
, info
);
1680 isl_gen6_buffer_fill_state_s(state
, info
);
1683 if (ISL_DEV_IS_HASWELL(dev
)) {
1684 isl_gen75_buffer_fill_state_s(state
, info
);
1686 isl_gen7_buffer_fill_state_s(state
, info
);
1690 isl_gen8_buffer_fill_state_s(state
, info
);
1693 isl_gen9_buffer_fill_state_s(state
, info
);
1696 assert(!"Cannot fill surface state for this gen");
1701 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1702 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1704 if (info
->depth_surf
&& info
->stencil_surf
) {
1705 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1706 assert(info
->depth_surf
== info
->stencil_surf
);
1707 assert(info
->depth_address
== info
->stencil_address
);
1709 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1712 if (info
->depth_surf
) {
1713 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1714 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1715 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1716 info
->depth_surf
->logical_level0_px
.depth
);
1718 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1719 info
->depth_surf
->logical_level0_px
.array_len
);
1723 if (info
->stencil_surf
) {
1724 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1725 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1726 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1727 info
->stencil_surf
->logical_level0_px
.depth
);
1729 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1730 info
->stencil_surf
->logical_level0_px
.array_len
);
1734 switch (ISL_DEV_GEN(dev
)) {
1736 if (ISL_DEV_IS_G4X(dev
)) {
1737 /* G45 surface state is the same as gen5 */
1738 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1740 isl_gen4_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1744 isl_gen5_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1747 isl_gen6_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1750 if (ISL_DEV_IS_HASWELL(dev
)) {
1751 isl_gen75_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1753 isl_gen7_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1757 isl_gen8_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1760 isl_gen9_emit_depth_stencil_hiz_s(dev
, batch
, info
);
1763 assert(!"Cannot fill surface state for this gen");
1768 * A variant of isl_surf_get_image_offset_sa() specific to
1769 * ISL_DIM_LAYOUT_GEN4_2D.
1772 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1773 uint32_t level
, uint32_t logical_array_layer
,
1774 uint32_t *x_offset_sa
,
1775 uint32_t *y_offset_sa
)
1777 assert(level
< surf
->levels
);
1778 if (surf
->dim
== ISL_SURF_DIM_3D
)
1779 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1781 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1783 const struct isl_extent3d image_align_sa
=
1784 isl_surf_get_image_alignment_sa(surf
);
1786 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1787 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1789 const uint32_t phys_layer
= logical_array_layer
*
1790 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1793 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1795 for (uint32_t l
= 0; l
< level
; ++l
) {
1797 uint32_t W
= isl_minify(W0
, l
);
1798 x
+= isl_align_npot(W
, image_align_sa
.w
);
1800 uint32_t H
= isl_minify(H0
, l
);
1801 y
+= isl_align_npot(H
, image_align_sa
.h
);
1810 * A variant of isl_surf_get_image_offset_sa() specific to
1811 * ISL_DIM_LAYOUT_GEN4_3D.
1814 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1815 uint32_t level
, uint32_t logical_z_offset_px
,
1816 uint32_t *x_offset_sa
,
1817 uint32_t *y_offset_sa
)
1819 assert(level
< surf
->levels
);
1820 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1821 assert(surf
->phys_level0_sa
.array_len
== 1);
1822 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1824 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1825 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1826 assert(surf
->phys_level0_sa
.array_len
== 6);
1827 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
1830 const struct isl_extent3d image_align_sa
=
1831 isl_surf_get_image_alignment_sa(surf
);
1833 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1834 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1835 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1836 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
1841 for (uint32_t l
= 0; l
< level
; ++l
) {
1842 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1843 const uint32_t level_d
=
1844 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
1846 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1848 y
+= level_h
* max_layers_vert
;
1851 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1852 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1853 const uint32_t level_d
=
1854 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
1857 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1859 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1860 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1867 * A variant of isl_surf_get_image_offset_sa() specific to
1868 * ISL_DIM_LAYOUT_GEN9_1D.
1871 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1872 uint32_t level
, uint32_t layer
,
1873 uint32_t *x_offset_sa
,
1874 uint32_t *y_offset_sa
)
1876 assert(level
< surf
->levels
);
1877 assert(layer
< surf
->phys_level0_sa
.array_len
);
1878 assert(surf
->phys_level0_sa
.height
== 1);
1879 assert(surf
->phys_level0_sa
.depth
== 1);
1880 assert(surf
->samples
== 1);
1882 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1883 const struct isl_extent3d image_align_sa
=
1884 isl_surf_get_image_alignment_sa(surf
);
1888 for (uint32_t l
= 0; l
< level
; ++l
) {
1889 uint32_t W
= isl_minify(W0
, l
);
1890 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1896 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1900 * Calculate the offset, in units of surface samples, to a subimage in the
1903 * @invariant level < surface levels
1904 * @invariant logical_array_layer < logical array length of surface
1905 * @invariant logical_z_offset_px < logical depth of surface at level
1908 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1910 uint32_t logical_array_layer
,
1911 uint32_t logical_z_offset_px
,
1912 uint32_t *x_offset_sa
,
1913 uint32_t *y_offset_sa
)
1915 assert(level
< surf
->levels
);
1916 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1917 assert(logical_z_offset_px
1918 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1920 switch (surf
->dim_layout
) {
1921 case ISL_DIM_LAYOUT_GEN9_1D
:
1922 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1923 x_offset_sa
, y_offset_sa
);
1925 case ISL_DIM_LAYOUT_GEN4_2D
:
1926 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1927 + logical_z_offset_px
,
1928 x_offset_sa
, y_offset_sa
);
1930 case ISL_DIM_LAYOUT_GEN4_3D
:
1931 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
1932 logical_z_offset_px
,
1933 x_offset_sa
, y_offset_sa
);
1937 unreachable("not reached");
1942 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1944 uint32_t logical_array_layer
,
1945 uint32_t logical_z_offset_px
,
1946 uint32_t *x_offset_el
,
1947 uint32_t *y_offset_el
)
1949 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1951 assert(level
< surf
->levels
);
1952 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1953 assert(logical_z_offset_px
1954 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1956 uint32_t x_offset_sa
, y_offset_sa
;
1957 isl_surf_get_image_offset_sa(surf
, level
,
1958 logical_array_layer
,
1959 logical_z_offset_px
,
1963 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1964 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1968 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
1971 uint32_t total_x_offset_el
,
1972 uint32_t total_y_offset_el
,
1973 uint32_t *base_address_offset
,
1974 uint32_t *x_offset_el
,
1975 uint32_t *y_offset_el
)
1977 if (tiling
== ISL_TILING_LINEAR
) {
1978 *base_address_offset
= total_y_offset_el
* row_pitch
+
1979 total_x_offset_el
* bs
;
1985 const uint32_t bpb
= bs
* 8;
1987 struct isl_tile_info tile_info
;
1988 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
1990 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1992 /* For non-power-of-two formats, we need the address to be both tile and
1993 * element-aligned. The easiest way to achieve this is to work with a tile
1994 * that is three times as wide as the regular tile.
1996 * The tile info returned by get_tile_info has a logical size that is an
1997 * integer number of tile_info.format_bpb size elements. To scale the
1998 * tile, we scale up the physical width and then treat the logical tile
1999 * size as if it has bpb size elements.
2001 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2002 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2004 /* Compute the offset into the tile */
2005 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2006 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2008 /* Compute the offset of the tile in units of whole tiles */
2009 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2010 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2012 *base_address_offset
=
2013 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
2014 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2018 isl_surf_get_depth_format(const struct isl_device
*dev
,
2019 const struct isl_surf
*surf
)
2021 /* Support for separate stencil buffers began in gen5. Support for
2022 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2023 * those that supported separate and interleaved stencil, were gen5 and
2026 * For a list of all available formats, see the Sandybridge PRM >> Volume
2027 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2031 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2033 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2036 assert(ISL_DEV_GEN(dev
) < 7);
2038 switch (surf
->format
) {
2040 unreachable("bad isl depth format");
2041 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2042 assert(ISL_DEV_GEN(dev
) < 7);
2043 return 0; /* D32_FLOAT_S8X24_UINT */
2044 case ISL_FORMAT_R32_FLOAT
:
2045 assert(!has_stencil
);
2046 return 1; /* D32_FLOAT */
2047 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2049 assert(ISL_DEV_GEN(dev
) < 7);
2050 return 2; /* D24_UNORM_S8_UINT */
2052 assert(ISL_DEV_GEN(dev
) >= 5);
2053 return 3; /* D24_UNORM_X8_UINT */
2055 case ISL_FORMAT_R16_UNORM
:
2056 assert(!has_stencil
);
2057 return 5; /* D16_UNORM */