2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "genxml/genX_bits.h"
39 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
40 uint32_t yt1
, uint32_t yt2
,
41 char *dst
, const char *src
,
42 uint32_t dst_pitch
, int32_t src_pitch
,
44 enum isl_tiling tiling
,
45 isl_memcpy_type copy_type
)
48 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
49 _isl_memcpy_linear_to_tiled_sse41(
50 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
56 _isl_memcpy_linear_to_tiled(
57 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
62 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
63 uint32_t yt1
, uint32_t yt2
,
64 char *dst
, const char *src
,
65 int32_t dst_pitch
, uint32_t src_pitch
,
67 enum isl_tiling tiling
,
68 isl_memcpy_type copy_type
)
71 if (copy_type
== ISL_MEMCPY_STREAMING_LOAD
) {
72 _isl_memcpy_tiled_to_linear_sse41(
73 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
79 _isl_memcpy_tiled_to_linear(
80 xt1
, xt2
, yt1
, yt2
, dst
, src
, dst_pitch
, src_pitch
, has_swizzling
,
84 void PRINTFLIKE(3, 4) UNUSED
85 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
91 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
94 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
98 isl_device_init(struct isl_device
*dev
,
99 const struct gen_device_info
*info
,
100 bool has_bit6_swizzling
)
102 /* Gen8+ don't have bit6 swizzling, ensure callsite is not confused. */
103 assert(!(has_bit6_swizzling
&& info
->gen
>= 8));
106 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
107 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
109 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
110 * device properties at buildtime. Verify that the macros with the device
111 * properties chosen during runtime.
113 ISL_DEV_GEN_SANITIZE(dev
);
114 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
116 /* Did we break hiz or stencil? */
117 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
118 assert(info
->has_hiz_and_separate_stencil
);
119 if (info
->must_use_separate_stencil
)
120 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
122 dev
->ss
.size
= RENDER_SURFACE_STATE_length(info
) * 4;
123 dev
->ss
.align
= isl_align(dev
->ss
.size
, 32);
125 dev
->ss
.clear_color_state_size
= CLEAR_COLOR_length(info
) * 4;
126 dev
->ss
.clear_color_state_offset
=
127 RENDER_SURFACE_STATE_ClearValueAddress_start(info
) / 32 * 4;
129 dev
->ss
.clear_value_size
=
130 isl_align(RENDER_SURFACE_STATE_RedClearColor_bits(info
) +
131 RENDER_SURFACE_STATE_GreenClearColor_bits(info
) +
132 RENDER_SURFACE_STATE_BlueClearColor_bits(info
) +
133 RENDER_SURFACE_STATE_AlphaClearColor_bits(info
), 32) / 8;
135 dev
->ss
.clear_value_offset
=
136 RENDER_SURFACE_STATE_RedClearColor_start(info
) / 32 * 4;
138 assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) % 8 == 0);
139 dev
->ss
.addr_offset
=
140 RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info
) / 8;
142 /* The "Auxiliary Surface Base Address" field starts a bit higher up
143 * because the bottom 12 bits are used for other things. Round down to
144 * the nearest dword before.
146 dev
->ss
.aux_addr_offset
=
147 (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info
) & ~31) / 8;
149 dev
->ds
.size
= _3DSTATE_DEPTH_BUFFER_length(info
) * 4;
150 assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
151 dev
->ds
.depth_offset
=
152 _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
154 if (dev
->use_separate_stencil
) {
155 dev
->ds
.size
+= _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
156 _3DSTATE_HIER_DEPTH_BUFFER_length(info
) * 4 +
157 _3DSTATE_CLEAR_PARAMS_length(info
) * 4;
159 assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
160 dev
->ds
.stencil_offset
=
161 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
162 _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info
) / 8;
164 assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) % 8 == 0);
166 _3DSTATE_DEPTH_BUFFER_length(info
) * 4 +
167 _3DSTATE_STENCIL_BUFFER_length(info
) * 4 +
168 _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info
) / 8;
170 dev
->ds
.stencil_offset
= 0;
171 dev
->ds
.hiz_offset
= 0;
176 * @brief Query the set of multisamples supported by the device.
178 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
181 isl_sample_count_mask_t ATTRIBUTE_CONST
182 isl_device_get_sample_counts(struct isl_device
*dev
)
184 if (ISL_DEV_GEN(dev
) >= 9) {
185 return ISL_SAMPLE_COUNT_1_BIT
|
186 ISL_SAMPLE_COUNT_2_BIT
|
187 ISL_SAMPLE_COUNT_4_BIT
|
188 ISL_SAMPLE_COUNT_8_BIT
|
189 ISL_SAMPLE_COUNT_16_BIT
;
190 } else if (ISL_DEV_GEN(dev
) >= 8) {
191 return ISL_SAMPLE_COUNT_1_BIT
|
192 ISL_SAMPLE_COUNT_2_BIT
|
193 ISL_SAMPLE_COUNT_4_BIT
|
194 ISL_SAMPLE_COUNT_8_BIT
;
195 } else if (ISL_DEV_GEN(dev
) >= 7) {
196 return ISL_SAMPLE_COUNT_1_BIT
|
197 ISL_SAMPLE_COUNT_4_BIT
|
198 ISL_SAMPLE_COUNT_8_BIT
;
199 } else if (ISL_DEV_GEN(dev
) >= 6) {
200 return ISL_SAMPLE_COUNT_1_BIT
|
201 ISL_SAMPLE_COUNT_4_BIT
;
203 return ISL_SAMPLE_COUNT_1_BIT
;
208 * @param[out] info is written only on success
211 isl_tiling_get_info(enum isl_tiling tiling
,
213 struct isl_tile_info
*tile_info
)
215 const uint32_t bs
= format_bpb
/ 8;
216 struct isl_extent2d logical_el
, phys_B
;
218 if (tiling
!= ISL_TILING_LINEAR
&& !isl_is_pow2(format_bpb
)) {
219 /* It is possible to have non-power-of-two formats in a tiled buffer.
220 * The easiest way to handle this is to treat the tile as if it is three
221 * times as wide. This way no pixel will ever cross a tile boundary.
222 * This really only works on legacy X and Y tiling formats.
224 assert(tiling
== ISL_TILING_X
|| tiling
== ISL_TILING_Y0
);
225 assert(bs
% 3 == 0 && isl_is_pow2(format_bpb
/ 3));
226 isl_tiling_get_info(tiling
, format_bpb
/ 3, tile_info
);
231 case ISL_TILING_LINEAR
:
233 logical_el
= isl_extent2d(1, 1);
234 phys_B
= isl_extent2d(bs
, 1);
239 logical_el
= isl_extent2d(512 / bs
, 8);
240 phys_B
= isl_extent2d(512, 8);
245 logical_el
= isl_extent2d(128 / bs
, 32);
246 phys_B
= isl_extent2d(128, 32);
251 logical_el
= isl_extent2d(64, 64);
252 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
254 * "If the surface is a stencil buffer (and thus has Tile Mode set
255 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
256 * computed based on width, as the stencil buffer is stored with two
259 * This, together with the fact that stencil buffers are referred to as
260 * being Y-tiled in the PRMs for older hardware implies that the
261 * physical size of a W-tile is actually the same as for a Y-tile.
263 phys_B
= isl_extent2d(128, 32);
267 case ISL_TILING_Ys
: {
268 bool is_Ys
= tiling
== ISL_TILING_Ys
;
271 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
272 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
274 logical_el
= isl_extent2d(width
/ bs
, height
);
275 phys_B
= isl_extent2d(width
, height
);
280 /* HiZ buffers are required to have ISL_FORMAT_HIZ which is an 8x4
281 * 128bpb format. The tiling has the same physical dimensions as
282 * Y-tiling but actually has two HiZ columns per Y-tiled column.
285 logical_el
= isl_extent2d(16, 16);
286 phys_B
= isl_extent2d(128, 32);
290 /* CCS surfaces are required to have one of the GENX_CCS_* formats which
291 * have a block size of 1 or 2 bits per block and each CCS element
292 * corresponds to one cache-line pair in the main surface. From the Sky
293 * Lake PRM Vol. 12 in the section on planes:
295 * "The Color Control Surface (CCS) contains the compression status
296 * of the cache-line pairs. The compression state of the cache-line
297 * pair is specified by 2 bits in the CCS. Each CCS cache-line
298 * represents an area on the main surface of 16x16 sets of 128 byte
299 * Y-tiled cache-line-pairs. CCS is always Y tiled."
301 * The CCS being Y-tiled implies that it's an 8x8 grid of cache-lines.
302 * Since each cache line corresponds to a 16x16 set of cache-line pairs,
303 * that yields total tile area of 128x128 cache-line pairs or CCS
304 * elements. On older hardware, each CCS element is 1 bit and the tile
305 * is 128x256 elements.
307 assert(format_bpb
== 1 || format_bpb
== 2);
308 logical_el
= isl_extent2d(128, 256 / format_bpb
);
309 phys_B
= isl_extent2d(128, 32);
313 unreachable("not reached");
316 *tile_info
= (struct isl_tile_info
) {
318 .format_bpb
= format_bpb
,
319 .logical_extent_el
= logical_el
,
320 .phys_extent_B
= phys_B
,
325 isl_color_value_is_zero(union isl_color_value value
,
326 enum isl_format format
)
328 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
330 #define RETURN_FALSE_IF_NOT_0(c, i) \
331 if (fmtl->channels.c.bits && value.u32[i] != 0) \
334 RETURN_FALSE_IF_NOT_0(r
, 0);
335 RETURN_FALSE_IF_NOT_0(g
, 1);
336 RETURN_FALSE_IF_NOT_0(b
, 2);
337 RETURN_FALSE_IF_NOT_0(a
, 3);
339 #undef RETURN_FALSE_IF_NOT_0
345 isl_color_value_is_zero_one(union isl_color_value value
,
346 enum isl_format format
)
348 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
350 #define RETURN_FALSE_IF_NOT_0_1(c, i, field) \
351 if (fmtl->channels.c.bits && value.field[i] != 0 && value.field[i] != 1) \
354 if (isl_format_has_int_channel(format
)) {
355 RETURN_FALSE_IF_NOT_0_1(r
, 0, u32
);
356 RETURN_FALSE_IF_NOT_0_1(g
, 1, u32
);
357 RETURN_FALSE_IF_NOT_0_1(b
, 2, u32
);
358 RETURN_FALSE_IF_NOT_0_1(a
, 3, u32
);
360 RETURN_FALSE_IF_NOT_0_1(r
, 0, f32
);
361 RETURN_FALSE_IF_NOT_0_1(g
, 1, f32
);
362 RETURN_FALSE_IF_NOT_0_1(b
, 2, f32
);
363 RETURN_FALSE_IF_NOT_0_1(a
, 3, f32
);
366 #undef RETURN_FALSE_IF_NOT_0_1
372 * @param[out] tiling is set only on success
375 isl_surf_choose_tiling(const struct isl_device
*dev
,
376 const struct isl_surf_init_info
*restrict info
,
377 enum isl_tiling
*tiling
)
379 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
381 /* HiZ surfaces always use the HiZ tiling */
382 if (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) {
383 assert(info
->format
== ISL_FORMAT_HIZ
);
384 assert(tiling_flags
== ISL_TILING_HIZ_BIT
);
385 *tiling
= ISL_TILING_HIZ
;
389 /* CCS surfaces always use the CCS tiling */
390 if (info
->usage
& ISL_SURF_USAGE_CCS_BIT
) {
391 assert(isl_format_get_layout(info
->format
)->txc
== ISL_TXC_CCS
);
392 assert(tiling_flags
== ISL_TILING_CCS_BIT
);
393 *tiling
= ISL_TILING_CCS
;
397 if (ISL_DEV_GEN(dev
) >= 6) {
398 isl_gen6_filter_tiling(dev
, info
, &tiling_flags
);
400 isl_gen4_filter_tiling(dev
, info
, &tiling_flags
);
403 #define CHOOSE(__tiling) \
405 if (tiling_flags & (1u << (__tiling))) { \
406 *tiling = (__tiling); \
411 /* Of the tiling modes remaining, choose the one that offers the best
415 if (info
->dim
== ISL_SURF_DIM_1D
) {
416 /* Prefer linear for 1D surfaces because they do not benefit from
417 * tiling. To the contrary, tiling leads to wasted memory and poor
418 * memory locality due to the swizzling and alignment restrictions
419 * required in tiled surfaces.
421 CHOOSE(ISL_TILING_LINEAR
);
424 CHOOSE(ISL_TILING_Ys
);
425 CHOOSE(ISL_TILING_Yf
);
426 CHOOSE(ISL_TILING_Y0
);
427 CHOOSE(ISL_TILING_X
);
428 CHOOSE(ISL_TILING_W
);
429 CHOOSE(ISL_TILING_LINEAR
);
433 /* No tiling mode accomodates the inputs. */
438 isl_choose_msaa_layout(const struct isl_device
*dev
,
439 const struct isl_surf_init_info
*info
,
440 enum isl_tiling tiling
,
441 enum isl_msaa_layout
*msaa_layout
)
443 if (ISL_DEV_GEN(dev
) >= 8) {
444 return isl_gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
445 } else if (ISL_DEV_GEN(dev
) >= 7) {
446 return isl_gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
447 } else if (ISL_DEV_GEN(dev
) >= 6) {
448 return isl_gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
450 return isl_gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
455 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
)
457 assert(isl_is_pow2(samples
));
459 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
462 * If the surface is multisampled and it is a depth or stencil surface
463 * or Multisampled Surface StorageFormat in SURFACE_STATE is
464 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
467 return (struct isl_extent2d
) {
468 .width
= 1 << ((ffs(samples
) - 0) / 2),
469 .height
= 1 << ((ffs(samples
) - 1) / 2),
474 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
475 uint32_t *width
, uint32_t *height
)
477 const struct isl_extent2d px_size_sa
=
478 isl_get_interleaved_msaa_px_size_sa(samples
);
481 *width
= isl_align(*width
, 2) * px_size_sa
.width
;
483 *height
= isl_align(*height
, 2) * px_size_sa
.height
;
486 static enum isl_array_pitch_span
487 isl_choose_array_pitch_span(const struct isl_device
*dev
,
488 const struct isl_surf_init_info
*restrict info
,
489 enum isl_dim_layout dim_layout
,
490 const struct isl_extent4d
*phys_level0_sa
)
492 switch (dim_layout
) {
493 case ISL_DIM_LAYOUT_GEN9_1D
:
494 case ISL_DIM_LAYOUT_GEN4_2D
:
495 if (ISL_DEV_GEN(dev
) >= 8) {
496 /* QPitch becomes programmable in Broadwell. So choose the
497 * most compact QPitch possible in order to conserve memory.
499 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
500 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
502 * - Software must ensure that this field is set to a value
503 * sufficiently large such that the array slices in the surface
504 * do not overlap. Refer to the Memory Data Formats section for
505 * information on how surfaces are stored in memory.
507 * - This field specifies the distance in rows between array
508 * slices. It is used only in the following cases:
510 * - Surface Array is enabled OR
511 * - Number of Mulitsamples is not NUMSAMPLES_1 and
512 * Multisampled Surface Storage Format set to MSFMT_MSS OR
513 * - Surface Type is SURFTYPE_CUBE
515 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
516 } else if (ISL_DEV_GEN(dev
) >= 7) {
517 /* Note that Ivybridge introduces
518 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
519 * driver more control over the QPitch.
522 if (phys_level0_sa
->array_len
== 1) {
523 /* The hardware will never use the QPitch. So choose the most
524 * compact QPitch possible in order to conserve memory.
526 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
529 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
530 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
)) {
531 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
532 * Section 6.18.4.7: Surface Arrays (p112):
534 * If Surface Array Spacing is set to ARYSPC_FULL (note that
535 * the depth buffer and stencil buffer have an implied value of
538 return ISL_ARRAY_PITCH_SPAN_FULL
;
541 if (info
->levels
== 1) {
542 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
545 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
548 return ISL_ARRAY_PITCH_SPAN_FULL
;
549 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
550 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
551 isl_surf_usage_is_stencil(info
->usage
)) {
552 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
553 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
555 * The separate stencil buffer does not support mip mapping, thus
556 * the storage for LODs other than LOD 0 is not needed.
558 assert(info
->levels
== 1);
559 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
561 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
562 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
563 isl_surf_usage_is_stencil(info
->usage
)) {
564 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
565 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
567 * The separate stencil buffer does not support mip mapping,
568 * thus the storage for LODs other than LOD 0 is not needed.
570 assert(info
->levels
== 1);
571 assert(phys_level0_sa
->array_len
== 1);
572 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
575 if (phys_level0_sa
->array_len
== 1) {
576 /* The hardware will never use the QPitch. So choose the most
577 * compact QPitch possible in order to conserve memory.
579 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
582 return ISL_ARRAY_PITCH_SPAN_FULL
;
585 case ISL_DIM_LAYOUT_GEN4_3D
:
586 /* The hardware will never use the QPitch. So choose the most
587 * compact QPitch possible in order to conserve memory.
589 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
591 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
592 /* Each array image in the gen6 stencil of HiZ surface is compact in the
593 * sense that every LOD is a compact array of the same size as LOD0.
595 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
598 unreachable("bad isl_dim_layout");
599 return ISL_ARRAY_PITCH_SPAN_FULL
;
603 isl_choose_image_alignment_el(const struct isl_device
*dev
,
604 const struct isl_surf_init_info
*restrict info
,
605 enum isl_tiling tiling
,
606 enum isl_dim_layout dim_layout
,
607 enum isl_msaa_layout msaa_layout
,
608 struct isl_extent3d
*image_align_el
)
610 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
611 if (fmtl
->txc
== ISL_TXC_MCS
) {
612 assert(tiling
== ISL_TILING_Y0
);
615 * IvyBrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)":
617 * Height, width, and layout of MCS buffer in this case must match with
618 * Render Target height, width, and layout. MCS buffer is tiledY.
620 * To avoid wasting memory, choose the smallest alignment possible:
621 * HALIGN_4 and VALIGN_4.
623 *image_align_el
= isl_extent3d(4, 4, 1);
625 } else if (info
->format
== ISL_FORMAT_HIZ
) {
626 assert(ISL_DEV_GEN(dev
) >= 6);
627 if (ISL_DEV_GEN(dev
) == 6) {
628 /* HiZ surfaces on Sandy Bridge are packed tightly. */
629 *image_align_el
= isl_extent3d(1, 1, 1);
631 /* On gen7+, HiZ surfaces are always aligned to 16x8 pixels in the
632 * primary surface which works out to 2x2 HiZ elments.
634 *image_align_el
= isl_extent3d(2, 2, 1);
639 if (ISL_DEV_GEN(dev
) >= 9) {
640 isl_gen9_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
641 msaa_layout
, image_align_el
);
642 } else if (ISL_DEV_GEN(dev
) >= 8) {
643 isl_gen8_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
644 msaa_layout
, image_align_el
);
645 } else if (ISL_DEV_GEN(dev
) >= 7) {
646 isl_gen7_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
647 msaa_layout
, image_align_el
);
648 } else if (ISL_DEV_GEN(dev
) >= 6) {
649 isl_gen6_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
650 msaa_layout
, image_align_el
);
652 isl_gen4_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
,
653 msaa_layout
, image_align_el
);
657 static enum isl_dim_layout
658 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
659 enum isl_surf_dim logical_dim
,
660 enum isl_tiling tiling
,
661 isl_surf_usage_flags_t usage
)
663 /* Sandy bridge needs a special layout for HiZ and stencil. */
664 if (ISL_DEV_GEN(dev
) == 6 &&
665 (tiling
== ISL_TILING_W
|| tiling
== ISL_TILING_HIZ
))
666 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
668 if (ISL_DEV_GEN(dev
) >= 9) {
669 switch (logical_dim
) {
670 case ISL_SURF_DIM_1D
:
671 /* From the Sky Lake PRM Vol. 5, "1D Surfaces":
673 * One-dimensional surfaces use a tiling mode of linear.
674 * Technically, they are not tiled resources, but the Tiled
675 * Resource Mode field in RENDER_SURFACE_STATE is still used to
676 * indicate the alignment requirements for this linear surface
677 * (See 1D Alignment requirements for how 4K and 64KB Tiled
678 * Resource Modes impact alignment). Alternatively, a 1D surface
679 * can be defined as a 2D tiled surface (e.g. TileY or TileX) with
682 * In other words, ISL_DIM_LAYOUT_GEN9_1D is only used for linear
683 * surfaces and, for tiled surfaces, ISL_DIM_LAYOUT_GEN4_2D is used.
685 if (tiling
== ISL_TILING_LINEAR
)
686 return ISL_DIM_LAYOUT_GEN9_1D
;
688 return ISL_DIM_LAYOUT_GEN4_2D
;
689 case ISL_SURF_DIM_2D
:
690 case ISL_SURF_DIM_3D
:
691 return ISL_DIM_LAYOUT_GEN4_2D
;
694 switch (logical_dim
) {
695 case ISL_SURF_DIM_1D
:
696 case ISL_SURF_DIM_2D
:
697 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
699 * The cube face textures are stored in the same way as 3D surfaces
700 * are stored (see section 6.17.5 for details). For cube surfaces,
701 * however, the depth is equal to the number of faces (always 6) and
702 * is not reduced for each MIP.
704 if (ISL_DEV_GEN(dev
) == 4 && (usage
& ISL_SURF_USAGE_CUBE_BIT
))
705 return ISL_DIM_LAYOUT_GEN4_3D
;
707 return ISL_DIM_LAYOUT_GEN4_2D
;
708 case ISL_SURF_DIM_3D
:
709 return ISL_DIM_LAYOUT_GEN4_3D
;
713 unreachable("bad isl_surf_dim");
714 return ISL_DIM_LAYOUT_GEN4_2D
;
718 * Calculate the physical extent of the surface's first level, in units of
719 * surface samples. The result is aligned to the format's compression block.
722 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
723 const struct isl_surf_init_info
*restrict info
,
724 enum isl_dim_layout dim_layout
,
725 enum isl_tiling tiling
,
726 enum isl_msaa_layout msaa_layout
,
727 struct isl_extent4d
*phys_level0_sa
)
729 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
731 if (isl_format_is_yuv(info
->format
))
732 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
735 case ISL_SURF_DIM_1D
:
736 assert(info
->height
== 1);
737 assert(info
->depth
== 1);
738 assert(info
->samples
== 1);
740 switch (dim_layout
) {
741 case ISL_DIM_LAYOUT_GEN4_3D
:
742 unreachable("bad isl_dim_layout");
744 case ISL_DIM_LAYOUT_GEN9_1D
:
745 case ISL_DIM_LAYOUT_GEN4_2D
:
746 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
747 *phys_level0_sa
= (struct isl_extent4d
) {
748 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
751 .a
= info
->array_len
,
757 case ISL_SURF_DIM_2D
:
758 if (ISL_DEV_GEN(dev
) == 4 && (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
))
759 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_3D
);
761 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
||
762 dim_layout
== ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
);
764 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
765 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
767 switch (msaa_layout
) {
768 case ISL_MSAA_LAYOUT_NONE
:
769 assert(info
->depth
== 1);
770 assert(info
->samples
== 1);
772 *phys_level0_sa
= (struct isl_extent4d
) {
773 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
774 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
776 .a
= info
->array_len
,
780 case ISL_MSAA_LAYOUT_ARRAY
:
781 assert(info
->depth
== 1);
782 assert(info
->levels
== 1);
783 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
784 assert(fmtl
->bw
== 1 && fmtl
->bh
== 1);
786 *phys_level0_sa
= (struct isl_extent4d
) {
790 .a
= info
->array_len
* info
->samples
,
794 case ISL_MSAA_LAYOUT_INTERLEAVED
:
795 assert(info
->depth
== 1);
796 assert(info
->levels
== 1);
797 assert(isl_format_supports_multisampling(dev
->info
, info
->format
));
799 *phys_level0_sa
= (struct isl_extent4d
) {
803 .a
= info
->array_len
,
806 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
810 phys_level0_sa
->w
= isl_align(phys_level0_sa
->w
, fmtl
->bw
);
811 phys_level0_sa
->h
= isl_align(phys_level0_sa
->h
, fmtl
->bh
);
816 case ISL_SURF_DIM_3D
:
817 assert(info
->array_len
== 1);
818 assert(info
->samples
== 1);
821 isl_finishme("%s:%s: compression block with depth > 1",
825 switch (dim_layout
) {
826 case ISL_DIM_LAYOUT_GEN9_1D
:
827 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
828 unreachable("bad isl_dim_layout");
830 case ISL_DIM_LAYOUT_GEN4_2D
:
831 assert(ISL_DEV_GEN(dev
) >= 9);
833 *phys_level0_sa
= (struct isl_extent4d
) {
834 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
835 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
841 case ISL_DIM_LAYOUT_GEN4_3D
:
842 assert(ISL_DEV_GEN(dev
) < 9);
843 *phys_level0_sa
= (struct isl_extent4d
) {
844 .w
= isl_align(info
->width
, fmtl
->bw
),
845 .h
= isl_align(info
->height
, fmtl
->bh
),
856 * Calculate the pitch between physical array slices, in units of rows of
860 isl_calc_array_pitch_el_rows_gen4_2d(
861 const struct isl_device
*dev
,
862 const struct isl_surf_init_info
*restrict info
,
863 const struct isl_tile_info
*tile_info
,
864 const struct isl_extent3d
*image_align_sa
,
865 const struct isl_extent4d
*phys_level0_sa
,
866 enum isl_array_pitch_span array_pitch_span
,
867 const struct isl_extent2d
*phys_slice0_sa
)
869 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
870 uint32_t pitch_sa_rows
= 0;
872 switch (array_pitch_span
) {
873 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
874 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
876 case ISL_ARRAY_PITCH_SPAN_FULL
: {
877 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
878 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
879 * Surfaces >> Surface Arrays.
881 uint32_t H0_sa
= phys_level0_sa
->h
;
882 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
884 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
885 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
888 if (ISL_DEV_GEN(dev
) >= 7) {
889 /* The QPitch equation changed slightly in Ivybridge. */
895 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
897 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
898 (info
->height
% 4 == 1)) {
899 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
900 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
902 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
903 * the value calculated in the equation above , for every
904 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
906 * XXX(chadv): Is the errata natural corollary of the physical
907 * layout of interleaved samples?
912 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
917 assert(pitch_sa_rows
% fmtl
->bh
== 0);
918 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
920 if (ISL_DEV_GEN(dev
) >= 9 && fmtl
->txc
== ISL_TXC_CCS
) {
922 * From the Sky Lake PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 632):
924 * "Mip-mapped and arrayed surfaces are supported with MCS buffer
925 * layout with these alignments in the RT space: Horizontal
926 * Alignment = 128 and Vertical Alignment = 64."
928 * From the Sky Lake PRM Vol. 2d, "RENDER_SURFACE_STATE" (p. 435):
930 * "For non-multisampled render target's CCS auxiliary surface,
931 * QPitch must be computed with Horizontal Alignment = 128 and
932 * Surface Vertical Alignment = 256. These alignments are only for
933 * CCS buffer and not for associated render target."
935 * The first restriction is already handled by isl_choose_image_alignment_el
936 * but the second restriction, which is an extension of the first, only
937 * applies to qpitch and must be applied here.
939 assert(fmtl
->bh
== 4);
940 pitch_el_rows
= isl_align(pitch_el_rows
, 256 / 4);
943 if (ISL_DEV_GEN(dev
) >= 9 &&
944 info
->dim
== ISL_SURF_DIM_3D
&&
945 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
946 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
948 * Tile Mode != Linear: This field must be set to an integer multiple
951 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
954 return pitch_el_rows
;
958 * A variant of isl_calc_phys_slice0_extent_sa() specific to
959 * ISL_DIM_LAYOUT_GEN4_2D.
962 isl_calc_phys_slice0_extent_sa_gen4_2d(
963 const struct isl_device
*dev
,
964 const struct isl_surf_init_info
*restrict info
,
965 enum isl_msaa_layout msaa_layout
,
966 const struct isl_extent3d
*image_align_sa
,
967 const struct isl_extent4d
*phys_level0_sa
,
968 struct isl_extent2d
*phys_slice0_sa
)
970 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
972 assert(phys_level0_sa
->depth
== 1);
974 if (info
->levels
== 1) {
975 /* Do not pad the surface to the image alignment. Instead, pad it only
976 * to the pixel format's block alignment.
978 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
979 * cycles on the below mipmap layout caluclations. Reducing the
980 * alignment here is safe because we later align the row pitch and array
981 * pitch to the tile boundary. It is safe even for
982 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
983 * to accomodate the interleaved samples.
985 * For linear surfaces, reducing the alignment here permits us to later
986 * choose an arbitrary, non-aligned row pitch. If the surface backs
987 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
988 * VkBufferImageCopy::bufferRowLength.
990 *phys_slice0_sa
= (struct isl_extent2d
) {
991 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
992 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
997 uint32_t slice_top_w
= 0;
998 uint32_t slice_bottom_w
= 0;
999 uint32_t slice_left_h
= 0;
1000 uint32_t slice_right_h
= 0;
1002 uint32_t W0
= phys_level0_sa
->w
;
1003 uint32_t H0
= phys_level0_sa
->h
;
1005 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1006 uint32_t W
= isl_minify(W0
, l
);
1007 uint32_t H
= isl_minify(H0
, l
);
1009 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1010 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
1016 } else if (l
== 1) {
1019 } else if (l
== 2) {
1020 slice_bottom_w
+= w
;
1027 *phys_slice0_sa
= (struct isl_extent2d
) {
1028 .w
= MAX(slice_top_w
, slice_bottom_w
),
1029 .h
= MAX(slice_left_h
, slice_right_h
),
1034 isl_calc_phys_total_extent_el_gen4_2d(
1035 const struct isl_device
*dev
,
1036 const struct isl_surf_init_info
*restrict info
,
1037 const struct isl_tile_info
*tile_info
,
1038 enum isl_msaa_layout msaa_layout
,
1039 const struct isl_extent3d
*image_align_sa
,
1040 const struct isl_extent4d
*phys_level0_sa
,
1041 enum isl_array_pitch_span array_pitch_span
,
1042 uint32_t *array_pitch_el_rows
,
1043 struct isl_extent2d
*total_extent_el
)
1045 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1047 struct isl_extent2d phys_slice0_sa
;
1048 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
1049 image_align_sa
, phys_level0_sa
,
1051 *array_pitch_el_rows
=
1052 isl_calc_array_pitch_el_rows_gen4_2d(dev
, info
, tile_info
,
1053 image_align_sa
, phys_level0_sa
,
1056 *total_extent_el
= (struct isl_extent2d
) {
1057 .w
= isl_assert_div(phys_slice0_sa
.w
, fmtl
->bw
),
1058 .h
= *array_pitch_el_rows
* (phys_level0_sa
->array_len
- 1) +
1059 isl_assert_div(phys_slice0_sa
.h
, fmtl
->bh
),
1064 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1065 * ISL_DIM_LAYOUT_GEN4_3D.
1068 isl_calc_phys_total_extent_el_gen4_3d(
1069 const struct isl_device
*dev
,
1070 const struct isl_surf_init_info
*restrict info
,
1071 const struct isl_extent3d
*image_align_sa
,
1072 const struct isl_extent4d
*phys_level0_sa
,
1073 uint32_t *array_pitch_el_rows
,
1074 struct isl_extent2d
*phys_total_el
)
1076 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1078 assert(info
->samples
== 1);
1080 if (info
->dim
!= ISL_SURF_DIM_3D
) {
1081 /* From the G45 PRM Vol. 1a, "6.17.4.1 Hardware Cube Map Layout":
1083 * The cube face textures are stored in the same way as 3D surfaces
1084 * are stored (see section 6.17.5 for details). For cube surfaces,
1085 * however, the depth is equal to the number of faces (always 6) and
1086 * is not reduced for each MIP.
1088 assert(ISL_DEV_GEN(dev
) == 4);
1089 assert(info
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1090 assert(phys_level0_sa
->array_len
== 6);
1092 assert(phys_level0_sa
->array_len
== 1);
1095 uint32_t total_w
= 0;
1096 uint32_t total_h
= 0;
1098 uint32_t W0
= phys_level0_sa
->w
;
1099 uint32_t H0
= phys_level0_sa
->h
;
1100 uint32_t D0
= phys_level0_sa
->d
;
1101 uint32_t A0
= phys_level0_sa
->a
;
1103 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1104 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
1105 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
1106 uint32_t level_d
= info
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : A0
;
1108 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
1109 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1111 total_w
= MAX(total_w
, level_w
* max_layers_horiz
);
1112 total_h
+= level_h
* max_layers_vert
;
1115 /* GEN4_3D layouts don't really have an array pitch since each LOD has a
1116 * different number of horizontal and vertical layers. We have to set it
1117 * to something, so at least make it true for LOD0.
1119 *array_pitch_el_rows
=
1120 isl_align_npot(phys_level0_sa
->h
, image_align_sa
->h
) / fmtl
->bw
;
1121 *phys_total_el
= (struct isl_extent2d
) {
1122 .w
= isl_assert_div(total_w
, fmtl
->bw
),
1123 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1128 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1129 * ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ.
1132 isl_calc_phys_total_extent_el_gen6_stencil_hiz(
1133 const struct isl_device
*dev
,
1134 const struct isl_surf_init_info
*restrict info
,
1135 const struct isl_tile_info
*tile_info
,
1136 const struct isl_extent3d
*image_align_sa
,
1137 const struct isl_extent4d
*phys_level0_sa
,
1138 uint32_t *array_pitch_el_rows
,
1139 struct isl_extent2d
*phys_total_el
)
1141 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1143 const struct isl_extent2d tile_extent_sa
= {
1144 .w
= tile_info
->logical_extent_el
.w
* fmtl
->bw
,
1145 .h
= tile_info
->logical_extent_el
.h
* fmtl
->bh
,
1147 /* Tile size is a multiple of image alignment */
1148 assert(tile_extent_sa
.w
% image_align_sa
->w
== 0);
1149 assert(tile_extent_sa
.h
% image_align_sa
->h
== 0);
1151 const uint32_t W0
= phys_level0_sa
->w
;
1152 const uint32_t H0
= phys_level0_sa
->h
;
1154 /* Each image has the same height as LOD0 because the hardware thinks
1155 * everything is LOD0
1157 const uint32_t H
= isl_align(H0
, image_align_sa
->h
) * phys_level0_sa
->a
;
1159 uint32_t total_top_w
= 0;
1160 uint32_t total_bottom_w
= 0;
1161 uint32_t total_h
= 0;
1163 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1164 const uint32_t W
= isl_minify(W0
, l
);
1166 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
1167 const uint32_t h
= isl_align(H
, tile_extent_sa
.h
);
1172 } else if (l
== 1) {
1176 total_bottom_w
+= w
;
1180 *array_pitch_el_rows
=
1181 isl_assert_div(isl_align(H0
, image_align_sa
->h
), fmtl
->bh
);
1182 *phys_total_el
= (struct isl_extent2d
) {
1183 .w
= isl_assert_div(MAX(total_top_w
, total_bottom_w
), fmtl
->bw
),
1184 .h
= isl_assert_div(total_h
, fmtl
->bh
),
1189 * A variant of isl_calc_phys_slice0_extent_sa() specific to
1190 * ISL_DIM_LAYOUT_GEN9_1D.
1193 isl_calc_phys_total_extent_el_gen9_1d(
1194 const struct isl_device
*dev
,
1195 const struct isl_surf_init_info
*restrict info
,
1196 const struct isl_extent3d
*image_align_sa
,
1197 const struct isl_extent4d
*phys_level0_sa
,
1198 uint32_t *array_pitch_el_rows
,
1199 struct isl_extent2d
*phys_total_el
)
1201 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1203 assert(phys_level0_sa
->height
/ fmtl
->bh
== 1);
1204 assert(phys_level0_sa
->depth
== 1);
1205 assert(info
->samples
== 1);
1206 assert(image_align_sa
->w
>= fmtl
->bw
);
1208 uint32_t slice_w
= 0;
1209 const uint32_t W0
= phys_level0_sa
->w
;
1211 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
1212 uint32_t W
= isl_minify(W0
, l
);
1213 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
1218 *array_pitch_el_rows
= 1;
1219 *phys_total_el
= (struct isl_extent2d
) {
1220 .w
= isl_assert_div(slice_w
, fmtl
->bw
),
1221 .h
= phys_level0_sa
->array_len
,
1226 * Calculate the two-dimensional total physical extent of the surface, in
1227 * units of surface elements.
1230 isl_calc_phys_total_extent_el(const struct isl_device
*dev
,
1231 const struct isl_surf_init_info
*restrict info
,
1232 const struct isl_tile_info
*tile_info
,
1233 enum isl_dim_layout dim_layout
,
1234 enum isl_msaa_layout msaa_layout
,
1235 const struct isl_extent3d
*image_align_sa
,
1236 const struct isl_extent4d
*phys_level0_sa
,
1237 enum isl_array_pitch_span array_pitch_span
,
1238 uint32_t *array_pitch_el_rows
,
1239 struct isl_extent2d
*total_extent_el
)
1241 switch (dim_layout
) {
1242 case ISL_DIM_LAYOUT_GEN9_1D
:
1243 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1244 isl_calc_phys_total_extent_el_gen9_1d(dev
, info
,
1245 image_align_sa
, phys_level0_sa
,
1246 array_pitch_el_rows
,
1249 case ISL_DIM_LAYOUT_GEN4_2D
:
1250 isl_calc_phys_total_extent_el_gen4_2d(dev
, info
, tile_info
, msaa_layout
,
1251 image_align_sa
, phys_level0_sa
,
1253 array_pitch_el_rows
,
1256 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
1257 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1258 isl_calc_phys_total_extent_el_gen6_stencil_hiz(dev
, info
, tile_info
,
1261 array_pitch_el_rows
,
1264 case ISL_DIM_LAYOUT_GEN4_3D
:
1265 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
1266 isl_calc_phys_total_extent_el_gen4_3d(dev
, info
,
1267 image_align_sa
, phys_level0_sa
,
1268 array_pitch_el_rows
,
1275 isl_calc_row_pitch_alignment(const struct isl_surf_init_info
*surf_info
,
1276 const struct isl_tile_info
*tile_info
)
1278 if (tile_info
->tiling
!= ISL_TILING_LINEAR
)
1279 return tile_info
->phys_extent_B
.width
;
1281 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
1282 * RENDER_SURFACE_STATE Surface Pitch (p349):
1284 * - For linear render target surfaces and surfaces accessed with the
1285 * typed data port messages, the pitch must be a multiple of the
1286 * element size for non-YUV surface formats. Pitch must be
1287 * a multiple of 2 * element size for YUV surface formats.
1289 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
1290 * ignore because isl doesn't do buffers.]
1292 * - For other linear surfaces, the pitch can be any multiple of
1295 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1296 const uint32_t bs
= fmtl
->bpb
/ 8;
1298 if (surf_info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1299 if (isl_format_is_yuv(surf_info
->format
)) {
1310 isl_calc_linear_min_row_pitch(const struct isl_device
*dev
,
1311 const struct isl_surf_init_info
*info
,
1312 const struct isl_extent2d
*phys_total_el
,
1313 uint32_t alignment_B
)
1315 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1316 const uint32_t bs
= fmtl
->bpb
/ 8;
1318 return isl_align_npot(bs
* phys_total_el
->w
, alignment_B
);
1322 isl_calc_tiled_min_row_pitch(const struct isl_device
*dev
,
1323 const struct isl_surf_init_info
*surf_info
,
1324 const struct isl_tile_info
*tile_info
,
1325 const struct isl_extent2d
*phys_total_el
,
1326 uint32_t alignment_B
)
1328 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf_info
->format
);
1330 assert(fmtl
->bpb
% tile_info
->format_bpb
== 0);
1332 const uint32_t tile_el_scale
= fmtl
->bpb
/ tile_info
->format_bpb
;
1333 const uint32_t total_w_tl
=
1334 isl_align_div(phys_total_el
->w
* tile_el_scale
,
1335 tile_info
->logical_extent_el
.width
);
1337 assert(alignment_B
== tile_info
->phys_extent_B
.width
);
1338 return total_w_tl
* tile_info
->phys_extent_B
.width
;
1342 isl_calc_min_row_pitch(const struct isl_device
*dev
,
1343 const struct isl_surf_init_info
*surf_info
,
1344 const struct isl_tile_info
*tile_info
,
1345 const struct isl_extent2d
*phys_total_el
,
1346 uint32_t alignment_B
)
1348 if (tile_info
->tiling
== ISL_TILING_LINEAR
) {
1349 return isl_calc_linear_min_row_pitch(dev
, surf_info
, phys_total_el
,
1352 return isl_calc_tiled_min_row_pitch(dev
, surf_info
, tile_info
,
1353 phys_total_el
, alignment_B
);
1358 * Is `pitch` in the valid range for a hardware bitfield, if the bitfield's
1359 * size is `bits` bits?
1361 * Hardware pitch fields are offset by 1. For example, if the size of
1362 * RENDER_SURFACE_STATE::SurfacePitch is B bits, then the range of valid
1363 * pitches is [1, 2^b] inclusive. If the surface pitch is N, then
1364 * RENDER_SURFACE_STATE::SurfacePitch must be set to N-1.
1367 pitch_in_range(uint32_t n
, uint32_t bits
)
1370 return likely(bits
!= 0 && 1 <= n
&& n
<= (1 << bits
));
1374 isl_calc_row_pitch(const struct isl_device
*dev
,
1375 const struct isl_surf_init_info
*surf_info
,
1376 const struct isl_tile_info
*tile_info
,
1377 enum isl_dim_layout dim_layout
,
1378 const struct isl_extent2d
*phys_total_el
,
1379 uint32_t *out_row_pitch_B
)
1381 uint32_t alignment_B
=
1382 isl_calc_row_pitch_alignment(surf_info
, tile_info
);
1384 /* If pitch isn't given and it can be chosen freely, align it by cache line
1385 * allowing one to use blit engine on the surface.
1387 if (surf_info
->row_pitch_B
== 0 && tile_info
->tiling
== ISL_TILING_LINEAR
) {
1388 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
1390 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
1391 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
1392 * enabled), this address must be 4KB-aligned. When Tiling is not
1393 * enabled, this address should be CL (64byte) aligned."
1395 alignment_B
= MAX2(alignment_B
, 64);
1398 const uint32_t min_row_pitch_B
=
1399 isl_calc_min_row_pitch(dev
, surf_info
, tile_info
, phys_total_el
,
1402 uint32_t row_pitch_B
= min_row_pitch_B
;
1404 if (surf_info
->row_pitch_B
!= 0) {
1405 row_pitch_B
= surf_info
->row_pitch_B
;
1407 if (row_pitch_B
< min_row_pitch_B
)
1410 if (row_pitch_B
% alignment_B
!= 0)
1414 const uint32_t row_pitch_tl
= row_pitch_B
/ tile_info
->phys_extent_B
.width
;
1416 if (row_pitch_B
== 0)
1419 if (dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
1420 /* SurfacePitch is ignored for this layout. */
1424 if ((surf_info
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1425 ISL_SURF_USAGE_TEXTURE_BIT
|
1426 ISL_SURF_USAGE_STORAGE_BIT
)) &&
1427 !pitch_in_range(row_pitch_B
, RENDER_SURFACE_STATE_SurfacePitch_bits(dev
->info
)))
1430 if ((surf_info
->usage
& (ISL_SURF_USAGE_CCS_BIT
|
1431 ISL_SURF_USAGE_MCS_BIT
)) &&
1432 !pitch_in_range(row_pitch_tl
, RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(dev
->info
)))
1435 if ((surf_info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1436 !pitch_in_range(row_pitch_B
, _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1439 if ((surf_info
->usage
& ISL_SURF_USAGE_HIZ_BIT
) &&
1440 !pitch_in_range(row_pitch_B
, _3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
)))
1443 const uint32_t stencil_pitch_bits
= dev
->use_separate_stencil
?
1444 _3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(dev
->info
) :
1445 _3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(dev
->info
);
1447 if ((surf_info
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) &&
1448 !pitch_in_range(row_pitch_B
, stencil_pitch_bits
))
1452 *out_row_pitch_B
= row_pitch_B
;
1457 isl_surf_init_s(const struct isl_device
*dev
,
1458 struct isl_surf
*surf
,
1459 const struct isl_surf_init_info
*restrict info
)
1461 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1463 const struct isl_extent4d logical_level0_px
= {
1467 .a
= info
->array_len
,
1470 enum isl_tiling tiling
;
1471 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1474 struct isl_tile_info tile_info
;
1475 isl_tiling_get_info(tiling
, fmtl
->bpb
, &tile_info
);
1477 const enum isl_dim_layout dim_layout
=
1478 isl_surf_choose_dim_layout(dev
, info
->dim
, tiling
, info
->usage
);
1480 enum isl_msaa_layout msaa_layout
;
1481 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1484 struct isl_extent3d image_align_el
;
1485 isl_choose_image_alignment_el(dev
, info
, tiling
, dim_layout
, msaa_layout
,
1488 struct isl_extent3d image_align_sa
=
1489 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1491 struct isl_extent4d phys_level0_sa
;
1492 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1494 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1495 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1497 enum isl_array_pitch_span array_pitch_span
=
1498 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1500 uint32_t array_pitch_el_rows
;
1501 struct isl_extent2d phys_total_el
;
1502 isl_calc_phys_total_extent_el(dev
, info
, &tile_info
,
1503 dim_layout
, msaa_layout
,
1504 &image_align_sa
, &phys_level0_sa
,
1505 array_pitch_span
, &array_pitch_el_rows
,
1508 uint32_t row_pitch_B
;
1509 if (!isl_calc_row_pitch(dev
, info
, &tile_info
, dim_layout
,
1510 &phys_total_el
, &row_pitch_B
))
1513 uint32_t base_alignment_B
;
1515 if (tiling
== ISL_TILING_LINEAR
) {
1516 size_B
= (uint64_t) row_pitch_B
* phys_total_el
.h
;
1518 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1520 * "The Base Address for linear render target surfaces and surfaces
1521 * accessed with the typed surface read/write data port messages must
1522 * be element-size aligned, for non-YUV surface formats, or a
1523 * multiple of 2 element-sizes for YUV surface formats. Other linear
1524 * surfaces have no alignment requirements (byte alignment is
1527 base_alignment_B
= MAX(1, info
->min_alignment_B
);
1528 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1529 if (isl_format_is_yuv(info
->format
)) {
1530 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 4);
1532 base_alignment_B
= MAX(base_alignment_B
, fmtl
->bpb
/ 8);
1535 base_alignment_B
= isl_round_up_to_power_of_two(base_alignment_B
);
1537 const uint32_t total_h_tl
=
1538 isl_align_div(phys_total_el
.h
, tile_info
.logical_extent_el
.height
);
1540 size_B
= (uint64_t) total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch_B
;
1542 const uint32_t tile_size_B
= tile_info
.phys_extent_B
.width
*
1543 tile_info
.phys_extent_B
.height
;
1544 assert(isl_is_pow2(info
->min_alignment_B
) && isl_is_pow2(tile_size_B
));
1545 base_alignment_B
= MAX(info
->min_alignment_B
, tile_size_B
);
1548 if (ISL_DEV_GEN(dev
) < 9) {
1549 /* From the Broadwell PRM Vol 5, Surface Layout:
1551 * "In addition to restrictions on maximum height, width, and depth,
1552 * surfaces are also restricted to a maximum size in bytes. This
1553 * maximum is 2 GB for all products and all surface types."
1555 * This comment is applicable to all Pre-gen9 platforms.
1557 if (size_B
> (uint64_t) 1 << 31)
1559 } else if (ISL_DEV_GEN(dev
) < 11) {
1560 /* From the Skylake PRM Vol 5, Maximum Surface Size in Bytes:
1561 * "In addition to restrictions on maximum height, width, and depth,
1562 * surfaces are also restricted to a maximum size of 2^38 bytes.
1563 * All pixels within the surface must be contained within 2^38 bytes
1564 * of the base address."
1566 if (size_B
> (uint64_t) 1 << 38)
1569 /* gen11+ platforms raised this limit to 2^44 bytes. */
1570 if (size_B
> (uint64_t) 1 << 44)
1574 *surf
= (struct isl_surf
) {
1576 .dim_layout
= dim_layout
,
1577 .msaa_layout
= msaa_layout
,
1579 .format
= info
->format
,
1581 .levels
= info
->levels
,
1582 .samples
= info
->samples
,
1584 .image_alignment_el
= image_align_el
,
1585 .logical_level0_px
= logical_level0_px
,
1586 .phys_level0_sa
= phys_level0_sa
,
1589 .alignment_B
= base_alignment_B
,
1590 .row_pitch_B
= row_pitch_B
,
1591 .array_pitch_el_rows
= array_pitch_el_rows
,
1592 .array_pitch_span
= array_pitch_span
,
1594 .usage
= info
->usage
,
1601 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1602 struct isl_tile_info
*tile_info
)
1604 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1605 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, tile_info
);
1609 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1610 const struct isl_surf
*surf
,
1611 struct isl_surf
*hiz_surf
)
1613 assert(ISL_DEV_GEN(dev
) >= 5 && ISL_DEV_USE_SEPARATE_STENCIL(dev
));
1615 /* Multisampled depth is always interleaved */
1616 assert(surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
1617 surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
);
1619 /* From the Broadwell PRM Vol. 7, "Hierarchical Depth Buffer":
1621 * "The Surface Type, Height, Width, Depth, Minimum Array Element, Render
1622 * Target View Extent, and Depth Coordinate Offset X/Y of the
1623 * hierarchical depth buffer are inherited from the depth buffer. The
1624 * height and width of the hierarchical depth buffer that must be
1625 * allocated are computed by the following formulas, where HZ is the
1626 * hierarchical depth buffer and Z is the depth buffer. The Z_Height,
1627 * Z_Width, and Z_Depth values given in these formulas are those present
1628 * in 3DSTATE_DEPTH_BUFFER incremented by one.
1630 * "The value of Z_Height and Z_Width must each be multiplied by 2 before
1631 * being applied to the table below if Number of Multisamples is set to
1632 * NUMSAMPLES_4. The value of Z_Height must be multiplied by 2 and
1633 * Z_Width must be multiplied by 4 before being applied to the table
1634 * below if Number of Multisamples is set to NUMSAMPLES_8."
1636 * In the Sky Lake PRM, the second paragraph is replaced with this:
1638 * "The Z_Height and Z_Width values must equal those present in
1639 * 3DSTATE_DEPTH_BUFFER incremented by one."
1641 * In other words, on Sandy Bridge through Broadwell, each 128-bit HiZ
1642 * block corresponds to a region of 8x4 samples in the primary depth
1643 * surface. On Sky Lake, on the other hand, each HiZ block corresponds to
1644 * a region of 8x4 pixels in the primary depth surface regardless of the
1645 * number of samples. The dimensions of a HiZ block in both pixels and
1646 * samples are given in the table below:
1648 * | SNB - BDW | SKL+
1649 * ------+-----------+-------------
1650 * 1x | 8 x 4 sa | 8 x 4 sa
1651 * MSAA | 8 x 4 px | 8 x 4 px
1652 * ------+-----------+-------------
1653 * 2x | 8 x 4 sa | 16 x 4 sa
1654 * MSAA | 4 x 4 px | 8 x 4 px
1655 * ------+-----------+-------------
1656 * 4x | 8 x 4 sa | 16 x 8 sa
1657 * MSAA | 4 x 2 px | 8 x 4 px
1658 * ------+-----------+-------------
1659 * 8x | 8 x 4 sa | 32 x 8 sa
1660 * MSAA | 2 x 2 px | 8 x 4 px
1661 * ------+-----------+-------------
1662 * 16x | N/A | 32 x 16 sa
1663 * MSAA | N/A | 8 x 4 px
1664 * ------+-----------+-------------
1666 * There are a number of different ways that this discrepency could be
1667 * handled. The way we have chosen is to simply make MSAA HiZ have the
1668 * same number of samples as the parent surface pre-Sky Lake and always be
1669 * single-sampled on Sky Lake and above. Since the block sizes of
1670 * compressed formats are given in samples, this neatly handles everything
1671 * without the need for additional HiZ formats with different block sizes
1674 const unsigned samples
= ISL_DEV_GEN(dev
) >= 9 ? 1 : surf
->samples
;
1676 return isl_surf_init(dev
, hiz_surf
,
1678 .format
= ISL_FORMAT_HIZ
,
1679 .width
= surf
->logical_level0_px
.width
,
1680 .height
= surf
->logical_level0_px
.height
,
1681 .depth
= surf
->logical_level0_px
.depth
,
1682 .levels
= surf
->levels
,
1683 .array_len
= surf
->logical_level0_px
.array_len
,
1685 .usage
= ISL_SURF_USAGE_HIZ_BIT
,
1686 .tiling_flags
= ISL_TILING_HIZ_BIT
);
1690 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1691 const struct isl_surf
*surf
,
1692 struct isl_surf
*mcs_surf
)
1694 assert(ISL_DEV_GEN(dev
) >= 7);
1696 /* It must be multisampled with an array layout */
1697 assert(surf
->samples
> 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
1699 /* The following are true of all multisampled surfaces */
1700 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1701 assert(surf
->levels
== 1);
1702 assert(surf
->logical_level0_px
.depth
== 1);
1704 /* The "Auxiliary Surface Pitch" field in RENDER_SURFACE_STATE is only 9
1705 * bits which means the maximum pitch of a compression surface is 512
1706 * tiles or 64KB (since MCS is always Y-tiled). Since a 16x MCS buffer is
1707 * 64bpp, this gives us a maximum width of 8192 pixels. We can create
1708 * larger multisampled surfaces, we just can't compress them. For 2x, 4x,
1709 * and 8x, we have enough room for the full 16k supported by the hardware.
1711 if (surf
->samples
== 16 && surf
->logical_level0_px
.width
> 8192)
1714 enum isl_format mcs_format
;
1715 switch (surf
->samples
) {
1716 case 2: mcs_format
= ISL_FORMAT_MCS_2X
; break;
1717 case 4: mcs_format
= ISL_FORMAT_MCS_4X
; break;
1718 case 8: mcs_format
= ISL_FORMAT_MCS_8X
; break;
1719 case 16: mcs_format
= ISL_FORMAT_MCS_16X
; break;
1721 unreachable("Invalid sample count");
1724 return isl_surf_init(dev
, mcs_surf
,
1725 .dim
= ISL_SURF_DIM_2D
,
1726 .format
= mcs_format
,
1727 .width
= surf
->logical_level0_px
.width
,
1728 .height
= surf
->logical_level0_px
.height
,
1731 .array_len
= surf
->logical_level0_px
.array_len
,
1732 .samples
= 1, /* MCS surfaces are really single-sampled */
1733 .usage
= ISL_SURF_USAGE_MCS_BIT
,
1734 .tiling_flags
= ISL_TILING_Y0_BIT
);
1738 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1739 const struct isl_surf
*surf
,
1740 struct isl_surf
*ccs_surf
,
1741 uint32_t row_pitch_B
)
1743 assert(surf
->samples
== 1 && surf
->msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
1744 assert(ISL_DEV_GEN(dev
) >= 7);
1746 if (surf
->usage
& ISL_SURF_USAGE_DISABLE_AUX_BIT
)
1749 /* The PRM doesn't say this explicitly, but fast-clears don't appear to
1750 * work for 3D textures until gen9 where the layout of 3D textures changes
1751 * to match 2D array textures.
1753 if (ISL_DEV_GEN(dev
) <= 8 && surf
->dim
!= ISL_SURF_DIM_2D
)
1756 /* From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652 (Color Clear of
1757 * Non-MultiSampler Render Target Restrictions):
1759 * "Support is for non-mip-mapped and non-array surface types only."
1761 * This restriction is lifted on gen8+. Technically, it may be possible to
1762 * create a CCS for an arrayed or mipmapped image and only enable CCS_D
1763 * when rendering to the base slice. However, there is no documentation
1764 * tell us what the hardware would do in that case or what it does if you
1765 * walk off the bases slice. (Does it ignore CCS or does it start
1766 * scribbling over random memory?) We play it safe and just follow the
1767 * docs and don't allow CCS_D for arrayed or mip-mapped surfaces.
1769 if (ISL_DEV_GEN(dev
) <= 7 &&
1770 (surf
->levels
> 1 || surf
->logical_level0_px
.array_len
> 1))
1773 if (isl_format_is_compressed(surf
->format
))
1776 /* TODO: More conditions where it can fail. */
1778 enum isl_format ccs_format
;
1779 if (ISL_DEV_GEN(dev
) >= 9) {
1780 if (!isl_tiling_is_any_y(surf
->tiling
))
1783 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1784 case 32: ccs_format
= ISL_FORMAT_GEN9_CCS_32BPP
; break;
1785 case 64: ccs_format
= ISL_FORMAT_GEN9_CCS_64BPP
; break;
1786 case 128: ccs_format
= ISL_FORMAT_GEN9_CCS_128BPP
; break;
1790 } else if (surf
->tiling
== ISL_TILING_Y0
) {
1791 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1792 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_Y
; break;
1793 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_Y
; break;
1794 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_Y
; break;
1798 } else if (surf
->tiling
== ISL_TILING_X
) {
1799 switch (isl_format_get_layout(surf
->format
)->bpb
) {
1800 case 32: ccs_format
= ISL_FORMAT_GEN7_CCS_32BPP_X
; break;
1801 case 64: ccs_format
= ISL_FORMAT_GEN7_CCS_64BPP_X
; break;
1802 case 128: ccs_format
= ISL_FORMAT_GEN7_CCS_128BPP_X
; break;
1810 return isl_surf_init(dev
, ccs_surf
,
1812 .format
= ccs_format
,
1813 .width
= surf
->logical_level0_px
.width
,
1814 .height
= surf
->logical_level0_px
.height
,
1815 .depth
= surf
->logical_level0_px
.depth
,
1816 .levels
= surf
->levels
,
1817 .array_len
= surf
->logical_level0_px
.array_len
,
1819 .row_pitch_B
= row_pitch_B
,
1820 .usage
= ISL_SURF_USAGE_CCS_BIT
,
1821 .tiling_flags
= ISL_TILING_CCS_BIT
);
1824 #define isl_genX_call(dev, func, ...) \
1825 switch (ISL_DEV_GEN(dev)) { \
1827 /* G45 surface state is the same as gen5 */ \
1828 if (ISL_DEV_IS_G4X(dev)) { \
1829 isl_gen5_##func(__VA_ARGS__); \
1831 isl_gen4_##func(__VA_ARGS__); \
1835 isl_gen5_##func(__VA_ARGS__); \
1838 isl_gen6_##func(__VA_ARGS__); \
1841 if (ISL_DEV_IS_HASWELL(dev)) { \
1842 isl_gen75_##func(__VA_ARGS__); \
1844 isl_gen7_##func(__VA_ARGS__); \
1848 isl_gen8_##func(__VA_ARGS__); \
1851 isl_gen9_##func(__VA_ARGS__); \
1854 isl_gen10_##func(__VA_ARGS__); \
1857 isl_gen11_##func(__VA_ARGS__); \
1860 assert(!"Unknown hardware generation"); \
1864 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1865 const struct isl_surf_fill_state_info
*restrict info
)
1868 isl_surf_usage_flags_t _base_usage
=
1869 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1870 ISL_SURF_USAGE_TEXTURE_BIT
|
1871 ISL_SURF_USAGE_STORAGE_BIT
);
1872 /* They may only specify one of the above bits at a time */
1873 assert(__builtin_popcount(_base_usage
) == 1);
1874 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1875 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1878 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1879 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1880 info
->surf
->logical_level0_px
.depth
);
1882 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1883 info
->surf
->logical_level0_px
.array_len
);
1886 isl_genX_call(dev
, surf_fill_state_s
, dev
, state
, info
);
1890 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1891 const struct isl_buffer_fill_state_info
*restrict info
)
1893 isl_genX_call(dev
, buffer_fill_state_s
, state
, info
);
1897 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1898 struct isl_extent3d size
)
1900 isl_genX_call(dev
, null_fill_state
, state
, size
);
1904 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1905 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
1907 if (info
->depth_surf
&& info
->stencil_surf
) {
1908 if (!dev
->info
->has_hiz_and_separate_stencil
) {
1909 assert(info
->depth_surf
== info
->stencil_surf
);
1910 assert(info
->depth_address
== info
->stencil_address
);
1912 assert(info
->depth_surf
->dim
== info
->stencil_surf
->dim
);
1915 if (info
->depth_surf
) {
1916 assert((info
->depth_surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
));
1917 if (info
->depth_surf
->dim
== ISL_SURF_DIM_3D
) {
1918 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1919 info
->depth_surf
->logical_level0_px
.depth
);
1921 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1922 info
->depth_surf
->logical_level0_px
.array_len
);
1926 if (info
->stencil_surf
) {
1927 assert((info
->stencil_surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
));
1928 if (info
->stencil_surf
->dim
== ISL_SURF_DIM_3D
) {
1929 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1930 info
->stencil_surf
->logical_level0_px
.depth
);
1932 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1933 info
->stencil_surf
->logical_level0_px
.array_len
);
1937 isl_genX_call(dev
, emit_depth_stencil_hiz_s
, dev
, batch
, info
);
1941 * A variant of isl_surf_get_image_offset_sa() specific to
1942 * ISL_DIM_LAYOUT_GEN4_2D.
1945 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1946 uint32_t level
, uint32_t logical_array_layer
,
1947 uint32_t *x_offset_sa
,
1948 uint32_t *y_offset_sa
)
1950 assert(level
< surf
->levels
);
1951 if (surf
->dim
== ISL_SURF_DIM_3D
)
1952 assert(logical_array_layer
< surf
->logical_level0_px
.depth
);
1954 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1956 const struct isl_extent3d image_align_sa
=
1957 isl_surf_get_image_alignment_sa(surf
);
1959 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1960 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1962 const uint32_t phys_layer
= logical_array_layer
*
1963 (surf
->msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
? surf
->samples
: 1);
1966 uint32_t y
= phys_layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1968 for (uint32_t l
= 0; l
< level
; ++l
) {
1970 uint32_t W
= isl_minify(W0
, l
);
1971 x
+= isl_align_npot(W
, image_align_sa
.w
);
1973 uint32_t H
= isl_minify(H0
, l
);
1974 y
+= isl_align_npot(H
, image_align_sa
.h
);
1983 * A variant of isl_surf_get_image_offset_sa() specific to
1984 * ISL_DIM_LAYOUT_GEN4_3D.
1987 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1988 uint32_t level
, uint32_t logical_z_offset_px
,
1989 uint32_t *x_offset_sa
,
1990 uint32_t *y_offset_sa
)
1992 assert(level
< surf
->levels
);
1993 if (surf
->dim
== ISL_SURF_DIM_3D
) {
1994 assert(surf
->phys_level0_sa
.array_len
== 1);
1995 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1997 assert(surf
->dim
== ISL_SURF_DIM_2D
);
1998 assert(surf
->usage
& ISL_SURF_USAGE_CUBE_BIT
);
1999 assert(surf
->phys_level0_sa
.array_len
== 6);
2000 assert(logical_z_offset_px
< surf
->phys_level0_sa
.array_len
);
2003 const struct isl_extent3d image_align_sa
=
2004 isl_surf_get_image_alignment_sa(surf
);
2006 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2007 const uint32_t H0
= surf
->phys_level0_sa
.height
;
2008 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
2009 const uint32_t AL
= surf
->phys_level0_sa
.array_len
;
2014 for (uint32_t l
= 0; l
< level
; ++l
) {
2015 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
2016 const uint32_t level_d
=
2017 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, l
) : AL
,
2019 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
2021 y
+= level_h
* max_layers_vert
;
2024 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
2025 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
2026 const uint32_t level_d
=
2027 isl_align_npot(surf
->dim
== ISL_SURF_DIM_3D
? isl_minify(D0
, level
) : AL
,
2030 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
2032 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
2033 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
2040 get_image_offset_sa_gen6_stencil_hiz(const struct isl_surf
*surf
,
2042 uint32_t logical_array_layer
,
2043 uint32_t *x_offset_sa
,
2044 uint32_t *y_offset_sa
)
2046 assert(level
< surf
->levels
);
2047 assert(surf
->logical_level0_px
.depth
== 1);
2048 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2050 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2052 const struct isl_extent3d image_align_sa
=
2053 isl_surf_get_image_alignment_sa(surf
);
2055 struct isl_tile_info tile_info
;
2056 isl_tiling_get_info(surf
->tiling
, fmtl
->bpb
, &tile_info
);
2057 const struct isl_extent2d tile_extent_sa
= {
2058 .w
= tile_info
.logical_extent_el
.w
* fmtl
->bw
,
2059 .h
= tile_info
.logical_extent_el
.h
* fmtl
->bh
,
2061 /* Tile size is a multiple of image alignment */
2062 assert(tile_extent_sa
.w
% image_align_sa
.w
== 0);
2063 assert(tile_extent_sa
.h
% image_align_sa
.h
== 0);
2065 const uint32_t W0
= surf
->phys_level0_sa
.w
;
2066 const uint32_t H0
= surf
->phys_level0_sa
.h
;
2068 /* Each image has the same height as LOD0 because the hardware thinks
2069 * everything is LOD0
2071 const uint32_t H
= isl_align(H0
, image_align_sa
.h
);
2073 /* Quick sanity check for consistency */
2074 if (surf
->phys_level0_sa
.array_len
> 1)
2075 assert(surf
->array_pitch_el_rows
== isl_assert_div(H
, fmtl
->bh
));
2077 uint32_t x
= 0, y
= 0;
2078 for (uint32_t l
= 0; l
< level
; ++l
) {
2079 const uint32_t W
= isl_minify(W0
, l
);
2081 const uint32_t w
= isl_align(W
, tile_extent_sa
.w
);
2082 const uint32_t h
= isl_align(H
* surf
->phys_level0_sa
.a
,
2092 y
+= H
* logical_array_layer
;
2099 * A variant of isl_surf_get_image_offset_sa() specific to
2100 * ISL_DIM_LAYOUT_GEN9_1D.
2103 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
2104 uint32_t level
, uint32_t layer
,
2105 uint32_t *x_offset_sa
,
2106 uint32_t *y_offset_sa
)
2108 assert(level
< surf
->levels
);
2109 assert(layer
< surf
->phys_level0_sa
.array_len
);
2110 assert(surf
->phys_level0_sa
.height
== 1);
2111 assert(surf
->phys_level0_sa
.depth
== 1);
2112 assert(surf
->samples
== 1);
2114 const uint32_t W0
= surf
->phys_level0_sa
.width
;
2115 const struct isl_extent3d image_align_sa
=
2116 isl_surf_get_image_alignment_sa(surf
);
2120 for (uint32_t l
= 0; l
< level
; ++l
) {
2121 uint32_t W
= isl_minify(W0
, l
);
2122 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
2128 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
2132 * Calculate the offset, in units of surface samples, to a subimage in the
2135 * @invariant level < surface levels
2136 * @invariant logical_array_layer < logical array length of surface
2137 * @invariant logical_z_offset_px < logical depth of surface at level
2140 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2142 uint32_t logical_array_layer
,
2143 uint32_t logical_z_offset_px
,
2144 uint32_t *x_offset_sa
,
2145 uint32_t *y_offset_sa
)
2147 assert(level
< surf
->levels
);
2148 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2149 assert(logical_z_offset_px
2150 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2152 switch (surf
->dim_layout
) {
2153 case ISL_DIM_LAYOUT_GEN9_1D
:
2154 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
2155 x_offset_sa
, y_offset_sa
);
2157 case ISL_DIM_LAYOUT_GEN4_2D
:
2158 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
2159 + logical_z_offset_px
,
2160 x_offset_sa
, y_offset_sa
);
2162 case ISL_DIM_LAYOUT_GEN4_3D
:
2163 get_image_offset_sa_gen4_3d(surf
, level
, logical_array_layer
+
2164 logical_z_offset_px
,
2165 x_offset_sa
, y_offset_sa
);
2167 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
2168 get_image_offset_sa_gen6_stencil_hiz(surf
, level
, logical_array_layer
+
2169 logical_z_offset_px
,
2170 x_offset_sa
, y_offset_sa
);
2174 unreachable("not reached");
2179 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2181 uint32_t logical_array_layer
,
2182 uint32_t logical_z_offset_px
,
2183 uint32_t *x_offset_el
,
2184 uint32_t *y_offset_el
)
2186 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2188 assert(level
< surf
->levels
);
2189 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
2190 assert(logical_z_offset_px
2191 < isl_minify(surf
->logical_level0_px
.depth
, level
));
2193 uint32_t x_offset_sa
, y_offset_sa
;
2194 isl_surf_get_image_offset_sa(surf
, level
,
2195 logical_array_layer
,
2196 logical_z_offset_px
,
2200 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
2201 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
2205 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2207 uint32_t logical_array_layer
,
2208 uint32_t logical_z_offset_px
,
2210 uint32_t *x_offset_sa
,
2211 uint32_t *y_offset_sa
)
2213 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2215 uint32_t total_x_offset_el
, total_y_offset_el
;
2216 isl_surf_get_image_offset_el(surf
, level
, logical_array_layer
,
2217 logical_z_offset_px
,
2219 &total_y_offset_el
);
2221 uint32_t x_offset_el
, y_offset_el
;
2222 isl_tiling_get_intratile_offset_el(surf
->tiling
, fmtl
->bpb
,
2231 *x_offset_sa
= x_offset_el
* fmtl
->bw
;
2233 assert(x_offset_el
== 0);
2237 *y_offset_sa
= y_offset_el
* fmtl
->bh
;
2239 assert(y_offset_el
== 0);
2244 isl_surf_get_image_surf(const struct isl_device
*dev
,
2245 const struct isl_surf
*surf
,
2247 uint32_t logical_array_layer
,
2248 uint32_t logical_z_offset_px
,
2249 struct isl_surf
*image_surf
,
2251 uint32_t *x_offset_sa
,
2252 uint32_t *y_offset_sa
)
2254 isl_surf_get_image_offset_B_tile_sa(surf
,
2256 logical_array_layer
,
2257 logical_z_offset_px
,
2262 /* Even for cube maps there will be only single face, therefore drop the
2263 * corresponding flag if present.
2265 const isl_surf_usage_flags_t usage
=
2266 surf
->usage
& (~ISL_SURF_USAGE_CUBE_BIT
);
2269 ok
= isl_surf_init(dev
, image_surf
,
2270 .dim
= ISL_SURF_DIM_2D
,
2271 .format
= surf
->format
,
2272 .width
= isl_minify(surf
->logical_level0_px
.w
, level
),
2273 .height
= isl_minify(surf
->logical_level0_px
.h
, level
),
2277 .samples
= surf
->samples
,
2278 .row_pitch_B
= surf
->row_pitch_B
,
2280 .tiling_flags
= (1 << surf
->tiling
));
2285 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2287 uint32_t row_pitch_B
,
2288 uint32_t total_x_offset_el
,
2289 uint32_t total_y_offset_el
,
2290 uint32_t *base_address_offset
,
2291 uint32_t *x_offset_el
,
2292 uint32_t *y_offset_el
)
2294 if (tiling
== ISL_TILING_LINEAR
) {
2295 assert(bpb
% 8 == 0);
2296 *base_address_offset
= total_y_offset_el
* row_pitch_B
+
2297 total_x_offset_el
* (bpb
/ 8);
2303 struct isl_tile_info tile_info
;
2304 isl_tiling_get_info(tiling
, bpb
, &tile_info
);
2306 assert(row_pitch_B
% tile_info
.phys_extent_B
.width
== 0);
2308 /* For non-power-of-two formats, we need the address to be both tile and
2309 * element-aligned. The easiest way to achieve this is to work with a tile
2310 * that is three times as wide as the regular tile.
2312 * The tile info returned by get_tile_info has a logical size that is an
2313 * integer number of tile_info.format_bpb size elements. To scale the
2314 * tile, we scale up the physical width and then treat the logical tile
2315 * size as if it has bpb size elements.
2317 const uint32_t tile_el_scale
= bpb
/ tile_info
.format_bpb
;
2318 tile_info
.phys_extent_B
.width
*= tile_el_scale
;
2320 /* Compute the offset into the tile */
2321 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
2322 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
2324 /* Compute the offset of the tile in units of whole tiles */
2325 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
2326 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
2328 *base_address_offset
=
2329 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch_B
+
2330 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
2334 isl_surf_get_depth_format(const struct isl_device
*dev
,
2335 const struct isl_surf
*surf
)
2337 /* Support for separate stencil buffers began in gen5. Support for
2338 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
2339 * those that supported separate and interleaved stencil, were gen5 and
2342 * For a list of all available formats, see the Sandybridge PRM >> Volume
2343 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
2347 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
2349 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
2352 assert(ISL_DEV_GEN(dev
) < 7);
2354 switch (surf
->format
) {
2356 unreachable("bad isl depth format");
2357 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
2358 assert(ISL_DEV_GEN(dev
) < 7);
2359 return 0; /* D32_FLOAT_S8X24_UINT */
2360 case ISL_FORMAT_R32_FLOAT
:
2361 assert(!has_stencil
);
2362 return 1; /* D32_FLOAT */
2363 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
2365 assert(ISL_DEV_GEN(dev
) < 7);
2366 return 2; /* D24_UNORM_S8_UINT */
2368 assert(ISL_DEV_GEN(dev
) >= 5);
2369 return 3; /* D24_UNORM_X8_UINT */
2371 case ISL_FORMAT_R16_UNORM
:
2372 assert(!has_stencil
);
2373 return 5; /* D16_UNORM */
2378 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
2379 struct isl_swizzle swizzle
)
2381 if (devinfo
->is_haswell
) {
2382 /* From the Haswell PRM,
2383 * RENDER_SURFACE_STATE::Shader Channel Select Red
2385 * "The Shader channel selects also define which shader channels are
2386 * written to which surface channel. If the Shader channel select is
2387 * SCS_ZERO or SCS_ONE then it is not written to the surface. If the
2388 * shader channel select is SCS_RED it is written to the surface red
2389 * channel and so on. If more than one shader channel select is set
2390 * to the same surface channel only the first shader channel in RGBA
2391 * order will be written."
2394 } else if (devinfo
->gen
<= 7) {
2395 /* Ivy Bridge and early doesn't have any swizzling */
2396 return isl_swizzle_is_identity(swizzle
);
2398 /* From the Sky Lake PRM Vol. 2d,
2399 * RENDER_SURFACE_STATE::Shader Channel Select Red
2401 * "For Render Target, Red, Green and Blue Shader Channel Selects
2402 * MUST be such that only valid components can be swapped i.e. only
2403 * change the order of components in the pixel. Any other values for
2404 * these Shader Channel Select fields are not valid for Render
2405 * Targets. This also means that there MUST not be multiple shader
2406 * channels mapped to the same RT channel."
2408 * From the Sky Lake PRM Vol. 2d,
2409 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
2411 * "For Render Target, this field MUST be programmed to
2412 * value = SCS_ALPHA."
2414 return (swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
2415 swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
2416 swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
) &&
2417 (swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
2418 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
2419 swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
) &&
2420 (swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
2421 swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
2422 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
) &&
2423 swizzle
.r
!= swizzle
.g
&&
2424 swizzle
.r
!= swizzle
.b
&&
2425 swizzle
.g
!= swizzle
.b
&&
2426 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
2430 static enum isl_channel_select
2431 swizzle_select(enum isl_channel_select chan
, struct isl_swizzle swizzle
)
2434 case ISL_CHANNEL_SELECT_ZERO
:
2435 case ISL_CHANNEL_SELECT_ONE
:
2437 case ISL_CHANNEL_SELECT_RED
:
2439 case ISL_CHANNEL_SELECT_GREEN
:
2441 case ISL_CHANNEL_SELECT_BLUE
:
2443 case ISL_CHANNEL_SELECT_ALPHA
:
2446 unreachable("Invalid swizzle component");
2451 * Returns the single swizzle that is equivalent to applying the two given
2452 * swizzles in sequence.
2455 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
)
2457 return (struct isl_swizzle
) {
2458 .r
= swizzle_select(first
.r
, second
),
2459 .g
= swizzle_select(first
.g
, second
),
2460 .b
= swizzle_select(first
.b
, second
),
2461 .a
= swizzle_select(first
.a
, second
),
2466 * Returns a swizzle that is the pseudo-inverse of this swizzle.
2469 isl_swizzle_invert(struct isl_swizzle swizzle
)
2471 /* Default to zero for channels which do not show up in the swizzle */
2472 enum isl_channel_select chans
[4] = {
2473 ISL_CHANNEL_SELECT_ZERO
,
2474 ISL_CHANNEL_SELECT_ZERO
,
2475 ISL_CHANNEL_SELECT_ZERO
,
2476 ISL_CHANNEL_SELECT_ZERO
,
2479 /* We go in ABGR order so that, if there are any duplicates, the first one
2480 * is taken if you look at it in RGBA order. This is what Haswell hardware
2481 * does for render target swizzles.
2483 if ((unsigned)(swizzle
.a
- ISL_CHANNEL_SELECT_RED
) < 4)
2484 chans
[swizzle
.a
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_ALPHA
;
2485 if ((unsigned)(swizzle
.b
- ISL_CHANNEL_SELECT_RED
) < 4)
2486 chans
[swizzle
.b
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_BLUE
;
2487 if ((unsigned)(swizzle
.g
- ISL_CHANNEL_SELECT_RED
) < 4)
2488 chans
[swizzle
.g
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_GREEN
;
2489 if ((unsigned)(swizzle
.r
- ISL_CHANNEL_SELECT_RED
) < 4)
2490 chans
[swizzle
.r
- ISL_CHANNEL_SELECT_RED
] = ISL_CHANNEL_SELECT_RED
;
2492 return (struct isl_swizzle
) { chans
[0], chans
[1], chans
[2], chans
[3] };