2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
36 void PRINTFLIKE(3, 4) UNUSED
37 __isl_finishme(const char *file
, int line
, const char *fmt
, ...)
43 vsnprintf(buf
, sizeof(buf
), fmt
, ap
);
46 fprintf(stderr
, "%s:%d: FINISHME: %s\n", file
, line
, buf
);
50 isl_device_init(struct isl_device
*dev
,
51 const struct brw_device_info
*info
,
52 bool has_bit6_swizzling
)
55 dev
->use_separate_stencil
= ISL_DEV_GEN(dev
) >= 6;
56 dev
->has_bit6_swizzling
= has_bit6_swizzling
;
58 /* The ISL_DEV macros may be defined in the CFLAGS, thus hardcoding some
59 * device properties at buildtime. Verify that the macros with the device
60 * properties chosen during runtime.
62 ISL_DEV_GEN_SANITIZE(dev
);
63 ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(dev
);
65 /* Did we break hiz or stencil? */
66 if (ISL_DEV_USE_SEPARATE_STENCIL(dev
))
67 assert(info
->has_hiz_and_separate_stencil
);
68 if (info
->must_use_separate_stencil
)
69 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
73 * @brief Query the set of multisamples supported by the device.
75 * This function always returns non-zero, as ISL_SAMPLE_COUNT_1_BIT is always
78 isl_sample_count_mask_t ATTRIBUTE_CONST
79 isl_device_get_sample_counts(struct isl_device
*dev
)
81 if (ISL_DEV_GEN(dev
) >= 9) {
82 return ISL_SAMPLE_COUNT_1_BIT
|
83 ISL_SAMPLE_COUNT_2_BIT
|
84 ISL_SAMPLE_COUNT_4_BIT
|
85 ISL_SAMPLE_COUNT_8_BIT
|
86 ISL_SAMPLE_COUNT_16_BIT
;
87 } else if (ISL_DEV_GEN(dev
) >= 8) {
88 return ISL_SAMPLE_COUNT_1_BIT
|
89 ISL_SAMPLE_COUNT_2_BIT
|
90 ISL_SAMPLE_COUNT_4_BIT
|
91 ISL_SAMPLE_COUNT_8_BIT
;
92 } else if (ISL_DEV_GEN(dev
) >= 7) {
93 return ISL_SAMPLE_COUNT_1_BIT
|
94 ISL_SAMPLE_COUNT_4_BIT
|
95 ISL_SAMPLE_COUNT_8_BIT
;
96 } else if (ISL_DEV_GEN(dev
) >= 6) {
97 return ISL_SAMPLE_COUNT_1_BIT
|
98 ISL_SAMPLE_COUNT_4_BIT
;
100 return ISL_SAMPLE_COUNT_1_BIT
;
105 * @param[out] info is written only on success
108 isl_tiling_get_info(const struct isl_device
*dev
,
109 enum isl_tiling tiling
,
111 struct isl_tile_info
*tile_info
)
113 const uint32_t bs
= format_bpb
/ 8;
114 struct isl_extent2d logical_el
, phys_B
;
117 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
120 case ISL_TILING_LINEAR
:
121 logical_el
= isl_extent2d(1, 1);
122 phys_B
= isl_extent2d(bs
, 1);
126 logical_el
= isl_extent2d(512 / bs
, 8);
127 phys_B
= isl_extent2d(512, 8);
131 logical_el
= isl_extent2d(128 / bs
, 32);
132 phys_B
= isl_extent2d(128, 32);
137 logical_el
= isl_extent2d(64, 64);
138 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfacePitch:
140 * "If the surface is a stencil buffer (and thus has Tile Mode set
141 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
142 * computed based on width, as the stencil buffer is stored with two
145 * This, together with the fact that stencil buffers are referred to as
146 * being Y-tiled in the PRMs for older hardware implies that the
147 * physical size of a W-tile is actually the same as for a Y-tile.
149 phys_B
= isl_extent2d(128, 32);
153 case ISL_TILING_Ys
: {
154 if (ISL_DEV_GEN(dev
) < 9)
157 if (!isl_is_pow2(bs
))
160 bool is_Ys
= tiling
== ISL_TILING_Ys
;
162 unsigned width
= 1 << (6 + (ffs(bs
) / 2) + (2 * is_Ys
));
163 unsigned height
= 1 << (6 - (ffs(bs
) / 2) + (2 * is_Ys
));
165 logical_el
= isl_extent2d(width
/ bs
, height
);
166 phys_B
= isl_extent2d(width
, height
);
171 unreachable("not reached");
174 *tile_info
= (struct isl_tile_info
) {
176 .logical_extent_el
= logical_el
,
177 .phys_extent_B
= phys_B
,
184 * @param[out] tiling is set only on success
187 isl_surf_choose_tiling(const struct isl_device
*dev
,
188 const struct isl_surf_init_info
*restrict info
,
189 enum isl_tiling
*tiling
)
191 isl_tiling_flags_t tiling_flags
= info
->tiling_flags
;
193 /* Filter if multiple tiling options are given */
194 if (!isl_is_pow2(tiling_flags
)) {
195 if (ISL_DEV_GEN(dev
) >= 7) {
196 gen7_filter_tiling(dev
, info
, &tiling_flags
);
198 isl_finishme("%s: gen%u", __func__
, ISL_DEV_GEN(dev
));
199 gen7_filter_tiling(dev
, info
, &tiling_flags
);
203 #define CHOOSE(__tiling) \
205 if (tiling_flags & (1u << (__tiling))) { \
206 *tiling = (__tiling); \
211 /* Of the tiling modes remaining, choose the one that offers the best
215 if (info
->dim
== ISL_SURF_DIM_1D
) {
216 /* Prefer linear for 1D surfaces because they do not benefit from
217 * tiling. To the contrary, tiling leads to wasted memory and poor
218 * memory locality due to the swizzling and alignment restrictions
219 * required in tiled surfaces.
221 CHOOSE(ISL_TILING_LINEAR
);
224 CHOOSE(ISL_TILING_Ys
);
225 CHOOSE(ISL_TILING_Yf
);
226 CHOOSE(ISL_TILING_Y0
);
227 CHOOSE(ISL_TILING_X
);
228 CHOOSE(ISL_TILING_W
);
229 CHOOSE(ISL_TILING_LINEAR
);
233 /* No tiling mode accomodates the inputs. */
238 isl_choose_msaa_layout(const struct isl_device
*dev
,
239 const struct isl_surf_init_info
*info
,
240 enum isl_tiling tiling
,
241 enum isl_msaa_layout
*msaa_layout
)
243 if (ISL_DEV_GEN(dev
) >= 8) {
244 return gen8_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
245 } else if (ISL_DEV_GEN(dev
) >= 7) {
246 return gen7_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
247 } else if (ISL_DEV_GEN(dev
) >= 6) {
248 return gen6_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
250 return gen4_choose_msaa_layout(dev
, info
, tiling
, msaa_layout
);
255 isl_msaa_interleaved_scale_px_to_sa(uint32_t samples
,
256 uint32_t *width
, uint32_t *height
)
258 assert(isl_is_pow2(samples
));
260 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
263 * If the surface is multisampled and it is a depth or stencil surface
264 * or Multisampled Surface StorageFormat in SURFACE_STATE is
265 * MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows before
269 *width
= isl_align(*width
, 2) << ((ffs(samples
) - 0) / 2);
271 *height
= isl_align(*height
, 2) << ((ffs(samples
) - 1) / 2);
274 static enum isl_array_pitch_span
275 isl_choose_array_pitch_span(const struct isl_device
*dev
,
276 const struct isl_surf_init_info
*restrict info
,
277 enum isl_dim_layout dim_layout
,
278 const struct isl_extent4d
*phys_level0_sa
)
280 switch (dim_layout
) {
281 case ISL_DIM_LAYOUT_GEN9_1D
:
282 case ISL_DIM_LAYOUT_GEN4_2D
:
283 if (ISL_DEV_GEN(dev
) >= 8) {
284 /* QPitch becomes programmable in Broadwell. So choose the
285 * most compact QPitch possible in order to conserve memory.
287 * From the Broadwell PRM >> Volume 2d: Command Reference: Structures
288 * >> RENDER_SURFACE_STATE Surface QPitch (p325):
290 * - Software must ensure that this field is set to a value
291 * sufficiently large such that the array slices in the surface
292 * do not overlap. Refer to the Memory Data Formats section for
293 * information on how surfaces are stored in memory.
295 * - This field specifies the distance in rows between array
296 * slices. It is used only in the following cases:
298 * - Surface Array is enabled OR
299 * - Number of Mulitsamples is not NUMSAMPLES_1 and
300 * Multisampled Surface Storage Format set to MSFMT_MSS OR
301 * - Surface Type is SURFTYPE_CUBE
303 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
304 } else if (ISL_DEV_GEN(dev
) >= 7) {
305 /* Note that Ivybridge introduces
306 * RENDER_SURFACE_STATE.SurfaceArraySpacing, which provides the
307 * driver more control over the QPitch.
310 if (phys_level0_sa
->array_len
== 1) {
311 /* The hardware will never use the QPitch. So choose the most
312 * compact QPitch possible in order to conserve memory.
314 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
317 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
318 /* From the Ivybridge PRM >> Volume 1 Part 1: Graphics Core >>
319 * Section 6.18.4.7: Surface Arrays (p112):
321 * If Surface Array Spacing is set to ARYSPC_FULL (note that
322 * the depth buffer and stencil buffer have an implied value of
325 return ISL_ARRAY_PITCH_SPAN_FULL
;
328 if (info
->levels
== 1) {
329 /* We are able to set RENDER_SURFACE_STATE.SurfaceArraySpacing
332 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
335 return ISL_ARRAY_PITCH_SPAN_FULL
;
336 } else if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
337 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
338 isl_surf_usage_is_stencil(info
->usage
)) {
339 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
340 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
342 * The separate stencil buffer does not support mip mapping, thus
343 * the storage for LODs other than LOD 0 is not needed.
345 assert(info
->levels
== 1);
346 assert(phys_level0_sa
->array_len
== 1);
347 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
349 if ((ISL_DEV_GEN(dev
) == 5 || ISL_DEV_GEN(dev
) == 6) &&
350 ISL_DEV_USE_SEPARATE_STENCIL(dev
) &&
351 isl_surf_usage_is_stencil(info
->usage
)) {
352 /* [ILK-SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
353 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
355 * The separate stencil buffer does not support mip mapping,
356 * thus the storage for LODs other than LOD 0 is not needed.
358 assert(info
->levels
== 1);
359 assert(phys_level0_sa
->array_len
== 1);
360 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
363 if (phys_level0_sa
->array_len
== 1) {
364 /* The hardware will never use the QPitch. So choose the most
365 * compact QPitch possible in order to conserve memory.
367 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
370 return ISL_ARRAY_PITCH_SPAN_FULL
;
373 case ISL_DIM_LAYOUT_GEN4_3D
:
374 /* The hardware will never use the QPitch. So choose the most
375 * compact QPitch possible in order to conserve memory.
377 return ISL_ARRAY_PITCH_SPAN_COMPACT
;
380 unreachable("bad isl_dim_layout");
381 return ISL_ARRAY_PITCH_SPAN_FULL
;
385 isl_choose_image_alignment_el(const struct isl_device
*dev
,
386 const struct isl_surf_init_info
*restrict info
,
387 enum isl_tiling tiling
,
388 enum isl_msaa_layout msaa_layout
,
389 struct isl_extent3d
*image_align_el
)
391 if (ISL_DEV_GEN(dev
) >= 9) {
392 gen9_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
394 } else if (ISL_DEV_GEN(dev
) >= 8) {
395 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
397 } else if (ISL_DEV_GEN(dev
) >= 7) {
398 gen7_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
400 } else if (ISL_DEV_GEN(dev
) >= 6) {
401 gen6_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
404 gen4_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
409 static enum isl_dim_layout
410 isl_surf_choose_dim_layout(const struct isl_device
*dev
,
411 enum isl_surf_dim logical_dim
)
413 if (ISL_DEV_GEN(dev
) >= 9) {
414 switch (logical_dim
) {
415 case ISL_SURF_DIM_1D
:
416 return ISL_DIM_LAYOUT_GEN9_1D
;
417 case ISL_SURF_DIM_2D
:
418 case ISL_SURF_DIM_3D
:
419 return ISL_DIM_LAYOUT_GEN4_2D
;
422 switch (logical_dim
) {
423 case ISL_SURF_DIM_1D
:
424 case ISL_SURF_DIM_2D
:
425 return ISL_DIM_LAYOUT_GEN4_2D
;
426 case ISL_SURF_DIM_3D
:
427 return ISL_DIM_LAYOUT_GEN4_3D
;
431 unreachable("bad isl_surf_dim");
432 return ISL_DIM_LAYOUT_GEN4_2D
;
436 * Calculate the physical extent of the surface's first level, in units of
437 * surface samples. The result is aligned to the format's compression block.
440 isl_calc_phys_level0_extent_sa(const struct isl_device
*dev
,
441 const struct isl_surf_init_info
*restrict info
,
442 enum isl_dim_layout dim_layout
,
443 enum isl_tiling tiling
,
444 enum isl_msaa_layout msaa_layout
,
445 struct isl_extent4d
*phys_level0_sa
)
447 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
449 if (isl_format_is_yuv(info
->format
))
450 isl_finishme("%s:%s: YUV format", __FILE__
, __func__
);
453 case ISL_SURF_DIM_1D
:
454 assert(info
->height
== 1);
455 assert(info
->depth
== 1);
456 assert(info
->samples
== 1);
457 assert(!isl_format_is_compressed(info
->format
));
459 switch (dim_layout
) {
460 case ISL_DIM_LAYOUT_GEN4_3D
:
461 unreachable("bad isl_dim_layout");
463 case ISL_DIM_LAYOUT_GEN9_1D
:
464 case ISL_DIM_LAYOUT_GEN4_2D
:
465 *phys_level0_sa
= (struct isl_extent4d
) {
469 .a
= info
->array_len
,
475 case ISL_SURF_DIM_2D
:
476 assert(dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
);
478 if (tiling
== ISL_TILING_Ys
&& info
->samples
> 1)
479 isl_finishme("%s:%s: multisample TileYs layout", __FILE__
, __func__
);
481 switch (msaa_layout
) {
482 case ISL_MSAA_LAYOUT_NONE
:
483 assert(info
->depth
== 1);
484 assert(info
->samples
== 1);
486 *phys_level0_sa
= (struct isl_extent4d
) {
487 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
488 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
490 .a
= info
->array_len
,
494 case ISL_MSAA_LAYOUT_ARRAY
:
495 assert(info
->depth
== 1);
496 assert(info
->array_len
== 1);
497 assert(!isl_format_is_compressed(info
->format
));
499 *phys_level0_sa
= (struct isl_extent4d
) {
507 case ISL_MSAA_LAYOUT_INTERLEAVED
:
508 assert(info
->depth
== 1);
509 assert(info
->array_len
== 1);
510 assert(!isl_format_is_compressed(info
->format
));
512 *phys_level0_sa
= (struct isl_extent4d
) {
519 isl_msaa_interleaved_scale_px_to_sa(info
->samples
,
526 case ISL_SURF_DIM_3D
:
527 assert(info
->array_len
== 1);
528 assert(info
->samples
== 1);
531 isl_finishme("%s:%s: compression block with depth > 1",
535 switch (dim_layout
) {
536 case ISL_DIM_LAYOUT_GEN9_1D
:
537 unreachable("bad isl_dim_layout");
539 case ISL_DIM_LAYOUT_GEN4_2D
:
540 assert(ISL_DEV_GEN(dev
) >= 9);
542 *phys_level0_sa
= (struct isl_extent4d
) {
543 .w
= isl_align_npot(info
->width
, fmtl
->bw
),
544 .h
= isl_align_npot(info
->height
, fmtl
->bh
),
550 case ISL_DIM_LAYOUT_GEN4_3D
:
551 assert(ISL_DEV_GEN(dev
) < 9);
552 *phys_level0_sa
= (struct isl_extent4d
) {
553 .w
= isl_align(info
->width
, fmtl
->bw
),
554 .h
= isl_align(info
->height
, fmtl
->bh
),
565 * A variant of isl_calc_phys_slice0_extent_sa() specific to
566 * ISL_DIM_LAYOUT_GEN4_2D.
569 isl_calc_phys_slice0_extent_sa_gen4_2d(
570 const struct isl_device
*dev
,
571 const struct isl_surf_init_info
*restrict info
,
572 enum isl_msaa_layout msaa_layout
,
573 const struct isl_extent3d
*image_align_sa
,
574 const struct isl_extent4d
*phys_level0_sa
,
575 struct isl_extent2d
*phys_slice0_sa
)
577 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
579 assert(phys_level0_sa
->depth
== 1);
581 if (info
->levels
== 1 && msaa_layout
!= ISL_MSAA_LAYOUT_INTERLEAVED
) {
582 /* Do not pad the surface to the image alignment. Instead, pad it only
583 * to the pixel format's block alignment.
585 * For tiled surfaces, using a reduced alignment here avoids wasting CPU
586 * cycles on the below mipmap layout caluclations. Reducing the
587 * alignment here is safe because we later align the row pitch and array
588 * pitch to the tile boundary. It is safe even for
589 * ISL_MSAA_LAYOUT_INTERLEAVED, because phys_level0_sa is already scaled
590 * to accomodate the interleaved samples.
592 * For linear surfaces, reducing the alignment here permits us to later
593 * choose an arbitrary, non-aligned row pitch. If the surface backs
594 * a VkBuffer, then an arbitrary pitch may be needed to accomodate
595 * VkBufferImageCopy::bufferRowLength.
597 *phys_slice0_sa
= (struct isl_extent2d
) {
598 .w
= isl_align_npot(phys_level0_sa
->w
, fmtl
->bw
),
599 .h
= isl_align_npot(phys_level0_sa
->h
, fmtl
->bh
),
604 uint32_t slice_top_w
= 0;
605 uint32_t slice_bottom_w
= 0;
606 uint32_t slice_left_h
= 0;
607 uint32_t slice_right_h
= 0;
609 uint32_t W0
= phys_level0_sa
->w
;
610 uint32_t H0
= phys_level0_sa
->h
;
612 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
613 uint32_t W
= isl_minify(W0
, l
);
614 uint32_t H
= isl_minify(H0
, l
);
616 if (msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
617 /* From the Broadwell PRM >> Volume 5: Memory Views >> Computing Mip Level
620 * If the surface is multisampled and it is a depth or stencil
621 * surface or Multisampled Surface StorageFormat in
622 * SURFACE_STATE is MSFMT_DEPTH_STENCIL, W_L and H_L must be
623 * adjusted as follows before proceeding: [...]
625 isl_msaa_interleaved_scale_px_to_sa(info
->samples
, &W
, &H
);
628 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
629 uint32_t h
= isl_align_npot(H
, image_align_sa
->h
);
646 *phys_slice0_sa
= (struct isl_extent2d
) {
647 .w
= MAX(slice_top_w
, slice_bottom_w
),
648 .h
= MAX(slice_left_h
, slice_right_h
),
653 * A variant of isl_calc_phys_slice0_extent_sa() specific to
654 * ISL_DIM_LAYOUT_GEN4_3D.
657 isl_calc_phys_slice0_extent_sa_gen4_3d(
658 const struct isl_device
*dev
,
659 const struct isl_surf_init_info
*restrict info
,
660 const struct isl_extent3d
*image_align_sa
,
661 const struct isl_extent4d
*phys_level0_sa
,
662 struct isl_extent2d
*phys_slice0_sa
)
664 assert(info
->samples
== 1);
665 assert(phys_level0_sa
->array_len
== 1);
667 uint32_t slice_w
= 0;
668 uint32_t slice_h
= 0;
670 uint32_t W0
= phys_level0_sa
->w
;
671 uint32_t H0
= phys_level0_sa
->h
;
672 uint32_t D0
= phys_level0_sa
->d
;
674 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
675 uint32_t level_w
= isl_align_npot(isl_minify(W0
, l
), image_align_sa
->w
);
676 uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
->h
);
677 uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
->d
);
679 uint32_t max_layers_horiz
= MIN(level_d
, 1u << l
);
680 uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
682 slice_w
= MAX(slice_w
, level_w
* max_layers_horiz
);
683 slice_h
+= level_h
* max_layers_vert
;
686 *phys_slice0_sa
= (struct isl_extent2d
) {
693 * A variant of isl_calc_phys_slice0_extent_sa() specific to
694 * ISL_DIM_LAYOUT_GEN9_1D.
697 isl_calc_phys_slice0_extent_sa_gen9_1d(
698 const struct isl_device
*dev
,
699 const struct isl_surf_init_info
*restrict info
,
700 const struct isl_extent3d
*image_align_sa
,
701 const struct isl_extent4d
*phys_level0_sa
,
702 struct isl_extent2d
*phys_slice0_sa
)
704 MAYBE_UNUSED
const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
706 assert(phys_level0_sa
->height
== 1);
707 assert(phys_level0_sa
->depth
== 1);
708 assert(info
->samples
== 1);
709 assert(image_align_sa
->w
>= fmtl
->bw
);
711 uint32_t slice_w
= 0;
712 const uint32_t W0
= phys_level0_sa
->w
;
714 for (uint32_t l
= 0; l
< info
->levels
; ++l
) {
715 uint32_t W
= isl_minify(W0
, l
);
716 uint32_t w
= isl_align_npot(W
, image_align_sa
->w
);
721 *phys_slice0_sa
= isl_extent2d(slice_w
, 1);
725 * Calculate the physical extent of the surface's first array slice, in units
726 * of surface samples. If the surface is multi-leveled, then the result will
727 * be aligned to \a image_align_sa.
730 isl_calc_phys_slice0_extent_sa(const struct isl_device
*dev
,
731 const struct isl_surf_init_info
*restrict info
,
732 enum isl_dim_layout dim_layout
,
733 enum isl_msaa_layout msaa_layout
,
734 const struct isl_extent3d
*image_align_sa
,
735 const struct isl_extent4d
*phys_level0_sa
,
736 struct isl_extent2d
*phys_slice0_sa
)
738 switch (dim_layout
) {
739 case ISL_DIM_LAYOUT_GEN9_1D
:
740 isl_calc_phys_slice0_extent_sa_gen9_1d(dev
, info
,
741 image_align_sa
, phys_level0_sa
,
744 case ISL_DIM_LAYOUT_GEN4_2D
:
745 isl_calc_phys_slice0_extent_sa_gen4_2d(dev
, info
, msaa_layout
,
746 image_align_sa
, phys_level0_sa
,
749 case ISL_DIM_LAYOUT_GEN4_3D
:
750 isl_calc_phys_slice0_extent_sa_gen4_3d(dev
, info
, image_align_sa
,
751 phys_level0_sa
, phys_slice0_sa
);
757 * Calculate the pitch between physical array slices, in units of rows of
761 isl_calc_array_pitch_el_rows(const struct isl_device
*dev
,
762 const struct isl_surf_init_info
*restrict info
,
763 const struct isl_tile_info
*tile_info
,
764 enum isl_dim_layout dim_layout
,
765 enum isl_array_pitch_span array_pitch_span
,
766 const struct isl_extent3d
*image_align_sa
,
767 const struct isl_extent4d
*phys_level0_sa
,
768 const struct isl_extent2d
*phys_slice0_sa
)
770 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
771 uint32_t pitch_sa_rows
= 0;
773 switch (dim_layout
) {
774 case ISL_DIM_LAYOUT_GEN9_1D
:
775 /* Each row is an array slice */
778 case ISL_DIM_LAYOUT_GEN4_2D
:
779 switch (array_pitch_span
) {
780 case ISL_ARRAY_PITCH_SPAN_COMPACT
:
781 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
783 case ISL_ARRAY_PITCH_SPAN_FULL
: {
784 /* The QPitch equation is found in the Broadwell PRM >> Volume 5:
785 * Memory Views >> Common Surface Formats >> Surface Layout >> 2D
786 * Surfaces >> Surface Arrays.
788 uint32_t H0_sa
= phys_level0_sa
->h
;
789 uint32_t H1_sa
= isl_minify(H0_sa
, 1);
791 uint32_t h0_sa
= isl_align_npot(H0_sa
, image_align_sa
->h
);
792 uint32_t h1_sa
= isl_align_npot(H1_sa
, image_align_sa
->h
);
795 if (ISL_DEV_GEN(dev
) >= 7) {
796 /* The QPitch equation changed slightly in Ivybridge. */
802 pitch_sa_rows
= h0_sa
+ h1_sa
+ (m
* image_align_sa
->h
);
804 if (ISL_DEV_GEN(dev
) == 6 && info
->samples
> 1 &&
805 (info
->height
% 4 == 1)) {
806 /* [SNB] Errata from the Sandy Bridge PRM >> Volume 4 Part 1:
807 * Graphics Core >> Section 7.18.3.7: Surface Arrays:
809 * [SNB] Errata: Sampler MSAA Qpitch will be 4 greater than
810 * the value calculated in the equation above , for every
811 * other odd Surface Height starting from 1 i.e. 1,5,9,13.
813 * XXX(chadv): Is the errata natural corollary of the physical
814 * layout of interleaved samples?
819 pitch_sa_rows
= isl_align_npot(pitch_sa_rows
, fmtl
->bh
);
824 case ISL_DIM_LAYOUT_GEN4_3D
:
825 assert(array_pitch_span
== ISL_ARRAY_PITCH_SPAN_COMPACT
);
826 pitch_sa_rows
= isl_align_npot(phys_slice0_sa
->h
, image_align_sa
->h
);
829 unreachable("bad isl_dim_layout");
833 assert(pitch_sa_rows
% fmtl
->bh
== 0);
834 uint32_t pitch_el_rows
= pitch_sa_rows
/ fmtl
->bh
;
836 if (ISL_DEV_GEN(dev
) >= 9 &&
837 info
->dim
== ISL_SURF_DIM_3D
&&
838 tile_info
->tiling
!= ISL_TILING_LINEAR
) {
839 /* From the Skylake BSpec >> RENDER_SURFACE_STATE >> Surface QPitch:
841 * Tile Mode != Linear: This field must be set to an integer multiple
844 pitch_el_rows
= isl_align(pitch_el_rows
, tile_info
->logical_extent_el
.height
);
847 return pitch_el_rows
;
851 * Calculate the pitch of each surface row, in bytes.
854 isl_calc_linear_row_pitch(const struct isl_device
*dev
,
855 const struct isl_surf_init_info
*restrict info
,
856 const struct isl_extent2d
*phys_slice0_sa
)
858 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
860 uint32_t row_pitch
= info
->min_pitch
;
862 /* First, align the surface to a cache line boundary, as the PRM explains
865 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
866 * Formats >> Surface Padding Requirements >> Render Target and Media
869 * The data port accesses data (pixels) outside of the surface if they
870 * are contained in the same cache request as pixels that are within the
871 * surface. These pixels will not be returned by the requesting message,
872 * however if these pixels lie outside of defined pages in the GTT,
873 * a GTT error will result when the cache request is processed. In order
874 * to avoid these GTT errors, “padding” at the bottom of the surface is
875 * sometimes necessary.
877 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
878 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
880 * The sampling engine accesses texels outside of the surface if they
881 * are contained in the same cache line as texels that are within the
882 * surface. These texels will not participate in any calculation
883 * performed by the sampling engine and will not affect the result of
884 * any sampling engine operation, however if these texels lie outside of
885 * defined pages in the GTT, a GTT error will result when the cache line
886 * is accessed. In order to avoid these GTT errors, “padding” at the
887 * bottom and right side of a sampling engine surface is sometimes
890 * It is possible that a cache line will straddle a page boundary if the
891 * base address or pitch is not aligned. All pages included in the cache
892 * lines that are part of the surface must map to valid GTT entries to
893 * avoid errors. To determine the necessary padding on the bottom and
894 * right side of the surface, refer to the table in Alignment Unit Size
895 * section for the i and j parameters for the surface format in use. The
896 * surface must then be extended to the next multiple of the alignment
897 * unit size in each dimension, and all texels contained in this
898 * extended surface must have valid GTT entries.
900 * For example, suppose the surface size is 15 texels by 10 texels and
901 * the alignment parameters are i=4 and j=2. In this case, the extended
902 * surface would be 16 by 10. Note that these calculations are done in
903 * texels, and must be converted to bytes based on the surface format
904 * being used to determine whether additional pages need to be defined.
906 assert(phys_slice0_sa
->w
% fmtl
->bw
== 0);
907 const uint32_t bs
= fmtl
->bpb
/ 8;
908 row_pitch
= MAX(row_pitch
, bs
* (phys_slice0_sa
->w
/ fmtl
->bw
));
910 /* From the Broadwel PRM >> Volume 2d: Command Reference: Structures >>
911 * RENDER_SURFACE_STATE Surface Pitch (p349):
913 * - For linear render target surfaces and surfaces accessed with the
914 * typed data port messages, the pitch must be a multiple of the
915 * element size for non-YUV surface formats. Pitch must be
916 * a multiple of 2 * element size for YUV surface formats.
918 * - [Requirements for SURFTYPE_BUFFER and SURFTYPE_STRBUF, which we
919 * ignore because isl doesn't do buffers.]
921 * - For other linear surfaces, the pitch can be any multiple of
924 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
925 if (isl_format_is_yuv(info
->format
)) {
926 row_pitch
= isl_align_npot(row_pitch
, 2 * bs
);
928 row_pitch
= isl_align_npot(row_pitch
, bs
);
936 * Calculate and apply any padding required for the surface.
938 * @param[inout] total_h_el is updated with the new height
939 * @param[out] pad_bytes is overwritten with additional padding requirements.
942 isl_apply_surface_padding(const struct isl_device
*dev
,
943 const struct isl_surf_init_info
*restrict info
,
944 const struct isl_tile_info
*tile_info
,
945 uint32_t *total_h_el
,
948 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
952 /* From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
953 * Formats >> Surface Padding Requirements >> Render Target and Media
956 * The data port accesses data (pixels) outside of the surface if they
957 * are contained in the same cache request as pixels that are within the
958 * surface. These pixels will not be returned by the requesting message,
959 * however if these pixels lie outside of defined pages in the GTT,
960 * a GTT error will result when the cache request is processed. In
961 * order to avoid these GTT errors, “padding” at the bottom of the
962 * surface is sometimes necessary.
964 * From the Broadwell PRM >> Volume 5: Memory Views >> Common Surface
965 * Formats >> Surface Padding Requirements >> Sampling Engine Surfaces:
967 * ... Lots of padding requirements, all listed separately below.
970 /* We can safely ignore the first padding requirement, quoted below,
971 * because isl doesn't do buffers.
973 * - [pre-BDW] For buffers, which have no inherent “height,” padding
974 * requirements are different. A buffer must be padded to the next
975 * multiple of 256 array elements, with an additional 16 bytes added
976 * beyond that to account for the L1 cache line.
980 * - For compressed textures [...], padding at the bottom of the surface
981 * is to an even compressed row.
983 if (isl_format_is_compressed(info
->format
))
984 *total_h_el
= isl_align(*total_h_el
, 2);
987 * - For cube surfaces, an additional two rows of padding are required
988 * at the bottom of the surface.
990 if (info
->usage
& ISL_SURF_USAGE_CUBE_BIT
)
994 * - For packed YUV, 96 bpt, 48 bpt, and 24 bpt surface formats,
995 * additional padding is required. These surfaces require an extra row
996 * plus 16 bytes of padding at the bottom in addition to the general
997 * padding requirements.
999 if (isl_format_is_yuv(info
->format
) &&
1000 (fmtl
->bpb
== 96 || fmtl
->bpb
== 48|| fmtl
->bpb
== 24)) {
1006 * - For linear surfaces, additional padding of 64 bytes is required at
1007 * the bottom of the surface. This is in addition to the padding
1010 if (tile_info
->tiling
== ISL_TILING_LINEAR
)
1013 /* The below text weakens, not strengthens, the padding requirements for
1014 * linear surfaces. Therefore we can safely ignore it.
1016 * - [BDW+] For SURFTYPE_BUFFER, SURFTYPE_1D, and SURFTYPE_2D non-array,
1017 * non-MSAA, non-mip-mapped surfaces in linear memory, the only
1018 * padding requirement is to the next aligned 64-byte boundary beyond
1019 * the end of the surface. The rest of the padding requirements
1020 * documented above do not apply to these surfaces.
1024 * - [SKL+] For SURFTYPE_2D and SURFTYPE_3D with linear mode and
1025 * height % 4 != 0, the surface must be padded with
1026 * 4-(height % 4)*Surface Pitch # of bytes.
1028 if (ISL_DEV_GEN(dev
) >= 9 &&
1029 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1030 (info
->dim
== ISL_SURF_DIM_2D
|| info
->dim
== ISL_SURF_DIM_3D
)) {
1031 *total_h_el
= isl_align(*total_h_el
, 4);
1035 * - [SKL+] For SURFTYPE_1D with linear mode, the surface must be padded
1036 * to 4 times the Surface Pitch # of bytes
1038 if (ISL_DEV_GEN(dev
) >= 9 &&
1039 tile_info
->tiling
== ISL_TILING_LINEAR
&&
1040 info
->dim
== ISL_SURF_DIM_1D
) {
1046 isl_surf_init_s(const struct isl_device
*dev
,
1047 struct isl_surf
*surf
,
1048 const struct isl_surf_init_info
*restrict info
)
1050 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
1052 const struct isl_extent4d logical_level0_px
= {
1056 .a
= info
->array_len
,
1059 enum isl_dim_layout dim_layout
=
1060 isl_surf_choose_dim_layout(dev
, info
->dim
);
1062 enum isl_tiling tiling
;
1063 if (!isl_surf_choose_tiling(dev
, info
, &tiling
))
1066 struct isl_tile_info tile_info
;
1067 if (!isl_tiling_get_info(dev
, tiling
, fmtl
->bpb
, &tile_info
))
1070 enum isl_msaa_layout msaa_layout
;
1071 if (!isl_choose_msaa_layout(dev
, info
, tiling
, &msaa_layout
))
1074 struct isl_extent3d image_align_el
;
1075 isl_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,
1078 struct isl_extent3d image_align_sa
=
1079 isl_extent3d_el_to_sa(info
->format
, image_align_el
);
1081 struct isl_extent4d phys_level0_sa
;
1082 isl_calc_phys_level0_extent_sa(dev
, info
, dim_layout
, tiling
, msaa_layout
,
1084 assert(phys_level0_sa
.w
% fmtl
->bw
== 0);
1085 assert(phys_level0_sa
.h
% fmtl
->bh
== 0);
1087 enum isl_array_pitch_span array_pitch_span
=
1088 isl_choose_array_pitch_span(dev
, info
, dim_layout
, &phys_level0_sa
);
1090 struct isl_extent2d phys_slice0_sa
;
1091 isl_calc_phys_slice0_extent_sa(dev
, info
, dim_layout
, msaa_layout
,
1092 &image_align_sa
, &phys_level0_sa
,
1094 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1095 assert(phys_slice0_sa
.h
% fmtl
->bh
== 0);
1097 const uint32_t array_pitch_el_rows
=
1098 isl_calc_array_pitch_el_rows(dev
, info
, &tile_info
, dim_layout
,
1099 array_pitch_span
, &image_align_sa
,
1100 &phys_level0_sa
, &phys_slice0_sa
);
1102 uint32_t total_h_el
= phys_level0_sa
.array_len
* array_pitch_el_rows
;
1105 isl_apply_surface_padding(dev
, info
, &tile_info
, &total_h_el
, &pad_bytes
);
1107 uint32_t row_pitch
, size
, base_alignment
;
1108 if (tiling
== ISL_TILING_LINEAR
) {
1109 row_pitch
= isl_calc_linear_row_pitch(dev
, info
, &phys_slice0_sa
);
1110 size
= row_pitch
* total_h_el
+ pad_bytes
;
1112 /* From the Broadwell PRM Vol 2d, RENDER_SURFACE_STATE::SurfaceBaseAddress:
1114 * "The Base Address for linear render target surfaces and surfaces
1115 * accessed with the typed surface read/write data port messages must
1116 * be element-size aligned, for non-YUV surface formats, or a
1117 * multiple of 2 element-sizes for YUV surface formats. Other linear
1118 * surfaces have no alignment requirements (byte alignment is
1121 base_alignment
= MAX(1, info
->min_alignment
);
1122 if (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
1123 if (isl_format_is_yuv(info
->format
)) {
1124 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 4);
1126 base_alignment
= MAX(base_alignment
, fmtl
->bpb
/ 8);
1130 assert(phys_slice0_sa
.w
% fmtl
->bw
== 0);
1131 const uint32_t total_w_el
= phys_slice0_sa
.width
/ fmtl
->bw
;
1132 const uint32_t total_w_tl
=
1133 isl_align_div(total_w_el
, tile_info
.logical_extent_el
.width
);
1135 row_pitch
= total_w_tl
* tile_info
.phys_extent_B
.width
;
1136 if (row_pitch
< info
->min_pitch
) {
1137 row_pitch
= isl_align(info
->min_pitch
, tile_info
.phys_extent_B
.width
);
1140 total_h_el
+= isl_align_div_npot(pad_bytes
, row_pitch
);
1141 const uint32_t total_h_tl
=
1142 isl_align_div(total_h_el
, tile_info
.logical_extent_el
.height
);
1144 size
= total_h_tl
* tile_info
.phys_extent_B
.height
* row_pitch
;
1146 const uint32_t tile_size
= tile_info
.phys_extent_B
.width
*
1147 tile_info
.phys_extent_B
.height
;
1148 assert(isl_is_pow2(info
->min_alignment
) && isl_is_pow2(tile_size
));
1149 base_alignment
= MAX(info
->min_alignment
, tile_size
);
1152 *surf
= (struct isl_surf
) {
1154 .dim_layout
= dim_layout
,
1155 .msaa_layout
= msaa_layout
,
1157 .format
= info
->format
,
1159 .levels
= info
->levels
,
1160 .samples
= info
->samples
,
1162 .image_alignment_el
= image_align_el
,
1163 .logical_level0_px
= logical_level0_px
,
1164 .phys_level0_sa
= phys_level0_sa
,
1167 .alignment
= base_alignment
,
1168 .row_pitch
= row_pitch
,
1169 .array_pitch_el_rows
= array_pitch_el_rows
,
1170 .array_pitch_span
= array_pitch_span
,
1172 .usage
= info
->usage
,
1179 isl_surf_get_tile_info(const struct isl_device
*dev
,
1180 const struct isl_surf
*surf
,
1181 struct isl_tile_info
*tile_info
)
1183 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1184 isl_tiling_get_info(dev
, surf
->tiling
, fmtl
->bpb
, tile_info
);
1188 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1189 const struct isl_surf_fill_state_info
*restrict info
)
1192 isl_surf_usage_flags_t _base_usage
=
1193 info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
1194 ISL_SURF_USAGE_TEXTURE_BIT
|
1195 ISL_SURF_USAGE_STORAGE_BIT
);
1196 /* They may only specify one of the above bits at a time */
1197 assert(__builtin_popcount(_base_usage
) == 1);
1198 /* The only other allowed bit is ISL_SURF_USAGE_CUBE_BIT */
1199 assert((info
->view
->usage
& ~ISL_SURF_USAGE_CUBE_BIT
) == _base_usage
);
1202 if (info
->surf
->dim
== ISL_SURF_DIM_3D
) {
1203 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1204 info
->surf
->logical_level0_px
.depth
);
1206 assert(info
->view
->base_array_layer
+ info
->view
->array_len
<=
1207 info
->surf
->logical_level0_px
.array_len
);
1210 switch (ISL_DEV_GEN(dev
)) {
1212 if (ISL_DEV_IS_HASWELL(dev
)) {
1213 isl_gen75_surf_fill_state_s(dev
, state
, info
);
1215 isl_gen7_surf_fill_state_s(dev
, state
, info
);
1219 isl_gen8_surf_fill_state_s(dev
, state
, info
);
1222 isl_gen9_surf_fill_state_s(dev
, state
, info
);
1225 assert(!"Cannot fill surface state for this gen");
1230 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1231 const struct isl_buffer_fill_state_info
*restrict info
)
1233 switch (ISL_DEV_GEN(dev
)) {
1235 if (ISL_DEV_IS_HASWELL(dev
)) {
1236 isl_gen75_buffer_fill_state_s(state
, info
);
1238 isl_gen7_buffer_fill_state_s(state
, info
);
1242 isl_gen8_buffer_fill_state_s(state
, info
);
1245 isl_gen9_buffer_fill_state_s(state
, info
);
1248 assert(!"Cannot fill surface state for this gen");
1253 * A variant of isl_surf_get_image_offset_sa() specific to
1254 * ISL_DIM_LAYOUT_GEN4_2D.
1257 get_image_offset_sa_gen4_2d(const struct isl_surf
*surf
,
1258 uint32_t level
, uint32_t layer
,
1259 uint32_t *x_offset_sa
,
1260 uint32_t *y_offset_sa
)
1262 assert(level
< surf
->levels
);
1263 assert(layer
< surf
->phys_level0_sa
.array_len
);
1264 assert(surf
->phys_level0_sa
.depth
== 1);
1266 const struct isl_extent3d image_align_sa
=
1267 isl_surf_get_image_alignment_sa(surf
);
1269 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1270 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1273 uint32_t y
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1275 for (uint32_t l
= 0; l
< level
; ++l
) {
1277 uint32_t W
= isl_minify(W0
, l
);
1279 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1280 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, &W
, NULL
);
1282 x
+= isl_align_npot(W
, image_align_sa
.w
);
1284 uint32_t H
= isl_minify(H0
, l
);
1286 if (surf
->msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
)
1287 isl_msaa_interleaved_scale_px_to_sa(surf
->samples
, NULL
, &H
);
1289 y
+= isl_align_npot(H
, image_align_sa
.h
);
1298 * A variant of isl_surf_get_image_offset_sa() specific to
1299 * ISL_DIM_LAYOUT_GEN4_3D.
1302 get_image_offset_sa_gen4_3d(const struct isl_surf
*surf
,
1303 uint32_t level
, uint32_t logical_z_offset_px
,
1304 uint32_t *x_offset_sa
,
1305 uint32_t *y_offset_sa
)
1307 assert(level
< surf
->levels
);
1308 assert(logical_z_offset_px
< isl_minify(surf
->phys_level0_sa
.depth
, level
));
1309 assert(surf
->phys_level0_sa
.array_len
== 1);
1311 const struct isl_extent3d image_align_sa
=
1312 isl_surf_get_image_alignment_sa(surf
);
1314 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1315 const uint32_t H0
= surf
->phys_level0_sa
.height
;
1316 const uint32_t D0
= surf
->phys_level0_sa
.depth
;
1321 for (uint32_t l
= 0; l
< level
; ++l
) {
1322 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, l
), image_align_sa
.h
);
1323 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, l
), image_align_sa
.d
);
1324 const uint32_t max_layers_vert
= isl_align(level_d
, 1u << l
) / (1u << l
);
1326 y
+= level_h
* max_layers_vert
;
1329 const uint32_t level_w
= isl_align_npot(isl_minify(W0
, level
), image_align_sa
.w
);
1330 const uint32_t level_h
= isl_align_npot(isl_minify(H0
, level
), image_align_sa
.h
);
1331 const uint32_t level_d
= isl_align_npot(isl_minify(D0
, level
), image_align_sa
.d
);
1333 const uint32_t max_layers_horiz
= MIN(level_d
, 1u << level
);
1335 x
+= level_w
* (logical_z_offset_px
% max_layers_horiz
);
1336 y
+= level_h
* (logical_z_offset_px
/ max_layers_horiz
);
1343 * A variant of isl_surf_get_image_offset_sa() specific to
1344 * ISL_DIM_LAYOUT_GEN9_1D.
1347 get_image_offset_sa_gen9_1d(const struct isl_surf
*surf
,
1348 uint32_t level
, uint32_t layer
,
1349 uint32_t *x_offset_sa
,
1350 uint32_t *y_offset_sa
)
1352 assert(level
< surf
->levels
);
1353 assert(layer
< surf
->phys_level0_sa
.array_len
);
1354 assert(surf
->phys_level0_sa
.height
== 1);
1355 assert(surf
->phys_level0_sa
.depth
== 1);
1356 assert(surf
->samples
== 1);
1358 const uint32_t W0
= surf
->phys_level0_sa
.width
;
1359 const struct isl_extent3d image_align_sa
=
1360 isl_surf_get_image_alignment_sa(surf
);
1364 for (uint32_t l
= 0; l
< level
; ++l
) {
1365 uint32_t W
= isl_minify(W0
, l
);
1366 uint32_t w
= isl_align_npot(W
, image_align_sa
.w
);
1372 *y_offset_sa
= layer
* isl_surf_get_array_pitch_sa_rows(surf
);
1376 * Calculate the offset, in units of surface samples, to a subimage in the
1379 * @invariant level < surface levels
1380 * @invariant logical_array_layer < logical array length of surface
1381 * @invariant logical_z_offset_px < logical depth of surface at level
1384 get_image_offset_sa(const struct isl_surf
*surf
,
1386 uint32_t logical_array_layer
,
1387 uint32_t logical_z_offset_px
,
1388 uint32_t *x_offset_sa
,
1389 uint32_t *y_offset_sa
)
1391 assert(level
< surf
->levels
);
1392 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1393 assert(logical_z_offset_px
1394 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1396 switch (surf
->dim_layout
) {
1397 case ISL_DIM_LAYOUT_GEN9_1D
:
1398 get_image_offset_sa_gen9_1d(surf
, level
, logical_array_layer
,
1399 x_offset_sa
, y_offset_sa
);
1401 case ISL_DIM_LAYOUT_GEN4_2D
:
1402 get_image_offset_sa_gen4_2d(surf
, level
, logical_array_layer
1403 + logical_z_offset_px
,
1404 x_offset_sa
, y_offset_sa
);
1406 case ISL_DIM_LAYOUT_GEN4_3D
:
1407 get_image_offset_sa_gen4_3d(surf
, level
, logical_z_offset_px
,
1408 x_offset_sa
, y_offset_sa
);
1412 unreachable("not reached");
1417 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1419 uint32_t logical_array_layer
,
1420 uint32_t logical_z_offset_px
,
1421 uint32_t *x_offset_el
,
1422 uint32_t *y_offset_el
)
1424 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1426 assert(level
< surf
->levels
);
1427 assert(logical_array_layer
< surf
->logical_level0_px
.array_len
);
1428 assert(logical_z_offset_px
1429 < isl_minify(surf
->logical_level0_px
.depth
, level
));
1431 uint32_t x_offset_sa
, y_offset_sa
;
1432 get_image_offset_sa(surf
, level
,
1433 logical_array_layer
,
1434 logical_z_offset_px
,
1438 *x_offset_el
= x_offset_sa
/ fmtl
->bw
;
1439 *y_offset_el
= y_offset_sa
/ fmtl
->bh
;
1443 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1444 enum isl_tiling tiling
,
1447 uint32_t total_x_offset_el
,
1448 uint32_t total_y_offset_el
,
1449 uint32_t *base_address_offset
,
1450 uint32_t *x_offset_el
,
1451 uint32_t *y_offset_el
)
1453 /* This function only really works for power-of-two surfaces. In
1454 * theory, we could make it work for non-power-of-two surfaces by going
1455 * to the left until we find a block that is bs-aligned. The Vulkan
1456 * driver doesn't use non-power-of-two tiled surfaces so we'll leave
1457 * this unimplemented for now.
1459 assert(tiling
== ISL_TILING_LINEAR
|| isl_is_pow2(bs
));
1461 if (tiling
== ISL_TILING_LINEAR
) {
1462 *base_address_offset
= total_y_offset_el
* row_pitch
+
1463 total_x_offset_el
* bs
;
1469 struct isl_tile_info tile_info
;
1470 isl_tiling_get_info(dev
, tiling
, bs
* 8, &tile_info
);
1472 /* Compute the offset into the tile */
1473 *x_offset_el
= total_x_offset_el
% tile_info
.logical_extent_el
.w
;
1474 *y_offset_el
= total_y_offset_el
% tile_info
.logical_extent_el
.h
;
1476 /* Compute the offset of the tile in units of whole tiles */
1477 uint32_t x_offset_tl
= total_x_offset_el
/ tile_info
.logical_extent_el
.w
;
1478 uint32_t y_offset_tl
= total_y_offset_el
/ tile_info
.logical_extent_el
.h
;
1480 assert(row_pitch
% tile_info
.phys_extent_B
.width
== 0);
1481 *base_address_offset
=
1482 y_offset_tl
* tile_info
.phys_extent_B
.h
* row_pitch
+
1483 x_offset_tl
* tile_info
.phys_extent_B
.h
* tile_info
.phys_extent_B
.w
;
1487 isl_surf_get_depth_format(const struct isl_device
*dev
,
1488 const struct isl_surf
*surf
)
1490 /* Support for separate stencil buffers began in gen5. Support for
1491 * interleaved depthstencil buffers ceased in gen7. The intermediate gens,
1492 * those that supported separate and interleaved stencil, were gen5 and
1495 * For a list of all available formats, see the Sandybridge PRM >> Volume
1496 * 2 Part 1: 3D/Media - 3D Pipeline >> 3DSTATE_DEPTH_BUFFER >> Surface
1500 bool has_stencil
= surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1502 assert(surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
);
1505 assert(ISL_DEV_GEN(dev
) < 7);
1507 switch (surf
->format
) {
1509 unreachable("bad isl depth format");
1510 case ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
:
1511 assert(ISL_DEV_GEN(dev
) < 7);
1512 return 0; /* D32_FLOAT_S8X24_UINT */
1513 case ISL_FORMAT_R32_FLOAT
:
1514 assert(!has_stencil
);
1515 return 1; /* D32_FLOAT */
1516 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
1518 assert(ISL_DEV_GEN(dev
) < 7);
1519 return 2; /* D24_UNORM_S8_UINT */
1521 assert(ISL_DEV_GEN(dev
) >= 5);
1522 return 3; /* D24_UNORM_X8_UINT */
1524 case ISL_FORMAT_R16_UNORM
:
1525 assert(!has_stencil
);
1526 return 5; /* D16_UNORM */