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[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51
52 struct gen_device_info;
53 struct brw_image_param;
54
55 #ifndef ISL_DEV_GEN
56 /**
57 * @brief Get the hardware generation of isl_device.
58 *
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 */
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #else
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
67 #endif
68
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
71 #endif
72
73 #ifndef ISL_DEV_IS_HASWELL
74 /**
75 * @brief Get the hardware generation of isl_device.
76 *
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 */
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
81 #endif
82
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
85 #endif
86
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 /**
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 */
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #else
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
97 #endif
98
99 /**
100 * Hardware enumeration SURFACE_FORMAT.
101 *
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
104 */
105 enum isl_format {
106 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
107 ISL_FORMAT_R32G32B32A32_SINT = 1,
108 ISL_FORMAT_R32G32B32A32_UINT = 2,
109 ISL_FORMAT_R32G32B32A32_UNORM = 3,
110 ISL_FORMAT_R32G32B32A32_SNORM = 4,
111 ISL_FORMAT_R64G64_FLOAT = 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
114 ISL_FORMAT_R32G32B32A32_USCALED = 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
116 ISL_FORMAT_R64G64_PASSTHRU = 33,
117 ISL_FORMAT_R32G32B32_FLOAT = 64,
118 ISL_FORMAT_R32G32B32_SINT = 65,
119 ISL_FORMAT_R32G32B32_UINT = 66,
120 ISL_FORMAT_R32G32B32_UNORM = 67,
121 ISL_FORMAT_R32G32B32_SNORM = 68,
122 ISL_FORMAT_R32G32B32_SSCALED = 69,
123 ISL_FORMAT_R32G32B32_USCALED = 70,
124 ISL_FORMAT_R32G32B32_SFIXED = 80,
125 ISL_FORMAT_R16G16B16A16_UNORM = 128,
126 ISL_FORMAT_R16G16B16A16_SNORM = 129,
127 ISL_FORMAT_R16G16B16A16_SINT = 130,
128 ISL_FORMAT_R16G16B16A16_UINT = 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
130 ISL_FORMAT_R32G32_FLOAT = 133,
131 ISL_FORMAT_R32G32_SINT = 134,
132 ISL_FORMAT_R32G32_UINT = 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
135 ISL_FORMAT_L32A32_FLOAT = 138,
136 ISL_FORMAT_R32G32_UNORM = 139,
137 ISL_FORMAT_R32G32_SNORM = 140,
138 ISL_FORMAT_R64_FLOAT = 141,
139 ISL_FORMAT_R16G16B16X16_UNORM = 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
141 ISL_FORMAT_A32X32_FLOAT = 144,
142 ISL_FORMAT_L32X32_FLOAT = 145,
143 ISL_FORMAT_I32X32_FLOAT = 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
145 ISL_FORMAT_R16G16B16A16_USCALED = 148,
146 ISL_FORMAT_R32G32_SSCALED = 149,
147 ISL_FORMAT_R32G32_USCALED = 150,
148 ISL_FORMAT_R32G32_FLOAT_LD = 151,
149 ISL_FORMAT_R32G32_SFIXED = 160,
150 ISL_FORMAT_R64_PASSTHRU = 161,
151 ISL_FORMAT_B8G8R8A8_UNORM = 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
153 ISL_FORMAT_R10G10B10A2_UNORM = 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
155 ISL_FORMAT_R10G10B10A2_UINT = 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
157 ISL_FORMAT_R8G8B8A8_UNORM = 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
159 ISL_FORMAT_R8G8B8A8_SNORM = 201,
160 ISL_FORMAT_R8G8B8A8_SINT = 202,
161 ISL_FORMAT_R8G8B8A8_UINT = 203,
162 ISL_FORMAT_R16G16_UNORM = 204,
163 ISL_FORMAT_R16G16_SNORM = 205,
164 ISL_FORMAT_R16G16_SINT = 206,
165 ISL_FORMAT_R16G16_UINT = 207,
166 ISL_FORMAT_R16G16_FLOAT = 208,
167 ISL_FORMAT_B10G10R10A2_UNORM = 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
169 ISL_FORMAT_R11G11B10_FLOAT = 211,
170 ISL_FORMAT_R32_SINT = 214,
171 ISL_FORMAT_R32_UINT = 215,
172 ISL_FORMAT_R32_FLOAT = 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
175 ISL_FORMAT_L32_UNORM = 221,
176 ISL_FORMAT_A32_UNORM = 222,
177 ISL_FORMAT_L16A16_UNORM = 223,
178 ISL_FORMAT_I24X8_UNORM = 224,
179 ISL_FORMAT_L24X8_UNORM = 225,
180 ISL_FORMAT_A24X8_UNORM = 226,
181 ISL_FORMAT_I32_FLOAT = 227,
182 ISL_FORMAT_L32_FLOAT = 228,
183 ISL_FORMAT_A32_FLOAT = 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
187 ISL_FORMAT_B8G8R8X8_UNORM = 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
189 ISL_FORMAT_R8G8B8X8_UNORM = 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
192 ISL_FORMAT_B10G10R10X2_UNORM = 238,
193 ISL_FORMAT_L16A16_FLOAT = 240,
194 ISL_FORMAT_R32_UNORM = 241,
195 ISL_FORMAT_R32_SNORM = 242,
196 ISL_FORMAT_R10G10B10X2_USCALED = 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
198 ISL_FORMAT_R8G8B8A8_USCALED = 245,
199 ISL_FORMAT_R16G16_SSCALED = 246,
200 ISL_FORMAT_R16G16_USCALED = 247,
201 ISL_FORMAT_R32_SSCALED = 248,
202 ISL_FORMAT_R32_USCALED = 249,
203 ISL_FORMAT_B5G6R5_UNORM = 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
205 ISL_FORMAT_B5G5R5A1_UNORM = 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
207 ISL_FORMAT_B4G4R4A4_UNORM = 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
209 ISL_FORMAT_R8G8_UNORM = 262,
210 ISL_FORMAT_R8G8_SNORM = 263,
211 ISL_FORMAT_R8G8_SINT = 264,
212 ISL_FORMAT_R8G8_UINT = 265,
213 ISL_FORMAT_R16_UNORM = 266,
214 ISL_FORMAT_R16_SNORM = 267,
215 ISL_FORMAT_R16_SINT = 268,
216 ISL_FORMAT_R16_UINT = 269,
217 ISL_FORMAT_R16_FLOAT = 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
220 ISL_FORMAT_I16_UNORM = 273,
221 ISL_FORMAT_L16_UNORM = 274,
222 ISL_FORMAT_A16_UNORM = 275,
223 ISL_FORMAT_L8A8_UNORM = 276,
224 ISL_FORMAT_I16_FLOAT = 277,
225 ISL_FORMAT_L16_FLOAT = 278,
226 ISL_FORMAT_A16_FLOAT = 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
229 ISL_FORMAT_B5G5R5X1_UNORM = 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
231 ISL_FORMAT_R8G8_SSCALED = 284,
232 ISL_FORMAT_R8G8_USCALED = 285,
233 ISL_FORMAT_R16_SSCALED = 286,
234 ISL_FORMAT_R16_USCALED = 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
237 ISL_FORMAT_A1B5G5R5_UNORM = 292,
238 ISL_FORMAT_A4B4G4R4_UNORM = 293,
239 ISL_FORMAT_L8A8_UINT = 294,
240 ISL_FORMAT_L8A8_SINT = 295,
241 ISL_FORMAT_R8_UNORM = 320,
242 ISL_FORMAT_R8_SNORM = 321,
243 ISL_FORMAT_R8_SINT = 322,
244 ISL_FORMAT_R8_UINT = 323,
245 ISL_FORMAT_A8_UNORM = 324,
246 ISL_FORMAT_I8_UNORM = 325,
247 ISL_FORMAT_L8_UNORM = 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
250 ISL_FORMAT_R8_SSCALED = 329,
251 ISL_FORMAT_R8_USCALED = 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
253 ISL_FORMAT_L8_UNORM_SRGB = 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
257 ISL_FORMAT_Y8_UNORM = 336,
258 ISL_FORMAT_L8_UINT = 338,
259 ISL_FORMAT_L8_SINT = 339,
260 ISL_FORMAT_I8_UINT = 340,
261 ISL_FORMAT_I8_SINT = 341,
262 ISL_FORMAT_DXT1_RGB_SRGB = 384,
263 ISL_FORMAT_R1_UNORM = 385,
264 ISL_FORMAT_YCRCB_NORMAL = 386,
265 ISL_FORMAT_YCRCB_SWAPUVY = 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
268 ISL_FORMAT_BC1_UNORM = 390,
269 ISL_FORMAT_BC2_UNORM = 391,
270 ISL_FORMAT_BC3_UNORM = 392,
271 ISL_FORMAT_BC4_UNORM = 393,
272 ISL_FORMAT_BC5_UNORM = 394,
273 ISL_FORMAT_BC1_UNORM_SRGB = 395,
274 ISL_FORMAT_BC2_UNORM_SRGB = 396,
275 ISL_FORMAT_BC3_UNORM_SRGB = 397,
276 ISL_FORMAT_MONO8 = 398,
277 ISL_FORMAT_YCRCB_SWAPUV = 399,
278 ISL_FORMAT_YCRCB_SWAPY = 400,
279 ISL_FORMAT_DXT1_RGB = 401,
280 ISL_FORMAT_FXT1 = 402,
281 ISL_FORMAT_R8G8B8_UNORM = 403,
282 ISL_FORMAT_R8G8B8_SNORM = 404,
283 ISL_FORMAT_R8G8B8_SSCALED = 405,
284 ISL_FORMAT_R8G8B8_USCALED = 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
286 ISL_FORMAT_R64G64B64_FLOAT = 408,
287 ISL_FORMAT_BC4_SNORM = 409,
288 ISL_FORMAT_BC5_SNORM = 410,
289 ISL_FORMAT_R16G16B16_FLOAT = 411,
290 ISL_FORMAT_R16G16B16_UNORM = 412,
291 ISL_FORMAT_R16G16B16_SNORM = 413,
292 ISL_FORMAT_R16G16B16_SSCALED = 414,
293 ISL_FORMAT_R16G16B16_USCALED = 415,
294 ISL_FORMAT_BC6H_SF16 = 417,
295 ISL_FORMAT_BC7_UNORM = 418,
296 ISL_FORMAT_BC7_UNORM_SRGB = 419,
297 ISL_FORMAT_BC6H_UF16 = 420,
298 ISL_FORMAT_PLANAR_420_8 = 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
300 ISL_FORMAT_ETC1_RGB8 = 425,
301 ISL_FORMAT_ETC2_RGB8 = 426,
302 ISL_FORMAT_EAC_R11 = 427,
303 ISL_FORMAT_EAC_RG11 = 428,
304 ISL_FORMAT_EAC_SIGNED_R11 = 429,
305 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
306 ISL_FORMAT_ETC2_SRGB8 = 431,
307 ISL_FORMAT_R16G16B16_UINT = 432,
308 ISL_FORMAT_R16G16B16_SINT = 433,
309 ISL_FORMAT_R32_SFIXED = 434,
310 ISL_FORMAT_R10G10B10A2_SNORM = 435,
311 ISL_FORMAT_R10G10B10A2_USCALED = 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
313 ISL_FORMAT_R10G10B10A2_SINT = 438,
314 ISL_FORMAT_B10G10R10A2_SNORM = 439,
315 ISL_FORMAT_B10G10R10A2_USCALED = 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
317 ISL_FORMAT_B10G10R10A2_UINT = 442,
318 ISL_FORMAT_B10G10R10A2_SINT = 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
321 ISL_FORMAT_ETC2_RGB8_PTA = 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
325 ISL_FORMAT_R8G8B8_UINT = 456,
326 ISL_FORMAT_R8G8B8_SINT = 457,
327 ISL_FORMAT_RAW = 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
356
357 /* The formats that follow are internal to ISL and as such don't have an
358 * explicit number. We'll just let the C compiler assign it for us. Any
359 * actual hardware formats *must* come before these in the list.
360 */
361
362 /* Formats for auxiliary surfaces */
363 ISL_FORMAT_HIZ,
364 ISL_FORMAT_MCS_2X,
365 ISL_FORMAT_MCS_4X,
366 ISL_FORMAT_MCS_8X,
367 ISL_FORMAT_MCS_16X,
368 ISL_FORMAT_GEN7_CCS_32BPP_X,
369 ISL_FORMAT_GEN7_CCS_64BPP_X,
370 ISL_FORMAT_GEN7_CCS_128BPP_X,
371 ISL_FORMAT_GEN7_CCS_32BPP_Y,
372 ISL_FORMAT_GEN7_CCS_64BPP_Y,
373 ISL_FORMAT_GEN7_CCS_128BPP_Y,
374 ISL_FORMAT_GEN9_CCS_32BPP,
375 ISL_FORMAT_GEN9_CCS_64BPP,
376 ISL_FORMAT_GEN9_CCS_128BPP,
377
378 /* Hardware doesn't understand this out-of-band value */
379 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
380 };
381
382 /**
383 * Numerical base type for channels of isl_format.
384 */
385 enum isl_base_type {
386 ISL_VOID,
387 ISL_RAW,
388 ISL_UNORM,
389 ISL_SNORM,
390 ISL_UFLOAT,
391 ISL_SFLOAT,
392 ISL_UFIXED,
393 ISL_SFIXED,
394 ISL_UINT,
395 ISL_SINT,
396 ISL_USCALED,
397 ISL_SSCALED,
398 };
399
400 /**
401 * Colorspace of isl_format.
402 */
403 enum isl_colorspace {
404 ISL_COLORSPACE_NONE = 0,
405 ISL_COLORSPACE_LINEAR,
406 ISL_COLORSPACE_SRGB,
407 ISL_COLORSPACE_YUV,
408 };
409
410 /**
411 * Texture compression mode of isl_format.
412 */
413 enum isl_txc {
414 ISL_TXC_NONE = 0,
415 ISL_TXC_DXT1,
416 ISL_TXC_DXT3,
417 ISL_TXC_DXT5,
418 ISL_TXC_FXT1,
419 ISL_TXC_RGTC1,
420 ISL_TXC_RGTC2,
421 ISL_TXC_BPTC,
422 ISL_TXC_ETC1,
423 ISL_TXC_ETC2,
424 ISL_TXC_ASTC,
425
426 /* Used for auxiliary surface formats */
427 ISL_TXC_HIZ,
428 ISL_TXC_MCS,
429 ISL_TXC_CCS,
430 };
431
432 /**
433 * @brief Hardware tile mode
434 *
435 * WARNING: These values differ from the hardware enum values, which are
436 * unstable across hardware generations.
437 *
438 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
439 * clearly distinguish it from Yf and Ys.
440 */
441 enum isl_tiling {
442 ISL_TILING_LINEAR = 0,
443 ISL_TILING_W,
444 ISL_TILING_X,
445 ISL_TILING_Y0, /**< Legacy Y tiling */
446 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
447 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
448 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
449 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
450 };
451
452 /**
453 * @defgroup Tiling Flags
454 * @{
455 */
456 typedef uint32_t isl_tiling_flags_t;
457 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
458 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
459 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
460 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
461 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
462 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
463 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
464 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
465 #define ISL_TILING_ANY_MASK (~0u)
466 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
467
468 /** Any Y tiling, including legacy Y tiling. */
469 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
470 ISL_TILING_Yf_BIT | \
471 ISL_TILING_Ys_BIT)
472
473 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
474 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
475 ISL_TILING_Ys_BIT)
476 /** @} */
477
478 /**
479 * @brief Logical dimension of surface.
480 *
481 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
482 * as 2D array surfaces.
483 */
484 enum isl_surf_dim {
485 ISL_SURF_DIM_1D,
486 ISL_SURF_DIM_2D,
487 ISL_SURF_DIM_3D,
488 };
489
490 /**
491 * @brief Physical layout of the surface's dimensions.
492 */
493 enum isl_dim_layout {
494 /**
495 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
496 * 6.17.3: 2D Surfaces.
497 *
498 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
499 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
500 *
501 * One-dimensional surfaces are identical to 2D surfaces with height of
502 * one.
503 *
504 * @invariant isl_surf::phys_level0_sa::depth == 1
505 */
506 ISL_DIM_LAYOUT_GEN4_2D,
507
508 /**
509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
510 * 6.17.5: 3D Surfaces.
511 *
512 * @invariant isl_surf::phys_level0_sa::array_len == 1
513 */
514 ISL_DIM_LAYOUT_GEN4_3D,
515
516 /**
517 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
518 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
519 */
520 ISL_DIM_LAYOUT_GEN9_1D,
521 };
522
523 enum isl_aux_usage {
524 /** No Auxiliary surface is used */
525 ISL_AUX_USAGE_NONE,
526
527 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
528 ISL_AUX_USAGE_HIZ,
529
530 /** The auxiliary surface is an MCS
531 *
532 * @invariant isl_surf::samples > 1
533 */
534 ISL_AUX_USAGE_MCS,
535
536 /** The auxiliary surface is a fast-clear-only compression surface
537 *
538 * @invariant isl_surf::samples == 1
539 */
540 ISL_AUX_USAGE_CCS_D,
541
542 /** The auxiliary surface provides full lossless color compression
543 *
544 * @invariant isl_surf::samples == 1
545 */
546 ISL_AUX_USAGE_CCS_E,
547 };
548
549 /* TODO(chadv): Explain */
550 enum isl_array_pitch_span {
551 ISL_ARRAY_PITCH_SPAN_FULL,
552 ISL_ARRAY_PITCH_SPAN_COMPACT,
553 };
554
555 /**
556 * @defgroup Surface Usage
557 * @{
558 */
559 typedef uint64_t isl_surf_usage_flags_t;
560 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
561 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
562 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
563 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
564 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
565 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
566 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
567 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
568 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
569 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
570 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
571 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
572 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
573 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
574 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
575 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
576 /** @} */
577
578 /**
579 * @brief A channel select (also known as texture swizzle) value
580 */
581 enum isl_channel_select {
582 ISL_CHANNEL_SELECT_ZERO = 0,
583 ISL_CHANNEL_SELECT_ONE = 1,
584 ISL_CHANNEL_SELECT_RED = 4,
585 ISL_CHANNEL_SELECT_GREEN = 5,
586 ISL_CHANNEL_SELECT_BLUE = 6,
587 ISL_CHANNEL_SELECT_ALPHA = 7,
588 };
589
590 /**
591 * Identical to VkSampleCountFlagBits.
592 */
593 enum isl_sample_count {
594 ISL_SAMPLE_COUNT_1_BIT = 1u,
595 ISL_SAMPLE_COUNT_2_BIT = 2u,
596 ISL_SAMPLE_COUNT_4_BIT = 4u,
597 ISL_SAMPLE_COUNT_8_BIT = 8u,
598 ISL_SAMPLE_COUNT_16_BIT = 16u,
599 };
600 typedef uint32_t isl_sample_count_mask_t;
601
602 /**
603 * @brief Multisample Format
604 */
605 enum isl_msaa_layout {
606 /**
607 * @brief Suface is single-sampled.
608 */
609 ISL_MSAA_LAYOUT_NONE,
610
611 /**
612 * @brief [SNB+] Interleaved Multisample Format
613 *
614 * In this format, multiple samples are interleaved into each cacheline.
615 * In other words, the sample index is swizzled into the low 6 bits of the
616 * surface's virtual address space.
617 *
618 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
619 * and its pixel format is 32bpp. Then the first cacheline is arranged
620 * thus:
621 *
622 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
623 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
624 *
625 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
626 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
627 *
628 * The hardware docs refer to this format with multiple terms. In
629 * Sandybridge, this is the only multisample format; so no term is used.
630 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
631 * Multisample Surface). Later hardware docs additionally refer to this
632 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
633 * color surfaces).
634 *
635 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
636 * Surface Behavior".
637 *
638 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
639 * Multisampled Surfaces".
640 */
641 ISL_MSAA_LAYOUT_INTERLEAVED,
642
643 /**
644 * @brief [IVB+] Array Multisample Format
645 *
646 * In this format, the surface's physical layout resembles that of a
647 * 2D array surface.
648 *
649 * Suppose the multisample surface's logical extent is (w, h) and its
650 * sample count is N. Then surface's physical extent is the same as
651 * a singlesample 2D surface whose logical extent is (w, h) and array
652 * length is N. Array slice `i` contains the pixel values for sample
653 * index `i`.
654 *
655 * The Ivybridge docs refer to surfaces in this format as UMS
656 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
657 * Surface). The Broadwell docs additionally refer to this format as
658 * MSFMT_MSS (MSS=Multisample Surface Storage).
659 *
660 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
661 * Multisample Surfaces".
662 *
663 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
664 * Multisample Surfaces".
665 */
666 ISL_MSAA_LAYOUT_ARRAY,
667 };
668
669
670 struct isl_device {
671 const struct gen_device_info *info;
672 bool use_separate_stencil;
673 bool has_bit6_swizzling;
674 };
675
676 struct isl_extent2d {
677 union { uint32_t w, width; };
678 union { uint32_t h, height; };
679 };
680
681 struct isl_extent3d {
682 union { uint32_t w, width; };
683 union { uint32_t h, height; };
684 union { uint32_t d, depth; };
685 };
686
687 struct isl_extent4d {
688 union { uint32_t w, width; };
689 union { uint32_t h, height; };
690 union { uint32_t d, depth; };
691 union { uint32_t a, array_len; };
692 };
693
694 struct isl_channel_layout {
695 enum isl_base_type type;
696 uint8_t bits; /**< Size in bits */
697 };
698
699 /**
700 * Each format has 3D block extent (width, height, depth). The block extent of
701 * compressed formats is that of the format's compression block. For example,
702 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
703 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
704 * is (w=1, h=1, d=1).
705 */
706 struct isl_format_layout {
707 enum isl_format format;
708 const char *name;
709
710 uint16_t bpb; /**< Bits per block */
711 uint8_t bw; /**< Block width, in pixels */
712 uint8_t bh; /**< Block height, in pixels */
713 uint8_t bd; /**< Block depth, in pixels */
714
715 struct {
716 struct isl_channel_layout r; /**< Red channel */
717 struct isl_channel_layout g; /**< Green channel */
718 struct isl_channel_layout b; /**< Blue channel */
719 struct isl_channel_layout a; /**< Alpha channel */
720 struct isl_channel_layout l; /**< Luminance channel */
721 struct isl_channel_layout i; /**< Intensity channel */
722 struct isl_channel_layout p; /**< Palette channel */
723 } channels;
724
725 enum isl_colorspace colorspace;
726 enum isl_txc txc;
727 };
728
729 struct isl_tile_info {
730 enum isl_tiling tiling;
731
732 /* The size (in bits per block) of a single surface element
733 *
734 * For surfaces with power-of-two formats, this is the same as
735 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
736 * The logical_extent_el field is in terms of elements of this size.
737 *
738 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
739 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
740 * of the tiling formats can actually hold an integer number of 96-bit
741 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
742 * 32-bit element size. It is the responsibility of the caller to
743 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
744 * the width of a surface in tiles, you would do:
745 *
746 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
747 * tile_info.logical_extent_el.width);
748 */
749 uint32_t format_bpb;
750
751 /** The logical size of the tile in units of format_bpb size elements
752 *
753 * This field determines how a given surface is cut up into tiles. It is
754 * used to compute the size of a surface in tiles and can be used to
755 * determine the location of the tile containing any given surface element.
756 * The exact value of this field depends heavily on the bits-per-block of
757 * the format being used.
758 */
759 struct isl_extent2d logical_extent_el;
760
761 /** The physical size of the tile in bytes and rows of bytes
762 *
763 * This field determines how the tiles of a surface are physically layed
764 * out in memory. The logical and physical tile extent are frequently the
765 * same but this is not always the case. For instance, a W-tile (which is
766 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
767 * its physical size is 128B x 32rows, the same as a Y-tile.
768 *
769 * @see isl_surf::row_pitch
770 */
771 struct isl_extent2d phys_extent_B;
772 };
773
774 /**
775 * @brief Input to surface initialization
776 *
777 * @invariant width >= 1
778 * @invariant height >= 1
779 * @invariant depth >= 1
780 * @invariant levels >= 1
781 * @invariant samples >= 1
782 * @invariant array_len >= 1
783 *
784 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
785 * @invariant if 2D then depth == 1
786 * @invariant if 3D then array_len == 1 and samples == 1
787 */
788 struct isl_surf_init_info {
789 enum isl_surf_dim dim;
790 enum isl_format format;
791
792 uint32_t width;
793 uint32_t height;
794 uint32_t depth;
795 uint32_t levels;
796 uint32_t array_len;
797 uint32_t samples;
798
799 /** Lower bound for isl_surf::alignment, in bytes. */
800 uint32_t min_alignment;
801
802 /** Lower bound for isl_surf::pitch, in bytes. */
803 uint32_t min_pitch;
804
805 isl_surf_usage_flags_t usage;
806
807 /** Flags that alter how ISL selects isl_surf::tiling. */
808 isl_tiling_flags_t tiling_flags;
809 };
810
811 struct isl_surf {
812 enum isl_surf_dim dim;
813 enum isl_dim_layout dim_layout;
814 enum isl_msaa_layout msaa_layout;
815 enum isl_tiling tiling;
816 enum isl_format format;
817
818 /**
819 * Alignment of the upper-left sample of each subimage, in units of surface
820 * elements.
821 */
822 struct isl_extent3d image_alignment_el;
823
824 /**
825 * Logical extent of the surface's base level, in units of pixels. This is
826 * identical to the extent defined in isl_surf_init_info.
827 */
828 struct isl_extent4d logical_level0_px;
829
830 /**
831 * Physical extent of the surface's base level, in units of physical
832 * surface samples and aligned to the format's compression block.
833 *
834 * Consider isl_dim_layout as an operator that transforms a logical surface
835 * layout to a physical surface layout. Then
836 *
837 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
838 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
839 */
840 struct isl_extent4d phys_level0_sa;
841
842 uint32_t levels;
843 uint32_t samples;
844
845 /** Total size of the surface, in bytes. */
846 uint32_t size;
847
848 /** Required alignment for the surface's base address. */
849 uint32_t alignment;
850
851 /**
852 * The interpretation of this field depends on the value of
853 * isl_tile_info::physical_extent_B. In particular, the width of the
854 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
855 * and the distance in bytes between vertically adjacent tiles in the image
856 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
857 *
858 * For linear images where isl_tile_info::physical_extent_B.height == 1,
859 * this cleanly reduces to being the distance, in bytes, between vertically
860 * adjacent surface elements.
861 *
862 * @see isl_tile_info::phys_extent_B;
863 */
864 uint32_t row_pitch;
865
866 /**
867 * Pitch between physical array slices, in rows of surface elements.
868 */
869 uint32_t array_pitch_el_rows;
870
871 enum isl_array_pitch_span array_pitch_span;
872
873 /** Copy of isl_surf_init_info::usage. */
874 isl_surf_usage_flags_t usage;
875 };
876
877 struct isl_swizzle {
878 enum isl_channel_select r:4;
879 enum isl_channel_select g:4;
880 enum isl_channel_select b:4;
881 enum isl_channel_select a:4;
882 };
883
884 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
885 .r = ISL_CHANNEL_SELECT_##R, \
886 .g = ISL_CHANNEL_SELECT_##G, \
887 .b = ISL_CHANNEL_SELECT_##B, \
888 .a = ISL_CHANNEL_SELECT_##A, \
889 })
890
891 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
892
893 struct isl_view {
894 /**
895 * Indicates the usage of the particular view
896 *
897 * Normally, this is one bit. However, for a cube map texture, it
898 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
899 */
900 isl_surf_usage_flags_t usage;
901
902 /**
903 * The format to use in the view
904 *
905 * This may differ from the format of the actual isl_surf but must have
906 * the same block size.
907 */
908 enum isl_format format;
909
910 uint32_t base_level;
911 uint32_t levels;
912
913 /**
914 * Base array layer
915 *
916 * For cube maps, both base_array_layer and array_len should be
917 * specified in terms of 2-D layers and must be a multiple of 6.
918 *
919 * 3-D textures are effectively treated as 2-D arrays when used as a
920 * storage image or render target. If `usage` contains
921 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
922 * base_array_layer and array_len are applied. If the surface is only used
923 * for texturing, they are ignored.
924 */
925 uint32_t base_array_layer;
926 uint32_t array_len;
927
928 struct isl_swizzle swizzle;
929 };
930
931 union isl_color_value {
932 float f32[4];
933 uint32_t u32[4];
934 int32_t i32[4];
935 };
936
937 struct isl_surf_fill_state_info {
938 const struct isl_surf *surf;
939 const struct isl_view *view;
940
941 /**
942 * The address of the surface in GPU memory.
943 */
944 uint64_t address;
945
946 /**
947 * The Memory Object Control state for the filled surface state.
948 *
949 * The exact format of this value depends on hardware generation.
950 */
951 uint32_t mocs;
952
953 /**
954 * The auxilary surface or NULL if no auxilary surface is to be used.
955 */
956 const struct isl_surf *aux_surf;
957 enum isl_aux_usage aux_usage;
958 uint64_t aux_address;
959
960 /**
961 * The clear color for this surface
962 *
963 * Valid values depend on hardware generation.
964 */
965 union isl_color_value clear_color;
966
967 /* Intra-tile offset */
968 uint16_t x_offset_sa, y_offset_sa;
969 };
970
971 struct isl_buffer_fill_state_info {
972 /**
973 * The address of the surface in GPU memory.
974 */
975 uint64_t address;
976
977 /**
978 * The size of the buffer
979 */
980 uint64_t size;
981
982 /**
983 * The Memory Object Control state for the filled surface state.
984 *
985 * The exact format of this value depends on hardware generation.
986 */
987 uint32_t mocs;
988
989 /**
990 * The format to use in the surface state
991 *
992 * This may differ from the format of the actual isl_surf but have the
993 * same block size.
994 */
995 enum isl_format format;
996
997 uint32_t stride;
998 };
999
1000 extern const struct isl_format_layout isl_format_layouts[];
1001
1002 void
1003 isl_device_init(struct isl_device *dev,
1004 const struct gen_device_info *info,
1005 bool has_bit6_swizzling);
1006
1007 isl_sample_count_mask_t ATTRIBUTE_CONST
1008 isl_device_get_sample_counts(struct isl_device *dev);
1009
1010 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1011 isl_format_get_layout(enum isl_format fmt)
1012 {
1013 return &isl_format_layouts[fmt];
1014 }
1015
1016 static inline const char * ATTRIBUTE_CONST
1017 isl_format_get_name(enum isl_format fmt)
1018 {
1019 return isl_format_layouts[fmt].name;
1020 }
1021
1022 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1023 enum isl_format format);
1024 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1025 enum isl_format format);
1026 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1027 enum isl_format format);
1028 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1029 enum isl_format format);
1030 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1031 enum isl_format format);
1032 bool isl_format_supports_lossless_compression(const struct gen_device_info *devinfo,
1033 enum isl_format format);
1034 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1035 enum isl_format format);
1036
1037 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1038 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1039 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1040 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1041 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1042 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1043
1044 static inline bool
1045 isl_format_has_normalized_channel(enum isl_format fmt)
1046 {
1047 return isl_format_has_unorm_channel(fmt) ||
1048 isl_format_has_snorm_channel(fmt);
1049 }
1050
1051 static inline bool
1052 isl_format_has_float_channel(enum isl_format fmt)
1053 {
1054 return isl_format_has_ufloat_channel(fmt) ||
1055 isl_format_has_sfloat_channel(fmt);
1056 }
1057
1058 static inline bool
1059 isl_format_has_int_channel(enum isl_format fmt)
1060 {
1061 return isl_format_has_uint_channel(fmt) ||
1062 isl_format_has_sint_channel(fmt);
1063 }
1064
1065 unsigned isl_format_get_num_channels(enum isl_format fmt);
1066
1067 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1068
1069 static inline bool
1070 isl_format_is_compressed(enum isl_format fmt)
1071 {
1072 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1073
1074 return fmtl->txc != ISL_TXC_NONE;
1075 }
1076
1077 static inline bool
1078 isl_format_has_bc_compression(enum isl_format fmt)
1079 {
1080 switch (isl_format_get_layout(fmt)->txc) {
1081 case ISL_TXC_DXT1:
1082 case ISL_TXC_DXT3:
1083 case ISL_TXC_DXT5:
1084 return true;
1085 case ISL_TXC_NONE:
1086 case ISL_TXC_FXT1:
1087 case ISL_TXC_RGTC1:
1088 case ISL_TXC_RGTC2:
1089 case ISL_TXC_BPTC:
1090 case ISL_TXC_ETC1:
1091 case ISL_TXC_ETC2:
1092 case ISL_TXC_ASTC:
1093 return false;
1094
1095 case ISL_TXC_HIZ:
1096 case ISL_TXC_MCS:
1097 case ISL_TXC_CCS:
1098 unreachable("Should not be called on an aux surface");
1099 }
1100
1101 unreachable("bad texture compression mode");
1102 return false;
1103 }
1104
1105 static inline bool
1106 isl_format_is_yuv(enum isl_format fmt)
1107 {
1108 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1109
1110 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1111 }
1112
1113 static inline bool
1114 isl_format_block_is_1x1x1(enum isl_format fmt)
1115 {
1116 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1117
1118 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1119 }
1120
1121 static inline bool
1122 isl_format_is_rgb(enum isl_format fmt)
1123 {
1124 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1125 isl_format_layouts[fmt].channels.g.bits > 0 &&
1126 isl_format_layouts[fmt].channels.b.bits > 0 &&
1127 isl_format_layouts[fmt].channels.a.bits == 0;
1128 }
1129
1130 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1131 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1132
1133 bool isl_is_storage_image_format(enum isl_format fmt);
1134
1135 enum isl_format
1136 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1137 enum isl_format fmt);
1138
1139 /* Returns true if this hardware supports typed load/store on a format with
1140 * the same size as the given format.
1141 */
1142 bool
1143 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1144 enum isl_format fmt);
1145
1146 static inline bool
1147 isl_tiling_is_any_y(enum isl_tiling tiling)
1148 {
1149 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1150 }
1151
1152 static inline bool
1153 isl_tiling_is_std_y(enum isl_tiling tiling)
1154 {
1155 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1156 }
1157
1158 struct isl_extent2d ATTRIBUTE_CONST
1159 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1160
1161 static inline bool
1162 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1163 {
1164 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1165 }
1166
1167 static inline bool
1168 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1169 {
1170 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1171 }
1172
1173 static inline bool
1174 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1175 {
1176 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1177 }
1178
1179 static inline bool
1180 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1181 {
1182 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1183 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1184 }
1185
1186 static inline bool
1187 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1188 {
1189 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1190 }
1191
1192 static inline bool
1193 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1194 {
1195 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1196 (info->format == ISL_FORMAT_R16_UNORM);
1197 }
1198
1199 static inline bool
1200 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1201 {
1202 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1203 (info->format == ISL_FORMAT_R32_FLOAT);
1204 }
1205
1206 static inline struct isl_extent2d
1207 isl_extent2d(uint32_t width, uint32_t height)
1208 {
1209 struct isl_extent2d e = { { 0 } };
1210
1211 e.width = width;
1212 e.height = height;
1213
1214 return e;
1215 }
1216
1217 static inline struct isl_extent3d
1218 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1219 {
1220 struct isl_extent3d e = { { 0 } };
1221
1222 e.width = width;
1223 e.height = height;
1224 e.depth = depth;
1225
1226 return e;
1227 }
1228
1229 static inline struct isl_extent4d
1230 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1231 uint32_t array_len)
1232 {
1233 struct isl_extent4d e = { { 0 } };
1234
1235 e.width = width;
1236 e.height = height;
1237 e.depth = depth;
1238 e.array_len = array_len;
1239
1240 return e;
1241 }
1242
1243 #define isl_surf_init(dev, surf, ...) \
1244 isl_surf_init_s((dev), (surf), \
1245 &(struct isl_surf_init_info) { __VA_ARGS__ });
1246
1247 bool
1248 isl_surf_init_s(const struct isl_device *dev,
1249 struct isl_surf *surf,
1250 const struct isl_surf_init_info *restrict info);
1251
1252 void
1253 isl_surf_get_tile_info(const struct isl_device *dev,
1254 const struct isl_surf *surf,
1255 struct isl_tile_info *tile_info);
1256
1257 void
1258 isl_surf_get_hiz_surf(const struct isl_device *dev,
1259 const struct isl_surf *surf,
1260 struct isl_surf *hiz_surf);
1261
1262 void
1263 isl_surf_get_mcs_surf(const struct isl_device *dev,
1264 const struct isl_surf *surf,
1265 struct isl_surf *mcs_surf);
1266
1267 bool
1268 isl_surf_get_ccs_surf(const struct isl_device *dev,
1269 const struct isl_surf *surf,
1270 struct isl_surf *ccs_surf);
1271
1272 #define isl_surf_fill_state(dev, state, ...) \
1273 isl_surf_fill_state_s((dev), (state), \
1274 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1275
1276 void
1277 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1278 const struct isl_surf_fill_state_info *restrict info);
1279
1280 #define isl_buffer_fill_state(dev, state, ...) \
1281 isl_buffer_fill_state_s((dev), (state), \
1282 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1283
1284 void
1285 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1286 const struct isl_buffer_fill_state_info *restrict info);
1287
1288 void
1289 isl_surf_fill_image_param(const struct isl_device *dev,
1290 struct brw_image_param *param,
1291 const struct isl_surf *surf,
1292 const struct isl_view *view);
1293
1294 void
1295 isl_buffer_fill_image_param(const struct isl_device *dev,
1296 struct brw_image_param *param,
1297 enum isl_format format,
1298 uint64_t size);
1299
1300 /**
1301 * Alignment of the upper-left sample of each subimage, in units of surface
1302 * elements.
1303 */
1304 static inline struct isl_extent3d
1305 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1306 {
1307 return surf->image_alignment_el;
1308 }
1309
1310 /**
1311 * Alignment of the upper-left sample of each subimage, in units of surface
1312 * samples.
1313 */
1314 static inline struct isl_extent3d
1315 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1316 {
1317 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1318
1319 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1320 fmtl->bh * surf->image_alignment_el.h,
1321 fmtl->bd * surf->image_alignment_el.d);
1322 }
1323
1324 /**
1325 * Pitch between vertically adjacent surface elements, in bytes.
1326 */
1327 static inline uint32_t
1328 isl_surf_get_row_pitch(const struct isl_surf *surf)
1329 {
1330 return surf->row_pitch;
1331 }
1332
1333 /**
1334 * Pitch between vertically adjacent surface elements, in units of surface elements.
1335 */
1336 static inline uint32_t
1337 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1338 {
1339 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1340
1341 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1342 return surf->row_pitch / (fmtl->bpb / 8);
1343 }
1344
1345 /**
1346 * Pitch between physical array slices, in rows of surface elements.
1347 */
1348 static inline uint32_t
1349 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1350 {
1351 return surf->array_pitch_el_rows;
1352 }
1353
1354 /**
1355 * Pitch between physical array slices, in units of surface elements.
1356 */
1357 static inline uint32_t
1358 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1359 {
1360 return isl_surf_get_array_pitch_el_rows(surf) *
1361 isl_surf_get_row_pitch_el(surf);
1362 }
1363
1364 /**
1365 * Pitch between physical array slices, in rows of surface samples.
1366 */
1367 static inline uint32_t
1368 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1369 {
1370 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1371 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1372 }
1373
1374 /**
1375 * Pitch between physical array slices, in bytes.
1376 */
1377 static inline uint32_t
1378 isl_surf_get_array_pitch(const struct isl_surf *surf)
1379 {
1380 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1381 }
1382
1383 /**
1384 * Calculate the offset, in units of surface samples, to a subimage in the
1385 * surface.
1386 *
1387 * @invariant level < surface levels
1388 * @invariant logical_array_layer < logical array length of surface
1389 * @invariant logical_z_offset_px < logical depth of surface at level
1390 */
1391 void
1392 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1393 uint32_t level,
1394 uint32_t logical_array_layer,
1395 uint32_t logical_z_offset_px,
1396 uint32_t *x_offset_sa,
1397 uint32_t *y_offset_sa);
1398
1399 /**
1400 * Calculate the offset, in units of surface elements, to a subimage in the
1401 * surface.
1402 *
1403 * @invariant level < surface levels
1404 * @invariant logical_array_layer < logical array length of surface
1405 * @invariant logical_z_offset_px < logical depth of surface at level
1406 */
1407 void
1408 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1409 uint32_t level,
1410 uint32_t logical_array_layer,
1411 uint32_t logical_z_offset_px,
1412 uint32_t *x_offset_el,
1413 uint32_t *y_offset_el);
1414
1415 /**
1416 * @brief Calculate the intratile offsets to a surface.
1417 *
1418 * In @a base_address_offset return the offset from the base of the surface to
1419 * the base address of the first tile of the subimage. In @a x_offset_B and
1420 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1421 * tile's base to the subimage's first surface element. The x and y offsets
1422 * are intratile offsets; that is, they do not exceed the boundary of the
1423 * surface's tiling format.
1424 */
1425 void
1426 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1427 enum isl_tiling tiling,
1428 uint8_t bs,
1429 uint32_t row_pitch,
1430 uint32_t total_x_offset_el,
1431 uint32_t total_y_offset_el,
1432 uint32_t *base_address_offset,
1433 uint32_t *x_offset_el,
1434 uint32_t *y_offset_el);
1435
1436 static inline void
1437 isl_tiling_get_intratile_offset_sa(const struct isl_device *dev,
1438 enum isl_tiling tiling,
1439 enum isl_format format,
1440 uint32_t row_pitch,
1441 uint32_t total_x_offset_sa,
1442 uint32_t total_y_offset_sa,
1443 uint32_t *base_address_offset,
1444 uint32_t *x_offset_sa,
1445 uint32_t *y_offset_sa)
1446 {
1447 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1448
1449 assert(fmtl->bpb % 8 == 0);
1450
1451 /* For computing the intratile offsets, we actually want a strange unit
1452 * which is samples for multisampled surfaces but elements for compressed
1453 * surfaces.
1454 */
1455 assert(total_x_offset_sa % fmtl->bw == 0);
1456 assert(total_y_offset_sa % fmtl->bh == 0);
1457 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
1458 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
1459
1460 isl_tiling_get_intratile_offset_el(dev, tiling, fmtl->bpb / 8, row_pitch,
1461 total_x_offset, total_y_offset,
1462 base_address_offset,
1463 x_offset_sa, y_offset_sa);
1464 *x_offset_sa *= fmtl->bw;
1465 *y_offset_sa *= fmtl->bh;
1466 }
1467
1468 /**
1469 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1470 *
1471 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1472 * @pre surf->format must be a valid format for depth surfaces
1473 */
1474 uint32_t
1475 isl_surf_get_depth_format(const struct isl_device *dev,
1476 const struct isl_surf *surf);
1477
1478 #ifdef __cplusplus
1479 }
1480 #endif
1481
1482 #endif /* ISL_H */