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isl: Round up some pitches to 512B for Gen12's CCS
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51
52 struct gen_device_info;
53 struct brw_image_param;
54
55 #ifndef ISL_DEV_GEN
56 /**
57 * @brief Get the hardware generation of isl_device.
58 *
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 */
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #else
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
67 #endif
68
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
71 #endif
72
73 #ifndef ISL_DEV_IS_HASWELL
74 /**
75 * @brief Get the hardware generation of isl_device.
76 *
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 */
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
81 #endif
82
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
85 #endif
86
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 /**
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 */
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #else
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
97 #endif
98
99 /**
100 * Hardware enumeration SURFACE_FORMAT.
101 *
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
104 */
105 enum isl_format {
106 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
107 ISL_FORMAT_R32G32B32A32_SINT = 1,
108 ISL_FORMAT_R32G32B32A32_UINT = 2,
109 ISL_FORMAT_R32G32B32A32_UNORM = 3,
110 ISL_FORMAT_R32G32B32A32_SNORM = 4,
111 ISL_FORMAT_R64G64_FLOAT = 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
114 ISL_FORMAT_R32G32B32A32_USCALED = 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
116 ISL_FORMAT_R64G64_PASSTHRU = 33,
117 ISL_FORMAT_R32G32B32_FLOAT = 64,
118 ISL_FORMAT_R32G32B32_SINT = 65,
119 ISL_FORMAT_R32G32B32_UINT = 66,
120 ISL_FORMAT_R32G32B32_UNORM = 67,
121 ISL_FORMAT_R32G32B32_SNORM = 68,
122 ISL_FORMAT_R32G32B32_SSCALED = 69,
123 ISL_FORMAT_R32G32B32_USCALED = 70,
124 ISL_FORMAT_R32G32B32_SFIXED = 80,
125 ISL_FORMAT_R16G16B16A16_UNORM = 128,
126 ISL_FORMAT_R16G16B16A16_SNORM = 129,
127 ISL_FORMAT_R16G16B16A16_SINT = 130,
128 ISL_FORMAT_R16G16B16A16_UINT = 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
130 ISL_FORMAT_R32G32_FLOAT = 133,
131 ISL_FORMAT_R32G32_SINT = 134,
132 ISL_FORMAT_R32G32_UINT = 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
135 ISL_FORMAT_L32A32_FLOAT = 138,
136 ISL_FORMAT_R32G32_UNORM = 139,
137 ISL_FORMAT_R32G32_SNORM = 140,
138 ISL_FORMAT_R64_FLOAT = 141,
139 ISL_FORMAT_R16G16B16X16_UNORM = 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
141 ISL_FORMAT_A32X32_FLOAT = 144,
142 ISL_FORMAT_L32X32_FLOAT = 145,
143 ISL_FORMAT_I32X32_FLOAT = 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
145 ISL_FORMAT_R16G16B16A16_USCALED = 148,
146 ISL_FORMAT_R32G32_SSCALED = 149,
147 ISL_FORMAT_R32G32_USCALED = 150,
148 ISL_FORMAT_R32G32_FLOAT_LD = 151,
149 ISL_FORMAT_R32G32_SFIXED = 160,
150 ISL_FORMAT_R64_PASSTHRU = 161,
151 ISL_FORMAT_B8G8R8A8_UNORM = 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
153 ISL_FORMAT_R10G10B10A2_UNORM = 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
155 ISL_FORMAT_R10G10B10A2_UINT = 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
157 ISL_FORMAT_R8G8B8A8_UNORM = 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
159 ISL_FORMAT_R8G8B8A8_SNORM = 201,
160 ISL_FORMAT_R8G8B8A8_SINT = 202,
161 ISL_FORMAT_R8G8B8A8_UINT = 203,
162 ISL_FORMAT_R16G16_UNORM = 204,
163 ISL_FORMAT_R16G16_SNORM = 205,
164 ISL_FORMAT_R16G16_SINT = 206,
165 ISL_FORMAT_R16G16_UINT = 207,
166 ISL_FORMAT_R16G16_FLOAT = 208,
167 ISL_FORMAT_B10G10R10A2_UNORM = 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
169 ISL_FORMAT_R11G11B10_FLOAT = 211,
170 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
171 ISL_FORMAT_R32_SINT = 214,
172 ISL_FORMAT_R32_UINT = 215,
173 ISL_FORMAT_R32_FLOAT = 216,
174 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
175 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
176 ISL_FORMAT_L32_UNORM = 221,
177 ISL_FORMAT_A32_UNORM = 222,
178 ISL_FORMAT_L16A16_UNORM = 223,
179 ISL_FORMAT_I24X8_UNORM = 224,
180 ISL_FORMAT_L24X8_UNORM = 225,
181 ISL_FORMAT_A24X8_UNORM = 226,
182 ISL_FORMAT_I32_FLOAT = 227,
183 ISL_FORMAT_L32_FLOAT = 228,
184 ISL_FORMAT_A32_FLOAT = 229,
185 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
186 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
187 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
188 ISL_FORMAT_B8G8R8X8_UNORM = 233,
189 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
190 ISL_FORMAT_R8G8B8X8_UNORM = 235,
191 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
192 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
193 ISL_FORMAT_B10G10R10X2_UNORM = 238,
194 ISL_FORMAT_L16A16_FLOAT = 240,
195 ISL_FORMAT_R32_UNORM = 241,
196 ISL_FORMAT_R32_SNORM = 242,
197 ISL_FORMAT_R10G10B10X2_USCALED = 243,
198 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
199 ISL_FORMAT_R8G8B8A8_USCALED = 245,
200 ISL_FORMAT_R16G16_SSCALED = 246,
201 ISL_FORMAT_R16G16_USCALED = 247,
202 ISL_FORMAT_R32_SSCALED = 248,
203 ISL_FORMAT_R32_USCALED = 249,
204 ISL_FORMAT_B5G6R5_UNORM = 256,
205 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
206 ISL_FORMAT_B5G5R5A1_UNORM = 258,
207 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
208 ISL_FORMAT_B4G4R4A4_UNORM = 260,
209 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
210 ISL_FORMAT_R8G8_UNORM = 262,
211 ISL_FORMAT_R8G8_SNORM = 263,
212 ISL_FORMAT_R8G8_SINT = 264,
213 ISL_FORMAT_R8G8_UINT = 265,
214 ISL_FORMAT_R16_UNORM = 266,
215 ISL_FORMAT_R16_SNORM = 267,
216 ISL_FORMAT_R16_SINT = 268,
217 ISL_FORMAT_R16_UINT = 269,
218 ISL_FORMAT_R16_FLOAT = 270,
219 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
220 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
221 ISL_FORMAT_I16_UNORM = 273,
222 ISL_FORMAT_L16_UNORM = 274,
223 ISL_FORMAT_A16_UNORM = 275,
224 ISL_FORMAT_L8A8_UNORM = 276,
225 ISL_FORMAT_I16_FLOAT = 277,
226 ISL_FORMAT_L16_FLOAT = 278,
227 ISL_FORMAT_A16_FLOAT = 279,
228 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
229 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
230 ISL_FORMAT_B5G5R5X1_UNORM = 282,
231 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
232 ISL_FORMAT_R8G8_SSCALED = 284,
233 ISL_FORMAT_R8G8_USCALED = 285,
234 ISL_FORMAT_R16_SSCALED = 286,
235 ISL_FORMAT_R16_USCALED = 287,
236 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
237 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
238 ISL_FORMAT_A1B5G5R5_UNORM = 292,
239 ISL_FORMAT_A4B4G4R4_UNORM = 293,
240 ISL_FORMAT_L8A8_UINT = 294,
241 ISL_FORMAT_L8A8_SINT = 295,
242 ISL_FORMAT_R8_UNORM = 320,
243 ISL_FORMAT_R8_SNORM = 321,
244 ISL_FORMAT_R8_SINT = 322,
245 ISL_FORMAT_R8_UINT = 323,
246 ISL_FORMAT_A8_UNORM = 324,
247 ISL_FORMAT_I8_UNORM = 325,
248 ISL_FORMAT_L8_UNORM = 326,
249 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
250 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
251 ISL_FORMAT_R8_SSCALED = 329,
252 ISL_FORMAT_R8_USCALED = 330,
253 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
254 ISL_FORMAT_L8_UNORM_SRGB = 332,
255 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
256 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
257 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
258 ISL_FORMAT_Y8_UNORM = 336,
259 ISL_FORMAT_L8_UINT = 338,
260 ISL_FORMAT_L8_SINT = 339,
261 ISL_FORMAT_I8_UINT = 340,
262 ISL_FORMAT_I8_SINT = 341,
263 ISL_FORMAT_DXT1_RGB_SRGB = 384,
264 ISL_FORMAT_R1_UNORM = 385,
265 ISL_FORMAT_YCRCB_NORMAL = 386,
266 ISL_FORMAT_YCRCB_SWAPUVY = 387,
267 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
268 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
269 ISL_FORMAT_BC1_UNORM = 390,
270 ISL_FORMAT_BC2_UNORM = 391,
271 ISL_FORMAT_BC3_UNORM = 392,
272 ISL_FORMAT_BC4_UNORM = 393,
273 ISL_FORMAT_BC5_UNORM = 394,
274 ISL_FORMAT_BC1_UNORM_SRGB = 395,
275 ISL_FORMAT_BC2_UNORM_SRGB = 396,
276 ISL_FORMAT_BC3_UNORM_SRGB = 397,
277 ISL_FORMAT_MONO8 = 398,
278 ISL_FORMAT_YCRCB_SWAPUV = 399,
279 ISL_FORMAT_YCRCB_SWAPY = 400,
280 ISL_FORMAT_DXT1_RGB = 401,
281 ISL_FORMAT_FXT1 = 402,
282 ISL_FORMAT_R8G8B8_UNORM = 403,
283 ISL_FORMAT_R8G8B8_SNORM = 404,
284 ISL_FORMAT_R8G8B8_SSCALED = 405,
285 ISL_FORMAT_R8G8B8_USCALED = 406,
286 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
287 ISL_FORMAT_R64G64B64_FLOAT = 408,
288 ISL_FORMAT_BC4_SNORM = 409,
289 ISL_FORMAT_BC5_SNORM = 410,
290 ISL_FORMAT_R16G16B16_FLOAT = 411,
291 ISL_FORMAT_R16G16B16_UNORM = 412,
292 ISL_FORMAT_R16G16B16_SNORM = 413,
293 ISL_FORMAT_R16G16B16_SSCALED = 414,
294 ISL_FORMAT_R16G16B16_USCALED = 415,
295 ISL_FORMAT_BC6H_SF16 = 417,
296 ISL_FORMAT_BC7_UNORM = 418,
297 ISL_FORMAT_BC7_UNORM_SRGB = 419,
298 ISL_FORMAT_BC6H_UF16 = 420,
299 ISL_FORMAT_PLANAR_420_8 = 421,
300 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
301 ISL_FORMAT_ETC1_RGB8 = 425,
302 ISL_FORMAT_ETC2_RGB8 = 426,
303 ISL_FORMAT_EAC_R11 = 427,
304 ISL_FORMAT_EAC_RG11 = 428,
305 ISL_FORMAT_EAC_SIGNED_R11 = 429,
306 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
307 ISL_FORMAT_ETC2_SRGB8 = 431,
308 ISL_FORMAT_R16G16B16_UINT = 432,
309 ISL_FORMAT_R16G16B16_SINT = 433,
310 ISL_FORMAT_R32_SFIXED = 434,
311 ISL_FORMAT_R10G10B10A2_SNORM = 435,
312 ISL_FORMAT_R10G10B10A2_USCALED = 436,
313 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
314 ISL_FORMAT_R10G10B10A2_SINT = 438,
315 ISL_FORMAT_B10G10R10A2_SNORM = 439,
316 ISL_FORMAT_B10G10R10A2_USCALED = 440,
317 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
318 ISL_FORMAT_B10G10R10A2_UINT = 442,
319 ISL_FORMAT_B10G10R10A2_SINT = 443,
320 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
321 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
322 ISL_FORMAT_ETC2_RGB8_PTA = 448,
323 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
324 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
325 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
326 ISL_FORMAT_R8G8B8_UINT = 456,
327 ISL_FORMAT_R8G8B8_SINT = 457,
328 ISL_FORMAT_RAW = 511,
329 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
330 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
331 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
332 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
333 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
334 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
335 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
336 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
337 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
338 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
339 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
340 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
341 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
342 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
343 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
344 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
345 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
346 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
347 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
348 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
349 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
350 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
351 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
352 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
353 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
354 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
355 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
356 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
357 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
358 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
359 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
360 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
361 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
362 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
363 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
364 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
365 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
366 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
367 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
368 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
369 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
370 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
371
372 /* The formats that follow are internal to ISL and as such don't have an
373 * explicit number. We'll just let the C compiler assign it for us. Any
374 * actual hardware formats *must* come before these in the list.
375 */
376
377 /* Formats for auxiliary surfaces */
378 ISL_FORMAT_HIZ,
379 ISL_FORMAT_MCS_2X,
380 ISL_FORMAT_MCS_4X,
381 ISL_FORMAT_MCS_8X,
382 ISL_FORMAT_MCS_16X,
383 ISL_FORMAT_GEN7_CCS_32BPP_X,
384 ISL_FORMAT_GEN7_CCS_64BPP_X,
385 ISL_FORMAT_GEN7_CCS_128BPP_X,
386 ISL_FORMAT_GEN7_CCS_32BPP_Y,
387 ISL_FORMAT_GEN7_CCS_64BPP_Y,
388 ISL_FORMAT_GEN7_CCS_128BPP_Y,
389 ISL_FORMAT_GEN9_CCS_32BPP,
390 ISL_FORMAT_GEN9_CCS_64BPP,
391 ISL_FORMAT_GEN9_CCS_128BPP,
392
393 /* An upper bound on the supported format enumerations */
394 ISL_NUM_FORMATS,
395
396 /* Hardware doesn't understand this out-of-band value */
397 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
398 };
399
400 /**
401 * Numerical base type for channels of isl_format.
402 */
403 enum isl_base_type {
404 ISL_VOID,
405 ISL_RAW,
406 ISL_UNORM,
407 ISL_SNORM,
408 ISL_UFLOAT,
409 ISL_SFLOAT,
410 ISL_UFIXED,
411 ISL_SFIXED,
412 ISL_UINT,
413 ISL_SINT,
414 ISL_USCALED,
415 ISL_SSCALED,
416 };
417
418 /**
419 * Colorspace of isl_format.
420 */
421 enum isl_colorspace {
422 ISL_COLORSPACE_NONE = 0,
423 ISL_COLORSPACE_LINEAR,
424 ISL_COLORSPACE_SRGB,
425 ISL_COLORSPACE_YUV,
426 };
427
428 /**
429 * Texture compression mode of isl_format.
430 */
431 enum isl_txc {
432 ISL_TXC_NONE = 0,
433 ISL_TXC_DXT1,
434 ISL_TXC_DXT3,
435 ISL_TXC_DXT5,
436 ISL_TXC_FXT1,
437 ISL_TXC_RGTC1,
438 ISL_TXC_RGTC2,
439 ISL_TXC_BPTC,
440 ISL_TXC_ETC1,
441 ISL_TXC_ETC2,
442 ISL_TXC_ASTC,
443
444 /* Used for auxiliary surface formats */
445 ISL_TXC_HIZ,
446 ISL_TXC_MCS,
447 ISL_TXC_CCS,
448 };
449
450 /**
451 * @brief Hardware tile mode
452 *
453 * WARNING: These values differ from the hardware enum values, which are
454 * unstable across hardware generations.
455 *
456 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
457 * clearly distinguish it from Yf and Ys.
458 */
459 enum isl_tiling {
460 ISL_TILING_LINEAR = 0,
461 ISL_TILING_W,
462 ISL_TILING_X,
463 ISL_TILING_Y0, /**< Legacy Y tiling */
464 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
465 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
466 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
467 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
468 };
469
470 /**
471 * @defgroup Tiling Flags
472 * @{
473 */
474 typedef uint32_t isl_tiling_flags_t;
475 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
476 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
477 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
478 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
479 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
480 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
481 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
482 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
483 #define ISL_TILING_ANY_MASK (~0u)
484 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
485
486 /** Any Y tiling, including legacy Y tiling. */
487 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
488 ISL_TILING_Yf_BIT | \
489 ISL_TILING_Ys_BIT)
490
491 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
492 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
493 ISL_TILING_Ys_BIT)
494 /** @} */
495
496 /**
497 * @brief Logical dimension of surface.
498 *
499 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
500 * as 2D array surfaces.
501 */
502 enum isl_surf_dim {
503 ISL_SURF_DIM_1D,
504 ISL_SURF_DIM_2D,
505 ISL_SURF_DIM_3D,
506 };
507
508 /**
509 * @brief Physical layout of the surface's dimensions.
510 */
511 enum isl_dim_layout {
512 /**
513 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
514 * 6.17.3: 2D Surfaces.
515 *
516 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
517 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
518 *
519 * One-dimensional surfaces are identical to 2D surfaces with height of
520 * one.
521 *
522 * @invariant isl_surf::phys_level0_sa::depth == 1
523 */
524 ISL_DIM_LAYOUT_GEN4_2D,
525
526 /**
527 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
528 * 6.17.5: 3D Surfaces.
529 *
530 * @invariant isl_surf::phys_level0_sa::array_len == 1
531 */
532 ISL_DIM_LAYOUT_GEN4_3D,
533
534 /**
535 * Special layout used for HiZ and stencil on Sandy Bridge to work around
536 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
537 * work the same as on gen7+ except that they don't technically support
538 * mipmapping. That does not, however, stop us from doing it. As far as
539 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
540 * single miplevel 2D (possibly array) image. The dimensions of that image
541 * are NOT minified.
542 *
543 * In order to implement HiZ and stencil on Sandy Bridge, we create one
544 * full-sized 2D (possibly array) image for every LOD with every image
545 * aligned to a page boundary. When the surface is used with the stencil
546 * or HiZ hardware, we manually offset to the image for the given LOD.
547 *
548 * As a memory saving measure, we pretend that the width of each miplevel
549 * is minified and we place LOD1 and above below LOD0 but horizontally
550 * adjacent to each other. When considered as full-sized images, LOD1 and
551 * above technically overlap. However, since we only write to part of that
552 * image, the hardware will never notice the overlap.
553 *
554 * This layout looks something like this:
555 *
556 * +---------+
557 * | |
558 * | |
559 * +---------+
560 * | |
561 * | |
562 * +---------+
563 *
564 * +----+ +-+ .
565 * | | +-+
566 * +----+
567 *
568 * +----+ +-+ .
569 * | | +-+
570 * +----+
571 */
572 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
573
574 /**
575 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
576 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
577 */
578 ISL_DIM_LAYOUT_GEN9_1D,
579 };
580
581 enum isl_aux_usage {
582 /** No Auxiliary surface is used */
583 ISL_AUX_USAGE_NONE,
584
585 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
586 ISL_AUX_USAGE_HIZ,
587
588 /** The auxiliary surface is an MCS
589 *
590 * @invariant isl_surf::samples > 1
591 */
592 ISL_AUX_USAGE_MCS,
593
594 /** The auxiliary surface is a fast-clear-only compression surface
595 *
596 * @invariant isl_surf::samples == 1
597 */
598 ISL_AUX_USAGE_CCS_D,
599
600 /** The auxiliary surface provides full lossless color compression
601 *
602 * @invariant isl_surf::samples == 1
603 */
604 ISL_AUX_USAGE_CCS_E,
605 };
606
607 /**
608 * Enum for keeping track of the state an auxiliary compressed surface.
609 *
610 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
611 * given slice (lod + array layer) can be in one of the six states described
612 * by this enum. Draw and resolve operations may cause the slice to change
613 * from one state to another. The six valid states are:
614 *
615 * 1) Clear: In this state, each block in the auxiliary surface contains a
616 * magic value that indicates that the block is in the clear state. If
617 * a block is in the clear state, it's values in the primary surface are
618 * ignored and the color of the samples in the block is taken either the
619 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
620 * depth. Since neither the primary surface nor the auxiliary surface
621 * contains the clear value, the surface can be cleared to a different
622 * color by simply changing the clear color without modifying either
623 * surface.
624 *
625 * 2) Partial Clear: In this state, each block in the auxiliary surface
626 * contains either the magic clear or pass-through value. See Clear and
627 * Pass-through for more details.
628 *
629 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
630 * nor the primary surface has a complete representation of the data.
631 * Instead, both surfaces must be used together or else rendering
632 * corruption may occur. Depending on the auxiliary compression format
633 * and the data, any given block in the primary surface may contain all,
634 * some, or none of the data required to reconstruct the actual sample
635 * values. Blocks may also be in the clear state (see Clear) and have
636 * their value taken from outside the surface.
637 *
638 * 4) Compressed w/o Clear: This state is identical to the state above
639 * except that no blocks are in the clear state. In this state, all of
640 * the data required to reconstruct the final sample values is contained
641 * in the auxiliary and primary surface and the clear value is not
642 * considered.
643 *
644 * 5) Resolved: In this state, the primary surface contains 100% of the
645 * data. The auxiliary surface is also valid so the surface can be
646 * validly used with or without aux enabled. The auxiliary surface may,
647 * however, contain non-trivial data and any update to the primary
648 * surface with aux disabled will cause the two to get out of sync.
649 *
650 * 6) Pass-through: In this state, the primary surface contains 100% of the
651 * data and every block in the auxiliary surface contains a magic value
652 * which indicates that the auxiliary surface should be ignored and the
653 * only the primary surface should be considered. Updating the primary
654 * surface without aux works fine and can be done repeatedly in this
655 * mode. Writing to a surface in pass-through mode with aux enabled may
656 * cause the auxiliary buffer to contain non-trivial data and no longer
657 * be in the pass-through state.
658 *
659 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
660 * data and the auxiliary surface is completely bogus. Any attempt to
661 * use the auxiliary surface is liable to result in rendering
662 * corruption. The only thing that one can do to re-enable aux once
663 * this state is reached is to use an ambiguate pass to transition into
664 * the pass-through state.
665 *
666 * Drawing with or without aux enabled may implicitly cause the surface to
667 * transition between these states. There are also four types of auxiliary
668 * compression operations which cause an explicit transition which are
669 * described by the isl_aux_op enum below.
670 *
671 * Not all operations are valid or useful in all states. The diagram below
672 * contains a complete description of the states and all valid and useful
673 * transitions except clear.
674 *
675 * Draw w/ Aux
676 * +----------+
677 * | |
678 * | +-------------+ Draw w/ Aux +-------------+
679 * +------>| Compressed |<-------------------| Clear |
680 * | w/ Clear |----->----+ | |
681 * +-------------+ | +-------------+
682 * | /|\ | | |
683 * | | | | |
684 * | | +------<-----+ | Draw w/
685 * | | | | Clear Only
686 * | | Full | | +----------+
687 * Partial | | Resolve | \|/ | |
688 * Resolve | | | +-------------+ |
689 * | | | | Partial |<------+
690 * | | | | Clear |<----------+
691 * | | | +-------------+ |
692 * | | | | |
693 * | | +------>---------+ Full |
694 * | | | Resolve |
695 * Draw w/ aux | | Partial Fast Clear | |
696 * +----------+ | +--------------------------+ | |
697 * | | \|/ | \|/ |
698 * | +-------------+ Full Resolve +-------------+ |
699 * +------>| Compressed |------------------->| Resolved | |
700 * | w/o Clear |<-------------------| | |
701 * +-------------+ Draw w/ Aux +-------------+ |
702 * /|\ | | |
703 * | Draw | | Draw |
704 * | w/ Aux | | w/o Aux |
705 * | Ambiguate | | |
706 * | +--------------------------+ | |
707 * Draw w/o Aux | | | Draw w/o Aux |
708 * +----------+ | | | +----------+ |
709 * | | | \|/ \|/ | | |
710 * | +-------------+ Ambiguate +-------------+ | |
711 * +------>| Pass- |<-------------------| Aux |<------+ |
712 * +------>| through | | Invalid | |
713 * | +-------------+ +-------------+ |
714 * | | | |
715 * +----------+ +-----------------------------------------------------+
716 * Draw w/ Partial Fast Clear
717 * Clear Only
718 *
719 *
720 * While the above general theory applies to all forms of auxiliary
721 * compression on Intel hardware, not all states and operations are available
722 * on all compression types. However, each of the auxiliary states and
723 * operations can be fairly easily mapped onto the above diagram:
724 *
725 * HiZ: Hierarchical depth compression is capable of being in any of the
726 * states above. Hardware provides three HiZ operations: "Depth
727 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
728 * Clear", "Full Resolve", and "Ambiguate" respectively. The
729 * hardware provides no HiZ partial resolve operation so the only way
730 * to get into the "Compressed w/o Clear" state is to render with HiZ
731 * when the surface is in the resolved or pass-through states.
732 *
733 * MCS: Multisample compression is technically capable of being in any of
734 * the states above except that most of them aren't useful. Both the
735 * render engine and the sampler support MCS compression and, apart
736 * from clear color, MCS is format-unaware so we leave the surface
737 * compressed 100% of the time. The hardware provides no MCS
738 * operations.
739 *
740 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
741 * the simplest forms of compression since they don't do anything
742 * beyond clear color tracking. They really only support three of
743 * the six states: Clear, Partial Clear, and Pass-through. The
744 * only CCS_D operation is "Resolve" which maps to a full resolve
745 * followed by an ambiguate.
746 *
747 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
748 * is capable of being in almost all of the above states. THe only
749 * exception is that it does not have separate resolved and pass-
750 * through states. Instead, the CCS_E full resolve operation does
751 * both a resolve and an ambiguate so it goes directly into the
752 * pass-through state. CCS_E also provides fast clear and partial
753 * resolve operations which work as described above.
754 *
755 * While it is technically possible to perform a CCS_E ambiguate, it
756 * is not provided by Sky Lake hardware so we choose to avoid the aux
757 * invalid state. If the aux invalid state were determined to be
758 * useful, a CCS ambiguate could be done by carefully rendering to
759 * the CCS and filling it with zeros.
760 */
761 enum isl_aux_state {
762 ISL_AUX_STATE_CLEAR = 0,
763 ISL_AUX_STATE_PARTIAL_CLEAR,
764 ISL_AUX_STATE_COMPRESSED_CLEAR,
765 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
766 ISL_AUX_STATE_RESOLVED,
767 ISL_AUX_STATE_PASS_THROUGH,
768 ISL_AUX_STATE_AUX_INVALID,
769 };
770
771 /**
772 * Enum which describes explicit aux transition operations.
773 */
774 enum isl_aux_op {
775 ISL_AUX_OP_NONE,
776
777 /** Fast Clear
778 *
779 * This operation writes the magic "clear" value to the auxiliary surface.
780 * This operation will safely transition any slice of a surface from any
781 * state to the clear state so long as the entire slice is fast cleared at
782 * once. A fast clear that only covers part of a slice of a surface is
783 * called a partial fast clear.
784 */
785 ISL_AUX_OP_FAST_CLEAR,
786
787 /** Full Resolve
788 *
789 * This operation combines the auxiliary surface data with the primary
790 * surface data and writes the result to the primary. For HiZ, the docs
791 * call this a depth resolve. For CCS, the hardware full resolve operation
792 * does both a full resolve and an ambiguate so it actually takes you all
793 * the way to the pass-through state.
794 */
795 ISL_AUX_OP_FULL_RESOLVE,
796
797 /** Partial Resolve
798 *
799 * This operation considers blocks which are in the "clear" state and
800 * writes the clear value directly into the primary or auxiliary surface.
801 * Once this operation completes, the surface is still compressed but no
802 * longer references the clear color. This operation is only available
803 * for CCS_E.
804 */
805 ISL_AUX_OP_PARTIAL_RESOLVE,
806
807 /** Ambiguate
808 *
809 * This operation throws away the current auxiliary data and replaces it
810 * with the magic pass-through value. If an ambiguate operation is
811 * performed when the primary surface does not contain 100% of the data,
812 * data will be lost. This operation is only implemented in hardware for
813 * depth where it is called a HiZ resolve.
814 */
815 ISL_AUX_OP_AMBIGUATE,
816 };
817
818 /* TODO(chadv): Explain */
819 enum isl_array_pitch_span {
820 ISL_ARRAY_PITCH_SPAN_FULL,
821 ISL_ARRAY_PITCH_SPAN_COMPACT,
822 };
823
824 /**
825 * @defgroup Surface Usage
826 * @{
827 */
828 typedef uint64_t isl_surf_usage_flags_t;
829 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
830 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
831 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
832 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
833 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
834 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
835 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
836 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
837 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
838 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
839 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
840 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
841 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
842 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
843 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
844 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
845 /** @} */
846
847 /**
848 * @defgroup Channel Mask
849 *
850 * These #define values are chosen to match the values of
851 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
852 *
853 * @{
854 */
855 typedef uint8_t isl_channel_mask_t;
856 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
857 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
858 #define ISL_CHANNEL_RED_BIT (1 << 2)
859 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
860 /** @} */
861
862 /**
863 * @brief A channel select (also known as texture swizzle) value
864 */
865 enum PACKED isl_channel_select {
866 ISL_CHANNEL_SELECT_ZERO = 0,
867 ISL_CHANNEL_SELECT_ONE = 1,
868 ISL_CHANNEL_SELECT_RED = 4,
869 ISL_CHANNEL_SELECT_GREEN = 5,
870 ISL_CHANNEL_SELECT_BLUE = 6,
871 ISL_CHANNEL_SELECT_ALPHA = 7,
872 };
873
874 /**
875 * Identical to VkSampleCountFlagBits.
876 */
877 enum isl_sample_count {
878 ISL_SAMPLE_COUNT_1_BIT = 1u,
879 ISL_SAMPLE_COUNT_2_BIT = 2u,
880 ISL_SAMPLE_COUNT_4_BIT = 4u,
881 ISL_SAMPLE_COUNT_8_BIT = 8u,
882 ISL_SAMPLE_COUNT_16_BIT = 16u,
883 };
884 typedef uint32_t isl_sample_count_mask_t;
885
886 /**
887 * @brief Multisample Format
888 */
889 enum isl_msaa_layout {
890 /**
891 * @brief Suface is single-sampled.
892 */
893 ISL_MSAA_LAYOUT_NONE,
894
895 /**
896 * @brief [SNB+] Interleaved Multisample Format
897 *
898 * In this format, multiple samples are interleaved into each cacheline.
899 * In other words, the sample index is swizzled into the low 6 bits of the
900 * surface's virtual address space.
901 *
902 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
903 * and its pixel format is 32bpp. Then the first cacheline is arranged
904 * thus:
905 *
906 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
907 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
908 *
909 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
910 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
911 *
912 * The hardware docs refer to this format with multiple terms. In
913 * Sandybridge, this is the only multisample format; so no term is used.
914 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
915 * Multisample Surface). Later hardware docs additionally refer to this
916 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
917 * color surfaces).
918 *
919 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
920 * Surface Behavior".
921 *
922 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
923 * Multisampled Surfaces".
924 */
925 ISL_MSAA_LAYOUT_INTERLEAVED,
926
927 /**
928 * @brief [IVB+] Array Multisample Format
929 *
930 * In this format, the surface's physical layout resembles that of a
931 * 2D array surface.
932 *
933 * Suppose the multisample surface's logical extent is (w, h) and its
934 * sample count is N. Then surface's physical extent is the same as
935 * a singlesample 2D surface whose logical extent is (w, h) and array
936 * length is N. Array slice `i` contains the pixel values for sample
937 * index `i`.
938 *
939 * The Ivybridge docs refer to surfaces in this format as UMS
940 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
941 * Surface). The Broadwell docs additionally refer to this format as
942 * MSFMT_MSS (MSS=Multisample Surface Storage).
943 *
944 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
945 * Multisample Surfaces".
946 *
947 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
948 * Multisample Surfaces".
949 */
950 ISL_MSAA_LAYOUT_ARRAY,
951 };
952
953 typedef enum {
954 ISL_MEMCPY = 0,
955 ISL_MEMCPY_BGRA8,
956 ISL_MEMCPY_STREAMING_LOAD,
957 ISL_MEMCPY_INVALID,
958 } isl_memcpy_type;
959
960 struct isl_device {
961 const struct gen_device_info *info;
962 bool use_separate_stencil;
963 bool has_bit6_swizzling;
964
965 /**
966 * Describes the layout of a RENDER_SURFACE_STATE structure for the
967 * current gen.
968 */
969 struct {
970 uint8_t size;
971 uint8_t align;
972 uint8_t addr_offset;
973 uint8_t aux_addr_offset;
974
975 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
976
977 /* size of the state buffer used to store the clear color + extra
978 * additional space used by the hardware */
979 uint8_t clear_color_state_size;
980 uint8_t clear_color_state_offset;
981 /* size of the clear color itself - used to copy it to/from a BO */
982 uint8_t clear_value_size;
983 uint8_t clear_value_offset;
984 } ss;
985
986 /**
987 * Describes the layout of the depth/stencil/hiz commands as emitted by
988 * isl_emit_depth_stencil_hiz.
989 */
990 struct {
991 uint8_t size;
992 uint8_t depth_offset;
993 uint8_t stencil_offset;
994 uint8_t hiz_offset;
995 } ds;
996 };
997
998 struct isl_extent2d {
999 union { uint32_t w, width; };
1000 union { uint32_t h, height; };
1001 };
1002
1003 struct isl_extent3d {
1004 union { uint32_t w, width; };
1005 union { uint32_t h, height; };
1006 union { uint32_t d, depth; };
1007 };
1008
1009 struct isl_extent4d {
1010 union { uint32_t w, width; };
1011 union { uint32_t h, height; };
1012 union { uint32_t d, depth; };
1013 union { uint32_t a, array_len; };
1014 };
1015
1016 struct isl_channel_layout {
1017 enum isl_base_type type;
1018 uint8_t start_bit; /**< Bit at which this channel starts */
1019 uint8_t bits; /**< Size in bits */
1020 };
1021
1022 /**
1023 * Each format has 3D block extent (width, height, depth). The block extent of
1024 * compressed formats is that of the format's compression block. For example,
1025 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1026 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1027 * is (w=1, h=1, d=1).
1028 */
1029 struct isl_format_layout {
1030 enum isl_format format;
1031 const char *name;
1032
1033 uint16_t bpb; /**< Bits per block */
1034 uint8_t bw; /**< Block width, in pixels */
1035 uint8_t bh; /**< Block height, in pixels */
1036 uint8_t bd; /**< Block depth, in pixels */
1037
1038 union {
1039 struct {
1040 struct isl_channel_layout r; /**< Red channel */
1041 struct isl_channel_layout g; /**< Green channel */
1042 struct isl_channel_layout b; /**< Blue channel */
1043 struct isl_channel_layout a; /**< Alpha channel */
1044 struct isl_channel_layout l; /**< Luminance channel */
1045 struct isl_channel_layout i; /**< Intensity channel */
1046 struct isl_channel_layout p; /**< Palette channel */
1047 } channels;
1048 struct isl_channel_layout channels_array[7];
1049 };
1050
1051 enum isl_colorspace colorspace;
1052 enum isl_txc txc;
1053 };
1054
1055 struct isl_tile_info {
1056 enum isl_tiling tiling;
1057
1058 /* The size (in bits per block) of a single surface element
1059 *
1060 * For surfaces with power-of-two formats, this is the same as
1061 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1062 * The logical_extent_el field is in terms of elements of this size.
1063 *
1064 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1065 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1066 * of the tiling formats can actually hold an integer number of 96-bit
1067 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1068 * 32-bit element size. It is the responsibility of the caller to
1069 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1070 * the width of a surface in tiles, you would do:
1071 *
1072 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1073 * tile_info.logical_extent_el.width);
1074 */
1075 uint32_t format_bpb;
1076
1077 /** The logical size of the tile in units of format_bpb size elements
1078 *
1079 * This field determines how a given surface is cut up into tiles. It is
1080 * used to compute the size of a surface in tiles and can be used to
1081 * determine the location of the tile containing any given surface element.
1082 * The exact value of this field depends heavily on the bits-per-block of
1083 * the format being used.
1084 */
1085 struct isl_extent2d logical_extent_el;
1086
1087 /** The physical size of the tile in bytes and rows of bytes
1088 *
1089 * This field determines how the tiles of a surface are physically layed
1090 * out in memory. The logical and physical tile extent are frequently the
1091 * same but this is not always the case. For instance, a W-tile (which is
1092 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1093 * its physical size is 128B x 32rows, the same as a Y-tile.
1094 *
1095 * @see isl_surf::row_pitch_B
1096 */
1097 struct isl_extent2d phys_extent_B;
1098 };
1099
1100 /**
1101 * Metadata about a DRM format modifier.
1102 */
1103 struct isl_drm_modifier_info {
1104 uint64_t modifier;
1105
1106 /** Text name of the modifier */
1107 const char *name;
1108
1109 /** ISL tiling implied by this modifier */
1110 enum isl_tiling tiling;
1111
1112 /** ISL aux usage implied by this modifier */
1113 enum isl_aux_usage aux_usage;
1114
1115 /** Whether or not this modifier supports clear color */
1116 bool supports_clear_color;
1117 };
1118
1119 /**
1120 * @brief Input to surface initialization
1121 *
1122 * @invariant width >= 1
1123 * @invariant height >= 1
1124 * @invariant depth >= 1
1125 * @invariant levels >= 1
1126 * @invariant samples >= 1
1127 * @invariant array_len >= 1
1128 *
1129 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1130 * @invariant if 2D then depth == 1
1131 * @invariant if 3D then array_len == 1 and samples == 1
1132 */
1133 struct isl_surf_init_info {
1134 enum isl_surf_dim dim;
1135 enum isl_format format;
1136
1137 uint32_t width;
1138 uint32_t height;
1139 uint32_t depth;
1140 uint32_t levels;
1141 uint32_t array_len;
1142 uint32_t samples;
1143
1144 /** Lower bound for isl_surf::alignment, in bytes. */
1145 uint32_t min_alignment_B;
1146
1147 /**
1148 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1149 * will fail if this is misaligned or out of bounds.
1150 */
1151 uint32_t row_pitch_B;
1152
1153 isl_surf_usage_flags_t usage;
1154
1155 /** Flags that alter how ISL selects isl_surf::tiling. */
1156 isl_tiling_flags_t tiling_flags;
1157 };
1158
1159 struct isl_surf {
1160 enum isl_surf_dim dim;
1161 enum isl_dim_layout dim_layout;
1162 enum isl_msaa_layout msaa_layout;
1163 enum isl_tiling tiling;
1164 enum isl_format format;
1165
1166 /**
1167 * Alignment of the upper-left sample of each subimage, in units of surface
1168 * elements.
1169 */
1170 struct isl_extent3d image_alignment_el;
1171
1172 /**
1173 * Logical extent of the surface's base level, in units of pixels. This is
1174 * identical to the extent defined in isl_surf_init_info.
1175 */
1176 struct isl_extent4d logical_level0_px;
1177
1178 /**
1179 * Physical extent of the surface's base level, in units of physical
1180 * surface samples.
1181 *
1182 * Consider isl_dim_layout as an operator that transforms a logical surface
1183 * layout to a physical surface layout. Then
1184 *
1185 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1186 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1187 */
1188 struct isl_extent4d phys_level0_sa;
1189
1190 uint32_t levels;
1191 uint32_t samples;
1192
1193 /** Total size of the surface, in bytes. */
1194 uint64_t size_B;
1195
1196 /** Required alignment for the surface's base address. */
1197 uint32_t alignment_B;
1198
1199 /**
1200 * The interpretation of this field depends on the value of
1201 * isl_tile_info::physical_extent_B. In particular, the width of the
1202 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1203 * and the distance in bytes between vertically adjacent tiles in the image
1204 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1205 *
1206 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1207 * this cleanly reduces to being the distance, in bytes, between vertically
1208 * adjacent surface elements.
1209 *
1210 * @see isl_tile_info::phys_extent_B;
1211 */
1212 uint32_t row_pitch_B;
1213
1214 /**
1215 * Pitch between physical array slices, in rows of surface elements.
1216 */
1217 uint32_t array_pitch_el_rows;
1218
1219 enum isl_array_pitch_span array_pitch_span;
1220
1221 /** Copy of isl_surf_init_info::usage. */
1222 isl_surf_usage_flags_t usage;
1223 };
1224
1225 struct isl_swizzle {
1226 enum isl_channel_select r:4;
1227 enum isl_channel_select g:4;
1228 enum isl_channel_select b:4;
1229 enum isl_channel_select a:4;
1230 };
1231
1232 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1233 .r = ISL_CHANNEL_SELECT_##R, \
1234 .g = ISL_CHANNEL_SELECT_##G, \
1235 .b = ISL_CHANNEL_SELECT_##B, \
1236 .a = ISL_CHANNEL_SELECT_##A, \
1237 })
1238
1239 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1240
1241 struct isl_view {
1242 /**
1243 * Indicates the usage of the particular view
1244 *
1245 * Normally, this is one bit. However, for a cube map texture, it
1246 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1247 */
1248 isl_surf_usage_flags_t usage;
1249
1250 /**
1251 * The format to use in the view
1252 *
1253 * This may differ from the format of the actual isl_surf but must have
1254 * the same block size.
1255 */
1256 enum isl_format format;
1257
1258 uint32_t base_level;
1259 uint32_t levels;
1260
1261 /**
1262 * Base array layer
1263 *
1264 * For cube maps, both base_array_layer and array_len should be
1265 * specified in terms of 2-D layers and must be a multiple of 6.
1266 *
1267 * 3-D textures are effectively treated as 2-D arrays when used as a
1268 * storage image or render target. If `usage` contains
1269 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1270 * base_array_layer and array_len are applied. If the surface is only used
1271 * for texturing, they are ignored.
1272 */
1273 uint32_t base_array_layer;
1274
1275 /**
1276 * Array Length
1277 *
1278 * Indicates the number of array elements starting at Base Array Layer.
1279 */
1280 uint32_t array_len;
1281
1282 struct isl_swizzle swizzle;
1283 };
1284
1285 union isl_color_value {
1286 float f32[4];
1287 uint32_t u32[4];
1288 int32_t i32[4];
1289 };
1290
1291 struct isl_surf_fill_state_info {
1292 const struct isl_surf *surf;
1293 const struct isl_view *view;
1294
1295 /**
1296 * The address of the surface in GPU memory.
1297 */
1298 uint64_t address;
1299
1300 /**
1301 * The Memory Object Control state for the filled surface state.
1302 *
1303 * The exact format of this value depends on hardware generation.
1304 */
1305 uint32_t mocs;
1306
1307 /**
1308 * The auxilary surface or NULL if no auxilary surface is to be used.
1309 */
1310 const struct isl_surf *aux_surf;
1311 enum isl_aux_usage aux_usage;
1312 uint64_t aux_address;
1313
1314 /**
1315 * The clear color for this surface
1316 *
1317 * Valid values depend on hardware generation.
1318 */
1319 union isl_color_value clear_color;
1320
1321 /**
1322 * Send only the clear value address
1323 *
1324 * If set, we only pass the clear address to the GPU and it will fetch it
1325 * from wherever it is.
1326 */
1327 bool use_clear_address;
1328 uint64_t clear_address;
1329
1330 /**
1331 * Surface write disables for gen4-5
1332 */
1333 isl_channel_mask_t write_disables;
1334
1335 /* Intra-tile offset */
1336 uint16_t x_offset_sa, y_offset_sa;
1337 };
1338
1339 struct isl_buffer_fill_state_info {
1340 /**
1341 * The address of the surface in GPU memory.
1342 */
1343 uint64_t address;
1344
1345 /**
1346 * The size of the buffer
1347 */
1348 uint64_t size_B;
1349
1350 /**
1351 * The Memory Object Control state for the filled surface state.
1352 *
1353 * The exact format of this value depends on hardware generation.
1354 */
1355 uint32_t mocs;
1356
1357 /**
1358 * The format to use in the surface state
1359 *
1360 * This may differ from the format of the actual isl_surf but have the
1361 * same block size.
1362 */
1363 enum isl_format format;
1364
1365 /**
1366 * The swizzle to use in the surface state
1367 */
1368 struct isl_swizzle swizzle;
1369
1370 uint32_t stride_B;
1371 };
1372
1373 struct isl_depth_stencil_hiz_emit_info {
1374 /**
1375 * The depth surface
1376 */
1377 const struct isl_surf *depth_surf;
1378
1379 /**
1380 * The stencil surface
1381 *
1382 * If separate stencil is not available, this must point to the same
1383 * isl_surf as depth_surf.
1384 */
1385 const struct isl_surf *stencil_surf;
1386
1387 /**
1388 * The view into the depth and stencil surfaces.
1389 *
1390 * This view applies to both surfaces simultaneously.
1391 */
1392 const struct isl_view *view;
1393
1394 /**
1395 * The address of the depth surface in GPU memory
1396 */
1397 uint64_t depth_address;
1398
1399 /**
1400 * The address of the stencil surface in GPU memory
1401 *
1402 * If separate stencil is not available, this must have the same value as
1403 * depth_address.
1404 */
1405 uint64_t stencil_address;
1406
1407 /**
1408 * The Memory Object Control state for depth and stencil buffers
1409 *
1410 * Both depth and stencil will get the same MOCS value. The exact format
1411 * of this value depends on hardware generation.
1412 */
1413 uint32_t mocs;
1414
1415 /**
1416 * The HiZ surface or NULL if HiZ is disabled.
1417 */
1418 const struct isl_surf *hiz_surf;
1419 enum isl_aux_usage hiz_usage;
1420 uint64_t hiz_address;
1421
1422 /**
1423 * The depth clear value
1424 */
1425 float depth_clear_value;
1426 };
1427
1428 extern const struct isl_format_layout isl_format_layouts[];
1429
1430 void
1431 isl_device_init(struct isl_device *dev,
1432 const struct gen_device_info *info,
1433 bool has_bit6_swizzling);
1434
1435 isl_sample_count_mask_t ATTRIBUTE_CONST
1436 isl_device_get_sample_counts(struct isl_device *dev);
1437
1438 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1439 isl_format_get_layout(enum isl_format fmt)
1440 {
1441 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1442 assert(fmt < ISL_NUM_FORMATS);
1443 return &isl_format_layouts[fmt];
1444 }
1445
1446 bool isl_format_is_valid(enum isl_format);
1447
1448 static inline const char * ATTRIBUTE_CONST
1449 isl_format_get_name(enum isl_format fmt)
1450 {
1451 return isl_format_get_layout(fmt)->name;
1452 }
1453
1454 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1455 enum isl_format format);
1456 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1457 enum isl_format format);
1458 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1459 enum isl_format format);
1460 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1461 enum isl_format format);
1462 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1463 enum isl_format format);
1464 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1465 enum isl_format format);
1466 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1467 enum isl_format format);
1468 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1469 enum isl_format format);
1470 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1471 enum isl_format format);
1472 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1473 enum isl_format format);
1474
1475 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1476 enum isl_format format1,
1477 enum isl_format format2);
1478
1479 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1480 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1481 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1482 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1483 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1484 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1485
1486 static inline bool
1487 isl_format_has_normalized_channel(enum isl_format fmt)
1488 {
1489 return isl_format_has_unorm_channel(fmt) ||
1490 isl_format_has_snorm_channel(fmt);
1491 }
1492
1493 static inline bool
1494 isl_format_has_float_channel(enum isl_format fmt)
1495 {
1496 return isl_format_has_ufloat_channel(fmt) ||
1497 isl_format_has_sfloat_channel(fmt);
1498 }
1499
1500 static inline bool
1501 isl_format_has_int_channel(enum isl_format fmt)
1502 {
1503 return isl_format_has_uint_channel(fmt) ||
1504 isl_format_has_sint_channel(fmt);
1505 }
1506
1507 bool isl_format_has_color_component(enum isl_format fmt,
1508 int component) ATTRIBUTE_CONST;
1509
1510 unsigned isl_format_get_num_channels(enum isl_format fmt);
1511
1512 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1513
1514 static inline bool
1515 isl_format_is_compressed(enum isl_format fmt)
1516 {
1517 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1518
1519 return fmtl->txc != ISL_TXC_NONE;
1520 }
1521
1522 static inline bool
1523 isl_format_has_bc_compression(enum isl_format fmt)
1524 {
1525 switch (isl_format_get_layout(fmt)->txc) {
1526 case ISL_TXC_DXT1:
1527 case ISL_TXC_DXT3:
1528 case ISL_TXC_DXT5:
1529 return true;
1530 case ISL_TXC_NONE:
1531 case ISL_TXC_FXT1:
1532 case ISL_TXC_RGTC1:
1533 case ISL_TXC_RGTC2:
1534 case ISL_TXC_BPTC:
1535 case ISL_TXC_ETC1:
1536 case ISL_TXC_ETC2:
1537 case ISL_TXC_ASTC:
1538 return false;
1539
1540 case ISL_TXC_HIZ:
1541 case ISL_TXC_MCS:
1542 case ISL_TXC_CCS:
1543 unreachable("Should not be called on an aux surface");
1544 }
1545
1546 unreachable("bad texture compression mode");
1547 return false;
1548 }
1549
1550 static inline bool
1551 isl_format_is_yuv(enum isl_format fmt)
1552 {
1553 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1554
1555 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1556 }
1557
1558 static inline bool
1559 isl_format_block_is_1x1x1(enum isl_format fmt)
1560 {
1561 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1562
1563 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1564 }
1565
1566 static inline bool
1567 isl_format_is_srgb(enum isl_format fmt)
1568 {
1569 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1570 }
1571
1572 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1573
1574 static inline bool
1575 isl_format_is_rgb(enum isl_format fmt)
1576 {
1577 if (isl_format_is_yuv(fmt))
1578 return false;
1579
1580 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1581
1582 return fmtl->channels.r.bits > 0 &&
1583 fmtl->channels.g.bits > 0 &&
1584 fmtl->channels.b.bits > 0 &&
1585 fmtl->channels.a.bits == 0;
1586 }
1587
1588 static inline bool
1589 isl_format_is_rgbx(enum isl_format fmt)
1590 {
1591 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1592
1593 return fmtl->channels.r.bits > 0 &&
1594 fmtl->channels.g.bits > 0 &&
1595 fmtl->channels.b.bits > 0 &&
1596 fmtl->channels.a.bits > 0 &&
1597 fmtl->channels.a.type == ISL_VOID;
1598 }
1599
1600 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1601 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1602 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1603
1604 void isl_color_value_pack(const union isl_color_value *value,
1605 enum isl_format format,
1606 uint32_t *data_out);
1607 void isl_color_value_unpack(union isl_color_value *value,
1608 enum isl_format format,
1609 const uint32_t *data_in);
1610
1611 bool isl_is_storage_image_format(enum isl_format fmt);
1612
1613 enum isl_format
1614 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1615 enum isl_format fmt);
1616
1617 /* Returns true if this hardware supports typed load/store on a format with
1618 * the same size as the given format.
1619 */
1620 bool
1621 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1622 enum isl_format fmt);
1623
1624 static inline bool
1625 isl_tiling_is_any_y(enum isl_tiling tiling)
1626 {
1627 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1628 }
1629
1630 static inline bool
1631 isl_tiling_is_std_y(enum isl_tiling tiling)
1632 {
1633 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1634 }
1635
1636 uint32_t
1637 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1638
1639 enum isl_tiling
1640 isl_tiling_from_i915_tiling(uint32_t tiling);
1641
1642 static inline bool
1643 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
1644 {
1645 return usage == ISL_AUX_USAGE_CCS_D ||
1646 usage == ISL_AUX_USAGE_CCS_E;
1647 }
1648
1649 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1650 isl_drm_modifier_get_info(uint64_t modifier);
1651
1652 static inline bool
1653 isl_drm_modifier_has_aux(uint64_t modifier)
1654 {
1655 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1656 }
1657
1658 /** Returns the default isl_aux_state for the given modifier.
1659 *
1660 * If we have a modifier which supports compression, then the auxiliary data
1661 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1662 * can be in any of the following:
1663 *
1664 * - ISL_AUX_STATE_CLEAR
1665 * - ISL_AUX_STATE_PARTIAL_CLEAR
1666 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1667 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1668 * - ISL_AUX_STATE_RESOLVED
1669 * - ISL_AUX_STATE_PASS_THROUGH
1670 *
1671 * If the modifier does not support fast-clears, then we are guaranteed
1672 * that the surface is at least partially resolved and the first three not
1673 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1674 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1675 * because they are the least common denominator of the set of possible aux
1676 * states and will yield a valid interpretation of the aux data.
1677 *
1678 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1679 */
1680 static inline enum isl_aux_state
1681 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1682 {
1683 const struct isl_drm_modifier_info *mod_info =
1684 isl_drm_modifier_get_info(modifier);
1685
1686 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1687 return ISL_AUX_STATE_AUX_INVALID;
1688
1689 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1690 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1691 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1692 }
1693
1694 struct isl_extent2d ATTRIBUTE_CONST
1695 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1696
1697 static inline bool
1698 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1699 {
1700 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1701 }
1702
1703 static inline bool
1704 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1705 {
1706 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1707 }
1708
1709 static inline bool
1710 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1711 {
1712 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1713 }
1714
1715 static inline bool
1716 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1717 {
1718 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1719 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1720 }
1721
1722 static inline bool
1723 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1724 {
1725 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1726 }
1727
1728 static inline bool
1729 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1730 {
1731 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1732 (info->format == ISL_FORMAT_R16_UNORM);
1733 }
1734
1735 static inline bool
1736 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1737 {
1738 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1739 (info->format == ISL_FORMAT_R32_FLOAT);
1740 }
1741
1742 static inline struct isl_extent2d
1743 isl_extent2d(uint32_t width, uint32_t height)
1744 {
1745 struct isl_extent2d e = { { 0 } };
1746
1747 e.width = width;
1748 e.height = height;
1749
1750 return e;
1751 }
1752
1753 static inline struct isl_extent3d
1754 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1755 {
1756 struct isl_extent3d e = { { 0 } };
1757
1758 e.width = width;
1759 e.height = height;
1760 e.depth = depth;
1761
1762 return e;
1763 }
1764
1765 static inline struct isl_extent4d
1766 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1767 uint32_t array_len)
1768 {
1769 struct isl_extent4d e = { { 0 } };
1770
1771 e.width = width;
1772 e.height = height;
1773 e.depth = depth;
1774 e.array_len = array_len;
1775
1776 return e;
1777 }
1778
1779 bool isl_color_value_is_zero(union isl_color_value value,
1780 enum isl_format format);
1781
1782 bool isl_color_value_is_zero_one(union isl_color_value value,
1783 enum isl_format format);
1784
1785 static inline bool
1786 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1787 {
1788 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1789 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1790 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1791 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1792 }
1793
1794 bool
1795 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1796 struct isl_swizzle swizzle);
1797
1798 struct isl_swizzle
1799 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
1800 struct isl_swizzle
1801 isl_swizzle_invert(struct isl_swizzle swizzle);
1802
1803 #define isl_surf_init(dev, surf, ...) \
1804 isl_surf_init_s((dev), (surf), \
1805 &(struct isl_surf_init_info) { __VA_ARGS__ });
1806
1807 bool
1808 isl_surf_init_s(const struct isl_device *dev,
1809 struct isl_surf *surf,
1810 const struct isl_surf_init_info *restrict info);
1811
1812 void
1813 isl_surf_get_tile_info(const struct isl_surf *surf,
1814 struct isl_tile_info *tile_info);
1815
1816 bool
1817 isl_surf_get_hiz_surf(const struct isl_device *dev,
1818 const struct isl_surf *surf,
1819 struct isl_surf *hiz_surf);
1820
1821 bool
1822 isl_surf_get_mcs_surf(const struct isl_device *dev,
1823 const struct isl_surf *surf,
1824 struct isl_surf *mcs_surf);
1825
1826 bool
1827 isl_surf_get_ccs_surf(const struct isl_device *dev,
1828 const struct isl_surf *surf,
1829 struct isl_surf *ccs_surf,
1830 uint32_t row_pitch_B /**< Ignored if 0 */);
1831
1832 #define isl_surf_fill_state(dev, state, ...) \
1833 isl_surf_fill_state_s((dev), (state), \
1834 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1835
1836 void
1837 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1838 const struct isl_surf_fill_state_info *restrict info);
1839
1840 #define isl_buffer_fill_state(dev, state, ...) \
1841 isl_buffer_fill_state_s((dev), (state), \
1842 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1843
1844 void
1845 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1846 const struct isl_buffer_fill_state_info *restrict info);
1847
1848 void
1849 isl_null_fill_state(const struct isl_device *dev, void *state,
1850 struct isl_extent3d size);
1851
1852 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1853 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1854 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1855
1856 void
1857 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
1858 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1859
1860 void
1861 isl_surf_fill_image_param(const struct isl_device *dev,
1862 struct brw_image_param *param,
1863 const struct isl_surf *surf,
1864 const struct isl_view *view);
1865
1866 void
1867 isl_buffer_fill_image_param(const struct isl_device *dev,
1868 struct brw_image_param *param,
1869 enum isl_format format,
1870 uint64_t size);
1871
1872 /**
1873 * Alignment of the upper-left sample of each subimage, in units of surface
1874 * elements.
1875 */
1876 static inline struct isl_extent3d
1877 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1878 {
1879 return surf->image_alignment_el;
1880 }
1881
1882 /**
1883 * Alignment of the upper-left sample of each subimage, in units of surface
1884 * samples.
1885 */
1886 static inline struct isl_extent3d
1887 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1888 {
1889 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1890
1891 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1892 fmtl->bh * surf->image_alignment_el.h,
1893 fmtl->bd * surf->image_alignment_el.d);
1894 }
1895
1896 /**
1897 * Logical extent of level 0 in units of surface elements.
1898 */
1899 static inline struct isl_extent4d
1900 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
1901 {
1902 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1903
1904 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
1905 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
1906 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
1907 surf->logical_level0_px.a);
1908 }
1909
1910 /**
1911 * Physical extent of level 0 in units of surface elements.
1912 */
1913 static inline struct isl_extent4d
1914 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
1915 {
1916 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1917
1918 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
1919 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
1920 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
1921 surf->phys_level0_sa.a);
1922 }
1923
1924 /**
1925 * Pitch between vertically adjacent surface elements, in bytes.
1926 */
1927 static inline uint32_t
1928 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
1929 {
1930 return surf->row_pitch_B;
1931 }
1932
1933 /**
1934 * Pitch between vertically adjacent surface elements, in units of surface elements.
1935 */
1936 static inline uint32_t
1937 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1938 {
1939 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1940
1941 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
1942 return surf->row_pitch_B / (fmtl->bpb / 8);
1943 }
1944
1945 /**
1946 * Pitch between physical array slices, in rows of surface elements.
1947 */
1948 static inline uint32_t
1949 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1950 {
1951 return surf->array_pitch_el_rows;
1952 }
1953
1954 /**
1955 * Pitch between physical array slices, in units of surface elements.
1956 */
1957 static inline uint32_t
1958 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1959 {
1960 return isl_surf_get_array_pitch_el_rows(surf) *
1961 isl_surf_get_row_pitch_el(surf);
1962 }
1963
1964 /**
1965 * Pitch between physical array slices, in rows of surface samples.
1966 */
1967 static inline uint32_t
1968 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1969 {
1970 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1971 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1972 }
1973
1974 /**
1975 * Pitch between physical array slices, in bytes.
1976 */
1977 static inline uint32_t
1978 isl_surf_get_array_pitch(const struct isl_surf *surf)
1979 {
1980 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
1981 }
1982
1983 /**
1984 * Calculate the offset, in units of surface samples, to a subimage in the
1985 * surface.
1986 *
1987 * @invariant level < surface levels
1988 * @invariant logical_array_layer < logical array length of surface
1989 * @invariant logical_z_offset_px < logical depth of surface at level
1990 */
1991 void
1992 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1993 uint32_t level,
1994 uint32_t logical_array_layer,
1995 uint32_t logical_z_offset_px,
1996 uint32_t *x_offset_sa,
1997 uint32_t *y_offset_sa);
1998
1999 /**
2000 * Calculate the offset, in units of surface elements, to a subimage in the
2001 * surface.
2002 *
2003 * @invariant level < surface levels
2004 * @invariant logical_array_layer < logical array length of surface
2005 * @invariant logical_z_offset_px < logical depth of surface at level
2006 */
2007 void
2008 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2009 uint32_t level,
2010 uint32_t logical_array_layer,
2011 uint32_t logical_z_offset_px,
2012 uint32_t *x_offset_el,
2013 uint32_t *y_offset_el);
2014
2015 /**
2016 * Calculate the offset, in bytes and intratile surface samples, to a
2017 * subimage in the surface.
2018 *
2019 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2020 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2021 * offsets to samples.
2022 *
2023 * @invariant level < surface levels
2024 * @invariant logical_array_layer < logical array length of surface
2025 * @invariant logical_z_offset_px < logical depth of surface at level
2026 */
2027 void
2028 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2029 uint32_t level,
2030 uint32_t logical_array_layer,
2031 uint32_t logical_z_offset_px,
2032 uint32_t *offset_B,
2033 uint32_t *x_offset_sa,
2034 uint32_t *y_offset_sa);
2035
2036 /**
2037 * Create an isl_surf that represents a particular subimage in the surface.
2038 *
2039 * The newly created surface will have a single miplevel and array slice. The
2040 * surface lives at the returned byte and intratile offsets, in samples.
2041 *
2042 * It is safe to call this function with surf == image_surf.
2043 *
2044 * @invariant level < surface levels
2045 * @invariant logical_array_layer < logical array length of surface
2046 * @invariant logical_z_offset_px < logical depth of surface at level
2047 */
2048 void
2049 isl_surf_get_image_surf(const struct isl_device *dev,
2050 const struct isl_surf *surf,
2051 uint32_t level,
2052 uint32_t logical_array_layer,
2053 uint32_t logical_z_offset_px,
2054 struct isl_surf *image_surf,
2055 uint32_t *offset_B,
2056 uint32_t *x_offset_sa,
2057 uint32_t *y_offset_sa);
2058
2059 /**
2060 * @brief Calculate the intratile offsets to a surface.
2061 *
2062 * In @a base_address_offset return the offset from the base of the surface to
2063 * the base address of the first tile of the subimage. In @a x_offset_B and
2064 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2065 * tile's base to the subimage's first surface element. The x and y offsets
2066 * are intratile offsets; that is, they do not exceed the boundary of the
2067 * surface's tiling format.
2068 */
2069 void
2070 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2071 uint32_t bpb,
2072 uint32_t row_pitch_B,
2073 uint32_t total_x_offset_el,
2074 uint32_t total_y_offset_el,
2075 uint32_t *base_address_offset,
2076 uint32_t *x_offset_el,
2077 uint32_t *y_offset_el);
2078
2079 static inline void
2080 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2081 enum isl_format format,
2082 uint32_t row_pitch_B,
2083 uint32_t total_x_offset_sa,
2084 uint32_t total_y_offset_sa,
2085 uint32_t *base_address_offset,
2086 uint32_t *x_offset_sa,
2087 uint32_t *y_offset_sa)
2088 {
2089 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2090
2091 /* For computing the intratile offsets, we actually want a strange unit
2092 * which is samples for multisampled surfaces but elements for compressed
2093 * surfaces.
2094 */
2095 assert(total_x_offset_sa % fmtl->bw == 0);
2096 assert(total_y_offset_sa % fmtl->bh == 0);
2097 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2098 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2099
2100 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
2101 total_x_offset, total_y_offset,
2102 base_address_offset,
2103 x_offset_sa, y_offset_sa);
2104 *x_offset_sa *= fmtl->bw;
2105 *y_offset_sa *= fmtl->bh;
2106 }
2107
2108 /**
2109 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2110 *
2111 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2112 * @pre surf->format must be a valid format for depth surfaces
2113 */
2114 uint32_t
2115 isl_surf_get_depth_format(const struct isl_device *dev,
2116 const struct isl_surf *surf);
2117
2118 /**
2119 * @brief performs a copy from linear to tiled surface
2120 *
2121 */
2122 void
2123 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2124 uint32_t yt1, uint32_t yt2,
2125 char *dst, const char *src,
2126 uint32_t dst_pitch, int32_t src_pitch,
2127 bool has_swizzling,
2128 enum isl_tiling tiling,
2129 isl_memcpy_type copy_type);
2130
2131 /**
2132 * @brief performs a copy from tiled to linear surface
2133 *
2134 */
2135 void
2136 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2137 uint32_t yt1, uint32_t yt2,
2138 char *dst, const char *src,
2139 int32_t dst_pitch, uint32_t src_pitch,
2140 bool has_swizzling,
2141 enum isl_tiling tiling,
2142 isl_memcpy_type copy_type);
2143
2144 #ifdef __cplusplus
2145 }
2146 #endif
2147
2148 #endif /* ISL_H */