projects / mesa.git / blob
? search:


2a840f48f72aac68dc0c129fe6e2854f01721e0a
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51
52 struct gen_device_info;
53 struct brw_image_param;
54
55 #ifndef ISL_DEV_GEN
56 /**
57 * @brief Get the hardware generation of isl_device.
58 *
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 */
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #else
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
67 #endif
68
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
71 #endif
72
73 #ifndef ISL_DEV_IS_HASWELL
74 /**
75 * @brief Get the hardware generation of isl_device.
76 *
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 */
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
81 #endif
82
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
85 #endif
86
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 /**
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 */
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #else
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
97 #endif
98
99 /**
100 * Hardware enumeration SURFACE_FORMAT.
101 *
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
104 */
105 enum isl_format {
106 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
107 ISL_FORMAT_R32G32B32A32_SINT = 1,
108 ISL_FORMAT_R32G32B32A32_UINT = 2,
109 ISL_FORMAT_R32G32B32A32_UNORM = 3,
110 ISL_FORMAT_R32G32B32A32_SNORM = 4,
111 ISL_FORMAT_R64G64_FLOAT = 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
114 ISL_FORMAT_R32G32B32A32_USCALED = 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
116 ISL_FORMAT_R64G64_PASSTHRU = 33,
117 ISL_FORMAT_R32G32B32_FLOAT = 64,
118 ISL_FORMAT_R32G32B32_SINT = 65,
119 ISL_FORMAT_R32G32B32_UINT = 66,
120 ISL_FORMAT_R32G32B32_UNORM = 67,
121 ISL_FORMAT_R32G32B32_SNORM = 68,
122 ISL_FORMAT_R32G32B32_SSCALED = 69,
123 ISL_FORMAT_R32G32B32_USCALED = 70,
124 ISL_FORMAT_R32G32B32_SFIXED = 80,
125 ISL_FORMAT_R16G16B16A16_UNORM = 128,
126 ISL_FORMAT_R16G16B16A16_SNORM = 129,
127 ISL_FORMAT_R16G16B16A16_SINT = 130,
128 ISL_FORMAT_R16G16B16A16_UINT = 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
130 ISL_FORMAT_R32G32_FLOAT = 133,
131 ISL_FORMAT_R32G32_SINT = 134,
132 ISL_FORMAT_R32G32_UINT = 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
135 ISL_FORMAT_L32A32_FLOAT = 138,
136 ISL_FORMAT_R32G32_UNORM = 139,
137 ISL_FORMAT_R32G32_SNORM = 140,
138 ISL_FORMAT_R64_FLOAT = 141,
139 ISL_FORMAT_R16G16B16X16_UNORM = 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
141 ISL_FORMAT_A32X32_FLOAT = 144,
142 ISL_FORMAT_L32X32_FLOAT = 145,
143 ISL_FORMAT_I32X32_FLOAT = 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
145 ISL_FORMAT_R16G16B16A16_USCALED = 148,
146 ISL_FORMAT_R32G32_SSCALED = 149,
147 ISL_FORMAT_R32G32_USCALED = 150,
148 ISL_FORMAT_R32G32_FLOAT_LD = 151,
149 ISL_FORMAT_R32G32_SFIXED = 160,
150 ISL_FORMAT_R64_PASSTHRU = 161,
151 ISL_FORMAT_B8G8R8A8_UNORM = 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
153 ISL_FORMAT_R10G10B10A2_UNORM = 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
155 ISL_FORMAT_R10G10B10A2_UINT = 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
157 ISL_FORMAT_R8G8B8A8_UNORM = 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
159 ISL_FORMAT_R8G8B8A8_SNORM = 201,
160 ISL_FORMAT_R8G8B8A8_SINT = 202,
161 ISL_FORMAT_R8G8B8A8_UINT = 203,
162 ISL_FORMAT_R16G16_UNORM = 204,
163 ISL_FORMAT_R16G16_SNORM = 205,
164 ISL_FORMAT_R16G16_SINT = 206,
165 ISL_FORMAT_R16G16_UINT = 207,
166 ISL_FORMAT_R16G16_FLOAT = 208,
167 ISL_FORMAT_B10G10R10A2_UNORM = 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
169 ISL_FORMAT_R11G11B10_FLOAT = 211,
170 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
171 ISL_FORMAT_R32_SINT = 214,
172 ISL_FORMAT_R32_UINT = 215,
173 ISL_FORMAT_R32_FLOAT = 216,
174 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
175 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
176 ISL_FORMAT_L32_UNORM = 221,
177 ISL_FORMAT_A32_UNORM = 222,
178 ISL_FORMAT_L16A16_UNORM = 223,
179 ISL_FORMAT_I24X8_UNORM = 224,
180 ISL_FORMAT_L24X8_UNORM = 225,
181 ISL_FORMAT_A24X8_UNORM = 226,
182 ISL_FORMAT_I32_FLOAT = 227,
183 ISL_FORMAT_L32_FLOAT = 228,
184 ISL_FORMAT_A32_FLOAT = 229,
185 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
186 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
187 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
188 ISL_FORMAT_B8G8R8X8_UNORM = 233,
189 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
190 ISL_FORMAT_R8G8B8X8_UNORM = 235,
191 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
192 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
193 ISL_FORMAT_B10G10R10X2_UNORM = 238,
194 ISL_FORMAT_L16A16_FLOAT = 240,
195 ISL_FORMAT_R32_UNORM = 241,
196 ISL_FORMAT_R32_SNORM = 242,
197 ISL_FORMAT_R10G10B10X2_USCALED = 243,
198 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
199 ISL_FORMAT_R8G8B8A8_USCALED = 245,
200 ISL_FORMAT_R16G16_SSCALED = 246,
201 ISL_FORMAT_R16G16_USCALED = 247,
202 ISL_FORMAT_R32_SSCALED = 248,
203 ISL_FORMAT_R32_USCALED = 249,
204 ISL_FORMAT_B5G6R5_UNORM = 256,
205 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
206 ISL_FORMAT_B5G5R5A1_UNORM = 258,
207 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
208 ISL_FORMAT_B4G4R4A4_UNORM = 260,
209 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
210 ISL_FORMAT_R8G8_UNORM = 262,
211 ISL_FORMAT_R8G8_SNORM = 263,
212 ISL_FORMAT_R8G8_SINT = 264,
213 ISL_FORMAT_R8G8_UINT = 265,
214 ISL_FORMAT_R16_UNORM = 266,
215 ISL_FORMAT_R16_SNORM = 267,
216 ISL_FORMAT_R16_SINT = 268,
217 ISL_FORMAT_R16_UINT = 269,
218 ISL_FORMAT_R16_FLOAT = 270,
219 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
220 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
221 ISL_FORMAT_I16_UNORM = 273,
222 ISL_FORMAT_L16_UNORM = 274,
223 ISL_FORMAT_A16_UNORM = 275,
224 ISL_FORMAT_L8A8_UNORM = 276,
225 ISL_FORMAT_I16_FLOAT = 277,
226 ISL_FORMAT_L16_FLOAT = 278,
227 ISL_FORMAT_A16_FLOAT = 279,
228 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
229 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
230 ISL_FORMAT_B5G5R5X1_UNORM = 282,
231 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
232 ISL_FORMAT_R8G8_SSCALED = 284,
233 ISL_FORMAT_R8G8_USCALED = 285,
234 ISL_FORMAT_R16_SSCALED = 286,
235 ISL_FORMAT_R16_USCALED = 287,
236 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
237 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
238 ISL_FORMAT_A1B5G5R5_UNORM = 292,
239 ISL_FORMAT_A4B4G4R4_UNORM = 293,
240 ISL_FORMAT_L8A8_UINT = 294,
241 ISL_FORMAT_L8A8_SINT = 295,
242 ISL_FORMAT_R8_UNORM = 320,
243 ISL_FORMAT_R8_SNORM = 321,
244 ISL_FORMAT_R8_SINT = 322,
245 ISL_FORMAT_R8_UINT = 323,
246 ISL_FORMAT_A8_UNORM = 324,
247 ISL_FORMAT_I8_UNORM = 325,
248 ISL_FORMAT_L8_UNORM = 326,
249 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
250 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
251 ISL_FORMAT_R8_SSCALED = 329,
252 ISL_FORMAT_R8_USCALED = 330,
253 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
254 ISL_FORMAT_L8_UNORM_SRGB = 332,
255 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
256 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
257 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
258 ISL_FORMAT_Y8_UNORM = 336,
259 ISL_FORMAT_L8_UINT = 338,
260 ISL_FORMAT_L8_SINT = 339,
261 ISL_FORMAT_I8_UINT = 340,
262 ISL_FORMAT_I8_SINT = 341,
263 ISL_FORMAT_DXT1_RGB_SRGB = 384,
264 ISL_FORMAT_R1_UNORM = 385,
265 ISL_FORMAT_YCRCB_NORMAL = 386,
266 ISL_FORMAT_YCRCB_SWAPUVY = 387,
267 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
268 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
269 ISL_FORMAT_BC1_UNORM = 390,
270 ISL_FORMAT_BC2_UNORM = 391,
271 ISL_FORMAT_BC3_UNORM = 392,
272 ISL_FORMAT_BC4_UNORM = 393,
273 ISL_FORMAT_BC5_UNORM = 394,
274 ISL_FORMAT_BC1_UNORM_SRGB = 395,
275 ISL_FORMAT_BC2_UNORM_SRGB = 396,
276 ISL_FORMAT_BC3_UNORM_SRGB = 397,
277 ISL_FORMAT_MONO8 = 398,
278 ISL_FORMAT_YCRCB_SWAPUV = 399,
279 ISL_FORMAT_YCRCB_SWAPY = 400,
280 ISL_FORMAT_DXT1_RGB = 401,
281 ISL_FORMAT_FXT1 = 402,
282 ISL_FORMAT_R8G8B8_UNORM = 403,
283 ISL_FORMAT_R8G8B8_SNORM = 404,
284 ISL_FORMAT_R8G8B8_SSCALED = 405,
285 ISL_FORMAT_R8G8B8_USCALED = 406,
286 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
287 ISL_FORMAT_R64G64B64_FLOAT = 408,
288 ISL_FORMAT_BC4_SNORM = 409,
289 ISL_FORMAT_BC5_SNORM = 410,
290 ISL_FORMAT_R16G16B16_FLOAT = 411,
291 ISL_FORMAT_R16G16B16_UNORM = 412,
292 ISL_FORMAT_R16G16B16_SNORM = 413,
293 ISL_FORMAT_R16G16B16_SSCALED = 414,
294 ISL_FORMAT_R16G16B16_USCALED = 415,
295 ISL_FORMAT_BC6H_SF16 = 417,
296 ISL_FORMAT_BC7_UNORM = 418,
297 ISL_FORMAT_BC7_UNORM_SRGB = 419,
298 ISL_FORMAT_BC6H_UF16 = 420,
299 ISL_FORMAT_PLANAR_420_8 = 421,
300 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
301 ISL_FORMAT_ETC1_RGB8 = 425,
302 ISL_FORMAT_ETC2_RGB8 = 426,
303 ISL_FORMAT_EAC_R11 = 427,
304 ISL_FORMAT_EAC_RG11 = 428,
305 ISL_FORMAT_EAC_SIGNED_R11 = 429,
306 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
307 ISL_FORMAT_ETC2_SRGB8 = 431,
308 ISL_FORMAT_R16G16B16_UINT = 432,
309 ISL_FORMAT_R16G16B16_SINT = 433,
310 ISL_FORMAT_R32_SFIXED = 434,
311 ISL_FORMAT_R10G10B10A2_SNORM = 435,
312 ISL_FORMAT_R10G10B10A2_USCALED = 436,
313 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
314 ISL_FORMAT_R10G10B10A2_SINT = 438,
315 ISL_FORMAT_B10G10R10A2_SNORM = 439,
316 ISL_FORMAT_B10G10R10A2_USCALED = 440,
317 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
318 ISL_FORMAT_B10G10R10A2_UINT = 442,
319 ISL_FORMAT_B10G10R10A2_SINT = 443,
320 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
321 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
322 ISL_FORMAT_ETC2_RGB8_PTA = 448,
323 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
324 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
325 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
326 ISL_FORMAT_R8G8B8_UINT = 456,
327 ISL_FORMAT_R8G8B8_SINT = 457,
328 ISL_FORMAT_RAW = 511,
329 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
330 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
331 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
332 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
333 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
334 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
335 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
336 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
337 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
338 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
339 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
340 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
341 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
342 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
343 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
344 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
345 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
346 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
347 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
348 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
349 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
350 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
351 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
352 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
353 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
354 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
355 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
356 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
357 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
358 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
359 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
360 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
361 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
362 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
363 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
364 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
365 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
366 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
367 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
368 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
369 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
370 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
371
372 /* The formats that follow are internal to ISL and as such don't have an
373 * explicit number. We'll just let the C compiler assign it for us. Any
374 * actual hardware formats *must* come before these in the list.
375 */
376
377 /* Formats for auxiliary surfaces */
378 ISL_FORMAT_HIZ,
379 ISL_FORMAT_MCS_2X,
380 ISL_FORMAT_MCS_4X,
381 ISL_FORMAT_MCS_8X,
382 ISL_FORMAT_MCS_16X,
383 ISL_FORMAT_GEN7_CCS_32BPP_X,
384 ISL_FORMAT_GEN7_CCS_64BPP_X,
385 ISL_FORMAT_GEN7_CCS_128BPP_X,
386 ISL_FORMAT_GEN7_CCS_32BPP_Y,
387 ISL_FORMAT_GEN7_CCS_64BPP_Y,
388 ISL_FORMAT_GEN7_CCS_128BPP_Y,
389 ISL_FORMAT_GEN9_CCS_32BPP,
390 ISL_FORMAT_GEN9_CCS_64BPP,
391 ISL_FORMAT_GEN9_CCS_128BPP,
392 ISL_FORMAT_GEN12_CCS_8BPP_Y0,
393 ISL_FORMAT_GEN12_CCS_16BPP_Y0,
394 ISL_FORMAT_GEN12_CCS_32BPP_Y0,
395 ISL_FORMAT_GEN12_CCS_64BPP_Y0,
396 ISL_FORMAT_GEN12_CCS_128BPP_Y0,
397
398 /* An upper bound on the supported format enumerations */
399 ISL_NUM_FORMATS,
400
401 /* Hardware doesn't understand this out-of-band value */
402 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
403 };
404
405 /**
406 * Numerical base type for channels of isl_format.
407 */
408 enum isl_base_type {
409 ISL_VOID,
410 ISL_RAW,
411 ISL_UNORM,
412 ISL_SNORM,
413 ISL_UFLOAT,
414 ISL_SFLOAT,
415 ISL_UFIXED,
416 ISL_SFIXED,
417 ISL_UINT,
418 ISL_SINT,
419 ISL_USCALED,
420 ISL_SSCALED,
421 };
422
423 /**
424 * Colorspace of isl_format.
425 */
426 enum isl_colorspace {
427 ISL_COLORSPACE_NONE = 0,
428 ISL_COLORSPACE_LINEAR,
429 ISL_COLORSPACE_SRGB,
430 ISL_COLORSPACE_YUV,
431 };
432
433 /**
434 * Texture compression mode of isl_format.
435 */
436 enum isl_txc {
437 ISL_TXC_NONE = 0,
438 ISL_TXC_DXT1,
439 ISL_TXC_DXT3,
440 ISL_TXC_DXT5,
441 ISL_TXC_FXT1,
442 ISL_TXC_RGTC1,
443 ISL_TXC_RGTC2,
444 ISL_TXC_BPTC,
445 ISL_TXC_ETC1,
446 ISL_TXC_ETC2,
447 ISL_TXC_ASTC,
448
449 /* Used for auxiliary surface formats */
450 ISL_TXC_HIZ,
451 ISL_TXC_MCS,
452 ISL_TXC_CCS,
453 };
454
455 /**
456 * @brief Hardware tile mode
457 *
458 * WARNING: These values differ from the hardware enum values, which are
459 * unstable across hardware generations.
460 *
461 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
462 * clearly distinguish it from Yf and Ys.
463 */
464 enum isl_tiling {
465 ISL_TILING_LINEAR = 0,
466 ISL_TILING_W,
467 ISL_TILING_X,
468 ISL_TILING_Y0, /**< Legacy Y tiling */
469 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
470 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
471 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
472 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
473 ISL_TILING_GEN12_CCS, /**< Tiling format for Gen12 CCS surfaces */
474 };
475
476 /**
477 * @defgroup Tiling Flags
478 * @{
479 */
480 typedef uint32_t isl_tiling_flags_t;
481 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
482 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
483 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
484 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
485 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
486 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
487 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
488 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
489 #define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
490 #define ISL_TILING_ANY_MASK (~0u)
491 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
492
493 /** Any Y tiling, including legacy Y tiling. */
494 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
495 ISL_TILING_Yf_BIT | \
496 ISL_TILING_Ys_BIT)
497
498 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
499 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
500 ISL_TILING_Ys_BIT)
501 /** @} */
502
503 /**
504 * @brief Logical dimension of surface.
505 *
506 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
507 * as 2D array surfaces.
508 */
509 enum isl_surf_dim {
510 ISL_SURF_DIM_1D,
511 ISL_SURF_DIM_2D,
512 ISL_SURF_DIM_3D,
513 };
514
515 /**
516 * @brief Physical layout of the surface's dimensions.
517 */
518 enum isl_dim_layout {
519 /**
520 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
521 * 6.17.3: 2D Surfaces.
522 *
523 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
524 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
525 *
526 * One-dimensional surfaces are identical to 2D surfaces with height of
527 * one.
528 *
529 * @invariant isl_surf::phys_level0_sa::depth == 1
530 */
531 ISL_DIM_LAYOUT_GEN4_2D,
532
533 /**
534 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
535 * 6.17.5: 3D Surfaces.
536 *
537 * @invariant isl_surf::phys_level0_sa::array_len == 1
538 */
539 ISL_DIM_LAYOUT_GEN4_3D,
540
541 /**
542 * Special layout used for HiZ and stencil on Sandy Bridge to work around
543 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
544 * work the same as on gen7+ except that they don't technically support
545 * mipmapping. That does not, however, stop us from doing it. As far as
546 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
547 * single miplevel 2D (possibly array) image. The dimensions of that image
548 * are NOT minified.
549 *
550 * In order to implement HiZ and stencil on Sandy Bridge, we create one
551 * full-sized 2D (possibly array) image for every LOD with every image
552 * aligned to a page boundary. When the surface is used with the stencil
553 * or HiZ hardware, we manually offset to the image for the given LOD.
554 *
555 * As a memory saving measure, we pretend that the width of each miplevel
556 * is minified and we place LOD1 and above below LOD0 but horizontally
557 * adjacent to each other. When considered as full-sized images, LOD1 and
558 * above technically overlap. However, since we only write to part of that
559 * image, the hardware will never notice the overlap.
560 *
561 * This layout looks something like this:
562 *
563 * +---------+
564 * | |
565 * | |
566 * +---------+
567 * | |
568 * | |
569 * +---------+
570 *
571 * +----+ +-+ .
572 * | | +-+
573 * +----+
574 *
575 * +----+ +-+ .
576 * | | +-+
577 * +----+
578 */
579 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
580
581 /**
582 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
583 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
584 */
585 ISL_DIM_LAYOUT_GEN9_1D,
586 };
587
588 enum isl_aux_usage {
589 /** No Auxiliary surface is used */
590 ISL_AUX_USAGE_NONE,
591
592 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
593 ISL_AUX_USAGE_HIZ,
594
595 /** The auxiliary surface is an MCS
596 *
597 * @invariant isl_surf::samples > 1
598 */
599 ISL_AUX_USAGE_MCS,
600
601 /** The auxiliary surface is a fast-clear-only compression surface
602 *
603 * @invariant isl_surf::samples == 1
604 */
605 ISL_AUX_USAGE_CCS_D,
606
607 /** The auxiliary surface provides full lossless color compression
608 *
609 * @invariant isl_surf::samples == 1
610 */
611 ISL_AUX_USAGE_CCS_E,
612
613 /** The auxiliary surface provides full lossless media color compression
614 *
615 * @invariant isl_surf::samples == 1
616 */
617 ISL_AUX_USAGE_MC,
618
619 /** The auxiliary surface is a HiZ surface and CCS is also enabled */
620 ISL_AUX_USAGE_HIZ_CCS,
621
622 /** The auxiliary surface is an MCS and CCS is also enabled
623 *
624 * @invariant isl_surf::samples > 1
625 */
626 ISL_AUX_USAGE_MCS_CCS,
627 };
628
629 /**
630 * Enum for keeping track of the state an auxiliary compressed surface.
631 *
632 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
633 * given slice (lod + array layer) can be in one of the six states described
634 * by this enum. Draw and resolve operations may cause the slice to change
635 * from one state to another. The six valid states are:
636 *
637 * 1) Clear: In this state, each block in the auxiliary surface contains a
638 * magic value that indicates that the block is in the clear state. If
639 * a block is in the clear state, it's values in the primary surface are
640 * ignored and the color of the samples in the block is taken either the
641 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
642 * depth. Since neither the primary surface nor the auxiliary surface
643 * contains the clear value, the surface can be cleared to a different
644 * color by simply changing the clear color without modifying either
645 * surface.
646 *
647 * 2) Partial Clear: In this state, each block in the auxiliary surface
648 * contains either the magic clear or pass-through value. See Clear and
649 * Pass-through for more details.
650 *
651 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
652 * nor the primary surface has a complete representation of the data.
653 * Instead, both surfaces must be used together or else rendering
654 * corruption may occur. Depending on the auxiliary compression format
655 * and the data, any given block in the primary surface may contain all,
656 * some, or none of the data required to reconstruct the actual sample
657 * values. Blocks may also be in the clear state (see Clear) and have
658 * their value taken from outside the surface.
659 *
660 * 4) Compressed w/o Clear: This state is identical to the state above
661 * except that no blocks are in the clear state. In this state, all of
662 * the data required to reconstruct the final sample values is contained
663 * in the auxiliary and primary surface and the clear value is not
664 * considered.
665 *
666 * 5) Resolved: In this state, the primary surface contains 100% of the
667 * data. The auxiliary surface is also valid so the surface can be
668 * validly used with or without aux enabled. The auxiliary surface may,
669 * however, contain non-trivial data and any update to the primary
670 * surface with aux disabled will cause the two to get out of sync.
671 *
672 * 6) Pass-through: In this state, the primary surface contains 100% of the
673 * data and every block in the auxiliary surface contains a magic value
674 * which indicates that the auxiliary surface should be ignored and the
675 * only the primary surface should be considered. Updating the primary
676 * surface without aux works fine and can be done repeatedly in this
677 * mode. Writing to a surface in pass-through mode with aux enabled may
678 * cause the auxiliary buffer to contain non-trivial data and no longer
679 * be in the pass-through state.
680 *
681 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
682 * data and the auxiliary surface is completely bogus. Any attempt to
683 * use the auxiliary surface is liable to result in rendering
684 * corruption. The only thing that one can do to re-enable aux once
685 * this state is reached is to use an ambiguate pass to transition into
686 * the pass-through state.
687 *
688 * Drawing with or without aux enabled may implicitly cause the surface to
689 * transition between these states. There are also four types of auxiliary
690 * compression operations which cause an explicit transition which are
691 * described by the isl_aux_op enum below.
692 *
693 * Not all operations are valid or useful in all states. The diagram below
694 * contains a complete description of the states and all valid and useful
695 * transitions except clear.
696 *
697 * Draw w/ Aux
698 * +----------+
699 * | |
700 * | +-------------+ Draw w/ Aux +-------------+
701 * +------>| Compressed |<-------------------| Clear |
702 * | w/ Clear |----->----+ | |
703 * +-------------+ | +-------------+
704 * | /|\ | | |
705 * | | | | |
706 * | | +------<-----+ | Draw w/
707 * | | | | Clear Only
708 * | | Full | | +----------+
709 * Partial | | Resolve | \|/ | |
710 * Resolve | | | +-------------+ |
711 * | | | | Partial |<------+
712 * | | | | Clear |<----------+
713 * | | | +-------------+ |
714 * | | | | |
715 * | | +------>---------+ Full |
716 * | | | Resolve |
717 * Draw w/ aux | | Partial Fast Clear | |
718 * +----------+ | +--------------------------+ | |
719 * | | \|/ | \|/ |
720 * | +-------------+ Full Resolve +-------------+ |
721 * +------>| Compressed |------------------->| Resolved | |
722 * | w/o Clear |<-------------------| | |
723 * +-------------+ Draw w/ Aux +-------------+ |
724 * /|\ | | |
725 * | Draw | | Draw |
726 * | w/ Aux | | w/o Aux |
727 * | Ambiguate | | |
728 * | +--------------------------+ | |
729 * Draw w/o Aux | | | Draw w/o Aux |
730 * +----------+ | | | +----------+ |
731 * | | | \|/ \|/ | | |
732 * | +-------------+ Ambiguate +-------------+ | |
733 * +------>| Pass- |<-------------------| Aux |<------+ |
734 * +------>| through | | Invalid | |
735 * | +-------------+ +-------------+ |
736 * | | | |
737 * +----------+ +-----------------------------------------------------+
738 * Draw w/ Partial Fast Clear
739 * Clear Only
740 *
741 *
742 * While the above general theory applies to all forms of auxiliary
743 * compression on Intel hardware, not all states and operations are available
744 * on all compression types. However, each of the auxiliary states and
745 * operations can be fairly easily mapped onto the above diagram:
746 *
747 * HiZ: Hierarchical depth compression is capable of being in any of the
748 * states above. Hardware provides three HiZ operations: "Depth
749 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
750 * Clear", "Full Resolve", and "Ambiguate" respectively. The
751 * hardware provides no HiZ partial resolve operation so the only way
752 * to get into the "Compressed w/o Clear" state is to render with HiZ
753 * when the surface is in the resolved or pass-through states.
754 *
755 * MCS: Multisample compression is technically capable of being in any of
756 * the states above except that most of them aren't useful. Both the
757 * render engine and the sampler support MCS compression and, apart
758 * from clear color, MCS is format-unaware so we leave the surface
759 * compressed 100% of the time. The hardware provides no MCS
760 * operations.
761 *
762 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
763 * the simplest forms of compression since they don't do anything
764 * beyond clear color tracking. They really only support three of
765 * the six states: Clear, Partial Clear, and Pass-through. The
766 * only CCS_D operation is "Resolve" which maps to a full resolve
767 * followed by an ambiguate.
768 *
769 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
770 * is capable of being in almost all of the above states. THe only
771 * exception is that it does not have separate resolved and pass-
772 * through states. Instead, the CCS_E full resolve operation does
773 * both a resolve and an ambiguate so it goes directly into the
774 * pass-through state. CCS_E also provides fast clear and partial
775 * resolve operations which work as described above.
776 *
777 * While it is technically possible to perform a CCS_E ambiguate, it
778 * is not provided by Sky Lake hardware so we choose to avoid the aux
779 * invalid state. If the aux invalid state were determined to be
780 * useful, a CCS ambiguate could be done by carefully rendering to
781 * the CCS and filling it with zeros.
782 */
783 enum isl_aux_state {
784 ISL_AUX_STATE_CLEAR = 0,
785 ISL_AUX_STATE_PARTIAL_CLEAR,
786 ISL_AUX_STATE_COMPRESSED_CLEAR,
787 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
788 ISL_AUX_STATE_RESOLVED,
789 ISL_AUX_STATE_PASS_THROUGH,
790 ISL_AUX_STATE_AUX_INVALID,
791 };
792
793 /**
794 * Enum which describes explicit aux transition operations.
795 */
796 enum isl_aux_op {
797 ISL_AUX_OP_NONE,
798
799 /** Fast Clear
800 *
801 * This operation writes the magic "clear" value to the auxiliary surface.
802 * This operation will safely transition any slice of a surface from any
803 * state to the clear state so long as the entire slice is fast cleared at
804 * once. A fast clear that only covers part of a slice of a surface is
805 * called a partial fast clear.
806 */
807 ISL_AUX_OP_FAST_CLEAR,
808
809 /** Full Resolve
810 *
811 * This operation combines the auxiliary surface data with the primary
812 * surface data and writes the result to the primary. For HiZ, the docs
813 * call this a depth resolve. For CCS, the hardware full resolve operation
814 * does both a full resolve and an ambiguate so it actually takes you all
815 * the way to the pass-through state.
816 */
817 ISL_AUX_OP_FULL_RESOLVE,
818
819 /** Partial Resolve
820 *
821 * This operation considers blocks which are in the "clear" state and
822 * writes the clear value directly into the primary or auxiliary surface.
823 * Once this operation completes, the surface is still compressed but no
824 * longer references the clear color. This operation is only available
825 * for CCS_E.
826 */
827 ISL_AUX_OP_PARTIAL_RESOLVE,
828
829 /** Ambiguate
830 *
831 * This operation throws away the current auxiliary data and replaces it
832 * with the magic pass-through value. If an ambiguate operation is
833 * performed when the primary surface does not contain 100% of the data,
834 * data will be lost. This operation is only implemented in hardware for
835 * depth where it is called a HiZ resolve.
836 */
837 ISL_AUX_OP_AMBIGUATE,
838 };
839
840 /* TODO(chadv): Explain */
841 enum isl_array_pitch_span {
842 ISL_ARRAY_PITCH_SPAN_FULL,
843 ISL_ARRAY_PITCH_SPAN_COMPACT,
844 };
845
846 /**
847 * @defgroup Surface Usage
848 * @{
849 */
850 typedef uint64_t isl_surf_usage_flags_t;
851 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
852 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
853 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
854 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
855 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
856 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
857 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
858 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
859 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
860 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
861 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
862 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
863 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
864 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
865 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
866 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
867 /** @} */
868
869 /**
870 * @defgroup Channel Mask
871 *
872 * These #define values are chosen to match the values of
873 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
874 *
875 * @{
876 */
877 typedef uint8_t isl_channel_mask_t;
878 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
879 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
880 #define ISL_CHANNEL_RED_BIT (1 << 2)
881 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
882 /** @} */
883
884 /**
885 * @brief A channel select (also known as texture swizzle) value
886 */
887 enum PACKED isl_channel_select {
888 ISL_CHANNEL_SELECT_ZERO = 0,
889 ISL_CHANNEL_SELECT_ONE = 1,
890 ISL_CHANNEL_SELECT_RED = 4,
891 ISL_CHANNEL_SELECT_GREEN = 5,
892 ISL_CHANNEL_SELECT_BLUE = 6,
893 ISL_CHANNEL_SELECT_ALPHA = 7,
894 };
895
896 /**
897 * Identical to VkSampleCountFlagBits.
898 */
899 enum isl_sample_count {
900 ISL_SAMPLE_COUNT_1_BIT = 1u,
901 ISL_SAMPLE_COUNT_2_BIT = 2u,
902 ISL_SAMPLE_COUNT_4_BIT = 4u,
903 ISL_SAMPLE_COUNT_8_BIT = 8u,
904 ISL_SAMPLE_COUNT_16_BIT = 16u,
905 };
906 typedef uint32_t isl_sample_count_mask_t;
907
908 /**
909 * @brief Multisample Format
910 */
911 enum isl_msaa_layout {
912 /**
913 * @brief Suface is single-sampled.
914 */
915 ISL_MSAA_LAYOUT_NONE,
916
917 /**
918 * @brief [SNB+] Interleaved Multisample Format
919 *
920 * In this format, multiple samples are interleaved into each cacheline.
921 * In other words, the sample index is swizzled into the low 6 bits of the
922 * surface's virtual address space.
923 *
924 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
925 * and its pixel format is 32bpp. Then the first cacheline is arranged
926 * thus:
927 *
928 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
929 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
930 *
931 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
932 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
933 *
934 * The hardware docs refer to this format with multiple terms. In
935 * Sandybridge, this is the only multisample format; so no term is used.
936 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
937 * Multisample Surface). Later hardware docs additionally refer to this
938 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
939 * color surfaces).
940 *
941 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
942 * Surface Behavior".
943 *
944 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
945 * Multisampled Surfaces".
946 */
947 ISL_MSAA_LAYOUT_INTERLEAVED,
948
949 /**
950 * @brief [IVB+] Array Multisample Format
951 *
952 * In this format, the surface's physical layout resembles that of a
953 * 2D array surface.
954 *
955 * Suppose the multisample surface's logical extent is (w, h) and its
956 * sample count is N. Then surface's physical extent is the same as
957 * a singlesample 2D surface whose logical extent is (w, h) and array
958 * length is N. Array slice `i` contains the pixel values for sample
959 * index `i`.
960 *
961 * The Ivybridge docs refer to surfaces in this format as UMS
962 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
963 * Surface). The Broadwell docs additionally refer to this format as
964 * MSFMT_MSS (MSS=Multisample Surface Storage).
965 *
966 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
967 * Multisample Surfaces".
968 *
969 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
970 * Multisample Surfaces".
971 */
972 ISL_MSAA_LAYOUT_ARRAY,
973 };
974
975 typedef enum {
976 ISL_MEMCPY = 0,
977 ISL_MEMCPY_BGRA8,
978 ISL_MEMCPY_STREAMING_LOAD,
979 ISL_MEMCPY_INVALID,
980 } isl_memcpy_type;
981
982 struct isl_device {
983 const struct gen_device_info *info;
984 bool use_separate_stencil;
985 bool has_bit6_swizzling;
986
987 /**
988 * Describes the layout of a RENDER_SURFACE_STATE structure for the
989 * current gen.
990 */
991 struct {
992 uint8_t size;
993 uint8_t align;
994 uint8_t addr_offset;
995 uint8_t aux_addr_offset;
996
997 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
998
999 /* size of the state buffer used to store the clear color + extra
1000 * additional space used by the hardware */
1001 uint8_t clear_color_state_size;
1002 uint8_t clear_color_state_offset;
1003 /* size of the clear color itself - used to copy it to/from a BO */
1004 uint8_t clear_value_size;
1005 uint8_t clear_value_offset;
1006 } ss;
1007
1008 /**
1009 * Describes the layout of the depth/stencil/hiz commands as emitted by
1010 * isl_emit_depth_stencil_hiz.
1011 */
1012 struct {
1013 uint8_t size;
1014 uint8_t depth_offset;
1015 uint8_t stencil_offset;
1016 uint8_t hiz_offset;
1017 } ds;
1018 };
1019
1020 struct isl_extent2d {
1021 union { uint32_t w, width; };
1022 union { uint32_t h, height; };
1023 };
1024
1025 struct isl_extent3d {
1026 union { uint32_t w, width; };
1027 union { uint32_t h, height; };
1028 union { uint32_t d, depth; };
1029 };
1030
1031 struct isl_extent4d {
1032 union { uint32_t w, width; };
1033 union { uint32_t h, height; };
1034 union { uint32_t d, depth; };
1035 union { uint32_t a, array_len; };
1036 };
1037
1038 struct isl_channel_layout {
1039 enum isl_base_type type;
1040 uint8_t start_bit; /**< Bit at which this channel starts */
1041 uint8_t bits; /**< Size in bits */
1042 };
1043
1044 /**
1045 * Each format has 3D block extent (width, height, depth). The block extent of
1046 * compressed formats is that of the format's compression block. For example,
1047 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1048 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1049 * is (w=1, h=1, d=1).
1050 */
1051 struct isl_format_layout {
1052 enum isl_format format;
1053 const char *name;
1054
1055 uint16_t bpb; /**< Bits per block */
1056 uint8_t bw; /**< Block width, in pixels */
1057 uint8_t bh; /**< Block height, in pixels */
1058 uint8_t bd; /**< Block depth, in pixels */
1059
1060 union {
1061 struct {
1062 struct isl_channel_layout r; /**< Red channel */
1063 struct isl_channel_layout g; /**< Green channel */
1064 struct isl_channel_layout b; /**< Blue channel */
1065 struct isl_channel_layout a; /**< Alpha channel */
1066 struct isl_channel_layout l; /**< Luminance channel */
1067 struct isl_channel_layout i; /**< Intensity channel */
1068 struct isl_channel_layout p; /**< Palette channel */
1069 } channels;
1070 struct isl_channel_layout channels_array[7];
1071 };
1072
1073 enum isl_colorspace colorspace;
1074 enum isl_txc txc;
1075 };
1076
1077 struct isl_tile_info {
1078 enum isl_tiling tiling;
1079
1080 /* The size (in bits per block) of a single surface element
1081 *
1082 * For surfaces with power-of-two formats, this is the same as
1083 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1084 * The logical_extent_el field is in terms of elements of this size.
1085 *
1086 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1087 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1088 * of the tiling formats can actually hold an integer number of 96-bit
1089 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1090 * 32-bit element size. It is the responsibility of the caller to
1091 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1092 * the width of a surface in tiles, you would do:
1093 *
1094 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1095 * tile_info.logical_extent_el.width);
1096 */
1097 uint32_t format_bpb;
1098
1099 /** The logical size of the tile in units of format_bpb size elements
1100 *
1101 * This field determines how a given surface is cut up into tiles. It is
1102 * used to compute the size of a surface in tiles and can be used to
1103 * determine the location of the tile containing any given surface element.
1104 * The exact value of this field depends heavily on the bits-per-block of
1105 * the format being used.
1106 */
1107 struct isl_extent2d logical_extent_el;
1108
1109 /** The physical size of the tile in bytes and rows of bytes
1110 *
1111 * This field determines how the tiles of a surface are physically layed
1112 * out in memory. The logical and physical tile extent are frequently the
1113 * same but this is not always the case. For instance, a W-tile (which is
1114 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1115 * its physical size is 128B x 32rows, the same as a Y-tile.
1116 *
1117 * @see isl_surf::row_pitch_B
1118 */
1119 struct isl_extent2d phys_extent_B;
1120 };
1121
1122 /**
1123 * Metadata about a DRM format modifier.
1124 */
1125 struct isl_drm_modifier_info {
1126 uint64_t modifier;
1127
1128 /** Text name of the modifier */
1129 const char *name;
1130
1131 /** ISL tiling implied by this modifier */
1132 enum isl_tiling tiling;
1133
1134 /** ISL aux usage implied by this modifier */
1135 enum isl_aux_usage aux_usage;
1136
1137 /** Whether or not this modifier supports clear color */
1138 bool supports_clear_color;
1139 };
1140
1141 /**
1142 * @brief Input to surface initialization
1143 *
1144 * @invariant width >= 1
1145 * @invariant height >= 1
1146 * @invariant depth >= 1
1147 * @invariant levels >= 1
1148 * @invariant samples >= 1
1149 * @invariant array_len >= 1
1150 *
1151 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1152 * @invariant if 2D then depth == 1
1153 * @invariant if 3D then array_len == 1 and samples == 1
1154 */
1155 struct isl_surf_init_info {
1156 enum isl_surf_dim dim;
1157 enum isl_format format;
1158
1159 uint32_t width;
1160 uint32_t height;
1161 uint32_t depth;
1162 uint32_t levels;
1163 uint32_t array_len;
1164 uint32_t samples;
1165
1166 /** Lower bound for isl_surf::alignment, in bytes. */
1167 uint32_t min_alignment_B;
1168
1169 /**
1170 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1171 * will fail if this is misaligned or out of bounds.
1172 */
1173 uint32_t row_pitch_B;
1174
1175 isl_surf_usage_flags_t usage;
1176
1177 /** Flags that alter how ISL selects isl_surf::tiling. */
1178 isl_tiling_flags_t tiling_flags;
1179 };
1180
1181 struct isl_surf {
1182 enum isl_surf_dim dim;
1183 enum isl_dim_layout dim_layout;
1184 enum isl_msaa_layout msaa_layout;
1185 enum isl_tiling tiling;
1186 enum isl_format format;
1187
1188 /**
1189 * Alignment of the upper-left sample of each subimage, in units of surface
1190 * elements.
1191 */
1192 struct isl_extent3d image_alignment_el;
1193
1194 /**
1195 * Logical extent of the surface's base level, in units of pixels. This is
1196 * identical to the extent defined in isl_surf_init_info.
1197 */
1198 struct isl_extent4d logical_level0_px;
1199
1200 /**
1201 * Physical extent of the surface's base level, in units of physical
1202 * surface samples.
1203 *
1204 * Consider isl_dim_layout as an operator that transforms a logical surface
1205 * layout to a physical surface layout. Then
1206 *
1207 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1208 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1209 */
1210 struct isl_extent4d phys_level0_sa;
1211
1212 uint32_t levels;
1213 uint32_t samples;
1214
1215 /** Total size of the surface, in bytes. */
1216 uint64_t size_B;
1217
1218 /** Required alignment for the surface's base address. */
1219 uint32_t alignment_B;
1220
1221 /**
1222 * The interpretation of this field depends on the value of
1223 * isl_tile_info::physical_extent_B. In particular, the width of the
1224 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1225 * and the distance in bytes between vertically adjacent tiles in the image
1226 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1227 *
1228 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1229 * this cleanly reduces to being the distance, in bytes, between vertically
1230 * adjacent surface elements.
1231 *
1232 * @see isl_tile_info::phys_extent_B;
1233 */
1234 uint32_t row_pitch_B;
1235
1236 /**
1237 * Pitch between physical array slices, in rows of surface elements.
1238 */
1239 uint32_t array_pitch_el_rows;
1240
1241 enum isl_array_pitch_span array_pitch_span;
1242
1243 /** Copy of isl_surf_init_info::usage. */
1244 isl_surf_usage_flags_t usage;
1245 };
1246
1247 struct isl_swizzle {
1248 enum isl_channel_select r:4;
1249 enum isl_channel_select g:4;
1250 enum isl_channel_select b:4;
1251 enum isl_channel_select a:4;
1252 };
1253
1254 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1255 .r = ISL_CHANNEL_SELECT_##R, \
1256 .g = ISL_CHANNEL_SELECT_##G, \
1257 .b = ISL_CHANNEL_SELECT_##B, \
1258 .a = ISL_CHANNEL_SELECT_##A, \
1259 })
1260
1261 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1262
1263 struct isl_view {
1264 /**
1265 * Indicates the usage of the particular view
1266 *
1267 * Normally, this is one bit. However, for a cube map texture, it
1268 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1269 */
1270 isl_surf_usage_flags_t usage;
1271
1272 /**
1273 * The format to use in the view
1274 *
1275 * This may differ from the format of the actual isl_surf but must have
1276 * the same block size.
1277 */
1278 enum isl_format format;
1279
1280 uint32_t base_level;
1281 uint32_t levels;
1282
1283 /**
1284 * Base array layer
1285 *
1286 * For cube maps, both base_array_layer and array_len should be
1287 * specified in terms of 2-D layers and must be a multiple of 6.
1288 *
1289 * 3-D textures are effectively treated as 2-D arrays when used as a
1290 * storage image or render target. If `usage` contains
1291 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1292 * base_array_layer and array_len are applied. If the surface is only used
1293 * for texturing, they are ignored.
1294 */
1295 uint32_t base_array_layer;
1296
1297 /**
1298 * Array Length
1299 *
1300 * Indicates the number of array elements starting at Base Array Layer.
1301 */
1302 uint32_t array_len;
1303
1304 struct isl_swizzle swizzle;
1305 };
1306
1307 union isl_color_value {
1308 float f32[4];
1309 uint32_t u32[4];
1310 int32_t i32[4];
1311 };
1312
1313 struct isl_surf_fill_state_info {
1314 const struct isl_surf *surf;
1315 const struct isl_view *view;
1316
1317 /**
1318 * The address of the surface in GPU memory.
1319 */
1320 uint64_t address;
1321
1322 /**
1323 * The Memory Object Control state for the filled surface state.
1324 *
1325 * The exact format of this value depends on hardware generation.
1326 */
1327 uint32_t mocs;
1328
1329 /**
1330 * The auxilary surface or NULL if no auxilary surface is to be used.
1331 */
1332 const struct isl_surf *aux_surf;
1333 enum isl_aux_usage aux_usage;
1334 uint64_t aux_address;
1335
1336 /**
1337 * The clear color for this surface
1338 *
1339 * Valid values depend on hardware generation.
1340 */
1341 union isl_color_value clear_color;
1342
1343 /**
1344 * Send only the clear value address
1345 *
1346 * If set, we only pass the clear address to the GPU and it will fetch it
1347 * from wherever it is.
1348 */
1349 bool use_clear_address;
1350 uint64_t clear_address;
1351
1352 /**
1353 * Surface write disables for gen4-5
1354 */
1355 isl_channel_mask_t write_disables;
1356
1357 /* Intra-tile offset */
1358 uint16_t x_offset_sa, y_offset_sa;
1359 };
1360
1361 struct isl_buffer_fill_state_info {
1362 /**
1363 * The address of the surface in GPU memory.
1364 */
1365 uint64_t address;
1366
1367 /**
1368 * The size of the buffer
1369 */
1370 uint64_t size_B;
1371
1372 /**
1373 * The Memory Object Control state for the filled surface state.
1374 *
1375 * The exact format of this value depends on hardware generation.
1376 */
1377 uint32_t mocs;
1378
1379 /**
1380 * The format to use in the surface state
1381 *
1382 * This may differ from the format of the actual isl_surf but have the
1383 * same block size.
1384 */
1385 enum isl_format format;
1386
1387 /**
1388 * The swizzle to use in the surface state
1389 */
1390 struct isl_swizzle swizzle;
1391
1392 uint32_t stride_B;
1393 };
1394
1395 struct isl_depth_stencil_hiz_emit_info {
1396 /**
1397 * The depth surface
1398 */
1399 const struct isl_surf *depth_surf;
1400
1401 /**
1402 * The stencil surface
1403 *
1404 * If separate stencil is not available, this must point to the same
1405 * isl_surf as depth_surf.
1406 */
1407 const struct isl_surf *stencil_surf;
1408
1409 /**
1410 * The view into the depth and stencil surfaces.
1411 *
1412 * This view applies to both surfaces simultaneously.
1413 */
1414 const struct isl_view *view;
1415
1416 /**
1417 * The address of the depth surface in GPU memory
1418 */
1419 uint64_t depth_address;
1420
1421 /**
1422 * The address of the stencil surface in GPU memory
1423 *
1424 * If separate stencil is not available, this must have the same value as
1425 * depth_address.
1426 */
1427 uint64_t stencil_address;
1428
1429 /**
1430 * The Memory Object Control state for depth and stencil buffers
1431 *
1432 * Both depth and stencil will get the same MOCS value. The exact format
1433 * of this value depends on hardware generation.
1434 */
1435 uint32_t mocs;
1436
1437 /**
1438 * The HiZ surface or NULL if HiZ is disabled.
1439 */
1440 const struct isl_surf *hiz_surf;
1441 enum isl_aux_usage hiz_usage;
1442 uint64_t hiz_address;
1443
1444 /**
1445 * The depth clear value
1446 */
1447 float depth_clear_value;
1448 };
1449
1450 extern const struct isl_format_layout isl_format_layouts[];
1451
1452 void
1453 isl_device_init(struct isl_device *dev,
1454 const struct gen_device_info *info,
1455 bool has_bit6_swizzling);
1456
1457 isl_sample_count_mask_t ATTRIBUTE_CONST
1458 isl_device_get_sample_counts(struct isl_device *dev);
1459
1460 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1461 isl_format_get_layout(enum isl_format fmt)
1462 {
1463 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1464 assert(fmt < ISL_NUM_FORMATS);
1465 return &isl_format_layouts[fmt];
1466 }
1467
1468 bool isl_format_is_valid(enum isl_format);
1469
1470 static inline const char * ATTRIBUTE_CONST
1471 isl_format_get_name(enum isl_format fmt)
1472 {
1473 return isl_format_get_layout(fmt)->name;
1474 }
1475
1476 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1477 enum isl_format format);
1478 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1479 enum isl_format format);
1480 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1481 enum isl_format format);
1482 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1483 enum isl_format format);
1484 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1485 enum isl_format format);
1486 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1487 enum isl_format format);
1488 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1489 enum isl_format format);
1490 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1491 enum isl_format format);
1492 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1493 enum isl_format format);
1494 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1495 enum isl_format format);
1496
1497 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1498 enum isl_format format1,
1499 enum isl_format format2);
1500
1501 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1502 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1503 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1504 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1505 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1506 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1507
1508 static inline bool
1509 isl_format_has_normalized_channel(enum isl_format fmt)
1510 {
1511 return isl_format_has_unorm_channel(fmt) ||
1512 isl_format_has_snorm_channel(fmt);
1513 }
1514
1515 static inline bool
1516 isl_format_has_float_channel(enum isl_format fmt)
1517 {
1518 return isl_format_has_ufloat_channel(fmt) ||
1519 isl_format_has_sfloat_channel(fmt);
1520 }
1521
1522 static inline bool
1523 isl_format_has_int_channel(enum isl_format fmt)
1524 {
1525 return isl_format_has_uint_channel(fmt) ||
1526 isl_format_has_sint_channel(fmt);
1527 }
1528
1529 bool isl_format_has_color_component(enum isl_format fmt,
1530 int component) ATTRIBUTE_CONST;
1531
1532 unsigned isl_format_get_num_channels(enum isl_format fmt);
1533
1534 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1535
1536 static inline bool
1537 isl_format_is_compressed(enum isl_format fmt)
1538 {
1539 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1540
1541 return fmtl->txc != ISL_TXC_NONE;
1542 }
1543
1544 static inline bool
1545 isl_format_has_bc_compression(enum isl_format fmt)
1546 {
1547 switch (isl_format_get_layout(fmt)->txc) {
1548 case ISL_TXC_DXT1:
1549 case ISL_TXC_DXT3:
1550 case ISL_TXC_DXT5:
1551 return true;
1552 case ISL_TXC_NONE:
1553 case ISL_TXC_FXT1:
1554 case ISL_TXC_RGTC1:
1555 case ISL_TXC_RGTC2:
1556 case ISL_TXC_BPTC:
1557 case ISL_TXC_ETC1:
1558 case ISL_TXC_ETC2:
1559 case ISL_TXC_ASTC:
1560 return false;
1561
1562 case ISL_TXC_HIZ:
1563 case ISL_TXC_MCS:
1564 case ISL_TXC_CCS:
1565 unreachable("Should not be called on an aux surface");
1566 }
1567
1568 unreachable("bad texture compression mode");
1569 return false;
1570 }
1571
1572 static inline bool
1573 isl_format_is_yuv(enum isl_format fmt)
1574 {
1575 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1576
1577 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1578 }
1579
1580 static inline bool
1581 isl_format_block_is_1x1x1(enum isl_format fmt)
1582 {
1583 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1584
1585 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1586 }
1587
1588 static inline bool
1589 isl_format_is_srgb(enum isl_format fmt)
1590 {
1591 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1592 }
1593
1594 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1595
1596 static inline bool
1597 isl_format_is_rgb(enum isl_format fmt)
1598 {
1599 if (isl_format_is_yuv(fmt))
1600 return false;
1601
1602 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1603
1604 return fmtl->channels.r.bits > 0 &&
1605 fmtl->channels.g.bits > 0 &&
1606 fmtl->channels.b.bits > 0 &&
1607 fmtl->channels.a.bits == 0;
1608 }
1609
1610 static inline bool
1611 isl_format_is_rgbx(enum isl_format fmt)
1612 {
1613 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1614
1615 return fmtl->channels.r.bits > 0 &&
1616 fmtl->channels.g.bits > 0 &&
1617 fmtl->channels.b.bits > 0 &&
1618 fmtl->channels.a.bits > 0 &&
1619 fmtl->channels.a.type == ISL_VOID;
1620 }
1621
1622 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1623 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1624 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1625
1626 void isl_color_value_pack(const union isl_color_value *value,
1627 enum isl_format format,
1628 uint32_t *data_out);
1629 void isl_color_value_unpack(union isl_color_value *value,
1630 enum isl_format format,
1631 const uint32_t *data_in);
1632
1633 bool isl_is_storage_image_format(enum isl_format fmt);
1634
1635 enum isl_format
1636 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1637 enum isl_format fmt);
1638
1639 /* Returns true if this hardware supports typed load/store on a format with
1640 * the same size as the given format.
1641 */
1642 bool
1643 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1644 enum isl_format fmt);
1645
1646 static inline enum isl_tiling
1647 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
1648 {
1649 assert(__builtin_popcount(flag) == 1);
1650 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
1651 }
1652
1653 static inline bool
1654 isl_tiling_is_any_y(enum isl_tiling tiling)
1655 {
1656 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1657 }
1658
1659 static inline bool
1660 isl_tiling_is_std_y(enum isl_tiling tiling)
1661 {
1662 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1663 }
1664
1665 uint32_t
1666 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1667
1668 enum isl_tiling
1669 isl_tiling_from_i915_tiling(uint32_t tiling);
1670
1671 static inline bool
1672 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
1673 {
1674 return usage == ISL_AUX_USAGE_HIZ ||
1675 usage == ISL_AUX_USAGE_HIZ_CCS;
1676 }
1677
1678 static inline bool
1679 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
1680 {
1681 return usage == ISL_AUX_USAGE_MCS ||
1682 usage == ISL_AUX_USAGE_MCS_CCS;
1683 }
1684
1685 static inline bool
1686 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
1687 {
1688 return usage == ISL_AUX_USAGE_CCS_D ||
1689 usage == ISL_AUX_USAGE_CCS_E ||
1690 usage == ISL_AUX_USAGE_MC ||
1691 usage == ISL_AUX_USAGE_HIZ_CCS ||
1692 usage == ISL_AUX_USAGE_MCS_CCS;
1693 }
1694
1695 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1696 isl_drm_modifier_get_info(uint64_t modifier);
1697
1698 static inline bool
1699 isl_drm_modifier_has_aux(uint64_t modifier)
1700 {
1701 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1702 }
1703
1704 /** Returns the default isl_aux_state for the given modifier.
1705 *
1706 * If we have a modifier which supports compression, then the auxiliary data
1707 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1708 * can be in any of the following:
1709 *
1710 * - ISL_AUX_STATE_CLEAR
1711 * - ISL_AUX_STATE_PARTIAL_CLEAR
1712 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1713 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1714 * - ISL_AUX_STATE_RESOLVED
1715 * - ISL_AUX_STATE_PASS_THROUGH
1716 *
1717 * If the modifier does not support fast-clears, then we are guaranteed
1718 * that the surface is at least partially resolved and the first three not
1719 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1720 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1721 * because they are the least common denominator of the set of possible aux
1722 * states and will yield a valid interpretation of the aux data.
1723 *
1724 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1725 */
1726 static inline enum isl_aux_state
1727 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1728 {
1729 const struct isl_drm_modifier_info *mod_info =
1730 isl_drm_modifier_get_info(modifier);
1731
1732 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1733 return ISL_AUX_STATE_AUX_INVALID;
1734
1735 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1736 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1737 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1738 }
1739
1740 struct isl_extent2d ATTRIBUTE_CONST
1741 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1742
1743 static inline bool
1744 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1745 {
1746 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1747 }
1748
1749 static inline bool
1750 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1751 {
1752 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1753 }
1754
1755 static inline bool
1756 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1757 {
1758 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1759 }
1760
1761 static inline bool
1762 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1763 {
1764 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1765 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1766 }
1767
1768 static inline bool
1769 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1770 {
1771 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1772 }
1773
1774 static inline bool
1775 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1776 {
1777 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1778 (info->format == ISL_FORMAT_R16_UNORM);
1779 }
1780
1781 static inline bool
1782 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1783 {
1784 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1785 (info->format == ISL_FORMAT_R32_FLOAT);
1786 }
1787
1788 static inline struct isl_extent2d
1789 isl_extent2d(uint32_t width, uint32_t height)
1790 {
1791 struct isl_extent2d e = { { 0 } };
1792
1793 e.width = width;
1794 e.height = height;
1795
1796 return e;
1797 }
1798
1799 static inline struct isl_extent3d
1800 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1801 {
1802 struct isl_extent3d e = { { 0 } };
1803
1804 e.width = width;
1805 e.height = height;
1806 e.depth = depth;
1807
1808 return e;
1809 }
1810
1811 static inline struct isl_extent4d
1812 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1813 uint32_t array_len)
1814 {
1815 struct isl_extent4d e = { { 0 } };
1816
1817 e.width = width;
1818 e.height = height;
1819 e.depth = depth;
1820 e.array_len = array_len;
1821
1822 return e;
1823 }
1824
1825 bool isl_color_value_is_zero(union isl_color_value value,
1826 enum isl_format format);
1827
1828 bool isl_color_value_is_zero_one(union isl_color_value value,
1829 enum isl_format format);
1830
1831 static inline bool
1832 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1833 {
1834 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1835 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1836 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1837 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1838 }
1839
1840 bool
1841 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1842 struct isl_swizzle swizzle);
1843
1844 struct isl_swizzle
1845 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
1846 struct isl_swizzle
1847 isl_swizzle_invert(struct isl_swizzle swizzle);
1848
1849 #define isl_surf_init(dev, surf, ...) \
1850 isl_surf_init_s((dev), (surf), \
1851 &(struct isl_surf_init_info) { __VA_ARGS__ });
1852
1853 bool
1854 isl_surf_init_s(const struct isl_device *dev,
1855 struct isl_surf *surf,
1856 const struct isl_surf_init_info *restrict info);
1857
1858 void
1859 isl_surf_get_tile_info(const struct isl_surf *surf,
1860 struct isl_tile_info *tile_info);
1861
1862 bool
1863 isl_surf_get_hiz_surf(const struct isl_device *dev,
1864 const struct isl_surf *surf,
1865 struct isl_surf *hiz_surf);
1866
1867 bool
1868 isl_surf_get_mcs_surf(const struct isl_device *dev,
1869 const struct isl_surf *surf,
1870 struct isl_surf *mcs_surf);
1871
1872 bool
1873 isl_surf_get_ccs_surf(const struct isl_device *dev,
1874 const struct isl_surf *surf,
1875 struct isl_surf *ccs_surf,
1876 uint32_t row_pitch_B /**< Ignored if 0 */);
1877
1878 #define isl_surf_fill_state(dev, state, ...) \
1879 isl_surf_fill_state_s((dev), (state), \
1880 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1881
1882 void
1883 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1884 const struct isl_surf_fill_state_info *restrict info);
1885
1886 #define isl_buffer_fill_state(dev, state, ...) \
1887 isl_buffer_fill_state_s((dev), (state), \
1888 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1889
1890 void
1891 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1892 const struct isl_buffer_fill_state_info *restrict info);
1893
1894 void
1895 isl_null_fill_state(const struct isl_device *dev, void *state,
1896 struct isl_extent3d size);
1897
1898 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1899 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1900 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1901
1902 void
1903 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
1904 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1905
1906 void
1907 isl_surf_fill_image_param(const struct isl_device *dev,
1908 struct brw_image_param *param,
1909 const struct isl_surf *surf,
1910 const struct isl_view *view);
1911
1912 void
1913 isl_buffer_fill_image_param(const struct isl_device *dev,
1914 struct brw_image_param *param,
1915 enum isl_format format,
1916 uint64_t size);
1917
1918 /**
1919 * Alignment of the upper-left sample of each subimage, in units of surface
1920 * elements.
1921 */
1922 static inline struct isl_extent3d
1923 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1924 {
1925 return surf->image_alignment_el;
1926 }
1927
1928 /**
1929 * Alignment of the upper-left sample of each subimage, in units of surface
1930 * samples.
1931 */
1932 static inline struct isl_extent3d
1933 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1934 {
1935 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1936
1937 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1938 fmtl->bh * surf->image_alignment_el.h,
1939 fmtl->bd * surf->image_alignment_el.d);
1940 }
1941
1942 /**
1943 * Logical extent of level 0 in units of surface elements.
1944 */
1945 static inline struct isl_extent4d
1946 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
1947 {
1948 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1949
1950 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
1951 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
1952 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
1953 surf->logical_level0_px.a);
1954 }
1955
1956 /**
1957 * Physical extent of level 0 in units of surface elements.
1958 */
1959 static inline struct isl_extent4d
1960 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
1961 {
1962 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1963
1964 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
1965 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
1966 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
1967 surf->phys_level0_sa.a);
1968 }
1969
1970 /**
1971 * Pitch between vertically adjacent surface elements, in bytes.
1972 */
1973 static inline uint32_t
1974 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
1975 {
1976 return surf->row_pitch_B;
1977 }
1978
1979 /**
1980 * Pitch between vertically adjacent surface elements, in units of surface elements.
1981 */
1982 static inline uint32_t
1983 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1984 {
1985 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1986
1987 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
1988 return surf->row_pitch_B / (fmtl->bpb / 8);
1989 }
1990
1991 /**
1992 * Pitch between physical array slices, in rows of surface elements.
1993 */
1994 static inline uint32_t
1995 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1996 {
1997 return surf->array_pitch_el_rows;
1998 }
1999
2000 /**
2001 * Pitch between physical array slices, in units of surface elements.
2002 */
2003 static inline uint32_t
2004 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2005 {
2006 return isl_surf_get_array_pitch_el_rows(surf) *
2007 isl_surf_get_row_pitch_el(surf);
2008 }
2009
2010 /**
2011 * Pitch between physical array slices, in rows of surface samples.
2012 */
2013 static inline uint32_t
2014 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2015 {
2016 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2017 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2018 }
2019
2020 /**
2021 * Pitch between physical array slices, in bytes.
2022 */
2023 static inline uint32_t
2024 isl_surf_get_array_pitch(const struct isl_surf *surf)
2025 {
2026 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2027 }
2028
2029 /**
2030 * Calculate the offset, in units of surface samples, to a subimage in the
2031 * surface.
2032 *
2033 * @invariant level < surface levels
2034 * @invariant logical_array_layer < logical array length of surface
2035 * @invariant logical_z_offset_px < logical depth of surface at level
2036 */
2037 void
2038 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2039 uint32_t level,
2040 uint32_t logical_array_layer,
2041 uint32_t logical_z_offset_px,
2042 uint32_t *x_offset_sa,
2043 uint32_t *y_offset_sa);
2044
2045 /**
2046 * Calculate the offset, in units of surface elements, to a subimage in the
2047 * surface.
2048 *
2049 * @invariant level < surface levels
2050 * @invariant logical_array_layer < logical array length of surface
2051 * @invariant logical_z_offset_px < logical depth of surface at level
2052 */
2053 void
2054 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2055 uint32_t level,
2056 uint32_t logical_array_layer,
2057 uint32_t logical_z_offset_px,
2058 uint32_t *x_offset_el,
2059 uint32_t *y_offset_el);
2060
2061 /**
2062 * Calculate the offset, in bytes and intratile surface samples, to a
2063 * subimage in the surface.
2064 *
2065 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2066 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2067 * offsets to samples.
2068 *
2069 * @invariant level < surface levels
2070 * @invariant logical_array_layer < logical array length of surface
2071 * @invariant logical_z_offset_px < logical depth of surface at level
2072 */
2073 void
2074 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2075 uint32_t level,
2076 uint32_t logical_array_layer,
2077 uint32_t logical_z_offset_px,
2078 uint32_t *offset_B,
2079 uint32_t *x_offset_sa,
2080 uint32_t *y_offset_sa);
2081
2082 /**
2083 * Create an isl_surf that represents a particular subimage in the surface.
2084 *
2085 * The newly created surface will have a single miplevel and array slice. The
2086 * surface lives at the returned byte and intratile offsets, in samples.
2087 *
2088 * It is safe to call this function with surf == image_surf.
2089 *
2090 * @invariant level < surface levels
2091 * @invariant logical_array_layer < logical array length of surface
2092 * @invariant logical_z_offset_px < logical depth of surface at level
2093 */
2094 void
2095 isl_surf_get_image_surf(const struct isl_device *dev,
2096 const struct isl_surf *surf,
2097 uint32_t level,
2098 uint32_t logical_array_layer,
2099 uint32_t logical_z_offset_px,
2100 struct isl_surf *image_surf,
2101 uint32_t *offset_B,
2102 uint32_t *x_offset_sa,
2103 uint32_t *y_offset_sa);
2104
2105 /**
2106 * @brief Calculate the intratile offsets to a surface.
2107 *
2108 * In @a base_address_offset return the offset from the base of the surface to
2109 * the base address of the first tile of the subimage. In @a x_offset_B and
2110 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2111 * tile's base to the subimage's first surface element. The x and y offsets
2112 * are intratile offsets; that is, they do not exceed the boundary of the
2113 * surface's tiling format.
2114 */
2115 void
2116 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2117 uint32_t bpb,
2118 uint32_t row_pitch_B,
2119 uint32_t total_x_offset_el,
2120 uint32_t total_y_offset_el,
2121 uint32_t *base_address_offset,
2122 uint32_t *x_offset_el,
2123 uint32_t *y_offset_el);
2124
2125 static inline void
2126 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2127 enum isl_format format,
2128 uint32_t row_pitch_B,
2129 uint32_t total_x_offset_sa,
2130 uint32_t total_y_offset_sa,
2131 uint32_t *base_address_offset,
2132 uint32_t *x_offset_sa,
2133 uint32_t *y_offset_sa)
2134 {
2135 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2136
2137 /* For computing the intratile offsets, we actually want a strange unit
2138 * which is samples for multisampled surfaces but elements for compressed
2139 * surfaces.
2140 */
2141 assert(total_x_offset_sa % fmtl->bw == 0);
2142 assert(total_y_offset_sa % fmtl->bh == 0);
2143 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2144 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2145
2146 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
2147 total_x_offset, total_y_offset,
2148 base_address_offset,
2149 x_offset_sa, y_offset_sa);
2150 *x_offset_sa *= fmtl->bw;
2151 *y_offset_sa *= fmtl->bh;
2152 }
2153
2154 /**
2155 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2156 *
2157 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2158 * @pre surf->format must be a valid format for depth surfaces
2159 */
2160 uint32_t
2161 isl_surf_get_depth_format(const struct isl_device *dev,
2162 const struct isl_surf *surf);
2163
2164 /**
2165 * @brief performs a copy from linear to tiled surface
2166 *
2167 */
2168 void
2169 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2170 uint32_t yt1, uint32_t yt2,
2171 char *dst, const char *src,
2172 uint32_t dst_pitch, int32_t src_pitch,
2173 bool has_swizzling,
2174 enum isl_tiling tiling,
2175 isl_memcpy_type copy_type);
2176
2177 /**
2178 * @brief performs a copy from tiled to linear surface
2179 *
2180 */
2181 void
2182 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2183 uint32_t yt1, uint32_t yt2,
2184 char *dst, const char *src,
2185 int32_t dst_pitch, uint32_t src_pitch,
2186 bool has_swizzling,
2187 enum isl_tiling tiling,
2188 isl_memcpy_type copy_type);
2189
2190 #ifdef __cplusplus
2191 }
2192 #endif
2193
2194 #endif /* ISL_H */