2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
45 #include "c99_compat.h"
46 #include "util/macros.h"
47 #include "util/format/u_format.h"
53 struct gen_device_info
;
54 struct brw_image_param
;
58 * @brief Get the hardware generation of isl_device.
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
63 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
64 #define ISL_DEV_GEN_SANITIZE(__dev)
66 #define ISL_DEV_GEN_SANITIZE(__dev) \
67 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
70 #ifndef ISL_DEV_IS_G4X
71 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
74 #ifndef ISL_DEV_IS_HASWELL
76 * @brief Get the hardware generation of isl_device.
78 * You can define this as a compile-time constant in the CFLAGS. For example,
79 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
81 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
84 #ifndef ISL_DEV_IS_BAYTRAIL
85 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
88 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
90 * You can define this as a compile-time constant in the CFLAGS. For example,
91 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
93 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
94 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
97 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
101 * Hardware enumeration SURFACE_FORMAT.
103 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
104 * Enumerations: SURFACE_FORMAT.
107 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
108 ISL_FORMAT_R32G32B32A32_SINT
= 1,
109 ISL_FORMAT_R32G32B32A32_UINT
= 2,
110 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
111 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
112 ISL_FORMAT_R64G64_FLOAT
= 5,
113 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
114 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
115 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
116 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
117 ISL_FORMAT_R64G64_PASSTHRU
= 33,
118 ISL_FORMAT_R32G32B32_FLOAT
= 64,
119 ISL_FORMAT_R32G32B32_SINT
= 65,
120 ISL_FORMAT_R32G32B32_UINT
= 66,
121 ISL_FORMAT_R32G32B32_UNORM
= 67,
122 ISL_FORMAT_R32G32B32_SNORM
= 68,
123 ISL_FORMAT_R32G32B32_SSCALED
= 69,
124 ISL_FORMAT_R32G32B32_USCALED
= 70,
125 ISL_FORMAT_R32G32B32_SFIXED
= 80,
126 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
127 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
128 ISL_FORMAT_R16G16B16A16_SINT
= 130,
129 ISL_FORMAT_R16G16B16A16_UINT
= 131,
130 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
131 ISL_FORMAT_R32G32_FLOAT
= 133,
132 ISL_FORMAT_R32G32_SINT
= 134,
133 ISL_FORMAT_R32G32_UINT
= 135,
134 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
135 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
136 ISL_FORMAT_L32A32_FLOAT
= 138,
137 ISL_FORMAT_R32G32_UNORM
= 139,
138 ISL_FORMAT_R32G32_SNORM
= 140,
139 ISL_FORMAT_R64_FLOAT
= 141,
140 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
141 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
142 ISL_FORMAT_A32X32_FLOAT
= 144,
143 ISL_FORMAT_L32X32_FLOAT
= 145,
144 ISL_FORMAT_I32X32_FLOAT
= 146,
145 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
146 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
147 ISL_FORMAT_R32G32_SSCALED
= 149,
148 ISL_FORMAT_R32G32_USCALED
= 150,
149 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
150 ISL_FORMAT_R32G32_SFIXED
= 160,
151 ISL_FORMAT_R64_PASSTHRU
= 161,
152 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
153 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
154 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
155 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
156 ISL_FORMAT_R10G10B10A2_UINT
= 196,
157 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
158 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
159 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
160 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
161 ISL_FORMAT_R8G8B8A8_SINT
= 202,
162 ISL_FORMAT_R8G8B8A8_UINT
= 203,
163 ISL_FORMAT_R16G16_UNORM
= 204,
164 ISL_FORMAT_R16G16_SNORM
= 205,
165 ISL_FORMAT_R16G16_SINT
= 206,
166 ISL_FORMAT_R16G16_UINT
= 207,
167 ISL_FORMAT_R16G16_FLOAT
= 208,
168 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
169 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
170 ISL_FORMAT_R11G11B10_FLOAT
= 211,
171 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM
= 213,
172 ISL_FORMAT_R32_SINT
= 214,
173 ISL_FORMAT_R32_UINT
= 215,
174 ISL_FORMAT_R32_FLOAT
= 216,
175 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
176 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
177 ISL_FORMAT_L32_UNORM
= 221,
178 ISL_FORMAT_A32_UNORM
= 222,
179 ISL_FORMAT_L16A16_UNORM
= 223,
180 ISL_FORMAT_I24X8_UNORM
= 224,
181 ISL_FORMAT_L24X8_UNORM
= 225,
182 ISL_FORMAT_A24X8_UNORM
= 226,
183 ISL_FORMAT_I32_FLOAT
= 227,
184 ISL_FORMAT_L32_FLOAT
= 228,
185 ISL_FORMAT_A32_FLOAT
= 229,
186 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
187 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
188 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
189 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
190 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
191 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
192 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
193 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
194 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
195 ISL_FORMAT_L16A16_FLOAT
= 240,
196 ISL_FORMAT_R32_UNORM
= 241,
197 ISL_FORMAT_R32_SNORM
= 242,
198 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
199 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
200 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
201 ISL_FORMAT_R16G16_SSCALED
= 246,
202 ISL_FORMAT_R16G16_USCALED
= 247,
203 ISL_FORMAT_R32_SSCALED
= 248,
204 ISL_FORMAT_R32_USCALED
= 249,
205 ISL_FORMAT_B5G6R5_UNORM
= 256,
206 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
207 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
208 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
209 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
210 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
211 ISL_FORMAT_R8G8_UNORM
= 262,
212 ISL_FORMAT_R8G8_SNORM
= 263,
213 ISL_FORMAT_R8G8_SINT
= 264,
214 ISL_FORMAT_R8G8_UINT
= 265,
215 ISL_FORMAT_R16_UNORM
= 266,
216 ISL_FORMAT_R16_SNORM
= 267,
217 ISL_FORMAT_R16_SINT
= 268,
218 ISL_FORMAT_R16_UINT
= 269,
219 ISL_FORMAT_R16_FLOAT
= 270,
220 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
221 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
222 ISL_FORMAT_I16_UNORM
= 273,
223 ISL_FORMAT_L16_UNORM
= 274,
224 ISL_FORMAT_A16_UNORM
= 275,
225 ISL_FORMAT_L8A8_UNORM
= 276,
226 ISL_FORMAT_I16_FLOAT
= 277,
227 ISL_FORMAT_L16_FLOAT
= 278,
228 ISL_FORMAT_A16_FLOAT
= 279,
229 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
230 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
231 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
232 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
233 ISL_FORMAT_R8G8_SSCALED
= 284,
234 ISL_FORMAT_R8G8_USCALED
= 285,
235 ISL_FORMAT_R16_SSCALED
= 286,
236 ISL_FORMAT_R16_USCALED
= 287,
237 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
238 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
239 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
240 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
241 ISL_FORMAT_L8A8_UINT
= 294,
242 ISL_FORMAT_L8A8_SINT
= 295,
243 ISL_FORMAT_R8_UNORM
= 320,
244 ISL_FORMAT_R8_SNORM
= 321,
245 ISL_FORMAT_R8_SINT
= 322,
246 ISL_FORMAT_R8_UINT
= 323,
247 ISL_FORMAT_A8_UNORM
= 324,
248 ISL_FORMAT_I8_UNORM
= 325,
249 ISL_FORMAT_L8_UNORM
= 326,
250 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
251 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
252 ISL_FORMAT_R8_SSCALED
= 329,
253 ISL_FORMAT_R8_USCALED
= 330,
254 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
255 ISL_FORMAT_L8_UNORM_SRGB
= 332,
256 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
257 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
258 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
259 ISL_FORMAT_Y8_UNORM
= 336,
260 ISL_FORMAT_L8_UINT
= 338,
261 ISL_FORMAT_L8_SINT
= 339,
262 ISL_FORMAT_I8_UINT
= 340,
263 ISL_FORMAT_I8_SINT
= 341,
264 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
265 ISL_FORMAT_R1_UNORM
= 385,
266 ISL_FORMAT_YCRCB_NORMAL
= 386,
267 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
268 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
269 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
270 ISL_FORMAT_BC1_UNORM
= 390,
271 ISL_FORMAT_BC2_UNORM
= 391,
272 ISL_FORMAT_BC3_UNORM
= 392,
273 ISL_FORMAT_BC4_UNORM
= 393,
274 ISL_FORMAT_BC5_UNORM
= 394,
275 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
276 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
277 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
278 ISL_FORMAT_MONO8
= 398,
279 ISL_FORMAT_YCRCB_SWAPUV
= 399,
280 ISL_FORMAT_YCRCB_SWAPY
= 400,
281 ISL_FORMAT_DXT1_RGB
= 401,
282 ISL_FORMAT_FXT1
= 402,
283 ISL_FORMAT_R8G8B8_UNORM
= 403,
284 ISL_FORMAT_R8G8B8_SNORM
= 404,
285 ISL_FORMAT_R8G8B8_SSCALED
= 405,
286 ISL_FORMAT_R8G8B8_USCALED
= 406,
287 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
288 ISL_FORMAT_R64G64B64_FLOAT
= 408,
289 ISL_FORMAT_BC4_SNORM
= 409,
290 ISL_FORMAT_BC5_SNORM
= 410,
291 ISL_FORMAT_R16G16B16_FLOAT
= 411,
292 ISL_FORMAT_R16G16B16_UNORM
= 412,
293 ISL_FORMAT_R16G16B16_SNORM
= 413,
294 ISL_FORMAT_R16G16B16_SSCALED
= 414,
295 ISL_FORMAT_R16G16B16_USCALED
= 415,
296 ISL_FORMAT_BC6H_SF16
= 417,
297 ISL_FORMAT_BC7_UNORM
= 418,
298 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
299 ISL_FORMAT_BC6H_UF16
= 420,
300 ISL_FORMAT_PLANAR_420_8
= 421,
301 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
302 ISL_FORMAT_ETC1_RGB8
= 425,
303 ISL_FORMAT_ETC2_RGB8
= 426,
304 ISL_FORMAT_EAC_R11
= 427,
305 ISL_FORMAT_EAC_RG11
= 428,
306 ISL_FORMAT_EAC_SIGNED_R11
= 429,
307 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
308 ISL_FORMAT_ETC2_SRGB8
= 431,
309 ISL_FORMAT_R16G16B16_UINT
= 432,
310 ISL_FORMAT_R16G16B16_SINT
= 433,
311 ISL_FORMAT_R32_SFIXED
= 434,
312 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
313 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
314 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
315 ISL_FORMAT_R10G10B10A2_SINT
= 438,
316 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
317 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
318 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
319 ISL_FORMAT_B10G10R10A2_UINT
= 442,
320 ISL_FORMAT_B10G10R10A2_SINT
= 443,
321 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
322 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
323 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
324 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
325 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
326 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
327 ISL_FORMAT_R8G8B8_UINT
= 456,
328 ISL_FORMAT_R8G8B8_SINT
= 457,
329 ISL_FORMAT_RAW
= 511,
330 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
331 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
332 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
333 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
334 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
335 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
336 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
337 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
338 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
339 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
340 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
341 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
342 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
343 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
344 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
345 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
346 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
347 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
348 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
349 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
350 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
351 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
352 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
353 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
354 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
355 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
356 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
357 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
358 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16
= 832,
359 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16
= 840,
360 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16
= 841,
361 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16
= 849,
362 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16
= 850,
363 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16
= 865,
364 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16
= 866,
365 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16
= 868,
366 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16
= 881,
367 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16
= 882,
368 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16
= 884,
369 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16
= 886,
370 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16
= 894,
371 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16
= 895,
373 /* The formats that follow are internal to ISL and as such don't have an
374 * explicit number. We'll just let the C compiler assign it for us. Any
375 * actual hardware formats *must* come before these in the list.
378 /* Formats for auxiliary surfaces */
384 ISL_FORMAT_GEN7_CCS_32BPP_X
,
385 ISL_FORMAT_GEN7_CCS_64BPP_X
,
386 ISL_FORMAT_GEN7_CCS_128BPP_X
,
387 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
388 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
389 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
390 ISL_FORMAT_GEN9_CCS_32BPP
,
391 ISL_FORMAT_GEN9_CCS_64BPP
,
392 ISL_FORMAT_GEN9_CCS_128BPP
,
393 ISL_FORMAT_GEN12_CCS_8BPP_Y0
,
394 ISL_FORMAT_GEN12_CCS_16BPP_Y0
,
395 ISL_FORMAT_GEN12_CCS_32BPP_Y0
,
396 ISL_FORMAT_GEN12_CCS_64BPP_Y0
,
397 ISL_FORMAT_GEN12_CCS_128BPP_Y0
,
399 /* An upper bound on the supported format enumerations */
402 /* Hardware doesn't understand this out-of-band value */
403 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
407 * Numerical base type for channels of isl_format.
425 * Colorspace of isl_format.
427 enum isl_colorspace
{
428 ISL_COLORSPACE_NONE
= 0,
429 ISL_COLORSPACE_LINEAR
,
435 * Texture compression mode of isl_format.
450 /* Used for auxiliary surface formats */
457 * @brief Hardware tile mode
459 * WARNING: These values differ from the hardware enum values, which are
460 * unstable across hardware generations.
462 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
463 * clearly distinguish it from Yf and Ys.
466 ISL_TILING_LINEAR
= 0,
469 ISL_TILING_Y0
, /**< Legacy Y tiling */
470 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
471 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
472 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
473 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
474 ISL_TILING_GEN12_CCS
, /**< Tiling format for Gen12 CCS surfaces */
478 * @defgroup Tiling Flags
481 typedef uint32_t isl_tiling_flags_t
;
482 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
483 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
484 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
485 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
486 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
487 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
488 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
489 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
490 #define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
491 #define ISL_TILING_ANY_MASK (~0u)
492 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
494 /** Any Y tiling, including legacy Y tiling. */
495 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
496 ISL_TILING_Yf_BIT | \
499 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
500 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
505 * @brief Logical dimension of surface.
507 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
508 * as 2D array surfaces.
517 * @brief Physical layout of the surface's dimensions.
519 enum isl_dim_layout
{
521 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
522 * 6.17.3: 2D Surfaces.
524 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
525 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
527 * One-dimensional surfaces are identical to 2D surfaces with height of
530 * @invariant isl_surf::phys_level0_sa::depth == 1
532 ISL_DIM_LAYOUT_GEN4_2D
,
535 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
536 * 6.17.5: 3D Surfaces.
538 * @invariant isl_surf::phys_level0_sa::array_len == 1
540 ISL_DIM_LAYOUT_GEN4_3D
,
543 * Special layout used for HiZ and stencil on Sandy Bridge to work around
544 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
545 * work the same as on gen7+ except that they don't technically support
546 * mipmapping. That does not, however, stop us from doing it. As far as
547 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
548 * single miplevel 2D (possibly array) image. The dimensions of that image
551 * In order to implement HiZ and stencil on Sandy Bridge, we create one
552 * full-sized 2D (possibly array) image for every LOD with every image
553 * aligned to a page boundary. When the surface is used with the stencil
554 * or HiZ hardware, we manually offset to the image for the given LOD.
556 * As a memory saving measure, we pretend that the width of each miplevel
557 * is minified and we place LOD1 and above below LOD0 but horizontally
558 * adjacent to each other. When considered as full-sized images, LOD1 and
559 * above technically overlap. However, since we only write to part of that
560 * image, the hardware will never notice the overlap.
562 * This layout looks something like this:
580 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
,
583 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
584 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
586 ISL_DIM_LAYOUT_GEN9_1D
,
590 /** No Auxiliary surface is used */
593 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
596 /** The auxiliary surface is an MCS
598 * @invariant isl_surf::samples > 1
602 /** The auxiliary surface is a fast-clear-only compression surface
604 * @invariant isl_surf::samples == 1
608 /** The auxiliary surface provides full lossless color compression
610 * @invariant isl_surf::samples == 1
614 /** The auxiliary surface provides full lossless media color compression
616 * @invariant isl_surf::samples == 1
620 /** The auxiliary surface is a HiZ surface operating in write-through mode
621 * and CCS is also enabled
623 * In this mode, the HiZ and CCS surfaces act as a single fused compression
624 * surface where resolves and ambiguates operate on both surfaces at the
625 * same time. In this mode, the HiZ surface operates in write-through
626 * mode where it is only used for accelerating depth testing and not for
627 * actual compression. The CCS-compressed surface contains valid data at
630 * @invariant isl_surf::samples == 1
632 ISL_AUX_USAGE_HIZ_CCS_WT
,
634 /** The auxiliary surface is a HiZ surface with and CCS is also enabled
636 * In this mode, the HiZ and CCS surfaces act as a single fused compression
637 * surface where resolves and ambiguates operate on both surfaces at the
638 * same time. In this mode, full HiZ compression is enabled and the
639 * CCS-compressed main surface may not contain valid data. The only way to
640 * read the surface outside of the depth hardware is to do a full resolve
641 * which resolves both HiZ and CCS so the surface is in the pass-through
644 ISL_AUX_USAGE_HIZ_CCS
,
646 /** The auxiliary surface is an MCS and CCS is also enabled
648 * @invariant isl_surf::samples > 1
650 ISL_AUX_USAGE_MCS_CCS
,
652 /** CCS auxiliary data is used to compress a stencil buffer
654 * @invariant isl_surf::samples == 1
656 ISL_AUX_USAGE_STC_CCS
,
660 * Enum for keeping track of the state an auxiliary compressed surface.
662 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
663 * given slice (lod + array layer) can be in one of the six states described
664 * by this enum. Draw and resolve operations may cause the slice to change
665 * from one state to another. The six valid states are:
667 * 1) Clear: In this state, each block in the auxiliary surface contains a
668 * magic value that indicates that the block is in the clear state. If
669 * a block is in the clear state, it's values in the primary surface are
670 * ignored and the color of the samples in the block is taken either the
671 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
672 * depth. Since neither the primary surface nor the auxiliary surface
673 * contains the clear value, the surface can be cleared to a different
674 * color by simply changing the clear color without modifying either
677 * 2) Partial Clear: In this state, each block in the auxiliary surface
678 * contains either the magic clear or pass-through value. See Clear and
679 * Pass-through for more details.
681 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
682 * nor the primary surface has a complete representation of the data.
683 * Instead, both surfaces must be used together or else rendering
684 * corruption may occur. Depending on the auxiliary compression format
685 * and the data, any given block in the primary surface may contain all,
686 * some, or none of the data required to reconstruct the actual sample
687 * values. Blocks may also be in the clear state (see Clear) and have
688 * their value taken from outside the surface.
690 * 4) Compressed w/o Clear: This state is identical to the state above
691 * except that no blocks are in the clear state. In this state, all of
692 * the data required to reconstruct the final sample values is contained
693 * in the auxiliary and primary surface and the clear value is not
696 * 5) Resolved: In this state, the primary surface contains 100% of the
697 * data. The auxiliary surface is also valid so the surface can be
698 * validly used with or without aux enabled. The auxiliary surface may,
699 * however, contain non-trivial data and any update to the primary
700 * surface with aux disabled will cause the two to get out of sync.
702 * 6) Pass-through: In this state, the primary surface contains 100% of the
703 * data and every block in the auxiliary surface contains a magic value
704 * which indicates that the auxiliary surface should be ignored and the
705 * only the primary surface should be considered. Updating the primary
706 * surface without aux works fine and can be done repeatedly in this
707 * mode. Writing to a surface in pass-through mode with aux enabled may
708 * cause the auxiliary buffer to contain non-trivial data and no longer
709 * be in the pass-through state.
711 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
712 * data and the auxiliary surface is completely bogus. Any attempt to
713 * use the auxiliary surface is liable to result in rendering
714 * corruption. The only thing that one can do to re-enable aux once
715 * this state is reached is to use an ambiguate pass to transition into
716 * the pass-through state.
718 * Drawing with or without aux enabled may implicitly cause the surface to
719 * transition between these states. There are also four types of auxiliary
720 * compression operations which cause an explicit transition which are
721 * described by the isl_aux_op enum below.
723 * Not all operations are valid or useful in all states. The diagram below
724 * contains a complete description of the states and all valid and useful
725 * transitions except clear.
730 * | +-------------+ Draw w/ Aux +-------------+
731 * +------>| Compressed |<-------------------| Clear |
732 * | w/ Clear |----->----+ | |
733 * +-------------+ | +-------------+
736 * | | +------<-----+ | Draw w/
738 * | | Full | | +----------+
739 * Partial | | Resolve | \|/ | |
740 * Resolve | | | +-------------+ |
741 * | | | | Partial |<------+
742 * | | | | Clear |<----------+
743 * | | | +-------------+ |
745 * | | +------>---------+ Full |
747 * Draw w/ aux | | Partial Fast Clear | |
748 * +----------+ | +--------------------------+ | |
750 * | +-------------+ Full Resolve +-------------+ |
751 * +------>| Compressed |------------------->| Resolved | |
752 * | w/o Clear |<-------------------| | |
753 * +-------------+ Draw w/ Aux +-------------+ |
756 * | w/ Aux | | w/o Aux |
758 * | +--------------------------+ | |
759 * Draw w/o Aux | | | Draw w/o Aux |
760 * +----------+ | | | +----------+ |
761 * | | | \|/ \|/ | | |
762 * | +-------------+ Ambiguate +-------------+ | |
763 * +------>| Pass- |<-------------------| Aux |<------+ |
764 * +------>| through | | Invalid | |
765 * | +-------------+ +-------------+ |
767 * +----------+ +-----------------------------------------------------+
768 * Draw w/ Partial Fast Clear
772 * While the above general theory applies to all forms of auxiliary
773 * compression on Intel hardware, not all states and operations are available
774 * on all compression types. However, each of the auxiliary states and
775 * operations can be fairly easily mapped onto the above diagram:
777 * HiZ: Hierarchical depth compression is capable of being in any of the
778 * states above. Hardware provides three HiZ operations: "Depth
779 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
780 * Clear", "Full Resolve", and "Ambiguate" respectively. The
781 * hardware provides no HiZ partial resolve operation so the only way
782 * to get into the "Compressed w/o Clear" state is to render with HiZ
783 * when the surface is in the resolved or pass-through states.
785 * MCS: Multisample compression is technically capable of being in any of
786 * the states above except that most of them aren't useful. Both the
787 * render engine and the sampler support MCS compression and, apart
788 * from clear color, MCS is format-unaware so we leave the surface
789 * compressed 100% of the time. The hardware provides no MCS
792 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
793 * the simplest forms of compression since they don't do anything
794 * beyond clear color tracking. They really only support three of
795 * the six states: Clear, Partial Clear, and Pass-through. The
796 * only CCS_D operation is "Resolve" which maps to a full resolve
797 * followed by an ambiguate.
799 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
800 * is capable of being in almost all of the above states. THe only
801 * exception is that it does not have separate resolved and pass-
802 * through states. Instead, the CCS_E full resolve operation does
803 * both a resolve and an ambiguate so it goes directly into the
804 * pass-through state. CCS_E also provides fast clear and partial
805 * resolve operations which work as described above.
807 * While it is technically possible to perform a CCS_E ambiguate, it
808 * is not provided by Sky Lake hardware so we choose to avoid the aux
809 * invalid state. If the aux invalid state were determined to be
810 * useful, a CCS ambiguate could be done by carefully rendering to
811 * the CCS and filling it with zeros.
815 ISL_AUX_STATE_ASSERT
,
818 ISL_AUX_STATE_PARTIAL_CLEAR
,
819 ISL_AUX_STATE_COMPRESSED_CLEAR
,
820 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
,
821 ISL_AUX_STATE_RESOLVED
,
822 ISL_AUX_STATE_PASS_THROUGH
,
823 ISL_AUX_STATE_AUX_INVALID
,
827 * Enum which describes explicit aux transition operations.
838 * This operation writes the magic "clear" value to the auxiliary surface.
839 * This operation will safely transition any slice of a surface from any
840 * state to the clear state so long as the entire slice is fast cleared at
841 * once. A fast clear that only covers part of a slice of a surface is
842 * called a partial fast clear.
844 ISL_AUX_OP_FAST_CLEAR
,
848 * This operation combines the auxiliary surface data with the primary
849 * surface data and writes the result to the primary. For HiZ, the docs
850 * call this a depth resolve. For CCS, the hardware full resolve operation
851 * does both a full resolve and an ambiguate so it actually takes you all
852 * the way to the pass-through state.
854 ISL_AUX_OP_FULL_RESOLVE
,
858 * This operation considers blocks which are in the "clear" state and
859 * writes the clear value directly into the primary or auxiliary surface.
860 * Once this operation completes, the surface is still compressed but no
861 * longer references the clear color. This operation is only available
864 ISL_AUX_OP_PARTIAL_RESOLVE
,
868 * This operation throws away the current auxiliary data and replaces it
869 * with the magic pass-through value. If an ambiguate operation is
870 * performed when the primary surface does not contain 100% of the data,
871 * data will be lost. This operation is only implemented in hardware for
872 * depth where it is called a HiZ resolve.
874 ISL_AUX_OP_AMBIGUATE
,
877 /* TODO(chadv): Explain */
878 enum isl_array_pitch_span
{
879 ISL_ARRAY_PITCH_SPAN_FULL
,
880 ISL_ARRAY_PITCH_SPAN_COMPACT
,
884 * @defgroup Surface Usage
887 typedef uint64_t isl_surf_usage_flags_t
;
888 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
889 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
890 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
891 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
892 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
893 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
894 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
895 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
896 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
897 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
898 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
899 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
900 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
901 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
902 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
903 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
907 * @defgroup Channel Mask
909 * These #define values are chosen to match the values of
910 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
914 typedef uint8_t isl_channel_mask_t
;
915 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
916 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
917 #define ISL_CHANNEL_RED_BIT (1 << 2)
918 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
922 * @brief A channel select (also known as texture swizzle) value
924 enum PACKED isl_channel_select
{
925 ISL_CHANNEL_SELECT_ZERO
= 0,
926 ISL_CHANNEL_SELECT_ONE
= 1,
927 ISL_CHANNEL_SELECT_RED
= 4,
928 ISL_CHANNEL_SELECT_GREEN
= 5,
929 ISL_CHANNEL_SELECT_BLUE
= 6,
930 ISL_CHANNEL_SELECT_ALPHA
= 7,
934 * Identical to VkSampleCountFlagBits.
936 enum isl_sample_count
{
937 ISL_SAMPLE_COUNT_1_BIT
= 1u,
938 ISL_SAMPLE_COUNT_2_BIT
= 2u,
939 ISL_SAMPLE_COUNT_4_BIT
= 4u,
940 ISL_SAMPLE_COUNT_8_BIT
= 8u,
941 ISL_SAMPLE_COUNT_16_BIT
= 16u,
943 typedef uint32_t isl_sample_count_mask_t
;
946 * @brief Multisample Format
948 enum isl_msaa_layout
{
950 * @brief Suface is single-sampled.
952 ISL_MSAA_LAYOUT_NONE
,
955 * @brief [SNB+] Interleaved Multisample Format
957 * In this format, multiple samples are interleaved into each cacheline.
958 * In other words, the sample index is swizzled into the low 6 bits of the
959 * surface's virtual address space.
961 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
962 * and its pixel format is 32bpp. Then the first cacheline is arranged
965 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
966 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
968 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
969 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
971 * The hardware docs refer to this format with multiple terms. In
972 * Sandybridge, this is the only multisample format; so no term is used.
973 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
974 * Multisample Surface). Later hardware docs additionally refer to this
975 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
978 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
981 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
982 * Multisampled Surfaces".
984 ISL_MSAA_LAYOUT_INTERLEAVED
,
987 * @brief [IVB+] Array Multisample Format
989 * In this format, the surface's physical layout resembles that of a
992 * Suppose the multisample surface's logical extent is (w, h) and its
993 * sample count is N. Then surface's physical extent is the same as
994 * a singlesample 2D surface whose logical extent is (w, h) and array
995 * length is N. Array slice `i` contains the pixel values for sample
998 * The Ivybridge docs refer to surfaces in this format as UMS
999 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
1000 * Surface). The Broadwell docs additionally refer to this format as
1001 * MSFMT_MSS (MSS=Multisample Surface Storage).
1003 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
1004 * Multisample Surfaces".
1006 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
1007 * Multisample Surfaces".
1009 ISL_MSAA_LAYOUT_ARRAY
,
1015 ISL_MEMCPY_STREAMING_LOAD
,
1020 const struct gen_device_info
*info
;
1021 bool use_separate_stencil
;
1022 bool has_bit6_swizzling
;
1025 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1031 uint8_t addr_offset
;
1032 uint8_t aux_addr_offset
;
1034 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1036 /* size of the state buffer used to store the clear color + extra
1037 * additional space used by the hardware */
1038 uint8_t clear_color_state_size
;
1039 uint8_t clear_color_state_offset
;
1040 /* size of the clear color itself - used to copy it to/from a BO */
1041 uint8_t clear_value_size
;
1042 uint8_t clear_value_offset
;
1046 * Describes the layout of the depth/stencil/hiz commands as emitted by
1047 * isl_emit_depth_stencil_hiz.
1051 uint8_t depth_offset
;
1052 uint8_t stencil_offset
;
1062 struct isl_extent2d
{
1063 union { uint32_t w
, width
; };
1064 union { uint32_t h
, height
; };
1067 struct isl_extent3d
{
1068 union { uint32_t w
, width
; };
1069 union { uint32_t h
, height
; };
1070 union { uint32_t d
, depth
; };
1073 struct isl_extent4d
{
1074 union { uint32_t w
, width
; };
1075 union { uint32_t h
, height
; };
1076 union { uint32_t d
, depth
; };
1077 union { uint32_t a
, array_len
; };
1080 struct isl_channel_layout
{
1081 enum isl_base_type type
;
1082 uint8_t start_bit
; /**< Bit at which this channel starts */
1083 uint8_t bits
; /**< Size in bits */
1087 * Each format has 3D block extent (width, height, depth). The block extent of
1088 * compressed formats is that of the format's compression block. For example,
1089 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1090 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1091 * is (w=1, h=1, d=1).
1093 struct isl_format_layout
{
1094 enum isl_format format
;
1097 uint16_t bpb
; /**< Bits per block */
1098 uint8_t bw
; /**< Block width, in pixels */
1099 uint8_t bh
; /**< Block height, in pixels */
1100 uint8_t bd
; /**< Block depth, in pixels */
1104 struct isl_channel_layout r
; /**< Red channel */
1105 struct isl_channel_layout g
; /**< Green channel */
1106 struct isl_channel_layout b
; /**< Blue channel */
1107 struct isl_channel_layout a
; /**< Alpha channel */
1108 struct isl_channel_layout l
; /**< Luminance channel */
1109 struct isl_channel_layout i
; /**< Intensity channel */
1110 struct isl_channel_layout p
; /**< Palette channel */
1112 struct isl_channel_layout channels_array
[7];
1115 enum isl_colorspace colorspace
;
1119 struct isl_tile_info
{
1120 enum isl_tiling tiling
;
1122 /* The size (in bits per block) of a single surface element
1124 * For surfaces with power-of-two formats, this is the same as
1125 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1126 * The logical_extent_el field is in terms of elements of this size.
1128 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1129 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1130 * of the tiling formats can actually hold an integer number of 96-bit
1131 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1132 * 32-bit element size. It is the responsibility of the caller to
1133 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1134 * the width of a surface in tiles, you would do:
1136 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1137 * tile_info.logical_extent_el.width);
1139 uint32_t format_bpb
;
1141 /** The logical size of the tile in units of format_bpb size elements
1143 * This field determines how a given surface is cut up into tiles. It is
1144 * used to compute the size of a surface in tiles and can be used to
1145 * determine the location of the tile containing any given surface element.
1146 * The exact value of this field depends heavily on the bits-per-block of
1147 * the format being used.
1149 struct isl_extent2d logical_extent_el
;
1151 /** The physical size of the tile in bytes and rows of bytes
1153 * This field determines how the tiles of a surface are physically layed
1154 * out in memory. The logical and physical tile extent are frequently the
1155 * same but this is not always the case. For instance, a W-tile (which is
1156 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1157 * its physical size is 128B x 32rows, the same as a Y-tile.
1159 * @see isl_surf::row_pitch_B
1161 struct isl_extent2d phys_extent_B
;
1165 * Metadata about a DRM format modifier.
1167 struct isl_drm_modifier_info
{
1170 /** Text name of the modifier */
1173 /** ISL tiling implied by this modifier */
1174 enum isl_tiling tiling
;
1176 /** ISL aux usage implied by this modifier */
1177 enum isl_aux_usage aux_usage
;
1179 /** Whether or not this modifier supports clear color */
1180 bool supports_clear_color
;
1184 * @brief Input to surface initialization
1186 * @invariant width >= 1
1187 * @invariant height >= 1
1188 * @invariant depth >= 1
1189 * @invariant levels >= 1
1190 * @invariant samples >= 1
1191 * @invariant array_len >= 1
1193 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1194 * @invariant if 2D then depth == 1
1195 * @invariant if 3D then array_len == 1 and samples == 1
1197 struct isl_surf_init_info
{
1198 enum isl_surf_dim dim
;
1199 enum isl_format format
;
1208 /** Lower bound for isl_surf::alignment, in bytes. */
1209 uint32_t min_alignment_B
;
1212 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1213 * will fail if this is misaligned or out of bounds.
1215 uint32_t row_pitch_B
;
1217 isl_surf_usage_flags_t usage
;
1219 /** Flags that alter how ISL selects isl_surf::tiling. */
1220 isl_tiling_flags_t tiling_flags
;
1224 enum isl_surf_dim dim
;
1225 enum isl_dim_layout dim_layout
;
1226 enum isl_msaa_layout msaa_layout
;
1227 enum isl_tiling tiling
;
1228 enum isl_format format
;
1231 * Alignment of the upper-left sample of each subimage, in units of surface
1234 struct isl_extent3d image_alignment_el
;
1237 * Logical extent of the surface's base level, in units of pixels. This is
1238 * identical to the extent defined in isl_surf_init_info.
1240 struct isl_extent4d logical_level0_px
;
1243 * Physical extent of the surface's base level, in units of physical
1246 * Consider isl_dim_layout as an operator that transforms a logical surface
1247 * layout to a physical surface layout. Then
1249 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1250 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1252 struct isl_extent4d phys_level0_sa
;
1257 /** Total size of the surface, in bytes. */
1260 /** Required alignment for the surface's base address. */
1261 uint32_t alignment_B
;
1264 * The interpretation of this field depends on the value of
1265 * isl_tile_info::physical_extent_B. In particular, the width of the
1266 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1267 * and the distance in bytes between vertically adjacent tiles in the image
1268 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1270 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1271 * this cleanly reduces to being the distance, in bytes, between vertically
1272 * adjacent surface elements.
1274 * @see isl_tile_info::phys_extent_B;
1276 uint32_t row_pitch_B
;
1279 * Pitch between physical array slices, in rows of surface elements.
1281 uint32_t array_pitch_el_rows
;
1283 enum isl_array_pitch_span array_pitch_span
;
1285 /** Copy of isl_surf_init_info::usage. */
1286 isl_surf_usage_flags_t usage
;
1289 struct isl_swizzle
{
1290 enum isl_channel_select r
:4;
1291 enum isl_channel_select g
:4;
1292 enum isl_channel_select b
:4;
1293 enum isl_channel_select a
:4;
1296 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1297 .r = ISL_CHANNEL_SELECT_##R, \
1298 .g = ISL_CHANNEL_SELECT_##G, \
1299 .b = ISL_CHANNEL_SELECT_##B, \
1300 .a = ISL_CHANNEL_SELECT_##A, \
1303 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1307 * Indicates the usage of the particular view
1309 * Normally, this is one bit. However, for a cube map texture, it
1310 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1312 isl_surf_usage_flags_t usage
;
1315 * The format to use in the view
1317 * This may differ from the format of the actual isl_surf but must have
1318 * the same block size.
1320 enum isl_format format
;
1322 uint32_t base_level
;
1328 * For cube maps, both base_array_layer and array_len should be
1329 * specified in terms of 2-D layers and must be a multiple of 6.
1331 * 3-D textures are effectively treated as 2-D arrays when used as a
1332 * storage image or render target. If `usage` contains
1333 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1334 * base_array_layer and array_len are applied. If the surface is only used
1335 * for texturing, they are ignored.
1337 uint32_t base_array_layer
;
1342 * Indicates the number of array elements starting at Base Array Layer.
1346 struct isl_swizzle swizzle
;
1349 union isl_color_value
{
1355 struct isl_surf_fill_state_info
{
1356 const struct isl_surf
*surf
;
1357 const struct isl_view
*view
;
1360 * The address of the surface in GPU memory.
1365 * The Memory Object Control state for the filled surface state.
1367 * The exact format of this value depends on hardware generation.
1372 * The auxilary surface or NULL if no auxilary surface is to be used.
1374 const struct isl_surf
*aux_surf
;
1375 enum isl_aux_usage aux_usage
;
1376 uint64_t aux_address
;
1379 * The clear color for this surface
1381 * Valid values depend on hardware generation.
1383 union isl_color_value clear_color
;
1386 * Send only the clear value address
1388 * If set, we only pass the clear address to the GPU and it will fetch it
1389 * from wherever it is.
1391 bool use_clear_address
;
1392 uint64_t clear_address
;
1395 * Surface write disables for gen4-5
1397 isl_channel_mask_t write_disables
;
1399 /* Intra-tile offset */
1400 uint16_t x_offset_sa
, y_offset_sa
;
1403 struct isl_buffer_fill_state_info
{
1405 * The address of the surface in GPU memory.
1410 * The size of the buffer
1415 * The Memory Object Control state for the filled surface state.
1417 * The exact format of this value depends on hardware generation.
1422 * The format to use in the surface state
1424 * This may differ from the format of the actual isl_surf but have the
1427 enum isl_format format
;
1430 * The swizzle to use in the surface state
1432 struct isl_swizzle swizzle
;
1437 struct isl_depth_stencil_hiz_emit_info
{
1441 const struct isl_surf
*depth_surf
;
1444 * The stencil surface
1446 * If separate stencil is not available, this must point to the same
1447 * isl_surf as depth_surf.
1449 const struct isl_surf
*stencil_surf
;
1452 * The view into the depth and stencil surfaces.
1454 * This view applies to both surfaces simultaneously.
1456 const struct isl_view
*view
;
1459 * The address of the depth surface in GPU memory
1461 uint64_t depth_address
;
1464 * The address of the stencil surface in GPU memory
1466 * If separate stencil is not available, this must have the same value as
1469 uint64_t stencil_address
;
1472 * The Memory Object Control state for depth and stencil buffers
1474 * Both depth and stencil will get the same MOCS value. The exact format
1475 * of this value depends on hardware generation.
1480 * The HiZ surface or NULL if HiZ is disabled.
1482 const struct isl_surf
*hiz_surf
;
1483 enum isl_aux_usage hiz_usage
;
1484 uint64_t hiz_address
;
1487 * The depth clear value
1489 float depth_clear_value
;
1492 * Track stencil aux usage for Gen >= 12
1494 enum isl_aux_usage stencil_aux_usage
;
1497 extern const struct isl_format_layout isl_format_layouts
[];
1500 isl_device_init(struct isl_device
*dev
,
1501 const struct gen_device_info
*info
,
1502 bool has_bit6_swizzling
);
1504 isl_sample_count_mask_t ATTRIBUTE_CONST
1505 isl_device_get_sample_counts(struct isl_device
*dev
);
1507 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
1508 isl_format_get_layout(enum isl_format fmt
)
1510 assert(fmt
!= ISL_FORMAT_UNSUPPORTED
);
1511 assert(fmt
< ISL_NUM_FORMATS
);
1512 return &isl_format_layouts
[fmt
];
1515 bool isl_format_is_valid(enum isl_format
);
1517 static inline const char * ATTRIBUTE_CONST
1518 isl_format_get_name(enum isl_format fmt
)
1520 return isl_format_get_layout(fmt
)->name
;
1523 enum isl_format
isl_format_for_pipe_format(enum pipe_format pf
);
1525 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
1526 enum isl_format format
);
1527 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
1528 enum isl_format format
);
1529 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
1530 enum isl_format format
);
1531 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
1532 enum isl_format format
);
1533 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
1534 enum isl_format format
);
1535 bool isl_format_supports_typed_writes(const struct gen_device_info
*devinfo
,
1536 enum isl_format format
);
1537 bool isl_format_supports_typed_reads(const struct gen_device_info
*devinfo
,
1538 enum isl_format format
);
1539 bool isl_format_supports_ccs_d(const struct gen_device_info
*devinfo
,
1540 enum isl_format format
);
1541 bool isl_format_supports_ccs_e(const struct gen_device_info
*devinfo
,
1542 enum isl_format format
);
1543 bool isl_format_supports_multisampling(const struct gen_device_info
*devinfo
,
1544 enum isl_format format
);
1546 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info
*devinfo
,
1547 enum isl_format format1
,
1548 enum isl_format format2
);
1549 uint8_t isl_format_get_aux_map_encoding(enum isl_format format
);
1551 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1552 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1553 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1554 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1555 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1556 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1559 isl_format_has_normalized_channel(enum isl_format fmt
)
1561 return isl_format_has_unorm_channel(fmt
) ||
1562 isl_format_has_snorm_channel(fmt
);
1566 isl_format_has_float_channel(enum isl_format fmt
)
1568 return isl_format_has_ufloat_channel(fmt
) ||
1569 isl_format_has_sfloat_channel(fmt
);
1573 isl_format_has_int_channel(enum isl_format fmt
)
1575 return isl_format_has_uint_channel(fmt
) ||
1576 isl_format_has_sint_channel(fmt
);
1579 bool isl_format_has_color_component(enum isl_format fmt
,
1580 int component
) ATTRIBUTE_CONST
;
1582 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1584 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1587 isl_format_is_compressed(enum isl_format fmt
)
1589 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1591 return fmtl
->txc
!= ISL_TXC_NONE
;
1595 isl_format_has_bc_compression(enum isl_format fmt
)
1597 switch (isl_format_get_layout(fmt
)->txc
) {
1615 unreachable("Should not be called on an aux surface");
1618 unreachable("bad texture compression mode");
1623 isl_format_is_yuv(enum isl_format fmt
)
1625 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1627 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1631 isl_format_block_is_1x1x1(enum isl_format fmt
)
1633 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1635 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1639 isl_format_is_srgb(enum isl_format fmt
)
1641 return isl_format_get_layout(fmt
)->colorspace
== ISL_COLORSPACE_SRGB
;
1644 enum isl_format
isl_format_srgb_to_linear(enum isl_format fmt
);
1647 isl_format_is_rgb(enum isl_format fmt
)
1649 if (isl_format_is_yuv(fmt
))
1652 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1654 return fmtl
->channels
.r
.bits
> 0 &&
1655 fmtl
->channels
.g
.bits
> 0 &&
1656 fmtl
->channels
.b
.bits
> 0 &&
1657 fmtl
->channels
.a
.bits
== 0;
1661 isl_format_is_rgbx(enum isl_format fmt
)
1663 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1665 return fmtl
->channels
.r
.bits
> 0 &&
1666 fmtl
->channels
.g
.bits
> 0 &&
1667 fmtl
->channels
.b
.bits
> 0 &&
1668 fmtl
->channels
.a
.bits
> 0 &&
1669 fmtl
->channels
.a
.type
== ISL_VOID
;
1672 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1673 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1674 enum isl_format
isl_format_rgbx_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1676 void isl_color_value_pack(const union isl_color_value
*value
,
1677 enum isl_format format
,
1678 uint32_t *data_out
);
1679 void isl_color_value_unpack(union isl_color_value
*value
,
1680 enum isl_format format
,
1681 const uint32_t *data_in
);
1683 bool isl_is_storage_image_format(enum isl_format fmt
);
1686 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1687 enum isl_format fmt
);
1689 /* Returns true if this hardware supports typed load/store on a format with
1690 * the same size as the given format.
1693 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1694 enum isl_format fmt
);
1696 static inline enum isl_tiling
1697 isl_tiling_flag_to_enum(isl_tiling_flags_t flag
)
1699 assert(__builtin_popcount(flag
) == 1);
1700 return (enum isl_tiling
) (__builtin_ffs(flag
) - 1);
1704 isl_tiling_is_any_y(enum isl_tiling tiling
)
1706 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1710 isl_tiling_is_std_y(enum isl_tiling tiling
)
1712 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1716 isl_tiling_to_i915_tiling(enum isl_tiling tiling
);
1719 isl_tiling_from_i915_tiling(uint32_t tiling
);
1722 * Return an isl_aux_op needed to enable an access to occur in an
1723 * isl_aux_state suitable for the isl_aux_usage.
1725 * NOTE: If the access will invalidate the main surface, this function should
1726 * not be called and the isl_aux_op of NONE should be used instead.
1727 * Otherwise, an extra (but still lossless) ambiguate may occur.
1729 * @invariant initial_state is possible with an isl_aux_usage compatible with
1730 * the given usage. Two usages are compatible if it's possible to
1731 * switch between them (e.g. CCS_E <-> CCS_D).
1732 * @invariant fast_clear is false if the aux doesn't support fast clears.
1735 isl_aux_prepare_access(enum isl_aux_state initial_state
,
1736 enum isl_aux_usage usage
,
1737 bool fast_clear_supported
);
1740 * Return the isl_aux_state entered after performing an isl_aux_op.
1742 * @invariant initial_state is possible with the given usage.
1743 * @invariant op is possible with the given usage.
1744 * @invariant op must not cause HW to read from an invalid aux.
1747 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state
,
1748 enum isl_aux_usage usage
,
1749 enum isl_aux_op op
);
1752 * Return the isl_aux_state entered after performing a write.
1754 * NOTE: full_surface should be true if the write covers the entire
1755 * slice. Setting it to false in this case will still result in a
1756 * correct (but imprecise) aux state.
1758 * @invariant if usage is not ISL_AUX_USAGE_NONE, then initial_state is
1759 * possible with the given usage.
1760 * @invariant usage can be ISL_AUX_USAGE_NONE iff:
1761 * * the main surface is valid, or
1762 * * the main surface is being invalidated/replaced.
1765 isl_aux_state_transition_write(enum isl_aux_state initial_state
,
1766 enum isl_aux_usage usage
,
1770 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage
);
1773 isl_aux_usage_has_hiz(enum isl_aux_usage usage
)
1775 return usage
== ISL_AUX_USAGE_HIZ
||
1776 usage
== ISL_AUX_USAGE_HIZ_CCS_WT
||
1777 usage
== ISL_AUX_USAGE_HIZ_CCS
;
1781 isl_aux_usage_has_mcs(enum isl_aux_usage usage
)
1783 return usage
== ISL_AUX_USAGE_MCS
||
1784 usage
== ISL_AUX_USAGE_MCS_CCS
;
1788 isl_aux_usage_has_ccs(enum isl_aux_usage usage
)
1790 return usage
== ISL_AUX_USAGE_CCS_D
||
1791 usage
== ISL_AUX_USAGE_CCS_E
||
1792 usage
== ISL_AUX_USAGE_MC
||
1793 usage
== ISL_AUX_USAGE_HIZ_CCS_WT
||
1794 usage
== ISL_AUX_USAGE_HIZ_CCS
||
1795 usage
== ISL_AUX_USAGE_MCS_CCS
||
1796 usage
== ISL_AUX_USAGE_STC_CCS
;
1800 isl_aux_state_has_valid_primary(enum isl_aux_state state
)
1802 return state
== ISL_AUX_STATE_RESOLVED
||
1803 state
== ISL_AUX_STATE_PASS_THROUGH
||
1804 state
== ISL_AUX_STATE_AUX_INVALID
;
1808 isl_aux_state_has_valid_aux(enum isl_aux_state state
)
1810 return state
!= ISL_AUX_STATE_AUX_INVALID
;
1813 const struct isl_drm_modifier_info
* ATTRIBUTE_CONST
1814 isl_drm_modifier_get_info(uint64_t modifier
);
1817 isl_drm_modifier_has_aux(uint64_t modifier
)
1819 return isl_drm_modifier_get_info(modifier
)->aux_usage
!= ISL_AUX_USAGE_NONE
;
1822 /** Returns the default isl_aux_state for the given modifier.
1824 * If we have a modifier which supports compression, then the auxiliary data
1825 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1826 * can be in any of the following:
1828 * - ISL_AUX_STATE_CLEAR
1829 * - ISL_AUX_STATE_PARTIAL_CLEAR
1830 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1831 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1832 * - ISL_AUX_STATE_RESOLVED
1833 * - ISL_AUX_STATE_PASS_THROUGH
1835 * If the modifier does not support fast-clears, then we are guaranteed
1836 * that the surface is at least partially resolved and the first three not
1837 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1838 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1839 * because they are the least common denominator of the set of possible aux
1840 * states and will yield a valid interpretation of the aux data.
1842 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1844 static inline enum isl_aux_state
1845 isl_drm_modifier_get_default_aux_state(uint64_t modifier
)
1847 const struct isl_drm_modifier_info
*mod_info
=
1848 isl_drm_modifier_get_info(modifier
);
1850 if (!mod_info
|| mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
)
1851 return ISL_AUX_STATE_AUX_INVALID
;
1853 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1854 return mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1855 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1858 struct isl_extent2d ATTRIBUTE_CONST
1859 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
);
1862 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1864 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1868 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1870 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1874 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1876 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1880 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1882 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1883 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1887 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1889 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1893 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1895 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1896 (info
->format
== ISL_FORMAT_R16_UNORM
);
1900 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1902 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1903 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1906 static inline struct isl_extent2d
1907 isl_extent2d(uint32_t width
, uint32_t height
)
1909 struct isl_extent2d e
= { { 0 } };
1917 static inline struct isl_extent3d
1918 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1920 struct isl_extent3d e
= { { 0 } };
1929 static inline struct isl_extent4d
1930 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1933 struct isl_extent4d e
= { { 0 } };
1938 e
.array_len
= array_len
;
1943 bool isl_color_value_is_zero(union isl_color_value value
,
1944 enum isl_format format
);
1946 bool isl_color_value_is_zero_one(union isl_color_value value
,
1947 enum isl_format format
);
1950 isl_swizzle_is_identity(struct isl_swizzle swizzle
)
1952 return swizzle
.r
== ISL_CHANNEL_SELECT_RED
&&
1953 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
&&
1954 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
&&
1955 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
1959 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
1960 struct isl_swizzle swizzle
);
1963 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
);
1965 isl_swizzle_invert(struct isl_swizzle swizzle
);
1967 #define isl_surf_init(dev, surf, ...) \
1968 isl_surf_init_s((dev), (surf), \
1969 &(struct isl_surf_init_info) { __VA_ARGS__ });
1972 isl_surf_init_s(const struct isl_device
*dev
,
1973 struct isl_surf
*surf
,
1974 const struct isl_surf_init_info
*restrict info
);
1977 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1978 struct isl_tile_info
*tile_info
);
1981 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1982 const struct isl_surf
*surf
,
1983 struct isl_surf
*hiz_surf
);
1986 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1987 const struct isl_surf
*surf
,
1988 struct isl_surf
*mcs_surf
);
1991 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1992 const struct isl_surf
*surf
,
1993 struct isl_surf
*aux_surf
,
1994 struct isl_surf
*extra_aux_surf
,
1995 uint32_t row_pitch_B
/**< Ignored if 0 */);
1997 #define isl_surf_fill_state(dev, state, ...) \
1998 isl_surf_fill_state_s((dev), (state), \
1999 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
2002 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
2003 const struct isl_surf_fill_state_info
*restrict info
);
2005 #define isl_buffer_fill_state(dev, state, ...) \
2006 isl_buffer_fill_state_s((dev), (state), \
2007 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
2010 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
2011 const struct isl_buffer_fill_state_info
*restrict info
);
2014 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
2015 struct isl_extent3d size
);
2017 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2018 isl_emit_depth_stencil_hiz_s((dev), (batch), \
2019 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2022 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
2023 const struct isl_depth_stencil_hiz_emit_info
*restrict info
);
2026 isl_surf_fill_image_param(const struct isl_device
*dev
,
2027 struct brw_image_param
*param
,
2028 const struct isl_surf
*surf
,
2029 const struct isl_view
*view
);
2032 isl_buffer_fill_image_param(const struct isl_device
*dev
,
2033 struct brw_image_param
*param
,
2034 enum isl_format format
,
2038 * Alignment of the upper-left sample of each subimage, in units of surface
2041 static inline struct isl_extent3d
2042 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
2044 return surf
->image_alignment_el
;
2048 * Alignment of the upper-left sample of each subimage, in units of surface
2051 static inline struct isl_extent3d
2052 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
2054 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2056 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
2057 fmtl
->bh
* surf
->image_alignment_el
.h
,
2058 fmtl
->bd
* surf
->image_alignment_el
.d
);
2062 * Logical extent of level 0 in units of surface elements.
2064 static inline struct isl_extent4d
2065 isl_surf_get_logical_level0_el(const struct isl_surf
*surf
)
2067 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2069 return isl_extent4d(DIV_ROUND_UP(surf
->logical_level0_px
.w
, fmtl
->bw
),
2070 DIV_ROUND_UP(surf
->logical_level0_px
.h
, fmtl
->bh
),
2071 DIV_ROUND_UP(surf
->logical_level0_px
.d
, fmtl
->bd
),
2072 surf
->logical_level0_px
.a
);
2076 * Physical extent of level 0 in units of surface elements.
2078 static inline struct isl_extent4d
2079 isl_surf_get_phys_level0_el(const struct isl_surf
*surf
)
2081 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2083 return isl_extent4d(DIV_ROUND_UP(surf
->phys_level0_sa
.w
, fmtl
->bw
),
2084 DIV_ROUND_UP(surf
->phys_level0_sa
.h
, fmtl
->bh
),
2085 DIV_ROUND_UP(surf
->phys_level0_sa
.d
, fmtl
->bd
),
2086 surf
->phys_level0_sa
.a
);
2090 * Pitch between vertically adjacent surface elements, in bytes.
2092 static inline uint32_t
2093 isl_surf_get_row_pitch_B(const struct isl_surf
*surf
)
2095 return surf
->row_pitch_B
;
2099 * Pitch between vertically adjacent surface elements, in units of surface elements.
2101 static inline uint32_t
2102 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
2104 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2106 assert(surf
->row_pitch_B
% (fmtl
->bpb
/ 8) == 0);
2107 return surf
->row_pitch_B
/ (fmtl
->bpb
/ 8);
2111 * Pitch between physical array slices, in rows of surface elements.
2113 static inline uint32_t
2114 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
2116 return surf
->array_pitch_el_rows
;
2120 * Pitch between physical array slices, in units of surface elements.
2122 static inline uint32_t
2123 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
2125 return isl_surf_get_array_pitch_el_rows(surf
) *
2126 isl_surf_get_row_pitch_el(surf
);
2130 * Pitch between physical array slices, in rows of surface samples.
2132 static inline uint32_t
2133 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
2135 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2136 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
2140 * Pitch between physical array slices, in bytes.
2142 static inline uint32_t
2143 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
2145 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch_B
;
2149 * Calculate the offset, in units of surface samples, to a subimage in the
2152 * @invariant level < surface levels
2153 * @invariant logical_array_layer < logical array length of surface
2154 * @invariant logical_z_offset_px < logical depth of surface at level
2157 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2159 uint32_t logical_array_layer
,
2160 uint32_t logical_z_offset_px
,
2161 uint32_t *x_offset_sa
,
2162 uint32_t *y_offset_sa
);
2165 * Calculate the offset, in units of surface elements, to a subimage in the
2168 * @invariant level < surface levels
2169 * @invariant logical_array_layer < logical array length of surface
2170 * @invariant logical_z_offset_px < logical depth of surface at level
2173 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2175 uint32_t logical_array_layer
,
2176 uint32_t logical_z_offset_px
,
2177 uint32_t *x_offset_el
,
2178 uint32_t *y_offset_el
);
2181 * Calculate the offset, in bytes and intratile surface samples, to a
2182 * subimage in the surface.
2184 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2185 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2186 * offsets to samples.
2188 * @invariant level < surface levels
2189 * @invariant logical_array_layer < logical array length of surface
2190 * @invariant logical_z_offset_px < logical depth of surface at level
2193 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2195 uint32_t logical_array_layer
,
2196 uint32_t logical_z_offset_px
,
2198 uint32_t *x_offset_sa
,
2199 uint32_t *y_offset_sa
);
2202 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2204 * The range returned will be the smallest memory range in which the give
2205 * subimage fits, rounded to even tiles. Intel images do not usually have a
2206 * direct subimage -> range mapping so the range returned may contain data
2207 * from other sub-images. The returned range is a half-open interval where
2208 * all of the addresses within the subimage are < end_tile_B.
2210 * @invariant level < surface levels
2211 * @invariant logical_array_layer < logical array length of surface
2212 * @invariant logical_z_offset_px < logical depth of surface at level
2215 isl_surf_get_image_range_B_tile(const struct isl_surf
*surf
,
2217 uint32_t logical_array_layer
,
2218 uint32_t logical_z_offset_px
,
2219 uint32_t *start_tile_B
,
2220 uint32_t *end_tile_B
);
2223 * Create an isl_surf that represents a particular subimage in the surface.
2225 * The newly created surface will have a single miplevel and array slice. The
2226 * surface lives at the returned byte and intratile offsets, in samples.
2228 * It is safe to call this function with surf == image_surf.
2230 * @invariant level < surface levels
2231 * @invariant logical_array_layer < logical array length of surface
2232 * @invariant logical_z_offset_px < logical depth of surface at level
2235 isl_surf_get_image_surf(const struct isl_device
*dev
,
2236 const struct isl_surf
*surf
,
2238 uint32_t logical_array_layer
,
2239 uint32_t logical_z_offset_px
,
2240 struct isl_surf
*image_surf
,
2242 uint32_t *x_offset_sa
,
2243 uint32_t *y_offset_sa
);
2246 * @brief Calculate the intratile offsets to a surface.
2248 * In @a base_address_offset return the offset from the base of the surface to
2249 * the base address of the first tile of the subimage. In @a x_offset_B and
2250 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2251 * tile's base to the subimage's first surface element. The x and y offsets
2252 * are intratile offsets; that is, they do not exceed the boundary of the
2253 * surface's tiling format.
2256 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2258 uint32_t row_pitch_B
,
2259 uint32_t total_x_offset_el
,
2260 uint32_t total_y_offset_el
,
2261 uint32_t *base_address_offset
,
2262 uint32_t *x_offset_el
,
2263 uint32_t *y_offset_el
);
2266 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling
,
2267 enum isl_format format
,
2268 uint32_t row_pitch_B
,
2269 uint32_t total_x_offset_sa
,
2270 uint32_t total_y_offset_sa
,
2271 uint32_t *base_address_offset
,
2272 uint32_t *x_offset_sa
,
2273 uint32_t *y_offset_sa
)
2275 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2277 /* For computing the intratile offsets, we actually want a strange unit
2278 * which is samples for multisampled surfaces but elements for compressed
2281 assert(total_x_offset_sa
% fmtl
->bw
== 0);
2282 assert(total_y_offset_sa
% fmtl
->bh
== 0);
2283 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
2284 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
2286 isl_tiling_get_intratile_offset_el(tiling
, fmtl
->bpb
, row_pitch_B
,
2287 total_x_offset
, total_y_offset
,
2288 base_address_offset
,
2289 x_offset_sa
, y_offset_sa
);
2290 *x_offset_sa
*= fmtl
->bw
;
2291 *y_offset_sa
*= fmtl
->bh
;
2295 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2297 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2298 * @pre surf->format must be a valid format for depth surfaces
2301 isl_surf_get_depth_format(const struct isl_device
*dev
,
2302 const struct isl_surf
*surf
);
2305 * @brief performs a copy from linear to tiled surface
2309 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
2310 uint32_t yt1
, uint32_t yt2
,
2311 char *dst
, const char *src
,
2312 uint32_t dst_pitch
, int32_t src_pitch
,
2314 enum isl_tiling tiling
,
2315 isl_memcpy_type copy_type
);
2318 * @brief performs a copy from tiled to linear surface
2322 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
2323 uint32_t yt1
, uint32_t yt2
,
2324 char *dst
, const char *src
,
2325 int32_t dst_pitch
, uint32_t src_pitch
,
2327 enum isl_tiling tiling
,
2328 isl_memcpy_type copy_type
);