2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
44 #include "util/macros.h"
50 struct brw_device_info
;
51 struct brw_image_param
;
55 * @brief Get the hardware generation of isl_device.
57 * You can define this as a compile-time constant in the CFLAGS. For example,
58 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #ifndef ISL_DEV_IS_HASWELL
65 * @brief Get the hardware generation of isl_device.
67 * You can define this as a compile-time constant in the CFLAGS. For example,
68 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
70 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
73 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
75 * You can define this as a compile-time constant in the CFLAGS. For example,
76 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
78 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
82 * Hardware enumeration SURFACE_FORMAT.
84 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
85 * Enumerations: SURFACE_FORMAT.
88 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
89 ISL_FORMAT_R32G32B32A32_SINT
= 1,
90 ISL_FORMAT_R32G32B32A32_UINT
= 2,
91 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
92 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
93 ISL_FORMAT_R64G64_FLOAT
= 5,
94 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
95 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
96 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
97 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
98 ISL_FORMAT_R64G64_PASSTHRU
= 33,
99 ISL_FORMAT_R32G32B32_FLOAT
= 64,
100 ISL_FORMAT_R32G32B32_SINT
= 65,
101 ISL_FORMAT_R32G32B32_UINT
= 66,
102 ISL_FORMAT_R32G32B32_UNORM
= 67,
103 ISL_FORMAT_R32G32B32_SNORM
= 68,
104 ISL_FORMAT_R32G32B32_SSCALED
= 69,
105 ISL_FORMAT_R32G32B32_USCALED
= 70,
106 ISL_FORMAT_R32G32B32_SFIXED
= 80,
107 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
108 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
109 ISL_FORMAT_R16G16B16A16_SINT
= 130,
110 ISL_FORMAT_R16G16B16A16_UINT
= 131,
111 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
112 ISL_FORMAT_R32G32_FLOAT
= 133,
113 ISL_FORMAT_R32G32_SINT
= 134,
114 ISL_FORMAT_R32G32_UINT
= 135,
115 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
116 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
117 ISL_FORMAT_L32A32_FLOAT
= 138,
118 ISL_FORMAT_R32G32_UNORM
= 139,
119 ISL_FORMAT_R32G32_SNORM
= 140,
120 ISL_FORMAT_R64_FLOAT
= 141,
121 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
122 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
123 ISL_FORMAT_A32X32_FLOAT
= 144,
124 ISL_FORMAT_L32X32_FLOAT
= 145,
125 ISL_FORMAT_I32X32_FLOAT
= 146,
126 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
127 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
128 ISL_FORMAT_R32G32_SSCALED
= 149,
129 ISL_FORMAT_R32G32_USCALED
= 150,
130 ISL_FORMAT_R32G32_SFIXED
= 160,
131 ISL_FORMAT_R64_PASSTHRU
= 161,
132 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
133 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
134 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
135 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
136 ISL_FORMAT_R10G10B10A2_UINT
= 196,
137 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
138 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
139 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
140 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
141 ISL_FORMAT_R8G8B8A8_SINT
= 202,
142 ISL_FORMAT_R8G8B8A8_UINT
= 203,
143 ISL_FORMAT_R16G16_UNORM
= 204,
144 ISL_FORMAT_R16G16_SNORM
= 205,
145 ISL_FORMAT_R16G16_SINT
= 206,
146 ISL_FORMAT_R16G16_UINT
= 207,
147 ISL_FORMAT_R16G16_FLOAT
= 208,
148 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
149 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
150 ISL_FORMAT_R11G11B10_FLOAT
= 211,
151 ISL_FORMAT_R32_SINT
= 214,
152 ISL_FORMAT_R32_UINT
= 215,
153 ISL_FORMAT_R32_FLOAT
= 216,
154 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
155 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
156 ISL_FORMAT_L32_UNORM
= 221,
157 ISL_FORMAT_A32_UNORM
= 222,
158 ISL_FORMAT_L16A16_UNORM
= 223,
159 ISL_FORMAT_I24X8_UNORM
= 224,
160 ISL_FORMAT_L24X8_UNORM
= 225,
161 ISL_FORMAT_A24X8_UNORM
= 226,
162 ISL_FORMAT_I32_FLOAT
= 227,
163 ISL_FORMAT_L32_FLOAT
= 228,
164 ISL_FORMAT_A32_FLOAT
= 229,
165 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
166 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
167 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
168 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
169 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
170 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
171 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
172 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
173 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
174 ISL_FORMAT_L16A16_FLOAT
= 240,
175 ISL_FORMAT_R32_UNORM
= 241,
176 ISL_FORMAT_R32_SNORM
= 242,
177 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
178 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
179 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
180 ISL_FORMAT_R16G16_SSCALED
= 246,
181 ISL_FORMAT_R16G16_USCALED
= 247,
182 ISL_FORMAT_R32_SSCALED
= 248,
183 ISL_FORMAT_R32_USCALED
= 249,
184 ISL_FORMAT_B5G6R5_UNORM
= 256,
185 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
186 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
187 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
188 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
189 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
190 ISL_FORMAT_R8G8_UNORM
= 262,
191 ISL_FORMAT_R8G8_SNORM
= 263,
192 ISL_FORMAT_R8G8_SINT
= 264,
193 ISL_FORMAT_R8G8_UINT
= 265,
194 ISL_FORMAT_R16_UNORM
= 266,
195 ISL_FORMAT_R16_SNORM
= 267,
196 ISL_FORMAT_R16_SINT
= 268,
197 ISL_FORMAT_R16_UINT
= 269,
198 ISL_FORMAT_R16_FLOAT
= 270,
199 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
200 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
201 ISL_FORMAT_I16_UNORM
= 273,
202 ISL_FORMAT_L16_UNORM
= 274,
203 ISL_FORMAT_A16_UNORM
= 275,
204 ISL_FORMAT_L8A8_UNORM
= 276,
205 ISL_FORMAT_I16_FLOAT
= 277,
206 ISL_FORMAT_L16_FLOAT
= 278,
207 ISL_FORMAT_A16_FLOAT
= 279,
208 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
209 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
210 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
211 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
212 ISL_FORMAT_R8G8_SSCALED
= 284,
213 ISL_FORMAT_R8G8_USCALED
= 285,
214 ISL_FORMAT_R16_SSCALED
= 286,
215 ISL_FORMAT_R16_USCALED
= 287,
216 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
217 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
218 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
219 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
220 ISL_FORMAT_L8A8_UINT
= 294,
221 ISL_FORMAT_L8A8_SINT
= 295,
222 ISL_FORMAT_R8_UNORM
= 320,
223 ISL_FORMAT_R8_SNORM
= 321,
224 ISL_FORMAT_R8_SINT
= 322,
225 ISL_FORMAT_R8_UINT
= 323,
226 ISL_FORMAT_A8_UNORM
= 324,
227 ISL_FORMAT_I8_UNORM
= 325,
228 ISL_FORMAT_L8_UNORM
= 326,
229 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
230 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
231 ISL_FORMAT_R8_SSCALED
= 329,
232 ISL_FORMAT_R8_USCALED
= 330,
233 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
234 ISL_FORMAT_L8_UNORM_SRGB
= 332,
235 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
236 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
237 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
238 ISL_FORMAT_Y8_UNORM
= 336,
239 ISL_FORMAT_L8_UINT
= 338,
240 ISL_FORMAT_L8_SINT
= 339,
241 ISL_FORMAT_I8_UINT
= 340,
242 ISL_FORMAT_I8_SINT
= 341,
243 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
244 ISL_FORMAT_R1_UNORM
= 385,
245 ISL_FORMAT_YCRCB_NORMAL
= 386,
246 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
247 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
248 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
249 ISL_FORMAT_BC1_UNORM
= 390,
250 ISL_FORMAT_BC2_UNORM
= 391,
251 ISL_FORMAT_BC3_UNORM
= 392,
252 ISL_FORMAT_BC4_UNORM
= 393,
253 ISL_FORMAT_BC5_UNORM
= 394,
254 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
255 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
256 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
257 ISL_FORMAT_MONO8
= 398,
258 ISL_FORMAT_YCRCB_SWAPUV
= 399,
259 ISL_FORMAT_YCRCB_SWAPY
= 400,
260 ISL_FORMAT_DXT1_RGB
= 401,
261 ISL_FORMAT_FXT1
= 402,
262 ISL_FORMAT_R8G8B8_UNORM
= 403,
263 ISL_FORMAT_R8G8B8_SNORM
= 404,
264 ISL_FORMAT_R8G8B8_SSCALED
= 405,
265 ISL_FORMAT_R8G8B8_USCALED
= 406,
266 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
267 ISL_FORMAT_R64G64B64_FLOAT
= 408,
268 ISL_FORMAT_BC4_SNORM
= 409,
269 ISL_FORMAT_BC5_SNORM
= 410,
270 ISL_FORMAT_R16G16B16_FLOAT
= 411,
271 ISL_FORMAT_R16G16B16_UNORM
= 412,
272 ISL_FORMAT_R16G16B16_SNORM
= 413,
273 ISL_FORMAT_R16G16B16_SSCALED
= 414,
274 ISL_FORMAT_R16G16B16_USCALED
= 415,
275 ISL_FORMAT_BC6H_SF16
= 417,
276 ISL_FORMAT_BC7_UNORM
= 418,
277 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
278 ISL_FORMAT_BC6H_UF16
= 420,
279 ISL_FORMAT_PLANAR_420_8
= 421,
280 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
281 ISL_FORMAT_ETC1_RGB8
= 425,
282 ISL_FORMAT_ETC2_RGB8
= 426,
283 ISL_FORMAT_EAC_R11
= 427,
284 ISL_FORMAT_EAC_RG11
= 428,
285 ISL_FORMAT_EAC_SIGNED_R11
= 429,
286 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
287 ISL_FORMAT_ETC2_SRGB8
= 431,
288 ISL_FORMAT_R16G16B16_UINT
= 432,
289 ISL_FORMAT_R16G16B16_SINT
= 433,
290 ISL_FORMAT_R32_SFIXED
= 434,
291 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
292 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
293 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
294 ISL_FORMAT_R10G10B10A2_SINT
= 438,
295 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
296 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
297 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
298 ISL_FORMAT_B10G10R10A2_UINT
= 442,
299 ISL_FORMAT_B10G10R10A2_SINT
= 443,
300 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
301 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
302 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
303 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
304 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
305 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
306 ISL_FORMAT_R8G8B8_UINT
= 456,
307 ISL_FORMAT_R8G8B8_SINT
= 457,
308 ISL_FORMAT_RAW
= 511,
310 /* Hardware doesn't understand this out-of-band value */
311 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
315 * Numerical base type for channels of isl_format.
333 * Colorspace of isl_format.
335 enum isl_colorspace
{
336 ISL_COLORSPACE_NONE
= 0,
337 ISL_COLORSPACE_LINEAR
,
343 * Texture compression mode of isl_format.
359 * @brief Hardware tile mode
361 * WARNING: These values differ from the hardware enum values, which are
362 * unstable across hardware generations.
364 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
365 * clearly distinguish it from Yf and Ys.
368 ISL_TILING_LINEAR
= 0,
371 ISL_TILING_Y0
, /**< Legacy Y tiling */
372 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
373 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
377 * @defgroup Tiling Flags
380 typedef uint32_t isl_tiling_flags_t
;
381 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
382 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
383 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
384 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
385 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
386 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
387 #define ISL_TILING_ANY_MASK (~0u)
388 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
390 /** Any Y tiling, including legacy Y tiling. */
391 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
392 ISL_TILING_Yf_BIT | \
395 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
396 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
401 * @brief Logical dimension of surface.
403 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
404 * as 2D array surfaces.
413 * @brief Physical layout of the surface's dimensions.
415 enum isl_dim_layout
{
417 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
418 * 6.17.3: 2D Surfaces.
420 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
421 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
423 * One-dimensional surfaces are identical to 2D surfaces with height of
426 * @invariant isl_surf::phys_level0_sa::depth == 1
428 ISL_DIM_LAYOUT_GEN4_2D
,
431 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
432 * 6.17.5: 3D Surfaces.
434 * @invariant isl_surf::phys_level0_sa::array_len == 1
436 ISL_DIM_LAYOUT_GEN4_3D
,
439 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
440 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
442 ISL_DIM_LAYOUT_GEN9_1D
,
445 /* TODO(chadv): Explain */
446 enum isl_array_pitch_span
{
447 ISL_ARRAY_PITCH_SPAN_FULL
,
448 ISL_ARRAY_PITCH_SPAN_COMPACT
,
452 * @defgroup Surface Usage
455 typedef uint64_t isl_surf_usage_flags_t
;
456 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
457 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
458 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
459 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
460 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
461 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
462 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
463 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
464 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
465 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
466 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
467 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
468 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
472 * @brief A channel select (also known as texture swizzle) value
474 enum isl_channel_select
{
475 ISL_CHANNEL_SELECT_ZERO
= 0,
476 ISL_CHANNEL_SELECT_ONE
= 1,
477 ISL_CHANNEL_SELECT_RED
= 4,
478 ISL_CHANNEL_SELECT_GREEN
= 5,
479 ISL_CHANNEL_SELECT_BLUE
= 6,
480 ISL_CHANNEL_SELECT_ALPHA
= 7,
484 * Identical to VkSampleCountFlagBits.
486 enum isl_sample_count
{
487 ISL_SAMPLE_COUNT_1_BIT
= 1u,
488 ISL_SAMPLE_COUNT_2_BIT
= 2u,
489 ISL_SAMPLE_COUNT_4_BIT
= 4u,
490 ISL_SAMPLE_COUNT_8_BIT
= 8u,
491 ISL_SAMPLE_COUNT_16_BIT
= 16u,
493 typedef uint32_t isl_sample_count_mask_t
;
496 * @brief Multisample Format
498 enum isl_msaa_layout
{
500 * @brief Suface is single-sampled.
502 ISL_MSAA_LAYOUT_NONE
,
505 * @brief [SNB+] Interleaved Multisample Format
507 * In this format, multiple samples are interleaved into each cacheline.
508 * In other words, the sample index is swizzled into the low 6 bits of the
509 * surface's virtual address space.
511 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
512 * and its pixel format is 32bpp. Then the first cacheline is arranged
515 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
516 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
518 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
519 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
521 * The hardware docs refer to this format with multiple terms. In
522 * Sandybridge, this is the only multisample format; so no term is used.
523 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
524 * Multisample Surface). Later hardware docs additionally refer to this
525 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
528 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
531 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
532 * Multisampled Surfaces".
534 ISL_MSAA_LAYOUT_INTERLEAVED
,
537 * @brief [IVB+] Array Multisample Format
539 * In this format, the surface's physical layout resembles that of a
542 * Suppose the multisample surface's logical extent is (w, h) and its
543 * sample count is N. Then surface's physical extent is the same as
544 * a singlesample 2D surface whose logical extent is (w, h) and array
545 * length is N. Array slice `i` contains the pixel values for sample
548 * The Ivybridge docs refer to surfaces in this format as UMS
549 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
550 * Surface). The Broadwell docs additionally refer to this format as
551 * MSFMT_MSS (MSS=Multisample Surface Storage).
553 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
554 * Multisample Surfaces".
556 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
557 * Multisample Surfaces".
559 ISL_MSAA_LAYOUT_ARRAY
,
564 const struct brw_device_info
*info
;
565 bool use_separate_stencil
;
566 bool has_bit6_swizzling
;
569 struct isl_extent2d
{
570 union { uint32_t w
, width
; };
571 union { uint32_t h
, height
; };
574 struct isl_extent3d
{
575 union { uint32_t w
, width
; };
576 union { uint32_t h
, height
; };
577 union { uint32_t d
, depth
; };
580 struct isl_extent4d
{
581 union { uint32_t w
, width
; };
582 union { uint32_t h
, height
; };
583 union { uint32_t d
, depth
; };
584 union { uint32_t a
, array_len
; };
587 struct isl_channel_layout
{
588 enum isl_base_type type
;
589 uint8_t bits
; /**< Size in bits */
593 * Each format has 3D block extent (width, height, depth). The block extent of
594 * compressed formats is that of the format's compression block. For example,
595 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
596 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
597 * is (w=1, h=1, d=1).
599 struct isl_format_layout
{
600 enum isl_format format
;
602 uint8_t bs
; /**< Block size, in bytes, rounded towards 0 */
603 uint8_t bw
; /**< Block width, in pixels */
604 uint8_t bh
; /**< Block height, in pixels */
605 uint8_t bd
; /**< Block depth, in pixels */
608 struct isl_channel_layout r
; /**< Red channel */
609 struct isl_channel_layout g
; /**< Green channel */
610 struct isl_channel_layout b
; /**< Blue channel */
611 struct isl_channel_layout a
; /**< Alpha channel */
612 struct isl_channel_layout l
; /**< Luminance channel */
613 struct isl_channel_layout i
; /**< Intensity channel */
614 struct isl_channel_layout p
; /**< Palette channel */
617 enum isl_colorspace colorspace
;
621 struct isl_tile_info
{
622 enum isl_tiling tiling
;
623 uint32_t width
; /**< in bytes */
624 uint32_t height
; /**< in rows of memory */
625 uint32_t size
; /**< in bytes */
629 * @brief Input to surface initialization
631 * @invariant width >= 1
632 * @invariant height >= 1
633 * @invariant depth >= 1
634 * @invariant levels >= 1
635 * @invariant samples >= 1
636 * @invariant array_len >= 1
638 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
639 * @invariant if 2D then depth == 1
640 * @invariant if 3D then array_len == 1 and samples == 1
642 struct isl_surf_init_info
{
643 enum isl_surf_dim dim
;
644 enum isl_format format
;
653 /** Lower bound for isl_surf::alignment, in bytes. */
654 uint32_t min_alignment
;
656 /** Lower bound for isl_surf::pitch, in bytes. */
659 isl_surf_usage_flags_t usage
;
661 /** Flags that alter how ISL selects isl_surf::tiling. */
662 isl_tiling_flags_t tiling_flags
;
666 enum isl_surf_dim dim
;
667 enum isl_dim_layout dim_layout
;
668 enum isl_msaa_layout msaa_layout
;
669 enum isl_tiling tiling
;
670 enum isl_format format
;
673 * Alignment of the upper-left sample of each subimage, in units of surface
676 struct isl_extent3d image_alignment_el
;
679 * Logical extent of the surface's base level, in units of pixels. This is
680 * identical to the extent defined in isl_surf_init_info.
682 struct isl_extent4d logical_level0_px
;
685 * Physical extent of the surface's base level, in units of physical
686 * surface samples and aligned to the format's compression block.
688 * Consider isl_dim_layout as an operator that transforms a logical surface
689 * layout to a physical surface layout. Then
691 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
692 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
694 struct isl_extent4d phys_level0_sa
;
699 /** Total size of the surface, in bytes. */
702 /** Required alignment for the surface's base address. */
706 * Pitch between vertically adjacent surface elements, in bytes.
711 * Pitch between physical array slices, in rows of surface elements.
713 uint32_t array_pitch_el_rows
;
715 enum isl_array_pitch_span array_pitch_span
;
717 /** Copy of isl_surf_init_info::usage. */
718 isl_surf_usage_flags_t usage
;
723 * Indicates the usage of the particular view
725 * Normally, this is one bit. However, for a cube map texture, it
726 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
728 isl_surf_usage_flags_t usage
;
731 * The format to use in the view
733 * This may differ from the format of the actual isl_surf but must have
734 * the same block size.
736 enum isl_format format
;
744 * For cube maps, both base_array_layer and array_len should be
745 * specified in terms of 2-D layers and must be a multiple of 6.
747 uint32_t base_array_layer
;
750 enum isl_channel_select channel_select
[4];
753 union isl_color_value
{
759 struct isl_surf_fill_state_info
{
760 const struct isl_surf
*surf
;
761 const struct isl_view
*view
;
764 * The address of the surface in GPU memory.
769 * The Memory Object Control state for the filled surface state.
771 * The exact format of this value depends on hardware generation.
776 * The clear color for this surface
778 * Valid values depend on hardware generation.
780 union isl_color_value clear_color
;
783 struct isl_buffer_fill_state_info
{
785 * The address of the surface in GPU memory.
790 * The size of the buffer
795 * The Memory Object Control state for the filled surface state.
797 * The exact format of this value depends on hardware generation.
802 * The format to use in the surface state
804 * This may differ from the format of the actual isl_surf but have the
807 enum isl_format format
;
812 extern const struct isl_format_layout isl_format_layouts
[];
815 isl_device_init(struct isl_device
*dev
,
816 const struct brw_device_info
*info
,
817 bool has_bit6_swizzling
);
819 isl_sample_count_mask_t ATTRIBUTE_CONST
820 isl_device_get_sample_counts(struct isl_device
*dev
);
822 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
823 isl_format_get_layout(enum isl_format fmt
)
825 return &isl_format_layouts
[fmt
];
829 isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
832 isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
835 isl_format_has_int_channel(enum isl_format fmt
)
837 return isl_format_has_uint_channel(fmt
) ||
838 isl_format_has_sint_channel(fmt
);
842 isl_format_is_compressed(enum isl_format fmt
)
844 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
846 return fmtl
->txc
!= ISL_TXC_NONE
;
850 isl_format_has_bc_compression(enum isl_format fmt
)
852 switch (isl_format_get_layout(fmt
)->txc
) {
867 unreachable("bad texture compression mode");
872 isl_format_is_yuv(enum isl_format fmt
)
874 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
876 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
880 isl_format_block_is_1x1x1(enum isl_format fmt
)
882 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
884 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
888 isl_format_is_rgb(enum isl_format fmt
)
890 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
891 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
892 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
893 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
896 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
897 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
899 bool isl_is_storage_image_format(enum isl_format fmt
);
902 isl_lower_storage_image_format(const struct isl_device
*dev
,
903 enum isl_format fmt
);
906 isl_tiling_is_any_y(enum isl_tiling tiling
)
908 return (1u << tiling
) & ISL_TILING_ANY_MASK
;
912 isl_tiling_is_std_y(enum isl_tiling tiling
)
914 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
918 isl_tiling_get_info(const struct isl_device
*dev
,
919 enum isl_tiling tiling
,
920 uint32_t format_block_size
,
921 struct isl_tile_info
*info
);
924 isl_tiling_get_extent(const struct isl_device
*dev
,
925 enum isl_tiling tiling
,
926 uint32_t format_block_size
,
927 struct isl_extent2d
*e
);
929 isl_surf_choose_tiling(const struct isl_device
*dev
,
930 const struct isl_surf_init_info
*restrict info
,
931 enum isl_tiling
*tiling
);
934 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
936 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
940 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
942 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
946 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
948 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
952 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
954 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
955 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
959 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
961 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
965 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
967 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
968 (info
->format
== ISL_FORMAT_R16_UNORM
);
972 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
974 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
975 (info
->format
== ISL_FORMAT_R32_FLOAT
);
978 static inline struct isl_extent2d
979 isl_extent2d(uint32_t width
, uint32_t height
)
981 return (struct isl_extent2d
) { .w
= width
, .h
= height
};
984 static inline struct isl_extent3d
985 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
987 return (struct isl_extent3d
) { .w
= width
, .h
= height
, .d
= depth
};
990 static inline struct isl_extent4d
991 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
994 return (struct isl_extent4d
) {
1002 #define isl_surf_init(dev, surf, ...) \
1003 isl_surf_init_s((dev), (surf), \
1004 &(struct isl_surf_init_info) { __VA_ARGS__ });
1007 isl_surf_init_s(const struct isl_device
*dev
,
1008 struct isl_surf
*surf
,
1009 const struct isl_surf_init_info
*restrict info
);
1012 isl_surf_get_tile_info(const struct isl_device
*dev
,
1013 const struct isl_surf
*surf
,
1014 struct isl_tile_info
*tile_info
);
1016 #define isl_surf_fill_state(dev, state, ...) \
1017 isl_surf_fill_state_s((dev), (state), \
1018 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1021 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1022 const struct isl_surf_fill_state_info
*restrict info
);
1024 #define isl_buffer_fill_state(dev, state, ...) \
1025 isl_buffer_fill_state_s((dev), (state), \
1026 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1029 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1030 const struct isl_buffer_fill_state_info
*restrict info
);
1033 isl_surf_fill_image_param(const struct isl_device
*dev
,
1034 struct brw_image_param
*param
,
1035 const struct isl_surf
*surf
,
1036 const struct isl_view
*view
);
1039 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1040 struct brw_image_param
*param
,
1041 enum isl_format format
,
1045 * Alignment of the upper-left sample of each subimage, in units of surface
1048 static inline struct isl_extent3d
1049 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1051 return surf
->image_alignment_el
;
1055 * Alignment of the upper-left sample of each subimage, in units of surface
1058 static inline struct isl_extent3d
1059 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1061 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1063 return (struct isl_extent3d
) {
1064 .w
= fmtl
->bw
* surf
->image_alignment_el
.w
,
1065 .h
= fmtl
->bh
* surf
->image_alignment_el
.h
,
1066 .d
= fmtl
->bd
* surf
->image_alignment_el
.d
,
1071 * Pitch between vertically adjacent surface elements, in bytes.
1073 static inline uint32_t
1074 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
1076 return surf
->row_pitch
;
1080 * Pitch between vertically adjacent surface elements, in units of surface elements.
1082 static inline uint32_t
1083 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1085 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1087 assert(surf
->row_pitch
% fmtl
->bs
== 0);
1088 return surf
->row_pitch
/ fmtl
->bs
;
1092 * Pitch between physical array slices, in rows of surface elements.
1094 static inline uint32_t
1095 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1097 return surf
->array_pitch_el_rows
;
1101 * Pitch between physical array slices, in units of surface elements.
1103 static inline uint32_t
1104 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1106 return isl_surf_get_array_pitch_el_rows(surf
) *
1107 isl_surf_get_row_pitch_el(surf
);
1111 * Pitch between physical array slices, in rows of surface samples.
1113 static inline uint32_t
1114 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1116 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1117 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1121 * Pitch between physical array slices, in bytes.
1123 static inline uint32_t
1124 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1126 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
1130 * Calculate the offset, in units of surface elements, to a subimage in the
1133 * @invariant level < surface levels
1134 * @invariant logical_array_layer < logical array length of surface
1135 * @invariant logical_z_offset_px < logical depth of surface at level
1138 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1140 uint32_t logical_array_layer
,
1141 uint32_t logical_z_offset_px
,
1142 uint32_t *x_offset_el
,
1143 uint32_t *y_offset_el
);
1146 * @brief Calculate the intratile offsets to a subimage in the surface.
1148 * In @a base_address_offset return the offset from the base of the surface to
1149 * the base address of the first tile of the subimage. In @a x_offset_el and
1150 * @a y_offset_el, return the offset, in units of surface elements, from the
1151 * tile's base to the subimage's first surface element. The x and y offsets
1152 * are intratile offsets; that is, they do not exceed the boundary of the
1153 * surface's tiling format.
1156 isl_surf_get_image_intratile_offset_el(const struct isl_device
*dev
,
1157 const struct isl_surf
*surf
,
1159 uint32_t logical_array_layer
,
1160 uint32_t logical_z_offset
,
1161 uint32_t *base_address_offset
,
1162 uint32_t *x_offset_el
,
1163 uint32_t *y_offset_el
);
1169 isl_surf_get_image_intratile_offset_el_xy(const struct isl_device
*dev
,
1170 const struct isl_surf
*surf
,
1171 uint32_t total_x_offset_el
,
1172 uint32_t total_y_offset_el
,
1173 uint32_t *base_address_offset
,
1174 uint32_t *x_offset_el
,
1175 uint32_t *y_offset_el
);
1178 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1180 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1181 * @pre surf->format must be a valid format for depth surfaces
1184 isl_surf_get_depth_format(const struct isl_device
*dev
,
1185 const struct isl_surf
*surf
);