2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
45 #include "c99_compat.h"
46 #include "util/macros.h"
52 struct gen_device_info
;
53 struct brw_image_param
;
57 * @brief Get the hardware generation of isl_device.
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
73 #ifndef ISL_DEV_IS_HASWELL
75 * @brief Get the hardware generation of isl_device.
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 * Hardware enumeration SURFACE_FORMAT.
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
106 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
107 ISL_FORMAT_R32G32B32A32_SINT
= 1,
108 ISL_FORMAT_R32G32B32A32_UINT
= 2,
109 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
110 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
111 ISL_FORMAT_R64G64_FLOAT
= 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
114 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
116 ISL_FORMAT_R64G64_PASSTHRU
= 33,
117 ISL_FORMAT_R32G32B32_FLOAT
= 64,
118 ISL_FORMAT_R32G32B32_SINT
= 65,
119 ISL_FORMAT_R32G32B32_UINT
= 66,
120 ISL_FORMAT_R32G32B32_UNORM
= 67,
121 ISL_FORMAT_R32G32B32_SNORM
= 68,
122 ISL_FORMAT_R32G32B32_SSCALED
= 69,
123 ISL_FORMAT_R32G32B32_USCALED
= 70,
124 ISL_FORMAT_R32G32B32_SFIXED
= 80,
125 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
126 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
127 ISL_FORMAT_R16G16B16A16_SINT
= 130,
128 ISL_FORMAT_R16G16B16A16_UINT
= 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
130 ISL_FORMAT_R32G32_FLOAT
= 133,
131 ISL_FORMAT_R32G32_SINT
= 134,
132 ISL_FORMAT_R32G32_UINT
= 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
135 ISL_FORMAT_L32A32_FLOAT
= 138,
136 ISL_FORMAT_R32G32_UNORM
= 139,
137 ISL_FORMAT_R32G32_SNORM
= 140,
138 ISL_FORMAT_R64_FLOAT
= 141,
139 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
141 ISL_FORMAT_A32X32_FLOAT
= 144,
142 ISL_FORMAT_L32X32_FLOAT
= 145,
143 ISL_FORMAT_I32X32_FLOAT
= 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
145 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
146 ISL_FORMAT_R32G32_SSCALED
= 149,
147 ISL_FORMAT_R32G32_USCALED
= 150,
148 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
149 ISL_FORMAT_R32G32_SFIXED
= 160,
150 ISL_FORMAT_R64_PASSTHRU
= 161,
151 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
153 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
155 ISL_FORMAT_R10G10B10A2_UINT
= 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
157 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
159 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
160 ISL_FORMAT_R8G8B8A8_SINT
= 202,
161 ISL_FORMAT_R8G8B8A8_UINT
= 203,
162 ISL_FORMAT_R16G16_UNORM
= 204,
163 ISL_FORMAT_R16G16_SNORM
= 205,
164 ISL_FORMAT_R16G16_SINT
= 206,
165 ISL_FORMAT_R16G16_UINT
= 207,
166 ISL_FORMAT_R16G16_FLOAT
= 208,
167 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
169 ISL_FORMAT_R11G11B10_FLOAT
= 211,
170 ISL_FORMAT_R32_SINT
= 214,
171 ISL_FORMAT_R32_UINT
= 215,
172 ISL_FORMAT_R32_FLOAT
= 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
175 ISL_FORMAT_L32_UNORM
= 221,
176 ISL_FORMAT_A32_UNORM
= 222,
177 ISL_FORMAT_L16A16_UNORM
= 223,
178 ISL_FORMAT_I24X8_UNORM
= 224,
179 ISL_FORMAT_L24X8_UNORM
= 225,
180 ISL_FORMAT_A24X8_UNORM
= 226,
181 ISL_FORMAT_I32_FLOAT
= 227,
182 ISL_FORMAT_L32_FLOAT
= 228,
183 ISL_FORMAT_A32_FLOAT
= 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
187 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
189 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
192 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
193 ISL_FORMAT_L16A16_FLOAT
= 240,
194 ISL_FORMAT_R32_UNORM
= 241,
195 ISL_FORMAT_R32_SNORM
= 242,
196 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
198 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
199 ISL_FORMAT_R16G16_SSCALED
= 246,
200 ISL_FORMAT_R16G16_USCALED
= 247,
201 ISL_FORMAT_R32_SSCALED
= 248,
202 ISL_FORMAT_R32_USCALED
= 249,
203 ISL_FORMAT_B5G6R5_UNORM
= 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
205 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
207 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
209 ISL_FORMAT_R8G8_UNORM
= 262,
210 ISL_FORMAT_R8G8_SNORM
= 263,
211 ISL_FORMAT_R8G8_SINT
= 264,
212 ISL_FORMAT_R8G8_UINT
= 265,
213 ISL_FORMAT_R16_UNORM
= 266,
214 ISL_FORMAT_R16_SNORM
= 267,
215 ISL_FORMAT_R16_SINT
= 268,
216 ISL_FORMAT_R16_UINT
= 269,
217 ISL_FORMAT_R16_FLOAT
= 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
220 ISL_FORMAT_I16_UNORM
= 273,
221 ISL_FORMAT_L16_UNORM
= 274,
222 ISL_FORMAT_A16_UNORM
= 275,
223 ISL_FORMAT_L8A8_UNORM
= 276,
224 ISL_FORMAT_I16_FLOAT
= 277,
225 ISL_FORMAT_L16_FLOAT
= 278,
226 ISL_FORMAT_A16_FLOAT
= 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
229 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
231 ISL_FORMAT_R8G8_SSCALED
= 284,
232 ISL_FORMAT_R8G8_USCALED
= 285,
233 ISL_FORMAT_R16_SSCALED
= 286,
234 ISL_FORMAT_R16_USCALED
= 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
237 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
238 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
239 ISL_FORMAT_L8A8_UINT
= 294,
240 ISL_FORMAT_L8A8_SINT
= 295,
241 ISL_FORMAT_R8_UNORM
= 320,
242 ISL_FORMAT_R8_SNORM
= 321,
243 ISL_FORMAT_R8_SINT
= 322,
244 ISL_FORMAT_R8_UINT
= 323,
245 ISL_FORMAT_A8_UNORM
= 324,
246 ISL_FORMAT_I8_UNORM
= 325,
247 ISL_FORMAT_L8_UNORM
= 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
250 ISL_FORMAT_R8_SSCALED
= 329,
251 ISL_FORMAT_R8_USCALED
= 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
253 ISL_FORMAT_L8_UNORM_SRGB
= 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
257 ISL_FORMAT_Y8_UNORM
= 336,
258 ISL_FORMAT_L8_UINT
= 338,
259 ISL_FORMAT_L8_SINT
= 339,
260 ISL_FORMAT_I8_UINT
= 340,
261 ISL_FORMAT_I8_SINT
= 341,
262 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
263 ISL_FORMAT_R1_UNORM
= 385,
264 ISL_FORMAT_YCRCB_NORMAL
= 386,
265 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
268 ISL_FORMAT_BC1_UNORM
= 390,
269 ISL_FORMAT_BC2_UNORM
= 391,
270 ISL_FORMAT_BC3_UNORM
= 392,
271 ISL_FORMAT_BC4_UNORM
= 393,
272 ISL_FORMAT_BC5_UNORM
= 394,
273 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
274 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
275 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
276 ISL_FORMAT_MONO8
= 398,
277 ISL_FORMAT_YCRCB_SWAPUV
= 399,
278 ISL_FORMAT_YCRCB_SWAPY
= 400,
279 ISL_FORMAT_DXT1_RGB
= 401,
280 ISL_FORMAT_FXT1
= 402,
281 ISL_FORMAT_R8G8B8_UNORM
= 403,
282 ISL_FORMAT_R8G8B8_SNORM
= 404,
283 ISL_FORMAT_R8G8B8_SSCALED
= 405,
284 ISL_FORMAT_R8G8B8_USCALED
= 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
286 ISL_FORMAT_R64G64B64_FLOAT
= 408,
287 ISL_FORMAT_BC4_SNORM
= 409,
288 ISL_FORMAT_BC5_SNORM
= 410,
289 ISL_FORMAT_R16G16B16_FLOAT
= 411,
290 ISL_FORMAT_R16G16B16_UNORM
= 412,
291 ISL_FORMAT_R16G16B16_SNORM
= 413,
292 ISL_FORMAT_R16G16B16_SSCALED
= 414,
293 ISL_FORMAT_R16G16B16_USCALED
= 415,
294 ISL_FORMAT_BC6H_SF16
= 417,
295 ISL_FORMAT_BC7_UNORM
= 418,
296 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
297 ISL_FORMAT_BC6H_UF16
= 420,
298 ISL_FORMAT_PLANAR_420_8
= 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
300 ISL_FORMAT_ETC1_RGB8
= 425,
301 ISL_FORMAT_ETC2_RGB8
= 426,
302 ISL_FORMAT_EAC_R11
= 427,
303 ISL_FORMAT_EAC_RG11
= 428,
304 ISL_FORMAT_EAC_SIGNED_R11
= 429,
305 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
306 ISL_FORMAT_ETC2_SRGB8
= 431,
307 ISL_FORMAT_R16G16B16_UINT
= 432,
308 ISL_FORMAT_R16G16B16_SINT
= 433,
309 ISL_FORMAT_R32_SFIXED
= 434,
310 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
311 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
313 ISL_FORMAT_R10G10B10A2_SINT
= 438,
314 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
315 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
317 ISL_FORMAT_B10G10R10A2_UINT
= 442,
318 ISL_FORMAT_B10G10R10A2_SINT
= 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
321 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
325 ISL_FORMAT_R8G8B8_UINT
= 456,
326 ISL_FORMAT_R8G8B8_SINT
= 457,
327 ISL_FORMAT_RAW
= 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16
= 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16
= 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16
= 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16
= 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16
= 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16
= 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16
= 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16
= 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16
= 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16
= 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16
= 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16
= 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16
= 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16
= 895,
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
376 /* Formats for auxiliary surfaces */
382 ISL_FORMAT_GEN7_CCS_32BPP_X
,
383 ISL_FORMAT_GEN7_CCS_64BPP_X
,
384 ISL_FORMAT_GEN7_CCS_128BPP_X
,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
388 ISL_FORMAT_GEN9_CCS_32BPP
,
389 ISL_FORMAT_GEN9_CCS_64BPP
,
390 ISL_FORMAT_GEN9_CCS_128BPP
,
392 /* An upper bound on the supported format enumerations */
395 /* Hardware doesn't understand this out-of-band value */
396 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
400 * Numerical base type for channels of isl_format.
418 * Colorspace of isl_format.
420 enum isl_colorspace
{
421 ISL_COLORSPACE_NONE
= 0,
422 ISL_COLORSPACE_LINEAR
,
428 * Texture compression mode of isl_format.
443 /* Used for auxiliary surface formats */
450 * @brief Hardware tile mode
452 * WARNING: These values differ from the hardware enum values, which are
453 * unstable across hardware generations.
455 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
456 * clearly distinguish it from Yf and Ys.
459 ISL_TILING_LINEAR
= 0,
462 ISL_TILING_Y0
, /**< Legacy Y tiling */
463 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
464 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
465 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
466 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
470 * @defgroup Tiling Flags
473 typedef uint32_t isl_tiling_flags_t
;
474 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
475 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
476 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
477 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
478 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
479 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
480 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
481 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
482 #define ISL_TILING_ANY_MASK (~0u)
483 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
485 /** Any Y tiling, including legacy Y tiling. */
486 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
487 ISL_TILING_Yf_BIT | \
490 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
491 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
496 * @brief Logical dimension of surface.
498 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
499 * as 2D array surfaces.
508 * @brief Physical layout of the surface's dimensions.
510 enum isl_dim_layout
{
512 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
513 * 6.17.3: 2D Surfaces.
515 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
516 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
518 * One-dimensional surfaces are identical to 2D surfaces with height of
521 * @invariant isl_surf::phys_level0_sa::depth == 1
523 ISL_DIM_LAYOUT_GEN4_2D
,
526 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
527 * 6.17.5: 3D Surfaces.
529 * @invariant isl_surf::phys_level0_sa::array_len == 1
531 ISL_DIM_LAYOUT_GEN4_3D
,
534 * Special layout used for HiZ and stencil on Sandy Bridge to work around
535 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
536 * work the same as on gen7+ except that they don't technically support
537 * mipmapping. That does not, however, stop us from doing it. As far as
538 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
539 * single miplevel 2D (possibly array) image. The dimensions of that image
542 * In order to implement HiZ and stencil on Sandy Bridge, we create one
543 * full-sized 2D (possibly array) image for every LOD with every image
544 * aligned to a page boundary. When the surface is used with the stencil
545 * or HiZ hardware, we manually offset to the image for the given LOD.
547 * As a memory saving measure, we pretend that the width of each miplevel
548 * is minified and we place LOD1 and above below LOD0 but horizontally
549 * adjacent to each other. When considered as full-sized images, LOD1 and
550 * above technically overlap. However, since we only write to part of that
551 * image, the hardware will never notice the overlap.
553 * This layout looks something like this:
571 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
,
574 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
575 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
577 ISL_DIM_LAYOUT_GEN9_1D
,
581 /** No Auxiliary surface is used */
584 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
587 /** The auxiliary surface is an MCS
589 * @invariant isl_surf::samples > 1
593 /** The auxiliary surface is a fast-clear-only compression surface
595 * @invariant isl_surf::samples == 1
599 /** The auxiliary surface provides full lossless color compression
601 * @invariant isl_surf::samples == 1
607 * Enum for keeping track of the state an auxiliary compressed surface.
609 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
610 * given slice (lod + array layer) can be in one of the six states described
611 * by this enum. Draw and resolve operations may cause the slice to change
612 * from one state to another. The six valid states are:
614 * 1) Clear: In this state, each block in the auxiliary surface contains a
615 * magic value that indicates that the block is in the clear state. If
616 * a block is in the clear state, it's values in the primary surface are
617 * ignored and the color of the samples in the block is taken either the
618 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
619 * depth. Since neither the primary surface nor the auxiliary surface
620 * contains the clear value, the surface can be cleared to a different
621 * color by simply changing the clear color without modifying either
624 * 2) Partial Clear: In this state, each block in the auxiliary surface
625 * contains either the magic clear or pass-through value. See Clear and
626 * Pass-through for more details.
628 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
629 * nor the primary surface has a complete representation of the data.
630 * Instead, both surfaces must be used together or else rendering
631 * corruption may occur. Depending on the auxiliary compression format
632 * and the data, any given block in the primary surface may contain all,
633 * some, or none of the data required to reconstruct the actual sample
634 * values. Blocks may also be in the clear state (see Clear) and have
635 * their value taken from outside the surface.
637 * 4) Compressed w/o Clear: This state is identical to the state above
638 * except that no blocks are in the clear state. In this state, all of
639 * the data required to reconstruct the final sample values is contained
640 * in the auxiliary and primary surface and the clear value is not
643 * 5) Resolved: In this state, the primary surface contains 100% of the
644 * data. The auxiliary surface is also valid so the surface can be
645 * validly used with or without aux enabled. The auxiliary surface may,
646 * however, contain non-trivial data and any update to the primary
647 * surface with aux disabled will cause the two to get out of sync.
649 * 6) Pass-through: In this state, the primary surface contains 100% of the
650 * data and every block in the auxiliary surface contains a magic value
651 * which indicates that the auxiliary surface should be ignored and the
652 * only the primary surface should be considered. Updating the primary
653 * surface without aux works fine and can be done repeatedly in this
654 * mode. Writing to a surface in pass-through mode with aux enabled may
655 * cause the auxiliary buffer to contain non-trivial data and no longer
656 * be in the pass-through state.
658 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
659 * data and the auxiliary surface is completely bogus. Any attempt to
660 * use the auxiliary surface is liable to result in rendering
661 * corruption. The only thing that one can do to re-enable aux once
662 * this state is reached is to use an ambiguate pass to transition into
663 * the pass-through state.
665 * Drawing with or without aux enabled may implicitly cause the surface to
666 * transition between these states. There are also four types of auxiliary
667 * compression operations which cause an explicit transition which are
668 * described by the isl_aux_op enum below.
670 * Not all operations are valid or useful in all states. The diagram below
671 * contains a complete description of the states and all valid and useful
672 * transitions except clear.
677 * | +-------------+ Draw w/ Aux +-------------+
678 * +------>| Compressed |<-------------------| Clear |
679 * | w/ Clear |----->----+ | |
680 * +-------------+ | +-------------+
683 * | | +------<-----+ | Draw w/
685 * | | Full | | +----------+
686 * Partial | | Resolve | \|/ | |
687 * Resolve | | | +-------------+ |
688 * | | | | Partial |<------+
689 * | | | | Clear |<----------+
690 * | | | +-------------+ |
692 * | | +------>---------+ Full |
694 * Draw w/ aux | | Partial Fast Clear | |
695 * +----------+ | +--------------------------+ | |
697 * | +-------------+ Full Resolve +-------------+ |
698 * +------>| Compressed |------------------->| Resolved | |
699 * | w/o Clear |<-------------------| | |
700 * +-------------+ Draw w/ Aux +-------------+ |
703 * | w/ Aux | | w/o Aux |
705 * | +--------------------------+ | |
706 * Draw w/o Aux | | | Draw w/o Aux |
707 * +----------+ | | | +----------+ |
708 * | | | \|/ \|/ | | |
709 * | +-------------+ Ambiguate +-------------+ | |
710 * +------>| Pass- |<-------------------| Aux |<------+ |
711 * +------>| through | | Invalid | |
712 * | +-------------+ +-------------+ |
714 * +----------+ +-----------------------------------------------------+
715 * Draw w/ Partial Fast Clear
719 * While the above general theory applies to all forms of auxiliary
720 * compression on Intel hardware, not all states and operations are available
721 * on all compression types. However, each of the auxiliary states and
722 * operations can be fairly easily mapped onto the above diagram:
724 * HiZ: Hierarchical depth compression is capable of being in any of the
725 * states above. Hardware provides three HiZ operations: "Depth
726 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
727 * Clear", "Full Resolve", and "Ambiguate" respectively. The
728 * hardware provides no HiZ partial resolve operation so the only way
729 * to get into the "Compressed w/o Clear" state is to render with HiZ
730 * when the surface is in the resolved or pass-through states.
732 * MCS: Multisample compression is technically capable of being in any of
733 * the states above except that most of them aren't useful. Both the
734 * render engine and the sampler support MCS compression and, apart
735 * from clear color, MCS is format-unaware so we leave the surface
736 * compressed 100% of the time. The hardware provides no MCS
739 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
740 * the simplest forms of compression since they don't do anything
741 * beyond clear color tracking. They really only support three of
742 * the six states: Clear, Partial Clear, and Pass-through. The
743 * only CCS_D operation is "Resolve" which maps to a full resolve
744 * followed by an ambiguate.
746 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
747 * is capable of being in almost all of the above states. THe only
748 * exception is that it does not have separate resolved and pass-
749 * through states. Instead, the CCS_E full resolve operation does
750 * both a resolve and an ambiguate so it goes directly into the
751 * pass-through state. CCS_E also provides fast clear and partial
752 * resolve operations which work as described above.
754 * While it is technically possible to perform a CCS_E ambiguate, it
755 * is not provided by Sky Lake hardware so we choose to avoid the aux
756 * invalid state. If the aux invalid state were determined to be
757 * useful, a CCS ambiguate could be done by carefully rendering to
758 * the CCS and filling it with zeros.
761 ISL_AUX_STATE_CLEAR
= 0,
762 ISL_AUX_STATE_PARTIAL_CLEAR
,
763 ISL_AUX_STATE_COMPRESSED_CLEAR
,
764 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
,
765 ISL_AUX_STATE_RESOLVED
,
766 ISL_AUX_STATE_PASS_THROUGH
,
767 ISL_AUX_STATE_AUX_INVALID
,
771 * Enum which describes explicit aux transition operations.
778 * This operation writes the magic "clear" value to the auxiliary surface.
779 * This operation will safely transition any slice of a surface from any
780 * state to the clear state so long as the entire slice is fast cleared at
781 * once. A fast clear that only covers part of a slice of a surface is
782 * called a partial fast clear.
784 ISL_AUX_OP_FAST_CLEAR
,
788 * This operation combines the auxiliary surface data with the primary
789 * surface data and writes the result to the primary. For HiZ, the docs
790 * call this a depth resolve. For CCS, the hardware full resolve operation
791 * does both a full resolve and an ambiguate so it actually takes you all
792 * the way to the pass-through state.
794 ISL_AUX_OP_FULL_RESOLVE
,
798 * This operation considers blocks which are in the "clear" state and
799 * writes the clear value directly into the primary or auxiliary surface.
800 * Once this operation completes, the surface is still compressed but no
801 * longer references the clear color. This operation is only available
804 ISL_AUX_OP_PARTIAL_RESOLVE
,
808 * This operation throws away the current auxiliary data and replaces it
809 * with the magic pass-through value. If an ambiguate operation is
810 * performed when the primary surface does not contain 100% of the data,
811 * data will be lost. This operation is only implemented in hardware for
812 * depth where it is called a HiZ resolve.
814 ISL_AUX_OP_AMBIGUATE
,
817 /* TODO(chadv): Explain */
818 enum isl_array_pitch_span
{
819 ISL_ARRAY_PITCH_SPAN_FULL
,
820 ISL_ARRAY_PITCH_SPAN_COMPACT
,
824 * @defgroup Surface Usage
827 typedef uint64_t isl_surf_usage_flags_t
;
828 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
829 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
830 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
831 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
832 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
833 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
834 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
835 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
836 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
837 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
838 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
839 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
840 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
841 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
842 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
843 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
847 * @defgroup Channel Mask
849 * These #define values are chosen to match the values of
850 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
854 typedef uint8_t isl_channel_mask_t
;
855 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
856 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
857 #define ISL_CHANNEL_RED_BIT (1 << 2)
858 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
862 * @brief A channel select (also known as texture swizzle) value
864 enum PACKED isl_channel_select
{
865 ISL_CHANNEL_SELECT_ZERO
= 0,
866 ISL_CHANNEL_SELECT_ONE
= 1,
867 ISL_CHANNEL_SELECT_RED
= 4,
868 ISL_CHANNEL_SELECT_GREEN
= 5,
869 ISL_CHANNEL_SELECT_BLUE
= 6,
870 ISL_CHANNEL_SELECT_ALPHA
= 7,
874 * Identical to VkSampleCountFlagBits.
876 enum isl_sample_count
{
877 ISL_SAMPLE_COUNT_1_BIT
= 1u,
878 ISL_SAMPLE_COUNT_2_BIT
= 2u,
879 ISL_SAMPLE_COUNT_4_BIT
= 4u,
880 ISL_SAMPLE_COUNT_8_BIT
= 8u,
881 ISL_SAMPLE_COUNT_16_BIT
= 16u,
883 typedef uint32_t isl_sample_count_mask_t
;
886 * @brief Multisample Format
888 enum isl_msaa_layout
{
890 * @brief Suface is single-sampled.
892 ISL_MSAA_LAYOUT_NONE
,
895 * @brief [SNB+] Interleaved Multisample Format
897 * In this format, multiple samples are interleaved into each cacheline.
898 * In other words, the sample index is swizzled into the low 6 bits of the
899 * surface's virtual address space.
901 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
902 * and its pixel format is 32bpp. Then the first cacheline is arranged
905 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
906 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
908 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
909 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
911 * The hardware docs refer to this format with multiple terms. In
912 * Sandybridge, this is the only multisample format; so no term is used.
913 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
914 * Multisample Surface). Later hardware docs additionally refer to this
915 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
918 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
921 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
922 * Multisampled Surfaces".
924 ISL_MSAA_LAYOUT_INTERLEAVED
,
927 * @brief [IVB+] Array Multisample Format
929 * In this format, the surface's physical layout resembles that of a
932 * Suppose the multisample surface's logical extent is (w, h) and its
933 * sample count is N. Then surface's physical extent is the same as
934 * a singlesample 2D surface whose logical extent is (w, h) and array
935 * length is N. Array slice `i` contains the pixel values for sample
938 * The Ivybridge docs refer to surfaces in this format as UMS
939 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
940 * Surface). The Broadwell docs additionally refer to this format as
941 * MSFMT_MSS (MSS=Multisample Surface Storage).
943 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
944 * Multisample Surfaces".
946 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
947 * Multisample Surfaces".
949 ISL_MSAA_LAYOUT_ARRAY
,
955 ISL_MEMCPY_STREAMING_LOAD
,
960 const struct gen_device_info
*info
;
961 bool use_separate_stencil
;
962 bool has_bit6_swizzling
;
965 * Describes the layout of a RENDER_SURFACE_STATE structure for the
972 uint8_t aux_addr_offset
;
974 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
976 /* size of the state buffer used to store the clear color + extra
977 * additional space used by the hardware */
978 uint8_t clear_color_state_size
;
979 uint8_t clear_color_state_offset
;
980 /* size of the clear color itself - used to copy it to/from a BO */
981 uint8_t clear_value_size
;
982 uint8_t clear_value_offset
;
986 * Describes the layout of the depth/stencil/hiz commands as emitted by
987 * isl_emit_depth_stencil_hiz.
991 uint8_t depth_offset
;
992 uint8_t stencil_offset
;
997 struct isl_extent2d
{
998 union { uint32_t w
, width
; };
999 union { uint32_t h
, height
; };
1002 struct isl_extent3d
{
1003 union { uint32_t w
, width
; };
1004 union { uint32_t h
, height
; };
1005 union { uint32_t d
, depth
; };
1008 struct isl_extent4d
{
1009 union { uint32_t w
, width
; };
1010 union { uint32_t h
, height
; };
1011 union { uint32_t d
, depth
; };
1012 union { uint32_t a
, array_len
; };
1015 struct isl_channel_layout
{
1016 enum isl_base_type type
;
1017 uint8_t start_bit
; /**< Bit at which this channel starts */
1018 uint8_t bits
; /**< Size in bits */
1022 * Each format has 3D block extent (width, height, depth). The block extent of
1023 * compressed formats is that of the format's compression block. For example,
1024 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1025 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1026 * is (w=1, h=1, d=1).
1028 struct isl_format_layout
{
1029 enum isl_format format
;
1032 uint16_t bpb
; /**< Bits per block */
1033 uint8_t bw
; /**< Block width, in pixels */
1034 uint8_t bh
; /**< Block height, in pixels */
1035 uint8_t bd
; /**< Block depth, in pixels */
1039 struct isl_channel_layout r
; /**< Red channel */
1040 struct isl_channel_layout g
; /**< Green channel */
1041 struct isl_channel_layout b
; /**< Blue channel */
1042 struct isl_channel_layout a
; /**< Alpha channel */
1043 struct isl_channel_layout l
; /**< Luminance channel */
1044 struct isl_channel_layout i
; /**< Intensity channel */
1045 struct isl_channel_layout p
; /**< Palette channel */
1047 struct isl_channel_layout channels_array
[7];
1050 enum isl_colorspace colorspace
;
1054 struct isl_tile_info
{
1055 enum isl_tiling tiling
;
1057 /* The size (in bits per block) of a single surface element
1059 * For surfaces with power-of-two formats, this is the same as
1060 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1061 * The logical_extent_el field is in terms of elements of this size.
1063 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1064 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1065 * of the tiling formats can actually hold an integer number of 96-bit
1066 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1067 * 32-bit element size. It is the responsibility of the caller to
1068 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1069 * the width of a surface in tiles, you would do:
1071 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1072 * tile_info.logical_extent_el.width);
1074 uint32_t format_bpb
;
1076 /** The logical size of the tile in units of format_bpb size elements
1078 * This field determines how a given surface is cut up into tiles. It is
1079 * used to compute the size of a surface in tiles and can be used to
1080 * determine the location of the tile containing any given surface element.
1081 * The exact value of this field depends heavily on the bits-per-block of
1082 * the format being used.
1084 struct isl_extent2d logical_extent_el
;
1086 /** The physical size of the tile in bytes and rows of bytes
1088 * This field determines how the tiles of a surface are physically layed
1089 * out in memory. The logical and physical tile extent are frequently the
1090 * same but this is not always the case. For instance, a W-tile (which is
1091 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1092 * its physical size is 128B x 32rows, the same as a Y-tile.
1094 * @see isl_surf::row_pitch_B
1096 struct isl_extent2d phys_extent_B
;
1100 * Metadata about a DRM format modifier.
1102 struct isl_drm_modifier_info
{
1105 /** Text name of the modifier */
1108 /** ISL tiling implied by this modifier */
1109 enum isl_tiling tiling
;
1111 /** ISL aux usage implied by this modifier */
1112 enum isl_aux_usage aux_usage
;
1114 /** Whether or not this modifier supports clear color */
1115 bool supports_clear_color
;
1119 * @brief Input to surface initialization
1121 * @invariant width >= 1
1122 * @invariant height >= 1
1123 * @invariant depth >= 1
1124 * @invariant levels >= 1
1125 * @invariant samples >= 1
1126 * @invariant array_len >= 1
1128 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1129 * @invariant if 2D then depth == 1
1130 * @invariant if 3D then array_len == 1 and samples == 1
1132 struct isl_surf_init_info
{
1133 enum isl_surf_dim dim
;
1134 enum isl_format format
;
1143 /** Lower bound for isl_surf::alignment, in bytes. */
1144 uint32_t min_alignment_B
;
1147 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1148 * will fail if this is misaligned or out of bounds.
1150 uint32_t row_pitch_B
;
1152 isl_surf_usage_flags_t usage
;
1154 /** Flags that alter how ISL selects isl_surf::tiling. */
1155 isl_tiling_flags_t tiling_flags
;
1159 enum isl_surf_dim dim
;
1160 enum isl_dim_layout dim_layout
;
1161 enum isl_msaa_layout msaa_layout
;
1162 enum isl_tiling tiling
;
1163 enum isl_format format
;
1166 * Alignment of the upper-left sample of each subimage, in units of surface
1169 struct isl_extent3d image_alignment_el
;
1172 * Logical extent of the surface's base level, in units of pixels. This is
1173 * identical to the extent defined in isl_surf_init_info.
1175 struct isl_extent4d logical_level0_px
;
1178 * Physical extent of the surface's base level, in units of physical
1181 * Consider isl_dim_layout as an operator that transforms a logical surface
1182 * layout to a physical surface layout. Then
1184 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1185 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1187 struct isl_extent4d phys_level0_sa
;
1192 /** Total size of the surface, in bytes. */
1195 /** Required alignment for the surface's base address. */
1196 uint32_t alignment_B
;
1199 * The interpretation of this field depends on the value of
1200 * isl_tile_info::physical_extent_B. In particular, the width of the
1201 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1202 * and the distance in bytes between vertically adjacent tiles in the image
1203 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1205 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1206 * this cleanly reduces to being the distance, in bytes, between vertically
1207 * adjacent surface elements.
1209 * @see isl_tile_info::phys_extent_B;
1211 uint32_t row_pitch_B
;
1214 * Pitch between physical array slices, in rows of surface elements.
1216 uint32_t array_pitch_el_rows
;
1218 enum isl_array_pitch_span array_pitch_span
;
1220 /** Copy of isl_surf_init_info::usage. */
1221 isl_surf_usage_flags_t usage
;
1224 struct isl_swizzle
{
1225 enum isl_channel_select r
:4;
1226 enum isl_channel_select g
:4;
1227 enum isl_channel_select b
:4;
1228 enum isl_channel_select a
:4;
1231 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1232 .r = ISL_CHANNEL_SELECT_##R, \
1233 .g = ISL_CHANNEL_SELECT_##G, \
1234 .b = ISL_CHANNEL_SELECT_##B, \
1235 .a = ISL_CHANNEL_SELECT_##A, \
1238 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1242 * Indicates the usage of the particular view
1244 * Normally, this is one bit. However, for a cube map texture, it
1245 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1247 isl_surf_usage_flags_t usage
;
1250 * The format to use in the view
1252 * This may differ from the format of the actual isl_surf but must have
1253 * the same block size.
1255 enum isl_format format
;
1257 uint32_t base_level
;
1263 * For cube maps, both base_array_layer and array_len should be
1264 * specified in terms of 2-D layers and must be a multiple of 6.
1266 * 3-D textures are effectively treated as 2-D arrays when used as a
1267 * storage image or render target. If `usage` contains
1268 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1269 * base_array_layer and array_len are applied. If the surface is only used
1270 * for texturing, they are ignored.
1272 uint32_t base_array_layer
;
1277 * Indicates the number of array elements starting at Base Array Layer.
1281 struct isl_swizzle swizzle
;
1284 union isl_color_value
{
1290 struct isl_surf_fill_state_info
{
1291 const struct isl_surf
*surf
;
1292 const struct isl_view
*view
;
1295 * The address of the surface in GPU memory.
1300 * The Memory Object Control state for the filled surface state.
1302 * The exact format of this value depends on hardware generation.
1307 * The auxilary surface or NULL if no auxilary surface is to be used.
1309 const struct isl_surf
*aux_surf
;
1310 enum isl_aux_usage aux_usage
;
1311 uint64_t aux_address
;
1314 * The clear color for this surface
1316 * Valid values depend on hardware generation.
1318 union isl_color_value clear_color
;
1321 * Send only the clear value address
1323 * If set, we only pass the clear address to the GPU and it will fetch it
1324 * from wherever it is.
1326 bool use_clear_address
;
1327 uint64_t clear_address
;
1330 * Surface write disables for gen4-5
1332 isl_channel_mask_t write_disables
;
1334 /* Intra-tile offset */
1335 uint16_t x_offset_sa
, y_offset_sa
;
1338 struct isl_buffer_fill_state_info
{
1340 * The address of the surface in GPU memory.
1345 * The size of the buffer
1350 * The Memory Object Control state for the filled surface state.
1352 * The exact format of this value depends on hardware generation.
1357 * The format to use in the surface state
1359 * This may differ from the format of the actual isl_surf but have the
1362 enum isl_format format
;
1365 * The swizzle to use in the surface state
1367 struct isl_swizzle swizzle
;
1372 struct isl_depth_stencil_hiz_emit_info
{
1376 const struct isl_surf
*depth_surf
;
1379 * The stencil surface
1381 * If separate stencil is not available, this must point to the same
1382 * isl_surf as depth_surf.
1384 const struct isl_surf
*stencil_surf
;
1387 * The view into the depth and stencil surfaces.
1389 * This view applies to both surfaces simultaneously.
1391 const struct isl_view
*view
;
1394 * The address of the depth surface in GPU memory
1396 uint64_t depth_address
;
1399 * The address of the stencil surface in GPU memory
1401 * If separate stencil is not available, this must have the same value as
1404 uint64_t stencil_address
;
1407 * The Memory Object Control state for depth and stencil buffers
1409 * Both depth and stencil will get the same MOCS value. The exact format
1410 * of this value depends on hardware generation.
1415 * The HiZ surface or NULL if HiZ is disabled.
1417 const struct isl_surf
*hiz_surf
;
1418 enum isl_aux_usage hiz_usage
;
1419 uint64_t hiz_address
;
1422 * The depth clear value
1424 float depth_clear_value
;
1427 extern const struct isl_format_layout isl_format_layouts
[];
1430 isl_device_init(struct isl_device
*dev
,
1431 const struct gen_device_info
*info
,
1432 bool has_bit6_swizzling
);
1434 isl_sample_count_mask_t ATTRIBUTE_CONST
1435 isl_device_get_sample_counts(struct isl_device
*dev
);
1437 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
1438 isl_format_get_layout(enum isl_format fmt
)
1440 assert(fmt
!= ISL_FORMAT_UNSUPPORTED
);
1441 assert(fmt
< ISL_NUM_FORMATS
);
1442 return &isl_format_layouts
[fmt
];
1445 bool isl_format_is_valid(enum isl_format
);
1447 static inline const char * ATTRIBUTE_CONST
1448 isl_format_get_name(enum isl_format fmt
)
1450 return isl_format_get_layout(fmt
)->name
;
1453 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
1454 enum isl_format format
);
1455 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
1456 enum isl_format format
);
1457 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
1458 enum isl_format format
);
1459 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
1460 enum isl_format format
);
1461 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
1462 enum isl_format format
);
1463 bool isl_format_supports_typed_writes(const struct gen_device_info
*devinfo
,
1464 enum isl_format format
);
1465 bool isl_format_supports_typed_reads(const struct gen_device_info
*devinfo
,
1466 enum isl_format format
);
1467 bool isl_format_supports_ccs_d(const struct gen_device_info
*devinfo
,
1468 enum isl_format format
);
1469 bool isl_format_supports_ccs_e(const struct gen_device_info
*devinfo
,
1470 enum isl_format format
);
1471 bool isl_format_supports_multisampling(const struct gen_device_info
*devinfo
,
1472 enum isl_format format
);
1474 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info
*devinfo
,
1475 enum isl_format format1
,
1476 enum isl_format format2
);
1478 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1479 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1480 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1481 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1482 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1483 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1486 isl_format_has_normalized_channel(enum isl_format fmt
)
1488 return isl_format_has_unorm_channel(fmt
) ||
1489 isl_format_has_snorm_channel(fmt
);
1493 isl_format_has_float_channel(enum isl_format fmt
)
1495 return isl_format_has_ufloat_channel(fmt
) ||
1496 isl_format_has_sfloat_channel(fmt
);
1500 isl_format_has_int_channel(enum isl_format fmt
)
1502 return isl_format_has_uint_channel(fmt
) ||
1503 isl_format_has_sint_channel(fmt
);
1506 bool isl_format_has_color_component(enum isl_format fmt
,
1507 int component
) ATTRIBUTE_CONST
;
1509 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1511 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1514 isl_format_is_compressed(enum isl_format fmt
)
1516 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1518 return fmtl
->txc
!= ISL_TXC_NONE
;
1522 isl_format_has_bc_compression(enum isl_format fmt
)
1524 switch (isl_format_get_layout(fmt
)->txc
) {
1542 unreachable("Should not be called on an aux surface");
1545 unreachable("bad texture compression mode");
1550 isl_format_is_yuv(enum isl_format fmt
)
1552 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1554 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1558 isl_format_block_is_1x1x1(enum isl_format fmt
)
1560 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1562 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1566 isl_format_is_srgb(enum isl_format fmt
)
1568 return isl_format_get_layout(fmt
)->colorspace
== ISL_COLORSPACE_SRGB
;
1571 enum isl_format
isl_format_srgb_to_linear(enum isl_format fmt
);
1574 isl_format_is_rgb(enum isl_format fmt
)
1576 if (isl_format_is_yuv(fmt
))
1579 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1581 return fmtl
->channels
.r
.bits
> 0 &&
1582 fmtl
->channels
.g
.bits
> 0 &&
1583 fmtl
->channels
.b
.bits
> 0 &&
1584 fmtl
->channels
.a
.bits
== 0;
1588 isl_format_is_rgbx(enum isl_format fmt
)
1590 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1592 return fmtl
->channels
.r
.bits
> 0 &&
1593 fmtl
->channels
.g
.bits
> 0 &&
1594 fmtl
->channels
.b
.bits
> 0 &&
1595 fmtl
->channels
.a
.bits
> 0 &&
1596 fmtl
->channels
.a
.type
== ISL_VOID
;
1599 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1600 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1601 enum isl_format
isl_format_rgbx_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1603 void isl_color_value_pack(const union isl_color_value
*value
,
1604 enum isl_format format
,
1605 uint32_t *data_out
);
1606 void isl_color_value_unpack(union isl_color_value
*value
,
1607 enum isl_format format
,
1608 const uint32_t *data_in
);
1610 bool isl_is_storage_image_format(enum isl_format fmt
);
1613 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1614 enum isl_format fmt
);
1616 /* Returns true if this hardware supports typed load/store on a format with
1617 * the same size as the given format.
1620 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1621 enum isl_format fmt
);
1624 isl_tiling_is_any_y(enum isl_tiling tiling
)
1626 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1630 isl_tiling_is_std_y(enum isl_tiling tiling
)
1632 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1636 isl_tiling_to_i915_tiling(enum isl_tiling tiling
);
1639 isl_tiling_from_i915_tiling(uint32_t tiling
);
1641 const struct isl_drm_modifier_info
* ATTRIBUTE_CONST
1642 isl_drm_modifier_get_info(uint64_t modifier
);
1645 isl_drm_modifier_has_aux(uint64_t modifier
)
1647 return isl_drm_modifier_get_info(modifier
)->aux_usage
!= ISL_AUX_USAGE_NONE
;
1650 /** Returns the default isl_aux_state for the given modifier.
1652 * If we have a modifier which supports compression, then the auxiliary data
1653 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1654 * can be in any of the following:
1656 * - ISL_AUX_STATE_CLEAR
1657 * - ISL_AUX_STATE_PARTIAL_CLEAR
1658 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1659 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1660 * - ISL_AUX_STATE_RESOLVED
1661 * - ISL_AUX_STATE_PASS_THROUGH
1663 * If the modifier does not support fast-clears, then we are guaranteed
1664 * that the surface is at least partially resolved and the first three not
1665 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1666 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1667 * because they are the least common denominator of the set of possible aux
1668 * states and will yield a valid interpretation of the aux data.
1670 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1672 static inline enum isl_aux_state
1673 isl_drm_modifier_get_default_aux_state(uint64_t modifier
)
1675 const struct isl_drm_modifier_info
*mod_info
=
1676 isl_drm_modifier_get_info(modifier
);
1678 if (!mod_info
|| mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
)
1679 return ISL_AUX_STATE_AUX_INVALID
;
1681 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1682 return mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1683 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1686 struct isl_extent2d ATTRIBUTE_CONST
1687 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
);
1690 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1692 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1696 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1698 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1702 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1704 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1708 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1710 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1711 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1715 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1717 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1721 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1723 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1724 (info
->format
== ISL_FORMAT_R16_UNORM
);
1728 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1730 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1731 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1734 static inline struct isl_extent2d
1735 isl_extent2d(uint32_t width
, uint32_t height
)
1737 struct isl_extent2d e
= { { 0 } };
1745 static inline struct isl_extent3d
1746 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1748 struct isl_extent3d e
= { { 0 } };
1757 static inline struct isl_extent4d
1758 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1761 struct isl_extent4d e
= { { 0 } };
1766 e
.array_len
= array_len
;
1771 bool isl_color_value_is_zero(union isl_color_value value
,
1772 enum isl_format format
);
1774 bool isl_color_value_is_zero_one(union isl_color_value value
,
1775 enum isl_format format
);
1778 isl_swizzle_is_identity(struct isl_swizzle swizzle
)
1780 return swizzle
.r
== ISL_CHANNEL_SELECT_RED
&&
1781 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
&&
1782 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
&&
1783 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
1787 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
1788 struct isl_swizzle swizzle
);
1791 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
);
1793 isl_swizzle_invert(struct isl_swizzle swizzle
);
1795 #define isl_surf_init(dev, surf, ...) \
1796 isl_surf_init_s((dev), (surf), \
1797 &(struct isl_surf_init_info) { __VA_ARGS__ });
1800 isl_surf_init_s(const struct isl_device
*dev
,
1801 struct isl_surf
*surf
,
1802 const struct isl_surf_init_info
*restrict info
);
1805 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1806 struct isl_tile_info
*tile_info
);
1809 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1810 const struct isl_surf
*surf
,
1811 struct isl_surf
*hiz_surf
);
1814 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1815 const struct isl_surf
*surf
,
1816 struct isl_surf
*mcs_surf
);
1819 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1820 const struct isl_surf
*surf
,
1821 struct isl_surf
*ccs_surf
,
1822 uint32_t row_pitch_B
/**< Ignored if 0 */);
1824 #define isl_surf_fill_state(dev, state, ...) \
1825 isl_surf_fill_state_s((dev), (state), \
1826 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1829 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1830 const struct isl_surf_fill_state_info
*restrict info
);
1832 #define isl_buffer_fill_state(dev, state, ...) \
1833 isl_buffer_fill_state_s((dev), (state), \
1834 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1837 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1838 const struct isl_buffer_fill_state_info
*restrict info
);
1841 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1842 struct isl_extent3d size
);
1844 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1845 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1846 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1849 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1850 const struct isl_depth_stencil_hiz_emit_info
*restrict info
);
1853 isl_surf_fill_image_param(const struct isl_device
*dev
,
1854 struct brw_image_param
*param
,
1855 const struct isl_surf
*surf
,
1856 const struct isl_view
*view
);
1859 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1860 struct brw_image_param
*param
,
1861 enum isl_format format
,
1865 * Alignment of the upper-left sample of each subimage, in units of surface
1868 static inline struct isl_extent3d
1869 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1871 return surf
->image_alignment_el
;
1875 * Alignment of the upper-left sample of each subimage, in units of surface
1878 static inline struct isl_extent3d
1879 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1881 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1883 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1884 fmtl
->bh
* surf
->image_alignment_el
.h
,
1885 fmtl
->bd
* surf
->image_alignment_el
.d
);
1889 * Logical extent of level 0 in units of surface elements.
1891 static inline struct isl_extent4d
1892 isl_surf_get_logical_level0_el(const struct isl_surf
*surf
)
1894 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1896 return isl_extent4d(DIV_ROUND_UP(surf
->logical_level0_px
.w
, fmtl
->bw
),
1897 DIV_ROUND_UP(surf
->logical_level0_px
.h
, fmtl
->bh
),
1898 DIV_ROUND_UP(surf
->logical_level0_px
.d
, fmtl
->bd
),
1899 surf
->logical_level0_px
.a
);
1903 * Physical extent of level 0 in units of surface elements.
1905 static inline struct isl_extent4d
1906 isl_surf_get_phys_level0_el(const struct isl_surf
*surf
)
1908 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1910 return isl_extent4d(DIV_ROUND_UP(surf
->phys_level0_sa
.w
, fmtl
->bw
),
1911 DIV_ROUND_UP(surf
->phys_level0_sa
.h
, fmtl
->bh
),
1912 DIV_ROUND_UP(surf
->phys_level0_sa
.d
, fmtl
->bd
),
1913 surf
->phys_level0_sa
.a
);
1917 * Pitch between vertically adjacent surface elements, in bytes.
1919 static inline uint32_t
1920 isl_surf_get_row_pitch_B(const struct isl_surf
*surf
)
1922 return surf
->row_pitch_B
;
1926 * Pitch between vertically adjacent surface elements, in units of surface elements.
1928 static inline uint32_t
1929 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1931 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1933 assert(surf
->row_pitch_B
% (fmtl
->bpb
/ 8) == 0);
1934 return surf
->row_pitch_B
/ (fmtl
->bpb
/ 8);
1938 * Pitch between physical array slices, in rows of surface elements.
1940 static inline uint32_t
1941 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1943 return surf
->array_pitch_el_rows
;
1947 * Pitch between physical array slices, in units of surface elements.
1949 static inline uint32_t
1950 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1952 return isl_surf_get_array_pitch_el_rows(surf
) *
1953 isl_surf_get_row_pitch_el(surf
);
1957 * Pitch between physical array slices, in rows of surface samples.
1959 static inline uint32_t
1960 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1962 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1963 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1967 * Pitch between physical array slices, in bytes.
1969 static inline uint32_t
1970 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1972 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch_B
;
1976 * Calculate the offset, in units of surface samples, to a subimage in the
1979 * @invariant level < surface levels
1980 * @invariant logical_array_layer < logical array length of surface
1981 * @invariant logical_z_offset_px < logical depth of surface at level
1984 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1986 uint32_t logical_array_layer
,
1987 uint32_t logical_z_offset_px
,
1988 uint32_t *x_offset_sa
,
1989 uint32_t *y_offset_sa
);
1992 * Calculate the offset, in units of surface elements, to a subimage in the
1995 * @invariant level < surface levels
1996 * @invariant logical_array_layer < logical array length of surface
1997 * @invariant logical_z_offset_px < logical depth of surface at level
2000 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2002 uint32_t logical_array_layer
,
2003 uint32_t logical_z_offset_px
,
2004 uint32_t *x_offset_el
,
2005 uint32_t *y_offset_el
);
2008 * Calculate the offset, in bytes and intratile surface samples, to a
2009 * subimage in the surface.
2011 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2012 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2013 * offsets to samples.
2015 * @invariant level < surface levels
2016 * @invariant logical_array_layer < logical array length of surface
2017 * @invariant logical_z_offset_px < logical depth of surface at level
2020 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2022 uint32_t logical_array_layer
,
2023 uint32_t logical_z_offset_px
,
2025 uint32_t *x_offset_sa
,
2026 uint32_t *y_offset_sa
);
2029 * Create an isl_surf that represents a particular subimage in the surface.
2031 * The newly created surface will have a single miplevel and array slice. The
2032 * surface lives at the returned byte and intratile offsets, in samples.
2034 * It is safe to call this function with surf == image_surf.
2036 * @invariant level < surface levels
2037 * @invariant logical_array_layer < logical array length of surface
2038 * @invariant logical_z_offset_px < logical depth of surface at level
2041 isl_surf_get_image_surf(const struct isl_device
*dev
,
2042 const struct isl_surf
*surf
,
2044 uint32_t logical_array_layer
,
2045 uint32_t logical_z_offset_px
,
2046 struct isl_surf
*image_surf
,
2048 uint32_t *x_offset_sa
,
2049 uint32_t *y_offset_sa
);
2052 * @brief Calculate the intratile offsets to a surface.
2054 * In @a base_address_offset return the offset from the base of the surface to
2055 * the base address of the first tile of the subimage. In @a x_offset_B and
2056 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2057 * tile's base to the subimage's first surface element. The x and y offsets
2058 * are intratile offsets; that is, they do not exceed the boundary of the
2059 * surface's tiling format.
2062 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2064 uint32_t row_pitch_B
,
2065 uint32_t total_x_offset_el
,
2066 uint32_t total_y_offset_el
,
2067 uint32_t *base_address_offset
,
2068 uint32_t *x_offset_el
,
2069 uint32_t *y_offset_el
);
2072 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling
,
2073 enum isl_format format
,
2074 uint32_t row_pitch_B
,
2075 uint32_t total_x_offset_sa
,
2076 uint32_t total_y_offset_sa
,
2077 uint32_t *base_address_offset
,
2078 uint32_t *x_offset_sa
,
2079 uint32_t *y_offset_sa
)
2081 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2083 /* For computing the intratile offsets, we actually want a strange unit
2084 * which is samples for multisampled surfaces but elements for compressed
2087 assert(total_x_offset_sa
% fmtl
->bw
== 0);
2088 assert(total_y_offset_sa
% fmtl
->bh
== 0);
2089 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
2090 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
2092 isl_tiling_get_intratile_offset_el(tiling
, fmtl
->bpb
, row_pitch_B
,
2093 total_x_offset
, total_y_offset
,
2094 base_address_offset
,
2095 x_offset_sa
, y_offset_sa
);
2096 *x_offset_sa
*= fmtl
->bw
;
2097 *y_offset_sa
*= fmtl
->bh
;
2101 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2103 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2104 * @pre surf->format must be a valid format for depth surfaces
2107 isl_surf_get_depth_format(const struct isl_device
*dev
,
2108 const struct isl_surf
*surf
);
2111 * @brief performs a copy from linear to tiled surface
2115 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
2116 uint32_t yt1
, uint32_t yt2
,
2117 char *dst
, const char *src
,
2118 uint32_t dst_pitch
, int32_t src_pitch
,
2120 enum isl_tiling tiling
,
2121 isl_memcpy_type copy_type
);
2124 * @brief performs a copy from tiled to linear surface
2128 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
2129 uint32_t yt1
, uint32_t yt2
,
2130 char *dst
, const char *src
,
2131 int32_t dst_pitch
, uint32_t src_pitch
,
2133 enum isl_tiling tiling
,
2134 isl_memcpy_type copy_type
);