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[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct brw_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
63 #else
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
66 #endif
67
68 #ifndef ISL_DEV_IS_HASWELL
69 /**
70 * @brief Get the hardware generation of isl_device.
71 *
72 * You can define this as a compile-time constant in the CFLAGS. For example,
73 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
74 */
75 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
76 #endif
77
78 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
79 /**
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
82 */
83 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
84 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
85 #else
86 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
87 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
88 #endif
89
90 /**
91 * Hardware enumeration SURFACE_FORMAT.
92 *
93 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
94 * Enumerations: SURFACE_FORMAT.
95 */
96 enum isl_format {
97 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
98 ISL_FORMAT_R32G32B32A32_SINT = 1,
99 ISL_FORMAT_R32G32B32A32_UINT = 2,
100 ISL_FORMAT_R32G32B32A32_UNORM = 3,
101 ISL_FORMAT_R32G32B32A32_SNORM = 4,
102 ISL_FORMAT_R64G64_FLOAT = 5,
103 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
104 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
105 ISL_FORMAT_R32G32B32A32_USCALED = 8,
106 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
107 ISL_FORMAT_R64G64_PASSTHRU = 33,
108 ISL_FORMAT_R32G32B32_FLOAT = 64,
109 ISL_FORMAT_R32G32B32_SINT = 65,
110 ISL_FORMAT_R32G32B32_UINT = 66,
111 ISL_FORMAT_R32G32B32_UNORM = 67,
112 ISL_FORMAT_R32G32B32_SNORM = 68,
113 ISL_FORMAT_R32G32B32_SSCALED = 69,
114 ISL_FORMAT_R32G32B32_USCALED = 70,
115 ISL_FORMAT_R32G32B32_SFIXED = 80,
116 ISL_FORMAT_R16G16B16A16_UNORM = 128,
117 ISL_FORMAT_R16G16B16A16_SNORM = 129,
118 ISL_FORMAT_R16G16B16A16_SINT = 130,
119 ISL_FORMAT_R16G16B16A16_UINT = 131,
120 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
121 ISL_FORMAT_R32G32_FLOAT = 133,
122 ISL_FORMAT_R32G32_SINT = 134,
123 ISL_FORMAT_R32G32_UINT = 135,
124 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
125 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
126 ISL_FORMAT_L32A32_FLOAT = 138,
127 ISL_FORMAT_R32G32_UNORM = 139,
128 ISL_FORMAT_R32G32_SNORM = 140,
129 ISL_FORMAT_R64_FLOAT = 141,
130 ISL_FORMAT_R16G16B16X16_UNORM = 142,
131 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
132 ISL_FORMAT_A32X32_FLOAT = 144,
133 ISL_FORMAT_L32X32_FLOAT = 145,
134 ISL_FORMAT_I32X32_FLOAT = 146,
135 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
136 ISL_FORMAT_R16G16B16A16_USCALED = 148,
137 ISL_FORMAT_R32G32_SSCALED = 149,
138 ISL_FORMAT_R32G32_USCALED = 150,
139 ISL_FORMAT_R32G32_FLOAT_LD = 151,
140 ISL_FORMAT_R32G32_SFIXED = 160,
141 ISL_FORMAT_R64_PASSTHRU = 161,
142 ISL_FORMAT_B8G8R8A8_UNORM = 192,
143 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
144 ISL_FORMAT_R10G10B10A2_UNORM = 194,
145 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
146 ISL_FORMAT_R10G10B10A2_UINT = 196,
147 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
148 ISL_FORMAT_R8G8B8A8_UNORM = 199,
149 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
150 ISL_FORMAT_R8G8B8A8_SNORM = 201,
151 ISL_FORMAT_R8G8B8A8_SINT = 202,
152 ISL_FORMAT_R8G8B8A8_UINT = 203,
153 ISL_FORMAT_R16G16_UNORM = 204,
154 ISL_FORMAT_R16G16_SNORM = 205,
155 ISL_FORMAT_R16G16_SINT = 206,
156 ISL_FORMAT_R16G16_UINT = 207,
157 ISL_FORMAT_R16G16_FLOAT = 208,
158 ISL_FORMAT_B10G10R10A2_UNORM = 209,
159 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
160 ISL_FORMAT_R11G11B10_FLOAT = 211,
161 ISL_FORMAT_R32_SINT = 214,
162 ISL_FORMAT_R32_UINT = 215,
163 ISL_FORMAT_R32_FLOAT = 216,
164 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
165 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
166 ISL_FORMAT_L32_UNORM = 221,
167 ISL_FORMAT_A32_UNORM = 222,
168 ISL_FORMAT_L16A16_UNORM = 223,
169 ISL_FORMAT_I24X8_UNORM = 224,
170 ISL_FORMAT_L24X8_UNORM = 225,
171 ISL_FORMAT_A24X8_UNORM = 226,
172 ISL_FORMAT_I32_FLOAT = 227,
173 ISL_FORMAT_L32_FLOAT = 228,
174 ISL_FORMAT_A32_FLOAT = 229,
175 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
176 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
177 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
178 ISL_FORMAT_B8G8R8X8_UNORM = 233,
179 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
180 ISL_FORMAT_R8G8B8X8_UNORM = 235,
181 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
182 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
183 ISL_FORMAT_B10G10R10X2_UNORM = 238,
184 ISL_FORMAT_L16A16_FLOAT = 240,
185 ISL_FORMAT_R32_UNORM = 241,
186 ISL_FORMAT_R32_SNORM = 242,
187 ISL_FORMAT_R10G10B10X2_USCALED = 243,
188 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
189 ISL_FORMAT_R8G8B8A8_USCALED = 245,
190 ISL_FORMAT_R16G16_SSCALED = 246,
191 ISL_FORMAT_R16G16_USCALED = 247,
192 ISL_FORMAT_R32_SSCALED = 248,
193 ISL_FORMAT_R32_USCALED = 249,
194 ISL_FORMAT_B5G6R5_UNORM = 256,
195 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
196 ISL_FORMAT_B5G5R5A1_UNORM = 258,
197 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
198 ISL_FORMAT_B4G4R4A4_UNORM = 260,
199 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
200 ISL_FORMAT_R8G8_UNORM = 262,
201 ISL_FORMAT_R8G8_SNORM = 263,
202 ISL_FORMAT_R8G8_SINT = 264,
203 ISL_FORMAT_R8G8_UINT = 265,
204 ISL_FORMAT_R16_UNORM = 266,
205 ISL_FORMAT_R16_SNORM = 267,
206 ISL_FORMAT_R16_SINT = 268,
207 ISL_FORMAT_R16_UINT = 269,
208 ISL_FORMAT_R16_FLOAT = 270,
209 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
210 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
211 ISL_FORMAT_I16_UNORM = 273,
212 ISL_FORMAT_L16_UNORM = 274,
213 ISL_FORMAT_A16_UNORM = 275,
214 ISL_FORMAT_L8A8_UNORM = 276,
215 ISL_FORMAT_I16_FLOAT = 277,
216 ISL_FORMAT_L16_FLOAT = 278,
217 ISL_FORMAT_A16_FLOAT = 279,
218 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
219 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
220 ISL_FORMAT_B5G5R5X1_UNORM = 282,
221 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
222 ISL_FORMAT_R8G8_SSCALED = 284,
223 ISL_FORMAT_R8G8_USCALED = 285,
224 ISL_FORMAT_R16_SSCALED = 286,
225 ISL_FORMAT_R16_USCALED = 287,
226 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
227 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
228 ISL_FORMAT_A1B5G5R5_UNORM = 292,
229 ISL_FORMAT_A4B4G4R4_UNORM = 293,
230 ISL_FORMAT_L8A8_UINT = 294,
231 ISL_FORMAT_L8A8_SINT = 295,
232 ISL_FORMAT_R8_UNORM = 320,
233 ISL_FORMAT_R8_SNORM = 321,
234 ISL_FORMAT_R8_SINT = 322,
235 ISL_FORMAT_R8_UINT = 323,
236 ISL_FORMAT_A8_UNORM = 324,
237 ISL_FORMAT_I8_UNORM = 325,
238 ISL_FORMAT_L8_UNORM = 326,
239 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
240 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
241 ISL_FORMAT_R8_SSCALED = 329,
242 ISL_FORMAT_R8_USCALED = 330,
243 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
244 ISL_FORMAT_L8_UNORM_SRGB = 332,
245 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
246 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
247 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
248 ISL_FORMAT_Y8_UNORM = 336,
249 ISL_FORMAT_L8_UINT = 338,
250 ISL_FORMAT_L8_SINT = 339,
251 ISL_FORMAT_I8_UINT = 340,
252 ISL_FORMAT_I8_SINT = 341,
253 ISL_FORMAT_DXT1_RGB_SRGB = 384,
254 ISL_FORMAT_R1_UNORM = 385,
255 ISL_FORMAT_YCRCB_NORMAL = 386,
256 ISL_FORMAT_YCRCB_SWAPUVY = 387,
257 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
258 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
259 ISL_FORMAT_BC1_UNORM = 390,
260 ISL_FORMAT_BC2_UNORM = 391,
261 ISL_FORMAT_BC3_UNORM = 392,
262 ISL_FORMAT_BC4_UNORM = 393,
263 ISL_FORMAT_BC5_UNORM = 394,
264 ISL_FORMAT_BC1_UNORM_SRGB = 395,
265 ISL_FORMAT_BC2_UNORM_SRGB = 396,
266 ISL_FORMAT_BC3_UNORM_SRGB = 397,
267 ISL_FORMAT_MONO8 = 398,
268 ISL_FORMAT_YCRCB_SWAPUV = 399,
269 ISL_FORMAT_YCRCB_SWAPY = 400,
270 ISL_FORMAT_DXT1_RGB = 401,
271 ISL_FORMAT_FXT1 = 402,
272 ISL_FORMAT_R8G8B8_UNORM = 403,
273 ISL_FORMAT_R8G8B8_SNORM = 404,
274 ISL_FORMAT_R8G8B8_SSCALED = 405,
275 ISL_FORMAT_R8G8B8_USCALED = 406,
276 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
277 ISL_FORMAT_R64G64B64_FLOAT = 408,
278 ISL_FORMAT_BC4_SNORM = 409,
279 ISL_FORMAT_BC5_SNORM = 410,
280 ISL_FORMAT_R16G16B16_FLOAT = 411,
281 ISL_FORMAT_R16G16B16_UNORM = 412,
282 ISL_FORMAT_R16G16B16_SNORM = 413,
283 ISL_FORMAT_R16G16B16_SSCALED = 414,
284 ISL_FORMAT_R16G16B16_USCALED = 415,
285 ISL_FORMAT_BC6H_SF16 = 417,
286 ISL_FORMAT_BC7_UNORM = 418,
287 ISL_FORMAT_BC7_UNORM_SRGB = 419,
288 ISL_FORMAT_BC6H_UF16 = 420,
289 ISL_FORMAT_PLANAR_420_8 = 421,
290 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
291 ISL_FORMAT_ETC1_RGB8 = 425,
292 ISL_FORMAT_ETC2_RGB8 = 426,
293 ISL_FORMAT_EAC_R11 = 427,
294 ISL_FORMAT_EAC_RG11 = 428,
295 ISL_FORMAT_EAC_SIGNED_R11 = 429,
296 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
297 ISL_FORMAT_ETC2_SRGB8 = 431,
298 ISL_FORMAT_R16G16B16_UINT = 432,
299 ISL_FORMAT_R16G16B16_SINT = 433,
300 ISL_FORMAT_R32_SFIXED = 434,
301 ISL_FORMAT_R10G10B10A2_SNORM = 435,
302 ISL_FORMAT_R10G10B10A2_USCALED = 436,
303 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
304 ISL_FORMAT_R10G10B10A2_SINT = 438,
305 ISL_FORMAT_B10G10R10A2_SNORM = 439,
306 ISL_FORMAT_B10G10R10A2_USCALED = 440,
307 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
308 ISL_FORMAT_B10G10R10A2_UINT = 442,
309 ISL_FORMAT_B10G10R10A2_SINT = 443,
310 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
311 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
312 ISL_FORMAT_ETC2_RGB8_PTA = 448,
313 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
314 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
315 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
316 ISL_FORMAT_R8G8B8_UINT = 456,
317 ISL_FORMAT_R8G8B8_SINT = 457,
318 ISL_FORMAT_RAW = 511,
319 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
320 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
321 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
322 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
323 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
324 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
325 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
326 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
327 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
328 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
329 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
330 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
331 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
332 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
347
348 /* Hardware doesn't understand this out-of-band value */
349 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
350 };
351
352 /**
353 * Numerical base type for channels of isl_format.
354 */
355 enum isl_base_type {
356 ISL_VOID,
357 ISL_RAW,
358 ISL_UNORM,
359 ISL_SNORM,
360 ISL_UFLOAT,
361 ISL_SFLOAT,
362 ISL_UFIXED,
363 ISL_SFIXED,
364 ISL_UINT,
365 ISL_SINT,
366 ISL_USCALED,
367 ISL_SSCALED,
368 };
369
370 /**
371 * Colorspace of isl_format.
372 */
373 enum isl_colorspace {
374 ISL_COLORSPACE_NONE = 0,
375 ISL_COLORSPACE_LINEAR,
376 ISL_COLORSPACE_SRGB,
377 ISL_COLORSPACE_YUV,
378 };
379
380 /**
381 * Texture compression mode of isl_format.
382 */
383 enum isl_txc {
384 ISL_TXC_NONE = 0,
385 ISL_TXC_DXT1,
386 ISL_TXC_DXT3,
387 ISL_TXC_DXT5,
388 ISL_TXC_FXT1,
389 ISL_TXC_RGTC1,
390 ISL_TXC_RGTC2,
391 ISL_TXC_BPTC,
392 ISL_TXC_ETC1,
393 ISL_TXC_ETC2,
394 ISL_TXC_ASTC,
395 };
396
397 /**
398 * @brief Hardware tile mode
399 *
400 * WARNING: These values differ from the hardware enum values, which are
401 * unstable across hardware generations.
402 *
403 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
404 * clearly distinguish it from Yf and Ys.
405 */
406 enum isl_tiling {
407 ISL_TILING_LINEAR = 0,
408 ISL_TILING_W,
409 ISL_TILING_X,
410 ISL_TILING_Y0, /**< Legacy Y tiling */
411 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
412 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
413 };
414
415 /**
416 * @defgroup Tiling Flags
417 * @{
418 */
419 typedef uint32_t isl_tiling_flags_t;
420 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
421 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
422 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
423 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
424 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
425 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
426 #define ISL_TILING_ANY_MASK (~0u)
427 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
428
429 /** Any Y tiling, including legacy Y tiling. */
430 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
431 ISL_TILING_Yf_BIT | \
432 ISL_TILING_Ys_BIT)
433
434 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
435 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
436 ISL_TILING_Ys_BIT)
437 /** @} */
438
439 /**
440 * @brief Logical dimension of surface.
441 *
442 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
443 * as 2D array surfaces.
444 */
445 enum isl_surf_dim {
446 ISL_SURF_DIM_1D,
447 ISL_SURF_DIM_2D,
448 ISL_SURF_DIM_3D,
449 };
450
451 /**
452 * @brief Physical layout of the surface's dimensions.
453 */
454 enum isl_dim_layout {
455 /**
456 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
457 * 6.17.3: 2D Surfaces.
458 *
459 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
460 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
461 *
462 * One-dimensional surfaces are identical to 2D surfaces with height of
463 * one.
464 *
465 * @invariant isl_surf::phys_level0_sa::depth == 1
466 */
467 ISL_DIM_LAYOUT_GEN4_2D,
468
469 /**
470 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
471 * 6.17.5: 3D Surfaces.
472 *
473 * @invariant isl_surf::phys_level0_sa::array_len == 1
474 */
475 ISL_DIM_LAYOUT_GEN4_3D,
476
477 /**
478 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
479 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
480 */
481 ISL_DIM_LAYOUT_GEN9_1D,
482 };
483
484 /* TODO(chadv): Explain */
485 enum isl_array_pitch_span {
486 ISL_ARRAY_PITCH_SPAN_FULL,
487 ISL_ARRAY_PITCH_SPAN_COMPACT,
488 };
489
490 /**
491 * @defgroup Surface Usage
492 * @{
493 */
494 typedef uint64_t isl_surf_usage_flags_t;
495 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
496 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
497 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
498 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
499 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
500 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
501 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
502 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
503 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
504 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
505 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
506 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
507 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
508 /** @} */
509
510 /**
511 * @brief A channel select (also known as texture swizzle) value
512 */
513 enum isl_channel_select {
514 ISL_CHANNEL_SELECT_ZERO = 0,
515 ISL_CHANNEL_SELECT_ONE = 1,
516 ISL_CHANNEL_SELECT_RED = 4,
517 ISL_CHANNEL_SELECT_GREEN = 5,
518 ISL_CHANNEL_SELECT_BLUE = 6,
519 ISL_CHANNEL_SELECT_ALPHA = 7,
520 };
521
522 /**
523 * Identical to VkSampleCountFlagBits.
524 */
525 enum isl_sample_count {
526 ISL_SAMPLE_COUNT_1_BIT = 1u,
527 ISL_SAMPLE_COUNT_2_BIT = 2u,
528 ISL_SAMPLE_COUNT_4_BIT = 4u,
529 ISL_SAMPLE_COUNT_8_BIT = 8u,
530 ISL_SAMPLE_COUNT_16_BIT = 16u,
531 };
532 typedef uint32_t isl_sample_count_mask_t;
533
534 /**
535 * @brief Multisample Format
536 */
537 enum isl_msaa_layout {
538 /**
539 * @brief Suface is single-sampled.
540 */
541 ISL_MSAA_LAYOUT_NONE,
542
543 /**
544 * @brief [SNB+] Interleaved Multisample Format
545 *
546 * In this format, multiple samples are interleaved into each cacheline.
547 * In other words, the sample index is swizzled into the low 6 bits of the
548 * surface's virtual address space.
549 *
550 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
551 * and its pixel format is 32bpp. Then the first cacheline is arranged
552 * thus:
553 *
554 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
555 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
556 *
557 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
558 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
559 *
560 * The hardware docs refer to this format with multiple terms. In
561 * Sandybridge, this is the only multisample format; so no term is used.
562 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
563 * Multisample Surface). Later hardware docs additionally refer to this
564 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
565 * color surfaces).
566 *
567 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
568 * Surface Behavior".
569 *
570 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
571 * Multisampled Surfaces".
572 */
573 ISL_MSAA_LAYOUT_INTERLEAVED,
574
575 /**
576 * @brief [IVB+] Array Multisample Format
577 *
578 * In this format, the surface's physical layout resembles that of a
579 * 2D array surface.
580 *
581 * Suppose the multisample surface's logical extent is (w, h) and its
582 * sample count is N. Then surface's physical extent is the same as
583 * a singlesample 2D surface whose logical extent is (w, h) and array
584 * length is N. Array slice `i` contains the pixel values for sample
585 * index `i`.
586 *
587 * The Ivybridge docs refer to surfaces in this format as UMS
588 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
589 * Surface). The Broadwell docs additionally refer to this format as
590 * MSFMT_MSS (MSS=Multisample Surface Storage).
591 *
592 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
593 * Multisample Surfaces".
594 *
595 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
596 * Multisample Surfaces".
597 */
598 ISL_MSAA_LAYOUT_ARRAY,
599 };
600
601
602 struct isl_device {
603 const struct brw_device_info *info;
604 bool use_separate_stencil;
605 bool has_bit6_swizzling;
606 };
607
608 struct isl_extent2d {
609 union { uint32_t w, width; };
610 union { uint32_t h, height; };
611 };
612
613 struct isl_extent3d {
614 union { uint32_t w, width; };
615 union { uint32_t h, height; };
616 union { uint32_t d, depth; };
617 };
618
619 struct isl_extent4d {
620 union { uint32_t w, width; };
621 union { uint32_t h, height; };
622 union { uint32_t d, depth; };
623 union { uint32_t a, array_len; };
624 };
625
626 struct isl_channel_layout {
627 enum isl_base_type type;
628 uint8_t bits; /**< Size in bits */
629 };
630
631 /**
632 * Each format has 3D block extent (width, height, depth). The block extent of
633 * compressed formats is that of the format's compression block. For example,
634 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
635 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
636 * is (w=1, h=1, d=1).
637 */
638 struct isl_format_layout {
639 enum isl_format format;
640 const char *name;
641
642 uint16_t bpb; /**< Bits per block */
643 uint8_t bw; /**< Block width, in pixels */
644 uint8_t bh; /**< Block height, in pixels */
645 uint8_t bd; /**< Block depth, in pixels */
646
647 struct {
648 struct isl_channel_layout r; /**< Red channel */
649 struct isl_channel_layout g; /**< Green channel */
650 struct isl_channel_layout b; /**< Blue channel */
651 struct isl_channel_layout a; /**< Alpha channel */
652 struct isl_channel_layout l; /**< Luminance channel */
653 struct isl_channel_layout i; /**< Intensity channel */
654 struct isl_channel_layout p; /**< Palette channel */
655 } channels;
656
657 enum isl_colorspace colorspace;
658 enum isl_txc txc;
659 };
660
661 struct isl_tile_info {
662 enum isl_tiling tiling;
663
664 /** The logical size of the tile in units of surface elements
665 *
666 * This field determines how a given surface is cut up into tiles. It is
667 * used to compute the size of a surface in tiles and can be used to
668 * determine the location of the tile containing any given surface element.
669 * The exact value of this field depends heavily on the bits-per-block of
670 * the format being used.
671 */
672 struct isl_extent2d logical_extent_el;
673
674 /** The physical size of the tile in bytes and rows of bytes
675 *
676 * This field determines how the tiles of a surface are physically layed
677 * out in memory. The logical and physical tile extent are frequently the
678 * same but this is not always the case. For instance, a W-tile (which is
679 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
680 * its physical size is 128B x 32rows, the same as a Y-tile.
681 *
682 * @see isl_surf::row_pitch
683 */
684 struct isl_extent2d phys_extent_B;
685 };
686
687 /**
688 * @brief Input to surface initialization
689 *
690 * @invariant width >= 1
691 * @invariant height >= 1
692 * @invariant depth >= 1
693 * @invariant levels >= 1
694 * @invariant samples >= 1
695 * @invariant array_len >= 1
696 *
697 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
698 * @invariant if 2D then depth == 1
699 * @invariant if 3D then array_len == 1 and samples == 1
700 */
701 struct isl_surf_init_info {
702 enum isl_surf_dim dim;
703 enum isl_format format;
704
705 uint32_t width;
706 uint32_t height;
707 uint32_t depth;
708 uint32_t levels;
709 uint32_t array_len;
710 uint32_t samples;
711
712 /** Lower bound for isl_surf::alignment, in bytes. */
713 uint32_t min_alignment;
714
715 /** Lower bound for isl_surf::pitch, in bytes. */
716 uint32_t min_pitch;
717
718 isl_surf_usage_flags_t usage;
719
720 /** Flags that alter how ISL selects isl_surf::tiling. */
721 isl_tiling_flags_t tiling_flags;
722 };
723
724 struct isl_surf {
725 enum isl_surf_dim dim;
726 enum isl_dim_layout dim_layout;
727 enum isl_msaa_layout msaa_layout;
728 enum isl_tiling tiling;
729 enum isl_format format;
730
731 /**
732 * Alignment of the upper-left sample of each subimage, in units of surface
733 * elements.
734 */
735 struct isl_extent3d image_alignment_el;
736
737 /**
738 * Logical extent of the surface's base level, in units of pixels. This is
739 * identical to the extent defined in isl_surf_init_info.
740 */
741 struct isl_extent4d logical_level0_px;
742
743 /**
744 * Physical extent of the surface's base level, in units of physical
745 * surface samples and aligned to the format's compression block.
746 *
747 * Consider isl_dim_layout as an operator that transforms a logical surface
748 * layout to a physical surface layout. Then
749 *
750 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
751 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
752 */
753 struct isl_extent4d phys_level0_sa;
754
755 uint32_t levels;
756 uint32_t samples;
757
758 /** Total size of the surface, in bytes. */
759 uint32_t size;
760
761 /** Required alignment for the surface's base address. */
762 uint32_t alignment;
763
764 /**
765 * The interpretation of this field depends on the value of
766 * isl_tile_info::physical_extent_B. In particular, the width of the
767 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
768 * and the distance in bytes between vertically adjacent tiles in the image
769 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
770 *
771 * For linear images where isl_tile_info::physical_extent_B.height == 1,
772 * this cleanly reduces to being the distance, in bytes, between vertically
773 * adjacent surface elements.
774 *
775 * @see isl_tile_info::phys_extent_B;
776 */
777 uint32_t row_pitch;
778
779 /**
780 * Pitch between physical array slices, in rows of surface elements.
781 */
782 uint32_t array_pitch_el_rows;
783
784 enum isl_array_pitch_span array_pitch_span;
785
786 /** Copy of isl_surf_init_info::usage. */
787 isl_surf_usage_flags_t usage;
788 };
789
790 struct isl_view {
791 /**
792 * Indicates the usage of the particular view
793 *
794 * Normally, this is one bit. However, for a cube map texture, it
795 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
796 */
797 isl_surf_usage_flags_t usage;
798
799 /**
800 * The format to use in the view
801 *
802 * This may differ from the format of the actual isl_surf but must have
803 * the same block size.
804 */
805 enum isl_format format;
806
807 uint32_t base_level;
808 uint32_t levels;
809
810 /**
811 * Base array layer
812 *
813 * For cube maps, both base_array_layer and array_len should be
814 * specified in terms of 2-D layers and must be a multiple of 6.
815 */
816 uint32_t base_array_layer;
817 uint32_t array_len;
818
819 enum isl_channel_select channel_select[4];
820 };
821
822 union isl_color_value {
823 float f32[4];
824 uint32_t u32[4];
825 int32_t i32[4];
826 };
827
828 struct isl_surf_fill_state_info {
829 const struct isl_surf *surf;
830 const struct isl_view *view;
831
832 /**
833 * The address of the surface in GPU memory.
834 */
835 uint64_t address;
836
837 /**
838 * The Memory Object Control state for the filled surface state.
839 *
840 * The exact format of this value depends on hardware generation.
841 */
842 uint32_t mocs;
843
844 /**
845 * The clear color for this surface
846 *
847 * Valid values depend on hardware generation.
848 */
849 union isl_color_value clear_color;
850 };
851
852 struct isl_buffer_fill_state_info {
853 /**
854 * The address of the surface in GPU memory.
855 */
856 uint64_t address;
857
858 /**
859 * The size of the buffer
860 */
861 uint64_t size;
862
863 /**
864 * The Memory Object Control state for the filled surface state.
865 *
866 * The exact format of this value depends on hardware generation.
867 */
868 uint32_t mocs;
869
870 /**
871 * The format to use in the surface state
872 *
873 * This may differ from the format of the actual isl_surf but have the
874 * same block size.
875 */
876 enum isl_format format;
877
878 uint32_t stride;
879 };
880
881 extern const struct isl_format_layout isl_format_layouts[];
882
883 void
884 isl_device_init(struct isl_device *dev,
885 const struct brw_device_info *info,
886 bool has_bit6_swizzling);
887
888 isl_sample_count_mask_t ATTRIBUTE_CONST
889 isl_device_get_sample_counts(struct isl_device *dev);
890
891 static inline const struct isl_format_layout * ATTRIBUTE_CONST
892 isl_format_get_layout(enum isl_format fmt)
893 {
894 return &isl_format_layouts[fmt];
895 }
896
897 static inline const char * ATTRIBUTE_CONST
898 isl_format_get_name(enum isl_format fmt)
899 {
900 return isl_format_layouts[fmt].name;
901 }
902
903 bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
904 enum isl_format format);
905 bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
906 enum isl_format format);
907 bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
908 enum isl_format format);
909 bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
910 enum isl_format format);
911 bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
912 enum isl_format format);
913 bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
914 enum isl_format format);
915
916 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
917 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
918 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
919 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
920 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
921 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
922
923 static inline bool
924 isl_format_has_normalized_channel(enum isl_format fmt)
925 {
926 return isl_format_has_unorm_channel(fmt) ||
927 isl_format_has_snorm_channel(fmt);
928 }
929
930 static inline bool
931 isl_format_has_float_channel(enum isl_format fmt)
932 {
933 return isl_format_has_ufloat_channel(fmt) ||
934 isl_format_has_sfloat_channel(fmt);
935 }
936
937 static inline bool
938 isl_format_has_int_channel(enum isl_format fmt)
939 {
940 return isl_format_has_uint_channel(fmt) ||
941 isl_format_has_sint_channel(fmt);
942 }
943
944 unsigned isl_format_get_num_channels(enum isl_format fmt);
945
946 static inline bool
947 isl_format_is_compressed(enum isl_format fmt)
948 {
949 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
950
951 return fmtl->txc != ISL_TXC_NONE;
952 }
953
954 static inline bool
955 isl_format_has_bc_compression(enum isl_format fmt)
956 {
957 switch (isl_format_get_layout(fmt)->txc) {
958 case ISL_TXC_DXT1:
959 case ISL_TXC_DXT3:
960 case ISL_TXC_DXT5:
961 return true;
962 case ISL_TXC_NONE:
963 case ISL_TXC_FXT1:
964 case ISL_TXC_RGTC1:
965 case ISL_TXC_RGTC2:
966 case ISL_TXC_BPTC:
967 case ISL_TXC_ETC1:
968 case ISL_TXC_ETC2:
969 case ISL_TXC_ASTC:
970 return false;
971 }
972
973 unreachable("bad texture compression mode");
974 return false;
975 }
976
977 static inline bool
978 isl_format_is_yuv(enum isl_format fmt)
979 {
980 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
981
982 return fmtl->colorspace == ISL_COLORSPACE_YUV;
983 }
984
985 static inline bool
986 isl_format_block_is_1x1x1(enum isl_format fmt)
987 {
988 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
989
990 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
991 }
992
993 static inline bool
994 isl_format_is_rgb(enum isl_format fmt)
995 {
996 return isl_format_layouts[fmt].channels.r.bits > 0 &&
997 isl_format_layouts[fmt].channels.g.bits > 0 &&
998 isl_format_layouts[fmt].channels.b.bits > 0 &&
999 isl_format_layouts[fmt].channels.a.bits == 0;
1000 }
1001
1002 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1003 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1004
1005 bool isl_is_storage_image_format(enum isl_format fmt);
1006
1007 enum isl_format
1008 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
1009 enum isl_format fmt);
1010
1011 /* Returns true if this hardware supports typed load/store on a format with
1012 * the same size as the given format.
1013 */
1014 bool
1015 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
1016 enum isl_format fmt);
1017
1018 static inline bool
1019 isl_tiling_is_any_y(enum isl_tiling tiling)
1020 {
1021 return (1u << tiling) & ISL_TILING_ANY_MASK;
1022 }
1023
1024 static inline bool
1025 isl_tiling_is_std_y(enum isl_tiling tiling)
1026 {
1027 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1028 }
1029
1030 bool
1031 isl_tiling_get_info(const struct isl_device *dev,
1032 enum isl_tiling tiling,
1033 uint32_t format_bpb,
1034 struct isl_tile_info *info);
1035 bool
1036 isl_surf_choose_tiling(const struct isl_device *dev,
1037 const struct isl_surf_init_info *restrict info,
1038 enum isl_tiling *tiling);
1039
1040 static inline bool
1041 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1042 {
1043 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1044 }
1045
1046 static inline bool
1047 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1048 {
1049 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1050 }
1051
1052 static inline bool
1053 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1054 {
1055 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1056 }
1057
1058 static inline bool
1059 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1060 {
1061 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1062 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1063 }
1064
1065 static inline bool
1066 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1067 {
1068 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1069 }
1070
1071 static inline bool
1072 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1073 {
1074 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1075 (info->format == ISL_FORMAT_R16_UNORM);
1076 }
1077
1078 static inline bool
1079 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1080 {
1081 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1082 (info->format == ISL_FORMAT_R32_FLOAT);
1083 }
1084
1085 static inline struct isl_extent2d
1086 isl_extent2d(uint32_t width, uint32_t height)
1087 {
1088 struct isl_extent2d e = { { 0 } };
1089
1090 e.width = width;
1091 e.height = height;
1092
1093 return e;
1094 }
1095
1096 static inline struct isl_extent3d
1097 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1098 {
1099 struct isl_extent3d e = { { 0 } };
1100
1101 e.width = width;
1102 e.height = height;
1103 e.depth = depth;
1104
1105 return e;
1106 }
1107
1108 static inline struct isl_extent4d
1109 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1110 uint32_t array_len)
1111 {
1112 struct isl_extent4d e = { { 0 } };
1113
1114 e.width = width;
1115 e.height = height;
1116 e.depth = depth;
1117 e.array_len = array_len;
1118
1119 return e;
1120 }
1121
1122 #define isl_surf_init(dev, surf, ...) \
1123 isl_surf_init_s((dev), (surf), \
1124 &(struct isl_surf_init_info) { __VA_ARGS__ });
1125
1126 bool
1127 isl_surf_init_s(const struct isl_device *dev,
1128 struct isl_surf *surf,
1129 const struct isl_surf_init_info *restrict info);
1130
1131 void
1132 isl_surf_get_tile_info(const struct isl_device *dev,
1133 const struct isl_surf *surf,
1134 struct isl_tile_info *tile_info);
1135
1136 #define isl_surf_fill_state(dev, state, ...) \
1137 isl_surf_fill_state_s((dev), (state), \
1138 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1139
1140 void
1141 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1142 const struct isl_surf_fill_state_info *restrict info);
1143
1144 #define isl_buffer_fill_state(dev, state, ...) \
1145 isl_buffer_fill_state_s((dev), (state), \
1146 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1147
1148 void
1149 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1150 const struct isl_buffer_fill_state_info *restrict info);
1151
1152 void
1153 isl_surf_fill_image_param(const struct isl_device *dev,
1154 struct brw_image_param *param,
1155 const struct isl_surf *surf,
1156 const struct isl_view *view);
1157
1158 void
1159 isl_buffer_fill_image_param(const struct isl_device *dev,
1160 struct brw_image_param *param,
1161 enum isl_format format,
1162 uint64_t size);
1163
1164 /**
1165 * Alignment of the upper-left sample of each subimage, in units of surface
1166 * elements.
1167 */
1168 static inline struct isl_extent3d
1169 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1170 {
1171 return surf->image_alignment_el;
1172 }
1173
1174 /**
1175 * Alignment of the upper-left sample of each subimage, in units of surface
1176 * samples.
1177 */
1178 static inline struct isl_extent3d
1179 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1180 {
1181 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1182
1183 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1184 fmtl->bh * surf->image_alignment_el.h,
1185 fmtl->bd * surf->image_alignment_el.d);
1186 }
1187
1188 /**
1189 * Pitch between vertically adjacent surface elements, in bytes.
1190 */
1191 static inline uint32_t
1192 isl_surf_get_row_pitch(const struct isl_surf *surf)
1193 {
1194 return surf->row_pitch;
1195 }
1196
1197 /**
1198 * Pitch between vertically adjacent surface elements, in units of surface elements.
1199 */
1200 static inline uint32_t
1201 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1202 {
1203 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1204
1205 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1206 return surf->row_pitch / (fmtl->bpb / 8);
1207 }
1208
1209 /**
1210 * Pitch between physical array slices, in rows of surface elements.
1211 */
1212 static inline uint32_t
1213 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1214 {
1215 return surf->array_pitch_el_rows;
1216 }
1217
1218 /**
1219 * Pitch between physical array slices, in units of surface elements.
1220 */
1221 static inline uint32_t
1222 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1223 {
1224 return isl_surf_get_array_pitch_el_rows(surf) *
1225 isl_surf_get_row_pitch_el(surf);
1226 }
1227
1228 /**
1229 * Pitch between physical array slices, in rows of surface samples.
1230 */
1231 static inline uint32_t
1232 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1233 {
1234 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1235 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1236 }
1237
1238 /**
1239 * Pitch between physical array slices, in bytes.
1240 */
1241 static inline uint32_t
1242 isl_surf_get_array_pitch(const struct isl_surf *surf)
1243 {
1244 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1245 }
1246
1247 /**
1248 * Calculate the offset, in units of surface elements, to a subimage in the
1249 * surface.
1250 *
1251 * @invariant level < surface levels
1252 * @invariant logical_array_layer < logical array length of surface
1253 * @invariant logical_z_offset_px < logical depth of surface at level
1254 */
1255 void
1256 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1257 uint32_t level,
1258 uint32_t logical_array_layer,
1259 uint32_t logical_z_offset_px,
1260 uint32_t *x_offset_el,
1261 uint32_t *y_offset_el);
1262
1263 /**
1264 * @brief Calculate the intratile offsets to a surface.
1265 *
1266 * In @a base_address_offset return the offset from the base of the surface to
1267 * the base address of the first tile of the subimage. In @a x_offset_B and
1268 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1269 * tile's base to the subimage's first surface element. The x and y offsets
1270 * are intratile offsets; that is, they do not exceed the boundary of the
1271 * surface's tiling format.
1272 */
1273 void
1274 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1275 enum isl_tiling tiling,
1276 uint8_t bs,
1277 uint32_t row_pitch,
1278 uint32_t total_x_offset_B,
1279 uint32_t total_y_offset_rows,
1280 uint32_t *base_address_offset,
1281 uint32_t *x_offset_B,
1282 uint32_t *y_offset_rows);
1283
1284 /**
1285 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1286 *
1287 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1288 * @pre surf->format must be a valid format for depth surfaces
1289 */
1290 uint32_t
1291 isl_surf_get_depth_format(const struct isl_device *dev,
1292 const struct isl_surf *surf);
1293
1294 #ifdef __cplusplus
1295 }
1296 #endif