2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
45 #include "c99_compat.h"
46 #include "util/macros.h"
52 struct gen_device_info
;
53 struct brw_image_param
;
57 * @brief Get the hardware generation of isl_device.
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
73 #ifndef ISL_DEV_IS_HASWELL
75 * @brief Get the hardware generation of isl_device.
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 * Hardware enumeration SURFACE_FORMAT.
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
106 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
107 ISL_FORMAT_R32G32B32A32_SINT
= 1,
108 ISL_FORMAT_R32G32B32A32_UINT
= 2,
109 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
110 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
111 ISL_FORMAT_R64G64_FLOAT
= 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
114 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
116 ISL_FORMAT_R64G64_PASSTHRU
= 33,
117 ISL_FORMAT_R32G32B32_FLOAT
= 64,
118 ISL_FORMAT_R32G32B32_SINT
= 65,
119 ISL_FORMAT_R32G32B32_UINT
= 66,
120 ISL_FORMAT_R32G32B32_UNORM
= 67,
121 ISL_FORMAT_R32G32B32_SNORM
= 68,
122 ISL_FORMAT_R32G32B32_SSCALED
= 69,
123 ISL_FORMAT_R32G32B32_USCALED
= 70,
124 ISL_FORMAT_R32G32B32_SFIXED
= 80,
125 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
126 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
127 ISL_FORMAT_R16G16B16A16_SINT
= 130,
128 ISL_FORMAT_R16G16B16A16_UINT
= 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
130 ISL_FORMAT_R32G32_FLOAT
= 133,
131 ISL_FORMAT_R32G32_SINT
= 134,
132 ISL_FORMAT_R32G32_UINT
= 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
135 ISL_FORMAT_L32A32_FLOAT
= 138,
136 ISL_FORMAT_R32G32_UNORM
= 139,
137 ISL_FORMAT_R32G32_SNORM
= 140,
138 ISL_FORMAT_R64_FLOAT
= 141,
139 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
141 ISL_FORMAT_A32X32_FLOAT
= 144,
142 ISL_FORMAT_L32X32_FLOAT
= 145,
143 ISL_FORMAT_I32X32_FLOAT
= 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
145 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
146 ISL_FORMAT_R32G32_SSCALED
= 149,
147 ISL_FORMAT_R32G32_USCALED
= 150,
148 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
149 ISL_FORMAT_R32G32_SFIXED
= 160,
150 ISL_FORMAT_R64_PASSTHRU
= 161,
151 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
153 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
155 ISL_FORMAT_R10G10B10A2_UINT
= 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
157 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
159 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
160 ISL_FORMAT_R8G8B8A8_SINT
= 202,
161 ISL_FORMAT_R8G8B8A8_UINT
= 203,
162 ISL_FORMAT_R16G16_UNORM
= 204,
163 ISL_FORMAT_R16G16_SNORM
= 205,
164 ISL_FORMAT_R16G16_SINT
= 206,
165 ISL_FORMAT_R16G16_UINT
= 207,
166 ISL_FORMAT_R16G16_FLOAT
= 208,
167 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
169 ISL_FORMAT_R11G11B10_FLOAT
= 211,
170 ISL_FORMAT_R32_SINT
= 214,
171 ISL_FORMAT_R32_UINT
= 215,
172 ISL_FORMAT_R32_FLOAT
= 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
175 ISL_FORMAT_L32_UNORM
= 221,
176 ISL_FORMAT_A32_UNORM
= 222,
177 ISL_FORMAT_L16A16_UNORM
= 223,
178 ISL_FORMAT_I24X8_UNORM
= 224,
179 ISL_FORMAT_L24X8_UNORM
= 225,
180 ISL_FORMAT_A24X8_UNORM
= 226,
181 ISL_FORMAT_I32_FLOAT
= 227,
182 ISL_FORMAT_L32_FLOAT
= 228,
183 ISL_FORMAT_A32_FLOAT
= 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
187 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
189 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
192 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
193 ISL_FORMAT_L16A16_FLOAT
= 240,
194 ISL_FORMAT_R32_UNORM
= 241,
195 ISL_FORMAT_R32_SNORM
= 242,
196 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
198 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
199 ISL_FORMAT_R16G16_SSCALED
= 246,
200 ISL_FORMAT_R16G16_USCALED
= 247,
201 ISL_FORMAT_R32_SSCALED
= 248,
202 ISL_FORMAT_R32_USCALED
= 249,
203 ISL_FORMAT_B5G6R5_UNORM
= 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
205 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
207 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
209 ISL_FORMAT_R8G8_UNORM
= 262,
210 ISL_FORMAT_R8G8_SNORM
= 263,
211 ISL_FORMAT_R8G8_SINT
= 264,
212 ISL_FORMAT_R8G8_UINT
= 265,
213 ISL_FORMAT_R16_UNORM
= 266,
214 ISL_FORMAT_R16_SNORM
= 267,
215 ISL_FORMAT_R16_SINT
= 268,
216 ISL_FORMAT_R16_UINT
= 269,
217 ISL_FORMAT_R16_FLOAT
= 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
220 ISL_FORMAT_I16_UNORM
= 273,
221 ISL_FORMAT_L16_UNORM
= 274,
222 ISL_FORMAT_A16_UNORM
= 275,
223 ISL_FORMAT_L8A8_UNORM
= 276,
224 ISL_FORMAT_I16_FLOAT
= 277,
225 ISL_FORMAT_L16_FLOAT
= 278,
226 ISL_FORMAT_A16_FLOAT
= 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
229 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
231 ISL_FORMAT_R8G8_SSCALED
= 284,
232 ISL_FORMAT_R8G8_USCALED
= 285,
233 ISL_FORMAT_R16_SSCALED
= 286,
234 ISL_FORMAT_R16_USCALED
= 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
237 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
238 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
239 ISL_FORMAT_L8A8_UINT
= 294,
240 ISL_FORMAT_L8A8_SINT
= 295,
241 ISL_FORMAT_R8_UNORM
= 320,
242 ISL_FORMAT_R8_SNORM
= 321,
243 ISL_FORMAT_R8_SINT
= 322,
244 ISL_FORMAT_R8_UINT
= 323,
245 ISL_FORMAT_A8_UNORM
= 324,
246 ISL_FORMAT_I8_UNORM
= 325,
247 ISL_FORMAT_L8_UNORM
= 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
250 ISL_FORMAT_R8_SSCALED
= 329,
251 ISL_FORMAT_R8_USCALED
= 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
253 ISL_FORMAT_L8_UNORM_SRGB
= 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
257 ISL_FORMAT_Y8_UNORM
= 336,
258 ISL_FORMAT_L8_UINT
= 338,
259 ISL_FORMAT_L8_SINT
= 339,
260 ISL_FORMAT_I8_UINT
= 340,
261 ISL_FORMAT_I8_SINT
= 341,
262 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
263 ISL_FORMAT_R1_UNORM
= 385,
264 ISL_FORMAT_YCRCB_NORMAL
= 386,
265 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
268 ISL_FORMAT_BC1_UNORM
= 390,
269 ISL_FORMAT_BC2_UNORM
= 391,
270 ISL_FORMAT_BC3_UNORM
= 392,
271 ISL_FORMAT_BC4_UNORM
= 393,
272 ISL_FORMAT_BC5_UNORM
= 394,
273 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
274 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
275 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
276 ISL_FORMAT_MONO8
= 398,
277 ISL_FORMAT_YCRCB_SWAPUV
= 399,
278 ISL_FORMAT_YCRCB_SWAPY
= 400,
279 ISL_FORMAT_DXT1_RGB
= 401,
280 ISL_FORMAT_FXT1
= 402,
281 ISL_FORMAT_R8G8B8_UNORM
= 403,
282 ISL_FORMAT_R8G8B8_SNORM
= 404,
283 ISL_FORMAT_R8G8B8_SSCALED
= 405,
284 ISL_FORMAT_R8G8B8_USCALED
= 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
286 ISL_FORMAT_R64G64B64_FLOAT
= 408,
287 ISL_FORMAT_BC4_SNORM
= 409,
288 ISL_FORMAT_BC5_SNORM
= 410,
289 ISL_FORMAT_R16G16B16_FLOAT
= 411,
290 ISL_FORMAT_R16G16B16_UNORM
= 412,
291 ISL_FORMAT_R16G16B16_SNORM
= 413,
292 ISL_FORMAT_R16G16B16_SSCALED
= 414,
293 ISL_FORMAT_R16G16B16_USCALED
= 415,
294 ISL_FORMAT_BC6H_SF16
= 417,
295 ISL_FORMAT_BC7_UNORM
= 418,
296 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
297 ISL_FORMAT_BC6H_UF16
= 420,
298 ISL_FORMAT_PLANAR_420_8
= 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
300 ISL_FORMAT_ETC1_RGB8
= 425,
301 ISL_FORMAT_ETC2_RGB8
= 426,
302 ISL_FORMAT_EAC_R11
= 427,
303 ISL_FORMAT_EAC_RG11
= 428,
304 ISL_FORMAT_EAC_SIGNED_R11
= 429,
305 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
306 ISL_FORMAT_ETC2_SRGB8
= 431,
307 ISL_FORMAT_R16G16B16_UINT
= 432,
308 ISL_FORMAT_R16G16B16_SINT
= 433,
309 ISL_FORMAT_R32_SFIXED
= 434,
310 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
311 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
313 ISL_FORMAT_R10G10B10A2_SINT
= 438,
314 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
315 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
317 ISL_FORMAT_B10G10R10A2_UINT
= 442,
318 ISL_FORMAT_B10G10R10A2_SINT
= 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
321 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
325 ISL_FORMAT_R8G8B8_UINT
= 456,
326 ISL_FORMAT_R8G8B8_SINT
= 457,
327 ISL_FORMAT_RAW
= 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16
= 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16
= 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16
= 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16
= 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16
= 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16
= 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16
= 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16
= 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16
= 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16
= 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16
= 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16
= 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16
= 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16
= 895,
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
376 /* Formats for auxiliary surfaces */
382 ISL_FORMAT_GEN7_CCS_32BPP_X
,
383 ISL_FORMAT_GEN7_CCS_64BPP_X
,
384 ISL_FORMAT_GEN7_CCS_128BPP_X
,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
388 ISL_FORMAT_GEN9_CCS_32BPP
,
389 ISL_FORMAT_GEN9_CCS_64BPP
,
390 ISL_FORMAT_GEN9_CCS_128BPP
,
392 /* Hardware doesn't understand this out-of-band value */
393 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
397 * Numerical base type for channels of isl_format.
415 * Colorspace of isl_format.
417 enum isl_colorspace
{
418 ISL_COLORSPACE_NONE
= 0,
419 ISL_COLORSPACE_LINEAR
,
425 * Texture compression mode of isl_format.
440 /* Used for auxiliary surface formats */
447 * @brief Hardware tile mode
449 * WARNING: These values differ from the hardware enum values, which are
450 * unstable across hardware generations.
452 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
453 * clearly distinguish it from Yf and Ys.
456 ISL_TILING_LINEAR
= 0,
459 ISL_TILING_Y0
, /**< Legacy Y tiling */
460 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
461 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
462 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
463 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
467 * @defgroup Tiling Flags
470 typedef uint32_t isl_tiling_flags_t
;
471 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
472 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
473 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
474 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
475 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
476 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
477 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
478 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
479 #define ISL_TILING_ANY_MASK (~0u)
480 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
482 /** Any Y tiling, including legacy Y tiling. */
483 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
484 ISL_TILING_Yf_BIT | \
487 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
488 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
493 * @brief Logical dimension of surface.
495 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
496 * as 2D array surfaces.
505 * @brief Physical layout of the surface's dimensions.
507 enum isl_dim_layout
{
509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
510 * 6.17.3: 2D Surfaces.
512 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
513 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
515 * One-dimensional surfaces are identical to 2D surfaces with height of
518 * @invariant isl_surf::phys_level0_sa::depth == 1
520 ISL_DIM_LAYOUT_GEN4_2D
,
523 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
524 * 6.17.5: 3D Surfaces.
526 * @invariant isl_surf::phys_level0_sa::array_len == 1
528 ISL_DIM_LAYOUT_GEN4_3D
,
531 * Special layout used for HiZ and stencil on Sandy Bridge to work around
532 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
533 * work the same as on gen7+ except that they don't technically support
534 * mipmapping. That does not, however, stop us from doing it. As far as
535 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
536 * single miplevel 2D (possibly array) image. The dimensions of that image
539 * In order to implement HiZ and stencil on Sandy Bridge, we create one
540 * full-sized 2D (possibly array) image for every LOD with every image
541 * aligned to a page boundary. When the surface is used with the stencil
542 * or HiZ hardware, we manually offset to the image for the given LOD.
544 * As a memory saving measure, we pretend that the width of each miplevel
545 * is minified and we place LOD1 and above below LOD0 but horizontally
546 * adjacent to each other. When considered as full-sized images, LOD1 and
547 * above technically overlap. However, since we only write to part of that
548 * image, the hardware will never notice the overlap.
550 * This layout looks something like this:
568 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
,
571 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
572 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
574 ISL_DIM_LAYOUT_GEN9_1D
,
578 /** No Auxiliary surface is used */
581 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
584 /** The auxiliary surface is an MCS
586 * @invariant isl_surf::samples > 1
590 /** The auxiliary surface is a fast-clear-only compression surface
592 * @invariant isl_surf::samples == 1
596 /** The auxiliary surface provides full lossless color compression
598 * @invariant isl_surf::samples == 1
604 * Enum for keeping track of the state an auxiliary compressed surface.
606 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
607 * given slice (lod + array layer) can be in one of the six states described
608 * by this enum. Draw and resolve operations may cause the slice to change
609 * from one state to another. The six valid states are:
611 * 1) Clear: In this state, each block in the auxiliary surface contains a
612 * magic value that indicates that the block is in the clear state. If
613 * a block is in the clear state, it's values in the primary surface are
614 * ignored and the color of the samples in the block is taken either the
615 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
616 * depth. Since neither the primary surface nor the auxiliary surface
617 * contains the clear value, the surface can be cleared to a different
618 * color by simply changing the clear color without modifying either
621 * 2) Partial Clear: In this state, each block in the auxiliary surface
622 * contains either the magic clear or pass-through value. See Clear and
623 * Pass-through for more details.
625 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
626 * nor the primary surface has a complete representation of the data.
627 * Instead, both surfaces must be used together or else rendering
628 * corruption may occur. Depending on the auxiliary compression format
629 * and the data, any given block in the primary surface may contain all,
630 * some, or none of the data required to reconstruct the actual sample
631 * values. Blocks may also be in the clear state (see Clear) and have
632 * their value taken from outside the surface.
634 * 4) Compressed w/o Clear: This state is identical to the state above
635 * except that no blocks are in the clear state. In this state, all of
636 * the data required to reconstruct the final sample values is contained
637 * in the auxiliary and primary surface and the clear value is not
640 * 5) Resolved: In this state, the primary surface contains 100% of the
641 * data. The auxiliary surface is also valid so the surface can be
642 * validly used with or without aux enabled. The auxiliary surface may,
643 * however, contain non-trivial data and any update to the primary
644 * surface with aux disabled will cause the two to get out of sync.
646 * 6) Pass-through: In this state, the primary surface contains 100% of the
647 * data and every block in the auxiliary surface contains a magic value
648 * which indicates that the auxiliary surface should be ignored and the
649 * only the primary surface should be considered. Updating the primary
650 * surface without aux works fine and can be done repeatedly in this
651 * mode. Writing to a surface in pass-through mode with aux enabled may
652 * cause the auxiliary buffer to contain non-trivial data and no longer
653 * be in the pass-through state.
655 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
656 * data and the auxiliary surface is completely bogus. Any attempt to
657 * use the auxiliary surface is liable to result in rendering
658 * corruption. The only thing that one can do to re-enable aux once
659 * this state is reached is to use an ambiguate pass to transition into
660 * the pass-through state.
662 * Drawing with or without aux enabled may implicitly cause the surface to
663 * transition between these states. There are also four types of auxiliary
664 * compression operations which cause an explicit transition which are
665 * described by the isl_aux_op enum below.
667 * Not all operations are valid or useful in all states. The diagram below
668 * contains a complete description of the states and all valid and useful
669 * transitions except clear.
674 * | +-------------+ Draw w/ Aux +-------------+
675 * +------>| Compressed |<-------------------| Clear |
676 * | w/ Clear |----->----+ | |
677 * +-------------+ | +-------------+
680 * | | +------<-----+ | Draw w/
682 * | | Full | | +----------+
683 * Partial | | Resolve | \|/ | |
684 * Resolve | | | +-------------+ |
685 * | | | | Partial |<------+
686 * | | | | Clear |<----------+
687 * | | | +-------------+ |
689 * | | +------>---------+ Full |
691 * Draw w/ aux | | Partial Fast Clear | |
692 * +----------+ | +--------------------------+ | |
694 * | +-------------+ Full Resolve +-------------+ |
695 * +------>| Compressed |------------------->| Resolved | |
696 * | w/o Clear |<-------------------| | |
697 * +-------------+ Draw w/ Aux +-------------+ |
700 * | w/ Aux | | w/o Aux |
702 * | +--------------------------+ | |
703 * Draw w/o Aux | | | Draw w/o Aux |
704 * +----------+ | | | +----------+ |
705 * | | | \|/ \|/ | | |
706 * | +-------------+ Ambiguate +-------------+ | |
707 * +------>| Pass- |<-------------------| Aux |<------+ |
708 * +------>| through | | Invalid | |
709 * | +-------------+ +-------------+ |
711 * +----------+ +-----------------------------------------------------+
712 * Draw w/ Partial Fast Clear
716 * While the above general theory applies to all forms of auxiliary
717 * compression on Intel hardware, not all states and operations are available
718 * on all compression types. However, each of the auxiliary states and
719 * operations can be fairly easily mapped onto the above diagram:
721 * HiZ: Hierarchical depth compression is capable of being in any of the
722 * states above. Hardware provides three HiZ operations: "Depth
723 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
724 * Clear", "Full Resolve", and "Ambiguate" respectively. The
725 * hardware provides no HiZ partial resolve operation so the only way
726 * to get into the "Compressed w/o Clear" state is to render with HiZ
727 * when the surface is in the resolved or pass-through states.
729 * MCS: Multisample compression is technically capable of being in any of
730 * the states above except that most of them aren't useful. Both the
731 * render engine and the sampler support MCS compression and, apart
732 * from clear color, MCS is format-unaware so we leave the surface
733 * compressed 100% of the time. The hardware provides no MCS
736 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
737 * the simplest forms of compression since they don't do anything
738 * beyond clear color tracking. They really only support three of
739 * the six states: Clear, Partial Clear, and Pass-through. The
740 * only CCS_D operation is "Resolve" which maps to a full resolve
741 * followed by an ambiguate.
743 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
744 * is capable of being in almost all of the above states. THe only
745 * exception is that it does not have separate resolved and pass-
746 * through states. Instead, the CCS_E full resolve operation does
747 * both a resolve and an ambiguate so it goes directly into the
748 * pass-through state. CCS_E also provides fast clear and partial
749 * resolve operations which work as described above.
751 * While it is technically possible to perform a CCS_E ambiguate, it
752 * is not provided by Sky Lake hardware so we choose to avoid the aux
753 * invalid state. If the aux invalid state were determined to be
754 * useful, a CCS ambiguate could be done by carefully rendering to
755 * the CCS and filling it with zeros.
758 ISL_AUX_STATE_CLEAR
= 0,
759 ISL_AUX_STATE_PARTIAL_CLEAR
,
760 ISL_AUX_STATE_COMPRESSED_CLEAR
,
761 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
,
762 ISL_AUX_STATE_RESOLVED
,
763 ISL_AUX_STATE_PASS_THROUGH
,
764 ISL_AUX_STATE_AUX_INVALID
,
768 * Enum which describes explicit aux transition operations.
775 * This operation writes the magic "clear" value to the auxiliary surface.
776 * This operation will safely transition any slice of a surface from any
777 * state to the clear state so long as the entire slice is fast cleared at
778 * once. A fast clear that only covers part of a slice of a surface is
779 * called a partial fast clear.
781 ISL_AUX_OP_FAST_CLEAR
,
785 * This operation combines the auxiliary surface data with the primary
786 * surface data and writes the result to the primary. For HiZ, the docs
787 * call this a depth resolve. For CCS, the hardware full resolve operation
788 * does both a full resolve and an ambiguate so it actually takes you all
789 * the way to the pass-through state.
791 ISL_AUX_OP_FULL_RESOLVE
,
795 * This operation considers blocks which are in the "clear" state and
796 * writes the clear value directly into the primary or auxiliary surface.
797 * Once this operation completes, the surface is still compressed but no
798 * longer references the clear color. This operation is only available
801 ISL_AUX_OP_PARTIAL_RESOLVE
,
805 * This operation throws away the current auxiliary data and replaces it
806 * with the magic pass-through value. If an ambiguate operation is
807 * performed when the primary surface does not contain 100% of the data,
808 * data will be lost. This operation is only implemented in hardware for
809 * depth where it is called a HiZ resolve.
811 ISL_AUX_OP_AMBIGUATE
,
814 /* TODO(chadv): Explain */
815 enum isl_array_pitch_span
{
816 ISL_ARRAY_PITCH_SPAN_FULL
,
817 ISL_ARRAY_PITCH_SPAN_COMPACT
,
821 * @defgroup Surface Usage
824 typedef uint64_t isl_surf_usage_flags_t
;
825 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
826 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
827 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
828 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
829 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
830 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
831 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
832 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
833 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
834 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
835 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
836 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
837 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
838 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
839 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
840 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
844 * @defgroup Channel Mask
846 * These #define values are chosen to match the values of
847 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
851 typedef uint8_t isl_channel_mask_t
;
852 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
853 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
854 #define ISL_CHANNEL_RED_BIT (1 << 2)
855 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
859 * @brief A channel select (also known as texture swizzle) value
861 enum isl_channel_select
{
862 ISL_CHANNEL_SELECT_ZERO
= 0,
863 ISL_CHANNEL_SELECT_ONE
= 1,
864 ISL_CHANNEL_SELECT_RED
= 4,
865 ISL_CHANNEL_SELECT_GREEN
= 5,
866 ISL_CHANNEL_SELECT_BLUE
= 6,
867 ISL_CHANNEL_SELECT_ALPHA
= 7,
871 * Identical to VkSampleCountFlagBits.
873 enum isl_sample_count
{
874 ISL_SAMPLE_COUNT_1_BIT
= 1u,
875 ISL_SAMPLE_COUNT_2_BIT
= 2u,
876 ISL_SAMPLE_COUNT_4_BIT
= 4u,
877 ISL_SAMPLE_COUNT_8_BIT
= 8u,
878 ISL_SAMPLE_COUNT_16_BIT
= 16u,
880 typedef uint32_t isl_sample_count_mask_t
;
883 * @brief Multisample Format
885 enum isl_msaa_layout
{
887 * @brief Suface is single-sampled.
889 ISL_MSAA_LAYOUT_NONE
,
892 * @brief [SNB+] Interleaved Multisample Format
894 * In this format, multiple samples are interleaved into each cacheline.
895 * In other words, the sample index is swizzled into the low 6 bits of the
896 * surface's virtual address space.
898 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
899 * and its pixel format is 32bpp. Then the first cacheline is arranged
902 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
903 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
905 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
906 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
908 * The hardware docs refer to this format with multiple terms. In
909 * Sandybridge, this is the only multisample format; so no term is used.
910 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
911 * Multisample Surface). Later hardware docs additionally refer to this
912 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
915 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
918 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
919 * Multisampled Surfaces".
921 ISL_MSAA_LAYOUT_INTERLEAVED
,
924 * @brief [IVB+] Array Multisample Format
926 * In this format, the surface's physical layout resembles that of a
929 * Suppose the multisample surface's logical extent is (w, h) and its
930 * sample count is N. Then surface's physical extent is the same as
931 * a singlesample 2D surface whose logical extent is (w, h) and array
932 * length is N. Array slice `i` contains the pixel values for sample
935 * The Ivybridge docs refer to surfaces in this format as UMS
936 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
937 * Surface). The Broadwell docs additionally refer to this format as
938 * MSFMT_MSS (MSS=Multisample Surface Storage).
940 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
941 * Multisample Surfaces".
943 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
944 * Multisample Surfaces".
946 ISL_MSAA_LAYOUT_ARRAY
,
951 const struct gen_device_info
*info
;
952 bool use_separate_stencil
;
953 bool has_bit6_swizzling
;
956 * Describes the layout of a RENDER_SURFACE_STATE structure for the
963 uint8_t aux_addr_offset
;
965 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
967 /* size of the state buffer used to store the clear color + extra
968 * additional space used by the hardware */
969 uint8_t clear_color_state_size
;
970 uint8_t clear_color_state_offset
;
971 /* size of the clear color itself - used to copy it to/from a BO */
972 uint8_t clear_value_size
;
973 uint8_t clear_value_offset
;
977 * Describes the layout of the depth/stencil/hiz commands as emitted by
978 * isl_emit_depth_stencil_hiz.
982 uint8_t depth_offset
;
983 uint8_t stencil_offset
;
988 struct isl_extent2d
{
989 union { uint32_t w
, width
; };
990 union { uint32_t h
, height
; };
993 struct isl_extent3d
{
994 union { uint32_t w
, width
; };
995 union { uint32_t h
, height
; };
996 union { uint32_t d
, depth
; };
999 struct isl_extent4d
{
1000 union { uint32_t w
, width
; };
1001 union { uint32_t h
, height
; };
1002 union { uint32_t d
, depth
; };
1003 union { uint32_t a
, array_len
; };
1006 struct isl_channel_layout
{
1007 enum isl_base_type type
;
1008 uint8_t bits
; /**< Size in bits */
1012 * Each format has 3D block extent (width, height, depth). The block extent of
1013 * compressed formats is that of the format's compression block. For example,
1014 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1015 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1016 * is (w=1, h=1, d=1).
1018 struct isl_format_layout
{
1019 enum isl_format format
;
1022 uint16_t bpb
; /**< Bits per block */
1023 uint8_t bw
; /**< Block width, in pixels */
1024 uint8_t bh
; /**< Block height, in pixels */
1025 uint8_t bd
; /**< Block depth, in pixels */
1029 struct isl_channel_layout r
; /**< Red channel */
1030 struct isl_channel_layout g
; /**< Green channel */
1031 struct isl_channel_layout b
; /**< Blue channel */
1032 struct isl_channel_layout a
; /**< Alpha channel */
1033 struct isl_channel_layout l
; /**< Luminance channel */
1034 struct isl_channel_layout i
; /**< Intensity channel */
1035 struct isl_channel_layout p
; /**< Palette channel */
1037 struct isl_channel_layout channels_array
[7];
1040 enum isl_colorspace colorspace
;
1044 struct isl_tile_info
{
1045 enum isl_tiling tiling
;
1047 /* The size (in bits per block) of a single surface element
1049 * For surfaces with power-of-two formats, this is the same as
1050 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1051 * The logical_extent_el field is in terms of elements of this size.
1053 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1054 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1055 * of the tiling formats can actually hold an integer number of 96-bit
1056 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1057 * 32-bit element size. It is the responsibility of the caller to
1058 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1059 * the width of a surface in tiles, you would do:
1061 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1062 * tile_info.logical_extent_el.width);
1064 uint32_t format_bpb
;
1066 /** The logical size of the tile in units of format_bpb size elements
1068 * This field determines how a given surface is cut up into tiles. It is
1069 * used to compute the size of a surface in tiles and can be used to
1070 * determine the location of the tile containing any given surface element.
1071 * The exact value of this field depends heavily on the bits-per-block of
1072 * the format being used.
1074 struct isl_extent2d logical_extent_el
;
1076 /** The physical size of the tile in bytes and rows of bytes
1078 * This field determines how the tiles of a surface are physically layed
1079 * out in memory. The logical and physical tile extent are frequently the
1080 * same but this is not always the case. For instance, a W-tile (which is
1081 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1082 * its physical size is 128B x 32rows, the same as a Y-tile.
1084 * @see isl_surf::row_pitch
1086 struct isl_extent2d phys_extent_B
;
1090 * Metadata about a DRM format modifier.
1092 struct isl_drm_modifier_info
{
1095 /** Text name of the modifier */
1098 /** ISL tiling implied by this modifier */
1099 enum isl_tiling tiling
;
1101 /** ISL aux usage implied by this modifier */
1102 enum isl_aux_usage aux_usage
;
1104 /** Whether or not this modifier supports clear color */
1105 bool supports_clear_color
;
1109 * @brief Input to surface initialization
1111 * @invariant width >= 1
1112 * @invariant height >= 1
1113 * @invariant depth >= 1
1114 * @invariant levels >= 1
1115 * @invariant samples >= 1
1116 * @invariant array_len >= 1
1118 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1119 * @invariant if 2D then depth == 1
1120 * @invariant if 3D then array_len == 1 and samples == 1
1122 struct isl_surf_init_info
{
1123 enum isl_surf_dim dim
;
1124 enum isl_format format
;
1133 /** Lower bound for isl_surf::alignment, in bytes. */
1134 uint32_t min_alignment
;
1137 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1138 * will fail if this is misaligned or out of bounds.
1142 isl_surf_usage_flags_t usage
;
1144 /** Flags that alter how ISL selects isl_surf::tiling. */
1145 isl_tiling_flags_t tiling_flags
;
1149 enum isl_surf_dim dim
;
1150 enum isl_dim_layout dim_layout
;
1151 enum isl_msaa_layout msaa_layout
;
1152 enum isl_tiling tiling
;
1153 enum isl_format format
;
1156 * Alignment of the upper-left sample of each subimage, in units of surface
1159 struct isl_extent3d image_alignment_el
;
1162 * Logical extent of the surface's base level, in units of pixels. This is
1163 * identical to the extent defined in isl_surf_init_info.
1165 struct isl_extent4d logical_level0_px
;
1168 * Physical extent of the surface's base level, in units of physical
1169 * surface samples and aligned to the format's compression block.
1171 * Consider isl_dim_layout as an operator that transforms a logical surface
1172 * layout to a physical surface layout. Then
1174 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1175 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1177 struct isl_extent4d phys_level0_sa
;
1182 /** Total size of the surface, in bytes. */
1185 /** Required alignment for the surface's base address. */
1189 * The interpretation of this field depends on the value of
1190 * isl_tile_info::physical_extent_B. In particular, the width of the
1191 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
1192 * and the distance in bytes between vertically adjacent tiles in the image
1193 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
1195 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1196 * this cleanly reduces to being the distance, in bytes, between vertically
1197 * adjacent surface elements.
1199 * @see isl_tile_info::phys_extent_B;
1204 * Pitch between physical array slices, in rows of surface elements.
1206 uint32_t array_pitch_el_rows
;
1208 enum isl_array_pitch_span array_pitch_span
;
1210 /** Copy of isl_surf_init_info::usage. */
1211 isl_surf_usage_flags_t usage
;
1214 struct isl_swizzle
{
1215 enum isl_channel_select r
:4;
1216 enum isl_channel_select g
:4;
1217 enum isl_channel_select b
:4;
1218 enum isl_channel_select a
:4;
1221 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1222 .r = ISL_CHANNEL_SELECT_##R, \
1223 .g = ISL_CHANNEL_SELECT_##G, \
1224 .b = ISL_CHANNEL_SELECT_##B, \
1225 .a = ISL_CHANNEL_SELECT_##A, \
1228 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1232 * Indicates the usage of the particular view
1234 * Normally, this is one bit. However, for a cube map texture, it
1235 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1237 isl_surf_usage_flags_t usage
;
1240 * The format to use in the view
1242 * This may differ from the format of the actual isl_surf but must have
1243 * the same block size.
1245 enum isl_format format
;
1247 uint32_t base_level
;
1253 * For cube maps, both base_array_layer and array_len should be
1254 * specified in terms of 2-D layers and must be a multiple of 6.
1256 * 3-D textures are effectively treated as 2-D arrays when used as a
1257 * storage image or render target. If `usage` contains
1258 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1259 * base_array_layer and array_len are applied. If the surface is only used
1260 * for texturing, they are ignored.
1262 uint32_t base_array_layer
;
1267 * Indicates the number of array elements starting at Base Array Layer.
1271 struct isl_swizzle swizzle
;
1274 union isl_color_value
{
1280 struct isl_surf_fill_state_info
{
1281 const struct isl_surf
*surf
;
1282 const struct isl_view
*view
;
1285 * The address of the surface in GPU memory.
1290 * The Memory Object Control state for the filled surface state.
1292 * The exact format of this value depends on hardware generation.
1297 * The auxilary surface or NULL if no auxilary surface is to be used.
1299 const struct isl_surf
*aux_surf
;
1300 enum isl_aux_usage aux_usage
;
1301 uint64_t aux_address
;
1304 * The clear color for this surface
1306 * Valid values depend on hardware generation.
1308 union isl_color_value clear_color
;
1311 * Send only the clear value address
1313 * If set, we only pass the clear address to the GPU and it will fetch it
1314 * from wherever it is.
1316 bool use_clear_address
;
1317 uint64_t clear_address
;
1320 * Surface write disables for gen4-5
1322 isl_channel_mask_t write_disables
;
1324 /* Intra-tile offset */
1325 uint16_t x_offset_sa
, y_offset_sa
;
1328 struct isl_buffer_fill_state_info
{
1330 * The address of the surface in GPU memory.
1335 * The size of the buffer
1340 * The Memory Object Control state for the filled surface state.
1342 * The exact format of this value depends on hardware generation.
1347 * The format to use in the surface state
1349 * This may differ from the format of the actual isl_surf but have the
1352 enum isl_format format
;
1357 struct isl_depth_stencil_hiz_emit_info
{
1361 const struct isl_surf
*depth_surf
;
1364 * The stencil surface
1366 * If separate stencil is not available, this must point to the same
1367 * isl_surf as depth_surf.
1369 const struct isl_surf
*stencil_surf
;
1372 * The view into the depth and stencil surfaces.
1374 * This view applies to both surfaces simultaneously.
1376 const struct isl_view
*view
;
1379 * The address of the depth surface in GPU memory
1381 uint64_t depth_address
;
1384 * The address of the stencil surface in GPU memory
1386 * If separate stencil is not available, this must have the same value as
1389 uint64_t stencil_address
;
1392 * The Memory Object Control state for depth and stencil buffers
1394 * Both depth and stencil will get the same MOCS value. The exact format
1395 * of this value depends on hardware generation.
1400 * The HiZ surface or NULL if HiZ is disabled.
1402 const struct isl_surf
*hiz_surf
;
1403 enum isl_aux_usage hiz_usage
;
1404 uint64_t hiz_address
;
1407 * The depth clear value
1409 float depth_clear_value
;
1412 extern const struct isl_format_layout isl_format_layouts
[];
1415 isl_device_init(struct isl_device
*dev
,
1416 const struct gen_device_info
*info
,
1417 bool has_bit6_swizzling
);
1419 isl_sample_count_mask_t ATTRIBUTE_CONST
1420 isl_device_get_sample_counts(struct isl_device
*dev
);
1422 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
1423 isl_format_get_layout(enum isl_format fmt
)
1425 return &isl_format_layouts
[fmt
];
1428 bool isl_format_is_valid(enum isl_format
);
1430 static inline const char * ATTRIBUTE_CONST
1431 isl_format_get_name(enum isl_format fmt
)
1433 return isl_format_layouts
[fmt
].name
;
1436 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
1437 enum isl_format format
);
1438 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
1439 enum isl_format format
);
1440 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
1441 enum isl_format format
);
1442 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
1443 enum isl_format format
);
1444 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
1445 enum isl_format format
);
1446 bool isl_format_supports_typed_writes(const struct gen_device_info
*devinfo
,
1447 enum isl_format format
);
1448 bool isl_format_supports_typed_reads(const struct gen_device_info
*devinfo
,
1449 enum isl_format format
);
1450 bool isl_format_supports_ccs_d(const struct gen_device_info
*devinfo
,
1451 enum isl_format format
);
1452 bool isl_format_supports_ccs_e(const struct gen_device_info
*devinfo
,
1453 enum isl_format format
);
1454 bool isl_format_supports_multisampling(const struct gen_device_info
*devinfo
,
1455 enum isl_format format
);
1457 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info
*devinfo
,
1458 enum isl_format format1
,
1459 enum isl_format format2
);
1461 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1462 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1463 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1464 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1465 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1466 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1469 isl_format_has_normalized_channel(enum isl_format fmt
)
1471 return isl_format_has_unorm_channel(fmt
) ||
1472 isl_format_has_snorm_channel(fmt
);
1476 isl_format_has_float_channel(enum isl_format fmt
)
1478 return isl_format_has_ufloat_channel(fmt
) ||
1479 isl_format_has_sfloat_channel(fmt
);
1483 isl_format_has_int_channel(enum isl_format fmt
)
1485 return isl_format_has_uint_channel(fmt
) ||
1486 isl_format_has_sint_channel(fmt
);
1489 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1491 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1494 isl_format_is_compressed(enum isl_format fmt
)
1496 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1498 return fmtl
->txc
!= ISL_TXC_NONE
;
1502 isl_format_has_bc_compression(enum isl_format fmt
)
1504 switch (isl_format_get_layout(fmt
)->txc
) {
1522 unreachable("Should not be called on an aux surface");
1525 unreachable("bad texture compression mode");
1530 isl_format_is_yuv(enum isl_format fmt
)
1532 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1534 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1538 isl_format_block_is_1x1x1(enum isl_format fmt
)
1540 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1542 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1546 isl_format_is_srgb(enum isl_format fmt
)
1548 return isl_format_layouts
[fmt
].colorspace
== ISL_COLORSPACE_SRGB
;
1551 enum isl_format
isl_format_srgb_to_linear(enum isl_format fmt
);
1554 isl_format_is_rgb(enum isl_format fmt
)
1556 if (isl_format_is_yuv(fmt
))
1558 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
1559 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
1560 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
1561 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
1564 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1565 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1567 bool isl_is_storage_image_format(enum isl_format fmt
);
1570 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1571 enum isl_format fmt
);
1573 /* Returns true if this hardware supports typed load/store on a format with
1574 * the same size as the given format.
1577 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1578 enum isl_format fmt
);
1581 isl_tiling_is_any_y(enum isl_tiling tiling
)
1583 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1587 isl_tiling_is_std_y(enum isl_tiling tiling
)
1589 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1593 isl_tiling_to_i915_tiling(enum isl_tiling tiling
);
1596 isl_tiling_from_i915_tiling(uint32_t tiling
);
1598 const struct isl_drm_modifier_info
* ATTRIBUTE_CONST
1599 isl_drm_modifier_get_info(uint64_t modifier
);
1602 isl_drm_modifier_has_aux(uint64_t modifier
)
1604 return isl_drm_modifier_get_info(modifier
)->aux_usage
!= ISL_AUX_USAGE_NONE
;
1607 /** Returns the default isl_aux_state for the given modifier.
1609 * If we have a modifier which supports compression, then the auxiliary data
1610 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1611 * can be in any of the following:
1613 * - ISL_AUX_STATE_CLEAR
1614 * - ISL_AUX_STATE_PARTIAL_CLEAR
1615 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1616 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1617 * - ISL_AUX_STATE_RESOLVED
1618 * - ISL_AUX_STATE_PASS_THROUGH
1620 * If the modifier does not support fast-clears, then we are guaranteed
1621 * that the surface is at least partially resolved and the first three not
1622 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1623 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1624 * because they are the least common denominator of the set of possible aux
1625 * states and will yield a valid interpretation of the aux data.
1627 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1629 static inline enum isl_aux_state
1630 isl_drm_modifier_get_default_aux_state(uint64_t modifier
)
1632 const struct isl_drm_modifier_info
*mod_info
=
1633 isl_drm_modifier_get_info(modifier
);
1635 if (!mod_info
|| mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
)
1636 return ISL_AUX_STATE_AUX_INVALID
;
1638 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1639 return mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1640 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1643 struct isl_extent2d ATTRIBUTE_CONST
1644 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
);
1647 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1649 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1653 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1655 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1659 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1661 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1665 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1667 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1668 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1672 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1674 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1678 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1680 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1681 (info
->format
== ISL_FORMAT_R16_UNORM
);
1685 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1687 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1688 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1691 static inline struct isl_extent2d
1692 isl_extent2d(uint32_t width
, uint32_t height
)
1694 struct isl_extent2d e
= { { 0 } };
1702 static inline struct isl_extent3d
1703 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1705 struct isl_extent3d e
= { { 0 } };
1714 static inline struct isl_extent4d
1715 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1718 struct isl_extent4d e
= { { 0 } };
1723 e
.array_len
= array_len
;
1728 bool isl_color_value_is_zero(union isl_color_value value
,
1729 enum isl_format format
);
1731 bool isl_color_value_is_zero_one(union isl_color_value value
,
1732 enum isl_format format
);
1735 isl_swizzle_is_identity(struct isl_swizzle swizzle
)
1737 return swizzle
.r
== ISL_CHANNEL_SELECT_RED
&&
1738 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
&&
1739 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
&&
1740 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
1744 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
1745 struct isl_swizzle swizzle
);
1748 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
);
1750 isl_swizzle_invert(struct isl_swizzle swizzle
);
1752 #define isl_surf_init(dev, surf, ...) \
1753 isl_surf_init_s((dev), (surf), \
1754 &(struct isl_surf_init_info) { __VA_ARGS__ });
1757 isl_surf_init_s(const struct isl_device
*dev
,
1758 struct isl_surf
*surf
,
1759 const struct isl_surf_init_info
*restrict info
);
1762 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1763 struct isl_tile_info
*tile_info
);
1766 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1767 const struct isl_surf
*surf
,
1768 struct isl_surf
*hiz_surf
);
1771 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1772 const struct isl_surf
*surf
,
1773 struct isl_surf
*mcs_surf
);
1776 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1777 const struct isl_surf
*surf
,
1778 struct isl_surf
*ccs_surf
,
1779 uint32_t row_pitch
/**< Ignored if 0 */);
1781 #define isl_surf_fill_state(dev, state, ...) \
1782 isl_surf_fill_state_s((dev), (state), \
1783 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1786 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1787 const struct isl_surf_fill_state_info
*restrict info
);
1789 #define isl_buffer_fill_state(dev, state, ...) \
1790 isl_buffer_fill_state_s((dev), (state), \
1791 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1794 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1795 const struct isl_buffer_fill_state_info
*restrict info
);
1798 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1799 struct isl_extent3d size
);
1801 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1802 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1803 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1806 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1807 const struct isl_depth_stencil_hiz_emit_info
*restrict info
);
1810 isl_surf_fill_image_param(const struct isl_device
*dev
,
1811 struct brw_image_param
*param
,
1812 const struct isl_surf
*surf
,
1813 const struct isl_view
*view
);
1816 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1817 struct brw_image_param
*param
,
1818 enum isl_format format
,
1822 * Alignment of the upper-left sample of each subimage, in units of surface
1825 static inline struct isl_extent3d
1826 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1828 return surf
->image_alignment_el
;
1832 * Alignment of the upper-left sample of each subimage, in units of surface
1835 static inline struct isl_extent3d
1836 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1838 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1840 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1841 fmtl
->bh
* surf
->image_alignment_el
.h
,
1842 fmtl
->bd
* surf
->image_alignment_el
.d
);
1846 * Pitch between vertically adjacent surface elements, in bytes.
1848 static inline uint32_t
1849 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
1851 return surf
->row_pitch
;
1855 * Pitch between vertically adjacent surface elements, in units of surface elements.
1857 static inline uint32_t
1858 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1860 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1862 assert(surf
->row_pitch
% (fmtl
->bpb
/ 8) == 0);
1863 return surf
->row_pitch
/ (fmtl
->bpb
/ 8);
1867 * Pitch between physical array slices, in rows of surface elements.
1869 static inline uint32_t
1870 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1872 return surf
->array_pitch_el_rows
;
1876 * Pitch between physical array slices, in units of surface elements.
1878 static inline uint32_t
1879 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1881 return isl_surf_get_array_pitch_el_rows(surf
) *
1882 isl_surf_get_row_pitch_el(surf
);
1886 * Pitch between physical array slices, in rows of surface samples.
1888 static inline uint32_t
1889 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1891 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1892 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1896 * Pitch between physical array slices, in bytes.
1898 static inline uint32_t
1899 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1901 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
1905 * Calculate the offset, in units of surface samples, to a subimage in the
1908 * @invariant level < surface levels
1909 * @invariant logical_array_layer < logical array length of surface
1910 * @invariant logical_z_offset_px < logical depth of surface at level
1913 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1915 uint32_t logical_array_layer
,
1916 uint32_t logical_z_offset_px
,
1917 uint32_t *x_offset_sa
,
1918 uint32_t *y_offset_sa
);
1921 * Calculate the offset, in units of surface elements, to a subimage in the
1924 * @invariant level < surface levels
1925 * @invariant logical_array_layer < logical array length of surface
1926 * @invariant logical_z_offset_px < logical depth of surface at level
1929 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1931 uint32_t logical_array_layer
,
1932 uint32_t logical_z_offset_px
,
1933 uint32_t *x_offset_el
,
1934 uint32_t *y_offset_el
);
1937 * Calculate the offset, in bytes and intratile surface samples, to a
1938 * subimage in the surface.
1940 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
1941 * result to isl_tiling_get_intratile_offset_el, and converting the tile
1942 * offsets to samples.
1944 * @invariant level < surface levels
1945 * @invariant logical_array_layer < logical array length of surface
1946 * @invariant logical_z_offset_px < logical depth of surface at level
1949 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
1951 uint32_t logical_array_layer
,
1952 uint32_t logical_z_offset_px
,
1954 uint32_t *x_offset_sa
,
1955 uint32_t *y_offset_sa
);
1958 * Create an isl_surf that represents a particular subimage in the surface.
1960 * The newly created surface will have a single miplevel and array slice. The
1961 * surface lives at the returned byte and intratile offsets, in samples.
1963 * It is safe to call this function with surf == image_surf.
1965 * @invariant level < surface levels
1966 * @invariant logical_array_layer < logical array length of surface
1967 * @invariant logical_z_offset_px < logical depth of surface at level
1970 isl_surf_get_image_surf(const struct isl_device
*dev
,
1971 const struct isl_surf
*surf
,
1973 uint32_t logical_array_layer
,
1974 uint32_t logical_z_offset_px
,
1975 struct isl_surf
*image_surf
,
1977 uint32_t *x_offset_sa
,
1978 uint32_t *y_offset_sa
);
1981 * @brief Calculate the intratile offsets to a surface.
1983 * In @a base_address_offset return the offset from the base of the surface to
1984 * the base address of the first tile of the subimage. In @a x_offset_B and
1985 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1986 * tile's base to the subimage's first surface element. The x and y offsets
1987 * are intratile offsets; that is, they do not exceed the boundary of the
1988 * surface's tiling format.
1991 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
1994 uint32_t total_x_offset_el
,
1995 uint32_t total_y_offset_el
,
1996 uint32_t *base_address_offset
,
1997 uint32_t *x_offset_el
,
1998 uint32_t *y_offset_el
);
2001 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling
,
2002 enum isl_format format
,
2004 uint32_t total_x_offset_sa
,
2005 uint32_t total_y_offset_sa
,
2006 uint32_t *base_address_offset
,
2007 uint32_t *x_offset_sa
,
2008 uint32_t *y_offset_sa
)
2010 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2012 /* For computing the intratile offsets, we actually want a strange unit
2013 * which is samples for multisampled surfaces but elements for compressed
2016 assert(total_x_offset_sa
% fmtl
->bw
== 0);
2017 assert(total_y_offset_sa
% fmtl
->bh
== 0);
2018 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
2019 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
2021 isl_tiling_get_intratile_offset_el(tiling
, fmtl
->bpb
, row_pitch
,
2022 total_x_offset
, total_y_offset
,
2023 base_address_offset
,
2024 x_offset_sa
, y_offset_sa
);
2025 *x_offset_sa
*= fmtl
->bw
;
2026 *y_offset_sa
*= fmtl
->bh
;
2030 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2032 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2033 * @pre surf->format must be a valid format for depth surfaces
2036 isl_surf_get_depth_format(const struct isl_device
*dev
,
2037 const struct isl_surf
*surf
);