src/intel/isl/isl.h

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file
  26  * @brief Intel Surface Layout
  27  *
  28  * Header Layout
  29  * -------------
  30  * The header is ordered as:
  31  *    - forward declarations
  32  *    - macros that may be overridden at compile-time for specific gens
  33  *    - enums and constants
  34  *    - structs and unions
  35  *    - functions
  36  */
  37
  38 #pragma once
  39
  40 #include <assert.h>
  41 #include <stdbool.h>
  42 #include <stdint.h>
  43
  44 #include "c99_compat.h"
  45 #include "util/macros.h"
  46
  47 #ifdef __cplusplus
  48 extern "C" {
  49 #endif
  50
  51 struct brw_device_info;
  52 struct brw_image_param;
  53
  54 #ifndef ISL_DEV_GEN
  55 /**
  56  * @brief Get the hardware generation of isl_device.
  57  *
  58  * You can define this as a compile-time constant in the CFLAGS. For example,
  59  * `gcc -DISL_DEV_GEN(dev)=9 ...`.
  60  */
  61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
  62 #define ISL_DEV_GEN_SANITIZE(__dev)
  63 #else
  64 #define ISL_DEV_GEN_SANITIZE(__dev) \
  65    (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
  66 #endif
  67
  68 #ifndef ISL_DEV_IS_HASWELL
  69 /**
  70  * @brief Get the hardware generation of isl_device.
  71  *
  72  * You can define this as a compile-time constant in the CFLAGS. For example,
  73  * `gcc -DISL_DEV_GEN(dev)=9 ...`.
  74  */
  75 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
  76 #endif
  77
  78 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
  79 /**
  80  * You can define this as a compile-time constant in the CFLAGS. For example,
  81  * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
  82  */
  83 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
  84 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
  85 #else
  86 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
  87    (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
  88 #endif
  89
  90 /**
  91  * Hardware enumeration SURFACE_FORMAT.
  92  *
  93  * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
  94  * Enumerations: SURFACE_FORMAT.
  95  */
  96 enum isl_format {
  97    ISL_FORMAT_R32G32B32A32_FLOAT =                               0,
  98    ISL_FORMAT_R32G32B32A32_SINT =                                1,
  99    ISL_FORMAT_R32G32B32A32_UINT =                                2,
 100    ISL_FORMAT_R32G32B32A32_UNORM =                               3,
 101    ISL_FORMAT_R32G32B32A32_SNORM =                               4,
 102    ISL_FORMAT_R64G64_FLOAT =                                     5,
 103    ISL_FORMAT_R32G32B32X32_FLOAT =                               6,
 104    ISL_FORMAT_R32G32B32A32_SSCALED =                             7,
 105    ISL_FORMAT_R32G32B32A32_USCALED =                             8,
 106    ISL_FORMAT_R32G32B32A32_SFIXED =                             32,
 107    ISL_FORMAT_R64G64_PASSTHRU =                                 33,
 108    ISL_FORMAT_R32G32B32_FLOAT =                                 64,
 109    ISL_FORMAT_R32G32B32_SINT =                                  65,
 110    ISL_FORMAT_R32G32B32_UINT =                                  66,
 111    ISL_FORMAT_R32G32B32_UNORM =                                 67,
 112    ISL_FORMAT_R32G32B32_SNORM =                                 68,
 113    ISL_FORMAT_R32G32B32_SSCALED =                               69,
 114    ISL_FORMAT_R32G32B32_USCALED =                               70,
 115    ISL_FORMAT_R32G32B32_SFIXED =                                80,
 116    ISL_FORMAT_R16G16B16A16_UNORM =                             128,
 117    ISL_FORMAT_R16G16B16A16_SNORM =                             129,
 118    ISL_FORMAT_R16G16B16A16_SINT =                              130,
 119    ISL_FORMAT_R16G16B16A16_UINT =                              131,
 120    ISL_FORMAT_R16G16B16A16_FLOAT =                             132,
 121    ISL_FORMAT_R32G32_FLOAT =                                   133,
 122    ISL_FORMAT_R32G32_SINT =                                    134,
 123    ISL_FORMAT_R32G32_UINT =                                    135,
 124    ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS =                       136,
 125    ISL_FORMAT_X32_TYPELESS_G8X24_UINT =                        137,
 126    ISL_FORMAT_L32A32_FLOAT =                                   138,
 127    ISL_FORMAT_R32G32_UNORM =                                   139,
 128    ISL_FORMAT_R32G32_SNORM =                                   140,
 129    ISL_FORMAT_R64_FLOAT =                                      141,
 130    ISL_FORMAT_R16G16B16X16_UNORM =                             142,
 131    ISL_FORMAT_R16G16B16X16_FLOAT =                             143,
 132    ISL_FORMAT_A32X32_FLOAT =                                   144,
 133    ISL_FORMAT_L32X32_FLOAT =                                   145,
 134    ISL_FORMAT_I32X32_FLOAT =                                   146,
 135    ISL_FORMAT_R16G16B16A16_SSCALED =                           147,
 136    ISL_FORMAT_R16G16B16A16_USCALED =                           148,
 137    ISL_FORMAT_R32G32_SSCALED =                                 149,
 138    ISL_FORMAT_R32G32_USCALED =                                 150,
 139    ISL_FORMAT_R32G32_FLOAT_LD =                                151,
 140    ISL_FORMAT_R32G32_SFIXED =                                  160,
 141    ISL_FORMAT_R64_PASSTHRU =                                   161,
 142    ISL_FORMAT_B8G8R8A8_UNORM =                                 192,
 143    ISL_FORMAT_B8G8R8A8_UNORM_SRGB =                            193,
 144    ISL_FORMAT_R10G10B10A2_UNORM =                              194,
 145    ISL_FORMAT_R10G10B10A2_UNORM_SRGB =                         195,
 146    ISL_FORMAT_R10G10B10A2_UINT =                               196,
 147    ISL_FORMAT_R10G10B10_SNORM_A2_UNORM =                       197,
 148    ISL_FORMAT_R8G8B8A8_UNORM =                                 199,
 149    ISL_FORMAT_R8G8B8A8_UNORM_SRGB =                            200,
 150    ISL_FORMAT_R8G8B8A8_SNORM =                                 201,
 151    ISL_FORMAT_R8G8B8A8_SINT =                                  202,
 152    ISL_FORMAT_R8G8B8A8_UINT =                                  203,
 153    ISL_FORMAT_R16G16_UNORM =                                   204,
 154    ISL_FORMAT_R16G16_SNORM =                                   205,
 155    ISL_FORMAT_R16G16_SINT =                                    206,
 156    ISL_FORMAT_R16G16_UINT =                                    207,
 157    ISL_FORMAT_R16G16_FLOAT =                                   208,
 158    ISL_FORMAT_B10G10R10A2_UNORM =                              209,
 159    ISL_FORMAT_B10G10R10A2_UNORM_SRGB =                         210,
 160    ISL_FORMAT_R11G11B10_FLOAT =                                211,
 161    ISL_FORMAT_R32_SINT =                                       214,
 162    ISL_FORMAT_R32_UINT =                                       215,
 163    ISL_FORMAT_R32_FLOAT =                                      216,
 164    ISL_FORMAT_R24_UNORM_X8_TYPELESS =                          217,
 165    ISL_FORMAT_X24_TYPELESS_G8_UINT =                           218,
 166    ISL_FORMAT_L32_UNORM =                                      221,
 167    ISL_FORMAT_A32_UNORM =                                      222,
 168    ISL_FORMAT_L16A16_UNORM =                                   223,
 169    ISL_FORMAT_I24X8_UNORM =                                    224,
 170    ISL_FORMAT_L24X8_UNORM =                                    225,
 171    ISL_FORMAT_A24X8_UNORM =                                    226,
 172    ISL_FORMAT_I32_FLOAT =                                      227,
 173    ISL_FORMAT_L32_FLOAT =                                      228,
 174    ISL_FORMAT_A32_FLOAT =                                      229,
 175    ISL_FORMAT_X8B8_UNORM_G8R8_SNORM =                          230,
 176    ISL_FORMAT_A8X8_UNORM_G8R8_SNORM =                          231,
 177    ISL_FORMAT_B8X8_UNORM_G8R8_SNORM =                          232,
 178    ISL_FORMAT_B8G8R8X8_UNORM =                                 233,
 179    ISL_FORMAT_B8G8R8X8_UNORM_SRGB =                            234,
 180    ISL_FORMAT_R8G8B8X8_UNORM =                                 235,
 181    ISL_FORMAT_R8G8B8X8_UNORM_SRGB =                            236,
 182    ISL_FORMAT_R9G9B9E5_SHAREDEXP =                             237,
 183    ISL_FORMAT_B10G10R10X2_UNORM =                              238,
 184    ISL_FORMAT_L16A16_FLOAT =                                   240,
 185    ISL_FORMAT_R32_UNORM =                                      241,
 186    ISL_FORMAT_R32_SNORM =                                      242,
 187    ISL_FORMAT_R10G10B10X2_USCALED =                            243,
 188    ISL_FORMAT_R8G8B8A8_SSCALED =                               244,
 189    ISL_FORMAT_R8G8B8A8_USCALED =                               245,
 190    ISL_FORMAT_R16G16_SSCALED =                                 246,
 191    ISL_FORMAT_R16G16_USCALED =                                 247,
 192    ISL_FORMAT_R32_SSCALED =                                    248,
 193    ISL_FORMAT_R32_USCALED =                                    249,
 194    ISL_FORMAT_B5G6R5_UNORM =                                   256,
 195    ISL_FORMAT_B5G6R5_UNORM_SRGB =                              257,
 196    ISL_FORMAT_B5G5R5A1_UNORM =                                 258,
 197    ISL_FORMAT_B5G5R5A1_UNORM_SRGB =                            259,
 198    ISL_FORMAT_B4G4R4A4_UNORM =                                 260,
 199    ISL_FORMAT_B4G4R4A4_UNORM_SRGB =                            261,
 200    ISL_FORMAT_R8G8_UNORM =                                     262,
 201    ISL_FORMAT_R8G8_SNORM =                                     263,
 202    ISL_FORMAT_R8G8_SINT =                                      264,
 203    ISL_FORMAT_R8G8_UINT =                                      265,
 204    ISL_FORMAT_R16_UNORM =                                      266,
 205    ISL_FORMAT_R16_SNORM =                                      267,
 206    ISL_FORMAT_R16_SINT =                                       268,
 207    ISL_FORMAT_R16_UINT =                                       269,
 208    ISL_FORMAT_R16_FLOAT =                                      270,
 209    ISL_FORMAT_A8P8_UNORM_PALETTE0 =                            271,
 210    ISL_FORMAT_A8P8_UNORM_PALETTE1 =                            272,
 211    ISL_FORMAT_I16_UNORM =                                      273,
 212    ISL_FORMAT_L16_UNORM =                                      274,
 213    ISL_FORMAT_A16_UNORM =                                      275,
 214    ISL_FORMAT_L8A8_UNORM =                                     276,
 215    ISL_FORMAT_I16_FLOAT =                                      277,
 216    ISL_FORMAT_L16_FLOAT =                                      278,
 217    ISL_FORMAT_A16_FLOAT =                                      279,
 218    ISL_FORMAT_L8A8_UNORM_SRGB =                                280,
 219    ISL_FORMAT_R5G5_SNORM_B6_UNORM =                            281,
 220    ISL_FORMAT_B5G5R5X1_UNORM =                                 282,
 221    ISL_FORMAT_B5G5R5X1_UNORM_SRGB =                            283,
 222    ISL_FORMAT_R8G8_SSCALED =                                   284,
 223    ISL_FORMAT_R8G8_USCALED =                                   285,
 224    ISL_FORMAT_R16_SSCALED =                                    286,
 225    ISL_FORMAT_R16_USCALED =                                    287,
 226    ISL_FORMAT_P8A8_UNORM_PALETTE0 =                            290,
 227    ISL_FORMAT_P8A8_UNORM_PALETTE1 =                            291,
 228    ISL_FORMAT_A1B5G5R5_UNORM =                                 292,
 229    ISL_FORMAT_A4B4G4R4_UNORM =                                 293,
 230    ISL_FORMAT_L8A8_UINT =                                      294,
 231    ISL_FORMAT_L8A8_SINT =                                      295,
 232    ISL_FORMAT_R8_UNORM =                                       320,
 233    ISL_FORMAT_R8_SNORM =                                       321,
 234    ISL_FORMAT_R8_SINT =                                        322,
 235    ISL_FORMAT_R8_UINT =                                        323,
 236    ISL_FORMAT_A8_UNORM =                                       324,
 237    ISL_FORMAT_I8_UNORM =                                       325,
 238    ISL_FORMAT_L8_UNORM =                                       326,
 239    ISL_FORMAT_P4A4_UNORM_PALETTE0 =                            327,
 240    ISL_FORMAT_A4P4_UNORM_PALETTE0 =                            328,
 241    ISL_FORMAT_R8_SSCALED =                                     329,
 242    ISL_FORMAT_R8_USCALED =                                     330,
 243    ISL_FORMAT_P8_UNORM_PALETTE0 =                              331,
 244    ISL_FORMAT_L8_UNORM_SRGB =                                  332,
 245    ISL_FORMAT_P8_UNORM_PALETTE1 =                              333,
 246    ISL_FORMAT_P4A4_UNORM_PALETTE1 =                            334,
 247    ISL_FORMAT_A4P4_UNORM_PALETTE1 =                            335,
 248    ISL_FORMAT_Y8_UNORM =                                       336,
 249    ISL_FORMAT_L8_UINT =                                        338,
 250    ISL_FORMAT_L8_SINT =                                        339,
 251    ISL_FORMAT_I8_UINT =                                        340,
 252    ISL_FORMAT_I8_SINT =                                        341,
 253    ISL_FORMAT_DXT1_RGB_SRGB =                                  384,
 254    ISL_FORMAT_R1_UNORM =                                       385,
 255    ISL_FORMAT_YCRCB_NORMAL =                                   386,
 256    ISL_FORMAT_YCRCB_SWAPUVY =                                  387,
 257    ISL_FORMAT_P2_UNORM_PALETTE0 =                              388,
 258    ISL_FORMAT_P2_UNORM_PALETTE1 =                              389,
 259    ISL_FORMAT_BC1_UNORM =                                      390,
 260    ISL_FORMAT_BC2_UNORM =                                      391,
 261    ISL_FORMAT_BC3_UNORM =                                      392,
 262    ISL_FORMAT_BC4_UNORM =                                      393,
 263    ISL_FORMAT_BC5_UNORM =                                      394,
 264    ISL_FORMAT_BC1_UNORM_SRGB =                                 395,
 265    ISL_FORMAT_BC2_UNORM_SRGB =                                 396,
 266    ISL_FORMAT_BC3_UNORM_SRGB =                                 397,
 267    ISL_FORMAT_MONO8 =                                          398,
 268    ISL_FORMAT_YCRCB_SWAPUV =                                   399,
 269    ISL_FORMAT_YCRCB_SWAPY =                                    400,
 270    ISL_FORMAT_DXT1_RGB =                                       401,
 271    ISL_FORMAT_FXT1 =                                           402,
 272    ISL_FORMAT_R8G8B8_UNORM =                                   403,
 273    ISL_FORMAT_R8G8B8_SNORM =                                   404,
 274    ISL_FORMAT_R8G8B8_SSCALED =                                 405,
 275    ISL_FORMAT_R8G8B8_USCALED =                                 406,
 276    ISL_FORMAT_R64G64B64A64_FLOAT =                             407,
 277    ISL_FORMAT_R64G64B64_FLOAT =                                408,
 278    ISL_FORMAT_BC4_SNORM =                                      409,
 279    ISL_FORMAT_BC5_SNORM =                                      410,
 280    ISL_FORMAT_R16G16B16_FLOAT =                                411,
 281    ISL_FORMAT_R16G16B16_UNORM =                                412,
 282    ISL_FORMAT_R16G16B16_SNORM =                                413,
 283    ISL_FORMAT_R16G16B16_SSCALED =                              414,
 284    ISL_FORMAT_R16G16B16_USCALED =                              415,
 285    ISL_FORMAT_BC6H_SF16 =                                      417,
 286    ISL_FORMAT_BC7_UNORM =                                      418,
 287    ISL_FORMAT_BC7_UNORM_SRGB =                                 419,
 288    ISL_FORMAT_BC6H_UF16 =                                      420,
 289    ISL_FORMAT_PLANAR_420_8 =                                   421,
 290    ISL_FORMAT_R8G8B8_UNORM_SRGB =                              424,
 291    ISL_FORMAT_ETC1_RGB8 =                                      425,
 292    ISL_FORMAT_ETC2_RGB8 =                                      426,
 293    ISL_FORMAT_EAC_R11 =                                        427,
 294    ISL_FORMAT_EAC_RG11 =                                       428,
 295    ISL_FORMAT_EAC_SIGNED_R11 =                                 429,
 296    ISL_FORMAT_EAC_SIGNED_RG11 =                                430,
 297    ISL_FORMAT_ETC2_SRGB8 =                                     431,
 298    ISL_FORMAT_R16G16B16_UINT =                                 432,
 299    ISL_FORMAT_R16G16B16_SINT =                                 433,
 300    ISL_FORMAT_R32_SFIXED =                                     434,
 301    ISL_FORMAT_R10G10B10A2_SNORM =                              435,
 302    ISL_FORMAT_R10G10B10A2_USCALED =                            436,
 303    ISL_FORMAT_R10G10B10A2_SSCALED =                            437,
 304    ISL_FORMAT_R10G10B10A2_SINT =                               438,
 305    ISL_FORMAT_B10G10R10A2_SNORM =                              439,
 306    ISL_FORMAT_B10G10R10A2_USCALED =                            440,
 307    ISL_FORMAT_B10G10R10A2_SSCALED =                            441,
 308    ISL_FORMAT_B10G10R10A2_UINT =                               442,
 309    ISL_FORMAT_B10G10R10A2_SINT =                               443,
 310    ISL_FORMAT_R64G64B64A64_PASSTHRU =                          444,
 311    ISL_FORMAT_R64G64B64_PASSTHRU =                             445,
 312    ISL_FORMAT_ETC2_RGB8_PTA =                                  448,
 313    ISL_FORMAT_ETC2_SRGB8_PTA =                                 449,
 314    ISL_FORMAT_ETC2_EAC_RGBA8 =                                 450,
 315    ISL_FORMAT_ETC2_EAC_SRGB8_A8 =                              451,
 316    ISL_FORMAT_R8G8B8_UINT =                                    456,
 317    ISL_FORMAT_R8G8B8_SINT =                                    457,
 318    ISL_FORMAT_RAW =                                            511,
 319    ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB =                         512,
 320    ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB =                         520,
 321    ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB =                         521,
 322    ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB =                         529,
 323    ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB =                         530,
 324    ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB =                         545,
 325    ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB =                         546,
 326    ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB =                         548,
 327    ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB =                        561,
 328    ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB =                        562,
 329    ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB =                        564,
 330    ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB =                       566,
 331    ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB =                       574,
 332    ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB =                       575,
 333    ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 =                          576,
 334    ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 =                          584,
 335    ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 =                          585,
 336    ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 =                          593,
 337    ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 =                          594,
 338    ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 =                          609,
 339    ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 =                          610,
 340    ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 =                          612,
 341    ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 =                         625,
 342    ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 =                         626,
 343    ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 =                         628,
 344    ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 =                        630,
 345    ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 =                        638,
 346    ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 =                        639,
 347
 348    /* Hardware doesn't understand this out-of-band value */
 349    ISL_FORMAT_UNSUPPORTED =                             UINT16_MAX,
 350 };
 351
 352 /**
 353  * Numerical base type for channels of isl_format.
 354  */
 355 enum isl_base_type {
 356    ISL_VOID,
 357    ISL_RAW,
 358    ISL_UNORM,
 359    ISL_SNORM,
 360    ISL_UFLOAT,
 361    ISL_SFLOAT,
 362    ISL_UFIXED,
 363    ISL_SFIXED,
 364    ISL_UINT,
 365    ISL_SINT,
 366    ISL_USCALED,
 367    ISL_SSCALED,
 368 };
 369
 370 /**
 371  * Colorspace of isl_format.
 372  */
 373 enum isl_colorspace {
 374    ISL_COLORSPACE_NONE = 0,
 375    ISL_COLORSPACE_LINEAR,
 376    ISL_COLORSPACE_SRGB,
 377    ISL_COLORSPACE_YUV,
 378 };
 379
 380 /**
 381  * Texture compression mode of isl_format.
 382  */
 383 enum isl_txc {
 384    ISL_TXC_NONE = 0,
 385    ISL_TXC_DXT1,
 386    ISL_TXC_DXT3,
 387    ISL_TXC_DXT5,
 388    ISL_TXC_FXT1,
 389    ISL_TXC_RGTC1,
 390    ISL_TXC_RGTC2,
 391    ISL_TXC_BPTC,
 392    ISL_TXC_ETC1,
 393    ISL_TXC_ETC2,
 394    ISL_TXC_ASTC,
 395 };
 396
 397 /**
 398  * @brief Hardware tile mode
 399  *
 400  * WARNING: These values differ from the hardware enum values, which are
 401  * unstable across hardware generations.
 402  *
 403  * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
 404  * clearly distinguish it from Yf and Ys.
 405  */
 406 enum isl_tiling {
 407    ISL_TILING_LINEAR = 0,
 408    ISL_TILING_W,
 409    ISL_TILING_X,
 410    ISL_TILING_Y0, /**< Legacy Y tiling */
 411    ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
 412    ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
 413 };
 414
 415 /**
 416  * @defgroup Tiling Flags
 417  * @{
 418  */
 419 typedef uint32_t isl_tiling_flags_t;
 420 #define ISL_TILING_LINEAR_BIT             (1u << ISL_TILING_LINEAR)
 421 #define ISL_TILING_W_BIT                  (1u << ISL_TILING_W)
 422 #define ISL_TILING_X_BIT                  (1u << ISL_TILING_X)
 423 #define ISL_TILING_Y0_BIT                 (1u << ISL_TILING_Y0)
 424 #define ISL_TILING_Yf_BIT                 (1u << ISL_TILING_Yf)
 425 #define ISL_TILING_Ys_BIT                 (1u << ISL_TILING_Ys)
 426 #define ISL_TILING_ANY_MASK               (~0u)
 427 #define ISL_TILING_NON_LINEAR_MASK        (~ISL_TILING_LINEAR_BIT)
 428
 429 /** Any Y tiling, including legacy Y tiling. */
 430 #define ISL_TILING_ANY_Y_MASK             (ISL_TILING_Y0_BIT | \
 431                                            ISL_TILING_Yf_BIT | \
 432                                            ISL_TILING_Ys_BIT)
 433
 434 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
 435 #define ISL_TILING_STD_Y_MASK             (ISL_TILING_Yf_BIT | \
 436                                            ISL_TILING_Ys_BIT)
 437 /** @} */
 438
 439 /**
 440  * @brief Logical dimension of surface.
 441  *
 442  * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
 443  * as 2D array surfaces.
 444  */
 445 enum isl_surf_dim {
 446    ISL_SURF_DIM_1D,
 447    ISL_SURF_DIM_2D,
 448    ISL_SURF_DIM_3D,
 449 };
 450
 451 /**
 452  * @brief Physical layout of the surface's dimensions.
 453  */
 454 enum isl_dim_layout {
 455    /**
 456     * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
 457     * 6.17.3: 2D Surfaces.
 458     *
 459     * On many gens, 1D surfaces share the same layout as 2D surfaces.  From
 460     * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
 461     *
 462     *    One-dimensional surfaces are identical to 2D surfaces with height of
 463     *    one.
 464     *
 465     * @invariant isl_surf::phys_level0_sa::depth == 1
 466     */
 467    ISL_DIM_LAYOUT_GEN4_2D,
 468
 469    /**
 470     * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
 471     * 6.17.5: 3D Surfaces.
 472     *
 473     * @invariant isl_surf::phys_level0_sa::array_len == 1
 474     */
 475    ISL_DIM_LAYOUT_GEN4_3D,
 476
 477    /**
 478     * For details, see the Skylake BSpec >> Memory Views >> Common Surface
 479     * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
 480     */
 481    ISL_DIM_LAYOUT_GEN9_1D,
 482 };
 483
 484 /* TODO(chadv): Explain */
 485 enum isl_array_pitch_span {
 486    ISL_ARRAY_PITCH_SPAN_FULL,
 487    ISL_ARRAY_PITCH_SPAN_COMPACT,
 488 };
 489
 490 /**
 491  * @defgroup Surface Usage
 492  * @{
 493  */
 494 typedef uint64_t isl_surf_usage_flags_t;
 495 #define ISL_SURF_USAGE_RENDER_TARGET_BIT       (1u << 0)
 496 #define ISL_SURF_USAGE_DEPTH_BIT               (1u << 1)
 497 #define ISL_SURF_USAGE_STENCIL_BIT             (1u << 2)
 498 #define ISL_SURF_USAGE_TEXTURE_BIT             (1u << 3)
 499 #define ISL_SURF_USAGE_CUBE_BIT                (1u << 4)
 500 #define ISL_SURF_USAGE_DISABLE_AUX_BIT         (1u << 5)
 501 #define ISL_SURF_USAGE_DISPLAY_BIT             (1u << 6)
 502 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT   (1u << 7)
 503 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT  (1u << 8)
 504 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT  (1u << 9)
 505 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT      (1u << 10)
 506 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT      (1u << 11)
 507 #define ISL_SURF_USAGE_STORAGE_BIT             (1u << 12)
 508 /** @} */
 509
 510 /**
 511  * @brief A channel select (also known as texture swizzle) value
 512  */
 513 enum isl_channel_select {
 514    ISL_CHANNEL_SELECT_ZERO = 0,
 515    ISL_CHANNEL_SELECT_ONE = 1,
 516    ISL_CHANNEL_SELECT_RED = 4,
 517    ISL_CHANNEL_SELECT_GREEN = 5,
 518    ISL_CHANNEL_SELECT_BLUE = 6,
 519    ISL_CHANNEL_SELECT_ALPHA = 7,
 520 };
 521
 522 /**
 523  * Identical to VkSampleCountFlagBits.
 524  */
 525 enum isl_sample_count {
 526    ISL_SAMPLE_COUNT_1_BIT     = 1u,
 527    ISL_SAMPLE_COUNT_2_BIT     = 2u,
 528    ISL_SAMPLE_COUNT_4_BIT     = 4u,
 529    ISL_SAMPLE_COUNT_8_BIT     = 8u,
 530    ISL_SAMPLE_COUNT_16_BIT    = 16u,
 531 };
 532 typedef uint32_t isl_sample_count_mask_t;
 533
 534 /**
 535  * @brief Multisample Format
 536  */
 537 enum isl_msaa_layout {
 538    /**
 539     * @brief Suface is single-sampled.
 540     */
 541    ISL_MSAA_LAYOUT_NONE,
 542
 543    /**
 544     * @brief [SNB+] Interleaved Multisample Format
 545     *
 546     * In this format, multiple samples are interleaved into each cacheline.
 547     * In other words, the sample index is swizzled into the low 6 bits of the
 548     * surface's virtual address space.
 549     *
 550     * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
 551     * and its pixel format is 32bpp. Then the first cacheline is arranged
 552     * thus:
 553     *
 554     *    (0,0,0) (0,1,0)   (0,0,1) (1,0,1)
 555     *    (1,0,0) (1,1,0)   (0,1,1) (1,1,1)
 556     *
 557     *    (0,0,2) (1,0,2)   (0,0,3) (1,0,3)
 558     *    (0,1,2) (1,1,2)   (0,1,3) (1,1,3)
 559     *
 560     * The hardware docs refer to this format with multiple terms.  In
 561     * Sandybridge, this is the only multisample format; so no term is used.
 562     * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
 563     * Multisample Surface). Later hardware docs additionally refer to this
 564     * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
 565     * color surfaces).
 566     *
 567     * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
 568     * Surface Behavior".
 569     *
 570     * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
 571     * Multisampled Surfaces".
 572     */
 573    ISL_MSAA_LAYOUT_INTERLEAVED,
 574
 575    /**
 576     * @brief [IVB+] Array Multisample Format
 577     *
 578     * In this format, the surface's physical layout resembles that of a
 579     * 2D array surface.
 580     *
 581     * Suppose the multisample surface's logical extent is (w, h) and its
 582     * sample count is N. Then surface's physical extent is the same as
 583     * a singlesample 2D surface whose logical extent is (w, h) and array
 584     * length is N.  Array slice `i` contains the pixel values for sample
 585     * index `i`.
 586     *
 587     * The Ivybridge docs refer to surfaces in this format as UMS
 588     * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
 589     * Surface). The Broadwell docs additionally refer to this format as
 590     * MSFMT_MSS (MSS=Multisample Surface Storage).
 591     *
 592     * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
 593     * Multisample Surfaces".
 594     *
 595     * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
 596     * Multisample Surfaces".
 597     */
 598    ISL_MSAA_LAYOUT_ARRAY,
 599 };
 600
 601
 602 struct isl_device {
 603    const struct brw_device_info *info;
 604    bool use_separate_stencil;
 605    bool has_bit6_swizzling;
 606 };
 607
 608 struct isl_extent2d {
 609    union { uint32_t w, width; };
 610    union { uint32_t h, height; };
 611 };
 612
 613 struct isl_extent3d {
 614    union { uint32_t w, width; };
 615    union { uint32_t h, height; };
 616    union { uint32_t d, depth; };
 617 };
 618
 619 struct isl_extent4d {
 620    union { uint32_t w, width; };
 621    union { uint32_t h, height; };
 622    union { uint32_t d, depth; };
 623    union { uint32_t a, array_len; };
 624 };
 625
 626 struct isl_channel_layout {
 627    enum isl_base_type type;
 628    uint8_t bits; /**< Size in bits */
 629 };
 630
 631 /**
 632  * Each format has 3D block extent (width, height, depth). The block extent of
 633  * compressed formats is that of the format's compression block. For example,
 634  * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1).  The block
 635  * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
 636  * is (w=1, h=1, d=1).
 637  */
 638 struct isl_format_layout {
 639    enum isl_format format;
 640    const char *name;
 641
 642    uint8_t bs; /**< Block size, in bytes, rounded towards 0 */
 643    uint8_t bw; /**< Block width, in pixels */
 644    uint8_t bh; /**< Block height, in pixels */
 645    uint8_t bd; /**< Block depth, in pixels */
 646
 647    struct {
 648       struct isl_channel_layout r; /**< Red channel */
 649       struct isl_channel_layout g; /**< Green channel */
 650       struct isl_channel_layout b; /**< Blue channel */
 651       struct isl_channel_layout a; /**< Alpha channel */
 652       struct isl_channel_layout l; /**< Luminance channel */
 653       struct isl_channel_layout i; /**< Intensity channel */
 654       struct isl_channel_layout p; /**< Palette channel */
 655    } channels;
 656
 657    enum isl_colorspace colorspace;
 658    enum isl_txc txc;
 659 };
 660
 661 struct isl_tile_info {
 662    enum isl_tiling tiling;
 663    uint32_t width; /**< in bytes */
 664    uint32_t height; /**< in rows of memory */
 665    uint32_t size; /**< in bytes */
 666 };
 667
 668 /**
 669  * @brief Input to surface initialization
 670  *
 671  * @invariant width >= 1
 672  * @invariant height >= 1
 673  * @invariant depth >= 1
 674  * @invariant levels >= 1
 675  * @invariant samples >= 1
 676  * @invariant array_len >= 1
 677  *
 678  * @invariant if 1D then height == 1 and depth == 1 and samples == 1
 679  * @invariant if 2D then depth == 1
 680  * @invariant if 3D then array_len == 1 and samples == 1
 681  */
 682 struct isl_surf_init_info {
 683    enum isl_surf_dim dim;
 684    enum isl_format format;
 685
 686    uint32_t width;
 687    uint32_t height;
 688    uint32_t depth;
 689    uint32_t levels;
 690    uint32_t array_len;
 691    uint32_t samples;
 692
 693    /** Lower bound for isl_surf::alignment, in bytes. */
 694    uint32_t min_alignment;
 695
 696    /** Lower bound for isl_surf::pitch, in bytes. */
 697    uint32_t min_pitch;
 698
 699    isl_surf_usage_flags_t usage;
 700
 701    /** Flags that alter how ISL selects isl_surf::tiling.  */
 702    isl_tiling_flags_t tiling_flags;
 703 };
 704
 705 struct isl_surf {
 706    enum isl_surf_dim dim;
 707    enum isl_dim_layout dim_layout;
 708    enum isl_msaa_layout msaa_layout;
 709    enum isl_tiling tiling;
 710    enum isl_format format;
 711
 712    /**
 713     * Alignment of the upper-left sample of each subimage, in units of surface
 714     * elements.
 715     */
 716    struct isl_extent3d image_alignment_el;
 717
 718    /**
 719     * Logical extent of the surface's base level, in units of pixels.  This is
 720     * identical to the extent defined in isl_surf_init_info.
 721     */
 722    struct isl_extent4d logical_level0_px;
 723
 724    /**
 725     * Physical extent of the surface's base level, in units of physical
 726     * surface samples and aligned to the format's compression block.
 727     *
 728     * Consider isl_dim_layout as an operator that transforms a logical surface
 729     * layout to a physical surface layout. Then
 730     *
 731     *    logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
 732     *    isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
 733     */
 734    struct isl_extent4d phys_level0_sa;
 735
 736    uint32_t levels;
 737    uint32_t samples;
 738
 739    /** Total size of the surface, in bytes. */
 740    uint32_t size;
 741
 742    /** Required alignment for the surface's base address. */
 743    uint32_t alignment;
 744
 745    /**
 746     * Pitch between vertically adjacent surface elements, in bytes.
 747     */
 748    uint32_t row_pitch;
 749
 750    /**
 751     * Pitch between physical array slices, in rows of surface elements.
 752     */
 753    uint32_t array_pitch_el_rows;
 754
 755    enum isl_array_pitch_span array_pitch_span;
 756
 757    /** Copy of isl_surf_init_info::usage. */
 758    isl_surf_usage_flags_t usage;
 759 };
 760
 761 struct isl_view {
 762    /**
 763     * Indicates the usage of the particular view
 764     *
 765     * Normally, this is one bit.  However, for a cube map texture, it
 766     * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
 767     */
 768    isl_surf_usage_flags_t usage;
 769
 770    /**
 771     * The format to use in the view
 772     *
 773     * This may differ from the format of the actual isl_surf but must have
 774     * the same block size.
 775     */
 776    enum isl_format format;
 777
 778    uint32_t base_level;
 779    uint32_t levels;
 780
 781    /**
 782     * Base array layer
 783     *
 784     * For cube maps, both base_array_layer and array_len should be
 785     * specified in terms of 2-D layers and must be a multiple of 6.
 786     */
 787    uint32_t base_array_layer;
 788    uint32_t array_len;
 789
 790    enum isl_channel_select channel_select[4];
 791 };
 792
 793 union isl_color_value {
 794    float f32[4];
 795    uint32_t u32[4];
 796    int32_t i32[4];
 797 };
 798
 799 struct isl_surf_fill_state_info {
 800    const struct isl_surf *surf;
 801    const struct isl_view *view;
 802
 803    /**
 804     * The address of the surface in GPU memory.
 805     */
 806    uint64_t address;
 807
 808    /**
 809     * The Memory Object Control state for the filled surface state.
 810     *
 811     * The exact format of this value depends on hardware generation.
 812     */
 813    uint32_t mocs;
 814
 815    /**
 816     * The clear color for this surface
 817     *
 818     * Valid values depend on hardware generation.
 819     */
 820    union isl_color_value clear_color;
 821 };
 822
 823 struct isl_buffer_fill_state_info {
 824    /**
 825     * The address of the surface in GPU memory.
 826     */
 827    uint64_t address;
 828
 829    /**
 830     * The size of the buffer
 831     */
 832    uint64_t size;
 833
 834    /**
 835     * The Memory Object Control state for the filled surface state.
 836     *
 837     * The exact format of this value depends on hardware generation.
 838     */
 839    uint32_t mocs;
 840
 841    /**
 842     * The format to use in the surface state
 843     *
 844     * This may differ from the format of the actual isl_surf but have the
 845     * same block size.
 846     */
 847    enum isl_format format;
 848
 849    uint32_t stride;
 850 };
 851
 852 extern const struct isl_format_layout isl_format_layouts[];
 853
 854 void
 855 isl_device_init(struct isl_device *dev,
 856                 const struct brw_device_info *info,
 857                 bool has_bit6_swizzling);
 858
 859 isl_sample_count_mask_t ATTRIBUTE_CONST
 860 isl_device_get_sample_counts(struct isl_device *dev);
 861
 862 static inline const struct isl_format_layout * ATTRIBUTE_CONST
 863 isl_format_get_layout(enum isl_format fmt)
 864 {
 865    return &isl_format_layouts[fmt];
 866 }
 867
 868 static inline const char * ATTRIBUTE_CONST
 869 isl_format_get_name(enum isl_format fmt)
 870 {
 871    return isl_format_layouts[fmt].name;
 872 }
 873
 874 bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
 875                                    enum isl_format format);
 876 bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
 877                                         enum isl_format format);
 878 bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
 879                                   enum isl_format format);
 880 bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
 881                                    enum isl_format format);
 882 bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
 883                                       enum isl_format format);
 884 bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
 885                                               enum isl_format format);
 886
 887 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 888 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 889 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 890 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 891 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 892 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
 893
 894 static inline bool
 895 isl_format_has_normalized_channel(enum isl_format fmt)
 896 {
 897    return isl_format_has_unorm_channel(fmt) ||
 898           isl_format_has_snorm_channel(fmt);
 899 }
 900
 901 static inline bool
 902 isl_format_has_float_channel(enum isl_format fmt)
 903 {
 904    return isl_format_has_ufloat_channel(fmt) ||
 905           isl_format_has_sfloat_channel(fmt);
 906 }
 907
 908 static inline bool
 909 isl_format_has_int_channel(enum isl_format fmt)
 910 {
 911    return isl_format_has_uint_channel(fmt) ||
 912           isl_format_has_sint_channel(fmt);
 913 }
 914
 915 unsigned isl_format_get_num_channels(enum isl_format fmt);
 916
 917 static inline bool
 918 isl_format_is_compressed(enum isl_format fmt)
 919 {
 920    const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
 921
 922    return fmtl->txc != ISL_TXC_NONE;
 923 }
 924
 925 static inline bool
 926 isl_format_has_bc_compression(enum isl_format fmt)
 927 {
 928    switch (isl_format_get_layout(fmt)->txc) {
 929    case ISL_TXC_DXT1:
 930    case ISL_TXC_DXT3:
 931    case ISL_TXC_DXT5:
 932       return true;
 933    case ISL_TXC_NONE:
 934    case ISL_TXC_FXT1:
 935    case ISL_TXC_RGTC1:
 936    case ISL_TXC_RGTC2:
 937    case ISL_TXC_BPTC:
 938    case ISL_TXC_ETC1:
 939    case ISL_TXC_ETC2:
 940    case ISL_TXC_ASTC:
 941       return false;
 942    }
 943
 944    unreachable("bad texture compression mode");
 945    return false;
 946 }
 947
 948 static inline bool
 949 isl_format_is_yuv(enum isl_format fmt)
 950 {
 951    const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
 952
 953    return fmtl->colorspace == ISL_COLORSPACE_YUV;
 954 }
 955
 956 static inline bool
 957 isl_format_block_is_1x1x1(enum isl_format fmt)
 958 {
 959    const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
 960
 961    return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
 962 }
 963
 964 static inline bool
 965 isl_format_is_rgb(enum isl_format fmt)
 966 {
 967    return isl_format_layouts[fmt].channels.r.bits > 0 &&
 968           isl_format_layouts[fmt].channels.g.bits > 0 &&
 969           isl_format_layouts[fmt].channels.b.bits > 0 &&
 970           isl_format_layouts[fmt].channels.a.bits == 0;
 971 }
 972
 973 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
 974 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
 975
 976 bool isl_is_storage_image_format(enum isl_format fmt);
 977
 978 enum isl_format
 979 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
 980                                enum isl_format fmt);
 981
 982 /* Returns true if this hardware supports typed load/store on a format with
 983  * the same size as the given format.
 984  */
 985 bool
 986 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
 987                                             enum isl_format fmt);
 988
 989 static inline bool
 990 isl_tiling_is_any_y(enum isl_tiling tiling)
 991 {
 992    return (1u << tiling) & ISL_TILING_ANY_MASK;
 993 }
 994
 995 static inline bool
 996 isl_tiling_is_std_y(enum isl_tiling tiling)
 997 {
 998    return (1u << tiling) & ISL_TILING_STD_Y_MASK;
 999 }
1000
1001 bool
1002 isl_tiling_get_info(const struct isl_device *dev,
1003                     enum isl_tiling tiling,
1004                     uint32_t format_block_size,
1005                     struct isl_tile_info *info);
1006
1007 void
1008 isl_tiling_get_extent(const struct isl_device *dev,
1009                       enum isl_tiling tiling,
1010                       uint32_t format_block_size,
1011                       struct isl_extent2d *e);
1012 bool
1013 isl_surf_choose_tiling(const struct isl_device *dev,
1014                        const struct isl_surf_init_info *restrict info,
1015                        enum isl_tiling *tiling);
1016
1017 static inline bool
1018 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1019 {
1020    return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1021 }
1022
1023 static inline bool
1024 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1025 {
1026    return usage & ISL_SURF_USAGE_DEPTH_BIT;
1027 }
1028
1029 static inline bool
1030 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1031 {
1032    return usage & ISL_SURF_USAGE_STENCIL_BIT;
1033 }
1034
1035 static inline bool
1036 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1037 {
1038    return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1039           (usage & ISL_SURF_USAGE_STENCIL_BIT);
1040 }
1041
1042 static inline bool
1043 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1044 {
1045    return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1046 }
1047
1048 static inline bool
1049 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1050 {
1051    return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1052           (info->format == ISL_FORMAT_R16_UNORM);
1053 }
1054
1055 static inline bool
1056 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1057 {
1058    return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1059           (info->format == ISL_FORMAT_R32_FLOAT);
1060 }
1061
1062 static inline struct isl_extent2d
1063 isl_extent2d(uint32_t width, uint32_t height)
1064 {
1065    struct isl_extent2d e = { { 0 } };
1066
1067    e.width = width;
1068    e.height = height;
1069
1070    return e;
1071 }
1072
1073 static inline struct isl_extent3d
1074 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1075 {
1076    struct isl_extent3d e = { { 0 } };
1077
1078    e.width = width;
1079    e.height = height;
1080    e.depth = depth;
1081
1082    return e;
1083 }
1084
1085 static inline struct isl_extent4d
1086 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1087              uint32_t array_len)
1088 {
1089    struct isl_extent4d e = { { 0 } };
1090
1091    e.width = width;
1092    e.height = height;
1093    e.depth = depth;
1094    e.array_len = array_len;
1095
1096    return e;
1097 }
1098
1099 #define isl_surf_init(dev, surf, ...) \
1100    isl_surf_init_s((dev), (surf), \
1101                    &(struct isl_surf_init_info) {  __VA_ARGS__ });
1102
1103 bool
1104 isl_surf_init_s(const struct isl_device *dev,
1105                 struct isl_surf *surf,
1106                 const struct isl_surf_init_info *restrict info);
1107
1108 void
1109 isl_surf_get_tile_info(const struct isl_device *dev,
1110                        const struct isl_surf *surf,
1111                        struct isl_tile_info *tile_info);
1112
1113 #define isl_surf_fill_state(dev, state, ...) \
1114    isl_surf_fill_state_s((dev), (state), \
1115                          &(struct isl_surf_fill_state_info) {  __VA_ARGS__ });
1116
1117 void
1118 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1119                       const struct isl_surf_fill_state_info *restrict info);
1120
1121 #define isl_buffer_fill_state(dev, state, ...) \
1122    isl_buffer_fill_state_s((dev), (state), \
1123                            &(struct isl_buffer_fill_state_info) {  __VA_ARGS__ });
1124
1125 void
1126 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1127                         const struct isl_buffer_fill_state_info *restrict info);
1128
1129 void
1130 isl_surf_fill_image_param(const struct isl_device *dev,
1131                           struct brw_image_param *param,
1132                           const struct isl_surf *surf,
1133                           const struct isl_view *view);
1134
1135 void
1136 isl_buffer_fill_image_param(const struct isl_device *dev,
1137                             struct brw_image_param *param,
1138                             enum isl_format format,
1139                             uint64_t size);
1140
1141 /**
1142  * Alignment of the upper-left sample of each subimage, in units of surface
1143  * elements.
1144  */
1145 static inline struct isl_extent3d
1146 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1147 {
1148    return surf->image_alignment_el;
1149 }
1150
1151 /**
1152  * Alignment of the upper-left sample of each subimage, in units of surface
1153  * samples.
1154  */
1155 static inline struct isl_extent3d
1156 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1157 {
1158    const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1159
1160    return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1161                        fmtl->bh * surf->image_alignment_el.h,
1162                        fmtl->bd * surf->image_alignment_el.d);
1163 }
1164
1165 /**
1166  * Pitch between vertically adjacent surface elements, in bytes.
1167  */
1168 static inline uint32_t
1169 isl_surf_get_row_pitch(const struct isl_surf *surf)
1170 {
1171    return surf->row_pitch;
1172 }
1173
1174 /**
1175  * Pitch between vertically adjacent surface elements, in units of surface elements.
1176  */
1177 static inline uint32_t
1178 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1179 {
1180    const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1181
1182    assert(surf->row_pitch % fmtl->bs == 0);
1183    return surf->row_pitch / fmtl->bs;
1184 }
1185
1186 /**
1187  * Pitch between physical array slices, in rows of surface elements.
1188  */
1189 static inline uint32_t
1190 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1191 {
1192    return surf->array_pitch_el_rows;
1193 }
1194
1195 /**
1196  * Pitch between physical array slices, in units of surface elements.
1197  */
1198 static inline uint32_t
1199 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1200 {
1201    return isl_surf_get_array_pitch_el_rows(surf) *
1202           isl_surf_get_row_pitch_el(surf);
1203 }
1204
1205 /**
1206  * Pitch between physical array slices, in rows of surface samples.
1207  */
1208 static inline uint32_t
1209 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1210 {
1211    const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1212    return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1213 }
1214
1215 /**
1216  * Pitch between physical array slices, in bytes.
1217  */
1218 static inline uint32_t
1219 isl_surf_get_array_pitch(const struct isl_surf *surf)
1220 {
1221    return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1222 }
1223
1224 /**
1225  * Calculate the offset, in units of surface elements, to a subimage in the
1226  * surface.
1227  *
1228  * @invariant level < surface levels
1229  * @invariant logical_array_layer < logical array length of surface
1230  * @invariant logical_z_offset_px < logical depth of surface at level
1231  */
1232 void
1233 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1234                              uint32_t level,
1235                              uint32_t logical_array_layer,
1236                              uint32_t logical_z_offset_px,
1237                              uint32_t *x_offset_el,
1238                              uint32_t *y_offset_el);
1239
1240 /**
1241  * @brief Calculate the intratile offsets to a surface.
1242  *
1243  * In @a base_address_offset return the offset from the base of the surface to
1244  * the base address of the first tile of the subimage. In @a x_offset_B and
1245  * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1246  * tile's base to the subimage's first surface element. The x and y offsets
1247  * are intratile offsets; that is, they do not exceed the boundary of the
1248  * surface's tiling format.
1249  */
1250 void
1251 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1252                                    enum isl_tiling tiling,
1253                                    uint8_t bs,
1254                                    uint32_t row_pitch,
1255                                    uint32_t total_x_offset_B,
1256                                    uint32_t total_y_offset_rows,
1257                                    uint32_t *base_address_offset,
1258                                    uint32_t *x_offset_B,
1259                                    uint32_t *y_offset_rows);
1260
1261 /**
1262  * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1263  *
1264  * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1265  * @pre surf->format must be a valid format for depth surfaces
1266  */
1267 uint32_t
1268 isl_surf_get_depth_format(const struct isl_device *dev,
1269                           const struct isl_surf *surf);
1270
1271 #ifdef __cplusplus
1272 }
1273 #endif