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intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47 #include "util/format/u_format.h"
48
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52
53 struct gen_device_info;
54 struct brw_image_param;
55
56 #ifndef ISL_DEV_GEN
57 /**
58 * @brief Get the hardware generation of isl_device.
59 *
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 */
63 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
64 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #else
66 #define ISL_DEV_GEN_SANITIZE(__dev) \
67 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
68 #endif
69
70 #ifndef ISL_DEV_IS_G4X
71 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
72 #endif
73
74 #ifndef ISL_DEV_IS_HASWELL
75 /**
76 * @brief Get the hardware generation of isl_device.
77 *
78 * You can define this as a compile-time constant in the CFLAGS. For example,
79 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 */
81 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
82 #endif
83
84 #ifndef ISL_DEV_IS_BAYTRAIL
85 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
86 #endif
87
88 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 /**
90 * You can define this as a compile-time constant in the CFLAGS. For example,
91 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 */
93 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
94 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #else
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
97 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
98 #endif
99
100 /**
101 * Hardware enumeration SURFACE_FORMAT.
102 *
103 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
104 * Enumerations: SURFACE_FORMAT.
105 */
106 enum isl_format {
107 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
108 ISL_FORMAT_R32G32B32A32_SINT = 1,
109 ISL_FORMAT_R32G32B32A32_UINT = 2,
110 ISL_FORMAT_R32G32B32A32_UNORM = 3,
111 ISL_FORMAT_R32G32B32A32_SNORM = 4,
112 ISL_FORMAT_R64G64_FLOAT = 5,
113 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
114 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
115 ISL_FORMAT_R32G32B32A32_USCALED = 8,
116 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
117 ISL_FORMAT_R64G64_PASSTHRU = 33,
118 ISL_FORMAT_R32G32B32_FLOAT = 64,
119 ISL_FORMAT_R32G32B32_SINT = 65,
120 ISL_FORMAT_R32G32B32_UINT = 66,
121 ISL_FORMAT_R32G32B32_UNORM = 67,
122 ISL_FORMAT_R32G32B32_SNORM = 68,
123 ISL_FORMAT_R32G32B32_SSCALED = 69,
124 ISL_FORMAT_R32G32B32_USCALED = 70,
125 ISL_FORMAT_R32G32B32_SFIXED = 80,
126 ISL_FORMAT_R16G16B16A16_UNORM = 128,
127 ISL_FORMAT_R16G16B16A16_SNORM = 129,
128 ISL_FORMAT_R16G16B16A16_SINT = 130,
129 ISL_FORMAT_R16G16B16A16_UINT = 131,
130 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
131 ISL_FORMAT_R32G32_FLOAT = 133,
132 ISL_FORMAT_R32G32_SINT = 134,
133 ISL_FORMAT_R32G32_UINT = 135,
134 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
135 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
136 ISL_FORMAT_L32A32_FLOAT = 138,
137 ISL_FORMAT_R32G32_UNORM = 139,
138 ISL_FORMAT_R32G32_SNORM = 140,
139 ISL_FORMAT_R64_FLOAT = 141,
140 ISL_FORMAT_R16G16B16X16_UNORM = 142,
141 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
142 ISL_FORMAT_A32X32_FLOAT = 144,
143 ISL_FORMAT_L32X32_FLOAT = 145,
144 ISL_FORMAT_I32X32_FLOAT = 146,
145 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
146 ISL_FORMAT_R16G16B16A16_USCALED = 148,
147 ISL_FORMAT_R32G32_SSCALED = 149,
148 ISL_FORMAT_R32G32_USCALED = 150,
149 ISL_FORMAT_R32G32_FLOAT_LD = 151,
150 ISL_FORMAT_R32G32_SFIXED = 160,
151 ISL_FORMAT_R64_PASSTHRU = 161,
152 ISL_FORMAT_B8G8R8A8_UNORM = 192,
153 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
154 ISL_FORMAT_R10G10B10A2_UNORM = 194,
155 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
156 ISL_FORMAT_R10G10B10A2_UINT = 196,
157 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
158 ISL_FORMAT_R8G8B8A8_UNORM = 199,
159 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
160 ISL_FORMAT_R8G8B8A8_SNORM = 201,
161 ISL_FORMAT_R8G8B8A8_SINT = 202,
162 ISL_FORMAT_R8G8B8A8_UINT = 203,
163 ISL_FORMAT_R16G16_UNORM = 204,
164 ISL_FORMAT_R16G16_SNORM = 205,
165 ISL_FORMAT_R16G16_SINT = 206,
166 ISL_FORMAT_R16G16_UINT = 207,
167 ISL_FORMAT_R16G16_FLOAT = 208,
168 ISL_FORMAT_B10G10R10A2_UNORM = 209,
169 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
170 ISL_FORMAT_R11G11B10_FLOAT = 211,
171 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
172 ISL_FORMAT_R32_SINT = 214,
173 ISL_FORMAT_R32_UINT = 215,
174 ISL_FORMAT_R32_FLOAT = 216,
175 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
176 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
177 ISL_FORMAT_L32_UNORM = 221,
178 ISL_FORMAT_A32_UNORM = 222,
179 ISL_FORMAT_L16A16_UNORM = 223,
180 ISL_FORMAT_I24X8_UNORM = 224,
181 ISL_FORMAT_L24X8_UNORM = 225,
182 ISL_FORMAT_A24X8_UNORM = 226,
183 ISL_FORMAT_I32_FLOAT = 227,
184 ISL_FORMAT_L32_FLOAT = 228,
185 ISL_FORMAT_A32_FLOAT = 229,
186 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
187 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
188 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
189 ISL_FORMAT_B8G8R8X8_UNORM = 233,
190 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
191 ISL_FORMAT_R8G8B8X8_UNORM = 235,
192 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
193 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
194 ISL_FORMAT_B10G10R10X2_UNORM = 238,
195 ISL_FORMAT_L16A16_FLOAT = 240,
196 ISL_FORMAT_R32_UNORM = 241,
197 ISL_FORMAT_R32_SNORM = 242,
198 ISL_FORMAT_R10G10B10X2_USCALED = 243,
199 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
200 ISL_FORMAT_R8G8B8A8_USCALED = 245,
201 ISL_FORMAT_R16G16_SSCALED = 246,
202 ISL_FORMAT_R16G16_USCALED = 247,
203 ISL_FORMAT_R32_SSCALED = 248,
204 ISL_FORMAT_R32_USCALED = 249,
205 ISL_FORMAT_B5G6R5_UNORM = 256,
206 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
207 ISL_FORMAT_B5G5R5A1_UNORM = 258,
208 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
209 ISL_FORMAT_B4G4R4A4_UNORM = 260,
210 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
211 ISL_FORMAT_R8G8_UNORM = 262,
212 ISL_FORMAT_R8G8_SNORM = 263,
213 ISL_FORMAT_R8G8_SINT = 264,
214 ISL_FORMAT_R8G8_UINT = 265,
215 ISL_FORMAT_R16_UNORM = 266,
216 ISL_FORMAT_R16_SNORM = 267,
217 ISL_FORMAT_R16_SINT = 268,
218 ISL_FORMAT_R16_UINT = 269,
219 ISL_FORMAT_R16_FLOAT = 270,
220 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
221 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
222 ISL_FORMAT_I16_UNORM = 273,
223 ISL_FORMAT_L16_UNORM = 274,
224 ISL_FORMAT_A16_UNORM = 275,
225 ISL_FORMAT_L8A8_UNORM = 276,
226 ISL_FORMAT_I16_FLOAT = 277,
227 ISL_FORMAT_L16_FLOAT = 278,
228 ISL_FORMAT_A16_FLOAT = 279,
229 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
230 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
231 ISL_FORMAT_B5G5R5X1_UNORM = 282,
232 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
233 ISL_FORMAT_R8G8_SSCALED = 284,
234 ISL_FORMAT_R8G8_USCALED = 285,
235 ISL_FORMAT_R16_SSCALED = 286,
236 ISL_FORMAT_R16_USCALED = 287,
237 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
238 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
239 ISL_FORMAT_A1B5G5R5_UNORM = 292,
240 ISL_FORMAT_A4B4G4R4_UNORM = 293,
241 ISL_FORMAT_L8A8_UINT = 294,
242 ISL_FORMAT_L8A8_SINT = 295,
243 ISL_FORMAT_R8_UNORM = 320,
244 ISL_FORMAT_R8_SNORM = 321,
245 ISL_FORMAT_R8_SINT = 322,
246 ISL_FORMAT_R8_UINT = 323,
247 ISL_FORMAT_A8_UNORM = 324,
248 ISL_FORMAT_I8_UNORM = 325,
249 ISL_FORMAT_L8_UNORM = 326,
250 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
251 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
252 ISL_FORMAT_R8_SSCALED = 329,
253 ISL_FORMAT_R8_USCALED = 330,
254 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
255 ISL_FORMAT_L8_UNORM_SRGB = 332,
256 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
257 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
258 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
259 ISL_FORMAT_Y8_UNORM = 336,
260 ISL_FORMAT_L8_UINT = 338,
261 ISL_FORMAT_L8_SINT = 339,
262 ISL_FORMAT_I8_UINT = 340,
263 ISL_FORMAT_I8_SINT = 341,
264 ISL_FORMAT_DXT1_RGB_SRGB = 384,
265 ISL_FORMAT_R1_UNORM = 385,
266 ISL_FORMAT_YCRCB_NORMAL = 386,
267 ISL_FORMAT_YCRCB_SWAPUVY = 387,
268 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
269 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
270 ISL_FORMAT_BC1_UNORM = 390,
271 ISL_FORMAT_BC2_UNORM = 391,
272 ISL_FORMAT_BC3_UNORM = 392,
273 ISL_FORMAT_BC4_UNORM = 393,
274 ISL_FORMAT_BC5_UNORM = 394,
275 ISL_FORMAT_BC1_UNORM_SRGB = 395,
276 ISL_FORMAT_BC2_UNORM_SRGB = 396,
277 ISL_FORMAT_BC3_UNORM_SRGB = 397,
278 ISL_FORMAT_MONO8 = 398,
279 ISL_FORMAT_YCRCB_SWAPUV = 399,
280 ISL_FORMAT_YCRCB_SWAPY = 400,
281 ISL_FORMAT_DXT1_RGB = 401,
282 ISL_FORMAT_FXT1 = 402,
283 ISL_FORMAT_R8G8B8_UNORM = 403,
284 ISL_FORMAT_R8G8B8_SNORM = 404,
285 ISL_FORMAT_R8G8B8_SSCALED = 405,
286 ISL_FORMAT_R8G8B8_USCALED = 406,
287 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
288 ISL_FORMAT_R64G64B64_FLOAT = 408,
289 ISL_FORMAT_BC4_SNORM = 409,
290 ISL_FORMAT_BC5_SNORM = 410,
291 ISL_FORMAT_R16G16B16_FLOAT = 411,
292 ISL_FORMAT_R16G16B16_UNORM = 412,
293 ISL_FORMAT_R16G16B16_SNORM = 413,
294 ISL_FORMAT_R16G16B16_SSCALED = 414,
295 ISL_FORMAT_R16G16B16_USCALED = 415,
296 ISL_FORMAT_BC6H_SF16 = 417,
297 ISL_FORMAT_BC7_UNORM = 418,
298 ISL_FORMAT_BC7_UNORM_SRGB = 419,
299 ISL_FORMAT_BC6H_UF16 = 420,
300 ISL_FORMAT_PLANAR_420_8 = 421,
301 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
302 ISL_FORMAT_ETC1_RGB8 = 425,
303 ISL_FORMAT_ETC2_RGB8 = 426,
304 ISL_FORMAT_EAC_R11 = 427,
305 ISL_FORMAT_EAC_RG11 = 428,
306 ISL_FORMAT_EAC_SIGNED_R11 = 429,
307 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
308 ISL_FORMAT_ETC2_SRGB8 = 431,
309 ISL_FORMAT_R16G16B16_UINT = 432,
310 ISL_FORMAT_R16G16B16_SINT = 433,
311 ISL_FORMAT_R32_SFIXED = 434,
312 ISL_FORMAT_R10G10B10A2_SNORM = 435,
313 ISL_FORMAT_R10G10B10A2_USCALED = 436,
314 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
315 ISL_FORMAT_R10G10B10A2_SINT = 438,
316 ISL_FORMAT_B10G10R10A2_SNORM = 439,
317 ISL_FORMAT_B10G10R10A2_USCALED = 440,
318 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
319 ISL_FORMAT_B10G10R10A2_UINT = 442,
320 ISL_FORMAT_B10G10R10A2_SINT = 443,
321 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
322 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
323 ISL_FORMAT_ETC2_RGB8_PTA = 448,
324 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
325 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
326 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
327 ISL_FORMAT_R8G8B8_UINT = 456,
328 ISL_FORMAT_R8G8B8_SINT = 457,
329 ISL_FORMAT_RAW = 511,
330 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
331 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
332 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
333 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
334 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
335 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
336 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
337 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
338 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
339 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
340 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
341 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
342 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
343 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
344 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
345 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
346 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
347 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
348 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
349 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
350 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
351 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
352 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
353 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
354 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
355 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
356 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
357 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
358 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
359 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
360 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
361 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
362 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
363 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
364 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
365 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
366 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
367 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
368 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
369 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
370 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
371 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
372
373 /* The formats that follow are internal to ISL and as such don't have an
374 * explicit number. We'll just let the C compiler assign it for us. Any
375 * actual hardware formats *must* come before these in the list.
376 */
377
378 /* Formats for auxiliary surfaces */
379 ISL_FORMAT_HIZ,
380 ISL_FORMAT_MCS_2X,
381 ISL_FORMAT_MCS_4X,
382 ISL_FORMAT_MCS_8X,
383 ISL_FORMAT_MCS_16X,
384 ISL_FORMAT_GEN7_CCS_32BPP_X,
385 ISL_FORMAT_GEN7_CCS_64BPP_X,
386 ISL_FORMAT_GEN7_CCS_128BPP_X,
387 ISL_FORMAT_GEN7_CCS_32BPP_Y,
388 ISL_FORMAT_GEN7_CCS_64BPP_Y,
389 ISL_FORMAT_GEN7_CCS_128BPP_Y,
390 ISL_FORMAT_GEN9_CCS_32BPP,
391 ISL_FORMAT_GEN9_CCS_64BPP,
392 ISL_FORMAT_GEN9_CCS_128BPP,
393 ISL_FORMAT_GEN12_CCS_8BPP_Y0,
394 ISL_FORMAT_GEN12_CCS_16BPP_Y0,
395 ISL_FORMAT_GEN12_CCS_32BPP_Y0,
396 ISL_FORMAT_GEN12_CCS_64BPP_Y0,
397 ISL_FORMAT_GEN12_CCS_128BPP_Y0,
398
399 /* An upper bound on the supported format enumerations */
400 ISL_NUM_FORMATS,
401
402 /* Hardware doesn't understand this out-of-band value */
403 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
404 };
405
406 /**
407 * Numerical base type for channels of isl_format.
408 */
409 enum isl_base_type {
410 ISL_VOID,
411 ISL_RAW,
412 ISL_UNORM,
413 ISL_SNORM,
414 ISL_UFLOAT,
415 ISL_SFLOAT,
416 ISL_UFIXED,
417 ISL_SFIXED,
418 ISL_UINT,
419 ISL_SINT,
420 ISL_USCALED,
421 ISL_SSCALED,
422 };
423
424 /**
425 * Colorspace of isl_format.
426 */
427 enum isl_colorspace {
428 ISL_COLORSPACE_NONE = 0,
429 ISL_COLORSPACE_LINEAR,
430 ISL_COLORSPACE_SRGB,
431 ISL_COLORSPACE_YUV,
432 };
433
434 /**
435 * Texture compression mode of isl_format.
436 */
437 enum isl_txc {
438 ISL_TXC_NONE = 0,
439 ISL_TXC_DXT1,
440 ISL_TXC_DXT3,
441 ISL_TXC_DXT5,
442 ISL_TXC_FXT1,
443 ISL_TXC_RGTC1,
444 ISL_TXC_RGTC2,
445 ISL_TXC_BPTC,
446 ISL_TXC_ETC1,
447 ISL_TXC_ETC2,
448 ISL_TXC_ASTC,
449
450 /* Used for auxiliary surface formats */
451 ISL_TXC_HIZ,
452 ISL_TXC_MCS,
453 ISL_TXC_CCS,
454 };
455
456 /**
457 * @brief Hardware tile mode
458 *
459 * WARNING: These values differ from the hardware enum values, which are
460 * unstable across hardware generations.
461 *
462 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
463 * clearly distinguish it from Yf and Ys.
464 */
465 enum isl_tiling {
466 ISL_TILING_LINEAR = 0,
467 ISL_TILING_W,
468 ISL_TILING_X,
469 ISL_TILING_Y0, /**< Legacy Y tiling */
470 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
471 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
472 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
473 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
474 ISL_TILING_GEN12_CCS, /**< Tiling format for Gen12 CCS surfaces */
475 };
476
477 /**
478 * @defgroup Tiling Flags
479 * @{
480 */
481 typedef uint32_t isl_tiling_flags_t;
482 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
483 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
484 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
485 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
486 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
487 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
488 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
489 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
490 #define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
491 #define ISL_TILING_ANY_MASK (~0u)
492 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
493
494 /** Any Y tiling, including legacy Y tiling. */
495 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
496 ISL_TILING_Yf_BIT | \
497 ISL_TILING_Ys_BIT)
498
499 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
500 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
501 ISL_TILING_Ys_BIT)
502 /** @} */
503
504 /**
505 * @brief Logical dimension of surface.
506 *
507 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
508 * as 2D array surfaces.
509 */
510 enum isl_surf_dim {
511 ISL_SURF_DIM_1D,
512 ISL_SURF_DIM_2D,
513 ISL_SURF_DIM_3D,
514 };
515
516 /**
517 * @brief Physical layout of the surface's dimensions.
518 */
519 enum isl_dim_layout {
520 /**
521 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
522 * 6.17.3: 2D Surfaces.
523 *
524 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
525 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
526 *
527 * One-dimensional surfaces are identical to 2D surfaces with height of
528 * one.
529 *
530 * @invariant isl_surf::phys_level0_sa::depth == 1
531 */
532 ISL_DIM_LAYOUT_GEN4_2D,
533
534 /**
535 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
536 * 6.17.5: 3D Surfaces.
537 *
538 * @invariant isl_surf::phys_level0_sa::array_len == 1
539 */
540 ISL_DIM_LAYOUT_GEN4_3D,
541
542 /**
543 * Special layout used for HiZ and stencil on Sandy Bridge to work around
544 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
545 * work the same as on gen7+ except that they don't technically support
546 * mipmapping. That does not, however, stop us from doing it. As far as
547 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
548 * single miplevel 2D (possibly array) image. The dimensions of that image
549 * are NOT minified.
550 *
551 * In order to implement HiZ and stencil on Sandy Bridge, we create one
552 * full-sized 2D (possibly array) image for every LOD with every image
553 * aligned to a page boundary. When the surface is used with the stencil
554 * or HiZ hardware, we manually offset to the image for the given LOD.
555 *
556 * As a memory saving measure, we pretend that the width of each miplevel
557 * is minified and we place LOD1 and above below LOD0 but horizontally
558 * adjacent to each other. When considered as full-sized images, LOD1 and
559 * above technically overlap. However, since we only write to part of that
560 * image, the hardware will never notice the overlap.
561 *
562 * This layout looks something like this:
563 *
564 * +---------+
565 * | |
566 * | |
567 * +---------+
568 * | |
569 * | |
570 * +---------+
571 *
572 * +----+ +-+ .
573 * | | +-+
574 * +----+
575 *
576 * +----+ +-+ .
577 * | | +-+
578 * +----+
579 */
580 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
581
582 /**
583 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
584 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
585 */
586 ISL_DIM_LAYOUT_GEN9_1D,
587 };
588
589 enum isl_aux_usage {
590 /** No Auxiliary surface is used */
591 ISL_AUX_USAGE_NONE,
592
593 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
594 ISL_AUX_USAGE_HIZ,
595
596 /** The auxiliary surface is an MCS
597 *
598 * @invariant isl_surf::samples > 1
599 */
600 ISL_AUX_USAGE_MCS,
601
602 /** The auxiliary surface is a fast-clear-only compression surface
603 *
604 * @invariant isl_surf::samples == 1
605 */
606 ISL_AUX_USAGE_CCS_D,
607
608 /** The auxiliary surface provides full lossless color compression
609 *
610 * @invariant isl_surf::samples == 1
611 */
612 ISL_AUX_USAGE_CCS_E,
613
614 /** The auxiliary surface provides full lossless media color compression
615 *
616 * @invariant isl_surf::samples == 1
617 */
618 ISL_AUX_USAGE_MC,
619
620 /** The auxiliary surface is a HiZ surface operating in write-through mode
621 * and CCS is also enabled
622 *
623 * In this mode, the HiZ and CCS surfaces act as a single fused compression
624 * surface where resolves and ambiguates operate on both surfaces at the
625 * same time. In this mode, the HiZ surface operates in write-through
626 * mode where it is only used for accelerating depth testing and not for
627 * actual compression. The CCS-compressed surface contains valid data at
628 * all times.
629 *
630 * @invariant isl_surf::samples == 1
631 */
632 ISL_AUX_USAGE_HIZ_CCS_WT,
633
634 /** The auxiliary surface is a HiZ surface with and CCS is also enabled
635 *
636 * In this mode, the HiZ and CCS surfaces act as a single fused compression
637 * surface where resolves and ambiguates operate on both surfaces at the
638 * same time. In this mode, full HiZ compression is enabled and the
639 * CCS-compressed main surface may not contain valid data. The only way to
640 * read the surface outside of the depth hardware is to do a full resolve
641 * which resolves both HiZ and CCS so the surface is in the pass-through
642 * state.
643 */
644 ISL_AUX_USAGE_HIZ_CCS,
645
646 /** The auxiliary surface is an MCS and CCS is also enabled
647 *
648 * @invariant isl_surf::samples > 1
649 */
650 ISL_AUX_USAGE_MCS_CCS,
651 };
652
653 /**
654 * Enum for keeping track of the state an auxiliary compressed surface.
655 *
656 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
657 * given slice (lod + array layer) can be in one of the six states described
658 * by this enum. Draw and resolve operations may cause the slice to change
659 * from one state to another. The six valid states are:
660 *
661 * 1) Clear: In this state, each block in the auxiliary surface contains a
662 * magic value that indicates that the block is in the clear state. If
663 * a block is in the clear state, it's values in the primary surface are
664 * ignored and the color of the samples in the block is taken either the
665 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
666 * depth. Since neither the primary surface nor the auxiliary surface
667 * contains the clear value, the surface can be cleared to a different
668 * color by simply changing the clear color without modifying either
669 * surface.
670 *
671 * 2) Partial Clear: In this state, each block in the auxiliary surface
672 * contains either the magic clear or pass-through value. See Clear and
673 * Pass-through for more details.
674 *
675 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
676 * nor the primary surface has a complete representation of the data.
677 * Instead, both surfaces must be used together or else rendering
678 * corruption may occur. Depending on the auxiliary compression format
679 * and the data, any given block in the primary surface may contain all,
680 * some, or none of the data required to reconstruct the actual sample
681 * values. Blocks may also be in the clear state (see Clear) and have
682 * their value taken from outside the surface.
683 *
684 * 4) Compressed w/o Clear: This state is identical to the state above
685 * except that no blocks are in the clear state. In this state, all of
686 * the data required to reconstruct the final sample values is contained
687 * in the auxiliary and primary surface and the clear value is not
688 * considered.
689 *
690 * 5) Resolved: In this state, the primary surface contains 100% of the
691 * data. The auxiliary surface is also valid so the surface can be
692 * validly used with or without aux enabled. The auxiliary surface may,
693 * however, contain non-trivial data and any update to the primary
694 * surface with aux disabled will cause the two to get out of sync.
695 *
696 * 6) Pass-through: In this state, the primary surface contains 100% of the
697 * data and every block in the auxiliary surface contains a magic value
698 * which indicates that the auxiliary surface should be ignored and the
699 * only the primary surface should be considered. Updating the primary
700 * surface without aux works fine and can be done repeatedly in this
701 * mode. Writing to a surface in pass-through mode with aux enabled may
702 * cause the auxiliary buffer to contain non-trivial data and no longer
703 * be in the pass-through state.
704 *
705 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
706 * data and the auxiliary surface is completely bogus. Any attempt to
707 * use the auxiliary surface is liable to result in rendering
708 * corruption. The only thing that one can do to re-enable aux once
709 * this state is reached is to use an ambiguate pass to transition into
710 * the pass-through state.
711 *
712 * Drawing with or without aux enabled may implicitly cause the surface to
713 * transition between these states. There are also four types of auxiliary
714 * compression operations which cause an explicit transition which are
715 * described by the isl_aux_op enum below.
716 *
717 * Not all operations are valid or useful in all states. The diagram below
718 * contains a complete description of the states and all valid and useful
719 * transitions except clear.
720 *
721 * Draw w/ Aux
722 * +----------+
723 * | |
724 * | +-------------+ Draw w/ Aux +-------------+
725 * +------>| Compressed |<-------------------| Clear |
726 * | w/ Clear |----->----+ | |
727 * +-------------+ | +-------------+
728 * | /|\ | | |
729 * | | | | |
730 * | | +------<-----+ | Draw w/
731 * | | | | Clear Only
732 * | | Full | | +----------+
733 * Partial | | Resolve | \|/ | |
734 * Resolve | | | +-------------+ |
735 * | | | | Partial |<------+
736 * | | | | Clear |<----------+
737 * | | | +-------------+ |
738 * | | | | |
739 * | | +------>---------+ Full |
740 * | | | Resolve |
741 * Draw w/ aux | | Partial Fast Clear | |
742 * +----------+ | +--------------------------+ | |
743 * | | \|/ | \|/ |
744 * | +-------------+ Full Resolve +-------------+ |
745 * +------>| Compressed |------------------->| Resolved | |
746 * | w/o Clear |<-------------------| | |
747 * +-------------+ Draw w/ Aux +-------------+ |
748 * /|\ | | |
749 * | Draw | | Draw |
750 * | w/ Aux | | w/o Aux |
751 * | Ambiguate | | |
752 * | +--------------------------+ | |
753 * Draw w/o Aux | | | Draw w/o Aux |
754 * +----------+ | | | +----------+ |
755 * | | | \|/ \|/ | | |
756 * | +-------------+ Ambiguate +-------------+ | |
757 * +------>| Pass- |<-------------------| Aux |<------+ |
758 * +------>| through | | Invalid | |
759 * | +-------------+ +-------------+ |
760 * | | | |
761 * +----------+ +-----------------------------------------------------+
762 * Draw w/ Partial Fast Clear
763 * Clear Only
764 *
765 *
766 * While the above general theory applies to all forms of auxiliary
767 * compression on Intel hardware, not all states and operations are available
768 * on all compression types. However, each of the auxiliary states and
769 * operations can be fairly easily mapped onto the above diagram:
770 *
771 * HiZ: Hierarchical depth compression is capable of being in any of the
772 * states above. Hardware provides three HiZ operations: "Depth
773 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
774 * Clear", "Full Resolve", and "Ambiguate" respectively. The
775 * hardware provides no HiZ partial resolve operation so the only way
776 * to get into the "Compressed w/o Clear" state is to render with HiZ
777 * when the surface is in the resolved or pass-through states.
778 *
779 * MCS: Multisample compression is technically capable of being in any of
780 * the states above except that most of them aren't useful. Both the
781 * render engine and the sampler support MCS compression and, apart
782 * from clear color, MCS is format-unaware so we leave the surface
783 * compressed 100% of the time. The hardware provides no MCS
784 * operations.
785 *
786 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
787 * the simplest forms of compression since they don't do anything
788 * beyond clear color tracking. They really only support three of
789 * the six states: Clear, Partial Clear, and Pass-through. The
790 * only CCS_D operation is "Resolve" which maps to a full resolve
791 * followed by an ambiguate.
792 *
793 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
794 * is capable of being in almost all of the above states. THe only
795 * exception is that it does not have separate resolved and pass-
796 * through states. Instead, the CCS_E full resolve operation does
797 * both a resolve and an ambiguate so it goes directly into the
798 * pass-through state. CCS_E also provides fast clear and partial
799 * resolve operations which work as described above.
800 *
801 * While it is technically possible to perform a CCS_E ambiguate, it
802 * is not provided by Sky Lake hardware so we choose to avoid the aux
803 * invalid state. If the aux invalid state were determined to be
804 * useful, a CCS ambiguate could be done by carefully rendering to
805 * the CCS and filling it with zeros.
806 */
807 enum isl_aux_state {
808 ISL_AUX_STATE_CLEAR = 0,
809 ISL_AUX_STATE_PARTIAL_CLEAR,
810 ISL_AUX_STATE_COMPRESSED_CLEAR,
811 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
812 ISL_AUX_STATE_RESOLVED,
813 ISL_AUX_STATE_PASS_THROUGH,
814 ISL_AUX_STATE_AUX_INVALID,
815 };
816
817 /**
818 * Enum which describes explicit aux transition operations.
819 */
820 enum isl_aux_op {
821 ISL_AUX_OP_NONE,
822
823 /** Fast Clear
824 *
825 * This operation writes the magic "clear" value to the auxiliary surface.
826 * This operation will safely transition any slice of a surface from any
827 * state to the clear state so long as the entire slice is fast cleared at
828 * once. A fast clear that only covers part of a slice of a surface is
829 * called a partial fast clear.
830 */
831 ISL_AUX_OP_FAST_CLEAR,
832
833 /** Full Resolve
834 *
835 * This operation combines the auxiliary surface data with the primary
836 * surface data and writes the result to the primary. For HiZ, the docs
837 * call this a depth resolve. For CCS, the hardware full resolve operation
838 * does both a full resolve and an ambiguate so it actually takes you all
839 * the way to the pass-through state.
840 */
841 ISL_AUX_OP_FULL_RESOLVE,
842
843 /** Partial Resolve
844 *
845 * This operation considers blocks which are in the "clear" state and
846 * writes the clear value directly into the primary or auxiliary surface.
847 * Once this operation completes, the surface is still compressed but no
848 * longer references the clear color. This operation is only available
849 * for CCS_E.
850 */
851 ISL_AUX_OP_PARTIAL_RESOLVE,
852
853 /** Ambiguate
854 *
855 * This operation throws away the current auxiliary data and replaces it
856 * with the magic pass-through value. If an ambiguate operation is
857 * performed when the primary surface does not contain 100% of the data,
858 * data will be lost. This operation is only implemented in hardware for
859 * depth where it is called a HiZ resolve.
860 */
861 ISL_AUX_OP_AMBIGUATE,
862 };
863
864 /* TODO(chadv): Explain */
865 enum isl_array_pitch_span {
866 ISL_ARRAY_PITCH_SPAN_FULL,
867 ISL_ARRAY_PITCH_SPAN_COMPACT,
868 };
869
870 /**
871 * @defgroup Surface Usage
872 * @{
873 */
874 typedef uint64_t isl_surf_usage_flags_t;
875 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
876 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
877 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
878 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
879 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
880 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
881 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
882 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
883 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
884 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
885 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
886 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
887 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
888 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
889 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
890 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
891 /** @} */
892
893 /**
894 * @defgroup Channel Mask
895 *
896 * These #define values are chosen to match the values of
897 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
898 *
899 * @{
900 */
901 typedef uint8_t isl_channel_mask_t;
902 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
903 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
904 #define ISL_CHANNEL_RED_BIT (1 << 2)
905 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
906 /** @} */
907
908 /**
909 * @brief A channel select (also known as texture swizzle) value
910 */
911 enum PACKED isl_channel_select {
912 ISL_CHANNEL_SELECT_ZERO = 0,
913 ISL_CHANNEL_SELECT_ONE = 1,
914 ISL_CHANNEL_SELECT_RED = 4,
915 ISL_CHANNEL_SELECT_GREEN = 5,
916 ISL_CHANNEL_SELECT_BLUE = 6,
917 ISL_CHANNEL_SELECT_ALPHA = 7,
918 };
919
920 /**
921 * Identical to VkSampleCountFlagBits.
922 */
923 enum isl_sample_count {
924 ISL_SAMPLE_COUNT_1_BIT = 1u,
925 ISL_SAMPLE_COUNT_2_BIT = 2u,
926 ISL_SAMPLE_COUNT_4_BIT = 4u,
927 ISL_SAMPLE_COUNT_8_BIT = 8u,
928 ISL_SAMPLE_COUNT_16_BIT = 16u,
929 };
930 typedef uint32_t isl_sample_count_mask_t;
931
932 /**
933 * @brief Multisample Format
934 */
935 enum isl_msaa_layout {
936 /**
937 * @brief Suface is single-sampled.
938 */
939 ISL_MSAA_LAYOUT_NONE,
940
941 /**
942 * @brief [SNB+] Interleaved Multisample Format
943 *
944 * In this format, multiple samples are interleaved into each cacheline.
945 * In other words, the sample index is swizzled into the low 6 bits of the
946 * surface's virtual address space.
947 *
948 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
949 * and its pixel format is 32bpp. Then the first cacheline is arranged
950 * thus:
951 *
952 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
953 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
954 *
955 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
956 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
957 *
958 * The hardware docs refer to this format with multiple terms. In
959 * Sandybridge, this is the only multisample format; so no term is used.
960 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
961 * Multisample Surface). Later hardware docs additionally refer to this
962 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
963 * color surfaces).
964 *
965 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
966 * Surface Behavior".
967 *
968 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
969 * Multisampled Surfaces".
970 */
971 ISL_MSAA_LAYOUT_INTERLEAVED,
972
973 /**
974 * @brief [IVB+] Array Multisample Format
975 *
976 * In this format, the surface's physical layout resembles that of a
977 * 2D array surface.
978 *
979 * Suppose the multisample surface's logical extent is (w, h) and its
980 * sample count is N. Then surface's physical extent is the same as
981 * a singlesample 2D surface whose logical extent is (w, h) and array
982 * length is N. Array slice `i` contains the pixel values for sample
983 * index `i`.
984 *
985 * The Ivybridge docs refer to surfaces in this format as UMS
986 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
987 * Surface). The Broadwell docs additionally refer to this format as
988 * MSFMT_MSS (MSS=Multisample Surface Storage).
989 *
990 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
991 * Multisample Surfaces".
992 *
993 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
994 * Multisample Surfaces".
995 */
996 ISL_MSAA_LAYOUT_ARRAY,
997 };
998
999 typedef enum {
1000 ISL_MEMCPY = 0,
1001 ISL_MEMCPY_BGRA8,
1002 ISL_MEMCPY_STREAMING_LOAD,
1003 ISL_MEMCPY_INVALID,
1004 } isl_memcpy_type;
1005
1006 struct isl_device {
1007 const struct gen_device_info *info;
1008 bool use_separate_stencil;
1009 bool has_bit6_swizzling;
1010
1011 /**
1012 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1013 * current gen.
1014 */
1015 struct {
1016 uint8_t size;
1017 uint8_t align;
1018 uint8_t addr_offset;
1019 uint8_t aux_addr_offset;
1020
1021 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1022
1023 /* size of the state buffer used to store the clear color + extra
1024 * additional space used by the hardware */
1025 uint8_t clear_color_state_size;
1026 uint8_t clear_color_state_offset;
1027 /* size of the clear color itself - used to copy it to/from a BO */
1028 uint8_t clear_value_size;
1029 uint8_t clear_value_offset;
1030 } ss;
1031
1032 /**
1033 * Describes the layout of the depth/stencil/hiz commands as emitted by
1034 * isl_emit_depth_stencil_hiz.
1035 */
1036 struct {
1037 uint8_t size;
1038 uint8_t depth_offset;
1039 uint8_t stencil_offset;
1040 uint8_t hiz_offset;
1041 } ds;
1042
1043 struct {
1044 uint32_t internal;
1045 uint32_t external;
1046 } mocs;
1047 };
1048
1049 struct isl_extent2d {
1050 union { uint32_t w, width; };
1051 union { uint32_t h, height; };
1052 };
1053
1054 struct isl_extent3d {
1055 union { uint32_t w, width; };
1056 union { uint32_t h, height; };
1057 union { uint32_t d, depth; };
1058 };
1059
1060 struct isl_extent4d {
1061 union { uint32_t w, width; };
1062 union { uint32_t h, height; };
1063 union { uint32_t d, depth; };
1064 union { uint32_t a, array_len; };
1065 };
1066
1067 struct isl_channel_layout {
1068 enum isl_base_type type;
1069 uint8_t start_bit; /**< Bit at which this channel starts */
1070 uint8_t bits; /**< Size in bits */
1071 };
1072
1073 /**
1074 * Each format has 3D block extent (width, height, depth). The block extent of
1075 * compressed formats is that of the format's compression block. For example,
1076 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1077 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1078 * is (w=1, h=1, d=1).
1079 */
1080 struct isl_format_layout {
1081 enum isl_format format;
1082 const char *name;
1083
1084 uint16_t bpb; /**< Bits per block */
1085 uint8_t bw; /**< Block width, in pixels */
1086 uint8_t bh; /**< Block height, in pixels */
1087 uint8_t bd; /**< Block depth, in pixels */
1088
1089 union {
1090 struct {
1091 struct isl_channel_layout r; /**< Red channel */
1092 struct isl_channel_layout g; /**< Green channel */
1093 struct isl_channel_layout b; /**< Blue channel */
1094 struct isl_channel_layout a; /**< Alpha channel */
1095 struct isl_channel_layout l; /**< Luminance channel */
1096 struct isl_channel_layout i; /**< Intensity channel */
1097 struct isl_channel_layout p; /**< Palette channel */
1098 } channels;
1099 struct isl_channel_layout channels_array[7];
1100 };
1101
1102 enum isl_colorspace colorspace;
1103 enum isl_txc txc;
1104 };
1105
1106 struct isl_tile_info {
1107 enum isl_tiling tiling;
1108
1109 /* The size (in bits per block) of a single surface element
1110 *
1111 * For surfaces with power-of-two formats, this is the same as
1112 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1113 * The logical_extent_el field is in terms of elements of this size.
1114 *
1115 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1116 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1117 * of the tiling formats can actually hold an integer number of 96-bit
1118 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1119 * 32-bit element size. It is the responsibility of the caller to
1120 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1121 * the width of a surface in tiles, you would do:
1122 *
1123 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1124 * tile_info.logical_extent_el.width);
1125 */
1126 uint32_t format_bpb;
1127
1128 /** The logical size of the tile in units of format_bpb size elements
1129 *
1130 * This field determines how a given surface is cut up into tiles. It is
1131 * used to compute the size of a surface in tiles and can be used to
1132 * determine the location of the tile containing any given surface element.
1133 * The exact value of this field depends heavily on the bits-per-block of
1134 * the format being used.
1135 */
1136 struct isl_extent2d logical_extent_el;
1137
1138 /** The physical size of the tile in bytes and rows of bytes
1139 *
1140 * This field determines how the tiles of a surface are physically layed
1141 * out in memory. The logical and physical tile extent are frequently the
1142 * same but this is not always the case. For instance, a W-tile (which is
1143 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1144 * its physical size is 128B x 32rows, the same as a Y-tile.
1145 *
1146 * @see isl_surf::row_pitch_B
1147 */
1148 struct isl_extent2d phys_extent_B;
1149 };
1150
1151 /**
1152 * Metadata about a DRM format modifier.
1153 */
1154 struct isl_drm_modifier_info {
1155 uint64_t modifier;
1156
1157 /** Text name of the modifier */
1158 const char *name;
1159
1160 /** ISL tiling implied by this modifier */
1161 enum isl_tiling tiling;
1162
1163 /** ISL aux usage implied by this modifier */
1164 enum isl_aux_usage aux_usage;
1165
1166 /** Whether or not this modifier supports clear color */
1167 bool supports_clear_color;
1168 };
1169
1170 /**
1171 * @brief Input to surface initialization
1172 *
1173 * @invariant width >= 1
1174 * @invariant height >= 1
1175 * @invariant depth >= 1
1176 * @invariant levels >= 1
1177 * @invariant samples >= 1
1178 * @invariant array_len >= 1
1179 *
1180 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1181 * @invariant if 2D then depth == 1
1182 * @invariant if 3D then array_len == 1 and samples == 1
1183 */
1184 struct isl_surf_init_info {
1185 enum isl_surf_dim dim;
1186 enum isl_format format;
1187
1188 uint32_t width;
1189 uint32_t height;
1190 uint32_t depth;
1191 uint32_t levels;
1192 uint32_t array_len;
1193 uint32_t samples;
1194
1195 /** Lower bound for isl_surf::alignment, in bytes. */
1196 uint32_t min_alignment_B;
1197
1198 /**
1199 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1200 * will fail if this is misaligned or out of bounds.
1201 */
1202 uint32_t row_pitch_B;
1203
1204 isl_surf_usage_flags_t usage;
1205
1206 /** Flags that alter how ISL selects isl_surf::tiling. */
1207 isl_tiling_flags_t tiling_flags;
1208 };
1209
1210 struct isl_surf {
1211 enum isl_surf_dim dim;
1212 enum isl_dim_layout dim_layout;
1213 enum isl_msaa_layout msaa_layout;
1214 enum isl_tiling tiling;
1215 enum isl_format format;
1216
1217 /**
1218 * Alignment of the upper-left sample of each subimage, in units of surface
1219 * elements.
1220 */
1221 struct isl_extent3d image_alignment_el;
1222
1223 /**
1224 * Logical extent of the surface's base level, in units of pixels. This is
1225 * identical to the extent defined in isl_surf_init_info.
1226 */
1227 struct isl_extent4d logical_level0_px;
1228
1229 /**
1230 * Physical extent of the surface's base level, in units of physical
1231 * surface samples.
1232 *
1233 * Consider isl_dim_layout as an operator that transforms a logical surface
1234 * layout to a physical surface layout. Then
1235 *
1236 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1237 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1238 */
1239 struct isl_extent4d phys_level0_sa;
1240
1241 uint32_t levels;
1242 uint32_t samples;
1243
1244 /** Total size of the surface, in bytes. */
1245 uint64_t size_B;
1246
1247 /** Required alignment for the surface's base address. */
1248 uint32_t alignment_B;
1249
1250 /**
1251 * The interpretation of this field depends on the value of
1252 * isl_tile_info::physical_extent_B. In particular, the width of the
1253 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1254 * and the distance in bytes between vertically adjacent tiles in the image
1255 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1256 *
1257 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1258 * this cleanly reduces to being the distance, in bytes, between vertically
1259 * adjacent surface elements.
1260 *
1261 * @see isl_tile_info::phys_extent_B;
1262 */
1263 uint32_t row_pitch_B;
1264
1265 /**
1266 * Pitch between physical array slices, in rows of surface elements.
1267 */
1268 uint32_t array_pitch_el_rows;
1269
1270 enum isl_array_pitch_span array_pitch_span;
1271
1272 /** Copy of isl_surf_init_info::usage. */
1273 isl_surf_usage_flags_t usage;
1274 };
1275
1276 struct isl_swizzle {
1277 enum isl_channel_select r:4;
1278 enum isl_channel_select g:4;
1279 enum isl_channel_select b:4;
1280 enum isl_channel_select a:4;
1281 };
1282
1283 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1284 .r = ISL_CHANNEL_SELECT_##R, \
1285 .g = ISL_CHANNEL_SELECT_##G, \
1286 .b = ISL_CHANNEL_SELECT_##B, \
1287 .a = ISL_CHANNEL_SELECT_##A, \
1288 })
1289
1290 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1291
1292 struct isl_view {
1293 /**
1294 * Indicates the usage of the particular view
1295 *
1296 * Normally, this is one bit. However, for a cube map texture, it
1297 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1298 */
1299 isl_surf_usage_flags_t usage;
1300
1301 /**
1302 * The format to use in the view
1303 *
1304 * This may differ from the format of the actual isl_surf but must have
1305 * the same block size.
1306 */
1307 enum isl_format format;
1308
1309 uint32_t base_level;
1310 uint32_t levels;
1311
1312 /**
1313 * Base array layer
1314 *
1315 * For cube maps, both base_array_layer and array_len should be
1316 * specified in terms of 2-D layers and must be a multiple of 6.
1317 *
1318 * 3-D textures are effectively treated as 2-D arrays when used as a
1319 * storage image or render target. If `usage` contains
1320 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1321 * base_array_layer and array_len are applied. If the surface is only used
1322 * for texturing, they are ignored.
1323 */
1324 uint32_t base_array_layer;
1325
1326 /**
1327 * Array Length
1328 *
1329 * Indicates the number of array elements starting at Base Array Layer.
1330 */
1331 uint32_t array_len;
1332
1333 struct isl_swizzle swizzle;
1334 };
1335
1336 union isl_color_value {
1337 float f32[4];
1338 uint32_t u32[4];
1339 int32_t i32[4];
1340 };
1341
1342 struct isl_surf_fill_state_info {
1343 const struct isl_surf *surf;
1344 const struct isl_view *view;
1345
1346 /**
1347 * The address of the surface in GPU memory.
1348 */
1349 uint64_t address;
1350
1351 /**
1352 * The Memory Object Control state for the filled surface state.
1353 *
1354 * The exact format of this value depends on hardware generation.
1355 */
1356 uint32_t mocs;
1357
1358 /**
1359 * The auxilary surface or NULL if no auxilary surface is to be used.
1360 */
1361 const struct isl_surf *aux_surf;
1362 enum isl_aux_usage aux_usage;
1363 uint64_t aux_address;
1364
1365 /**
1366 * The clear color for this surface
1367 *
1368 * Valid values depend on hardware generation.
1369 */
1370 union isl_color_value clear_color;
1371
1372 /**
1373 * Send only the clear value address
1374 *
1375 * If set, we only pass the clear address to the GPU and it will fetch it
1376 * from wherever it is.
1377 */
1378 bool use_clear_address;
1379 uint64_t clear_address;
1380
1381 /**
1382 * Surface write disables for gen4-5
1383 */
1384 isl_channel_mask_t write_disables;
1385
1386 /* Intra-tile offset */
1387 uint16_t x_offset_sa, y_offset_sa;
1388 };
1389
1390 struct isl_buffer_fill_state_info {
1391 /**
1392 * The address of the surface in GPU memory.
1393 */
1394 uint64_t address;
1395
1396 /**
1397 * The size of the buffer
1398 */
1399 uint64_t size_B;
1400
1401 /**
1402 * The Memory Object Control state for the filled surface state.
1403 *
1404 * The exact format of this value depends on hardware generation.
1405 */
1406 uint32_t mocs;
1407
1408 /**
1409 * The format to use in the surface state
1410 *
1411 * This may differ from the format of the actual isl_surf but have the
1412 * same block size.
1413 */
1414 enum isl_format format;
1415
1416 /**
1417 * The swizzle to use in the surface state
1418 */
1419 struct isl_swizzle swizzle;
1420
1421 uint32_t stride_B;
1422 };
1423
1424 struct isl_depth_stencil_hiz_emit_info {
1425 /**
1426 * The depth surface
1427 */
1428 const struct isl_surf *depth_surf;
1429
1430 /**
1431 * The stencil surface
1432 *
1433 * If separate stencil is not available, this must point to the same
1434 * isl_surf as depth_surf.
1435 */
1436 const struct isl_surf *stencil_surf;
1437
1438 /**
1439 * The view into the depth and stencil surfaces.
1440 *
1441 * This view applies to both surfaces simultaneously.
1442 */
1443 const struct isl_view *view;
1444
1445 /**
1446 * The address of the depth surface in GPU memory
1447 */
1448 uint64_t depth_address;
1449
1450 /**
1451 * The address of the stencil surface in GPU memory
1452 *
1453 * If separate stencil is not available, this must have the same value as
1454 * depth_address.
1455 */
1456 uint64_t stencil_address;
1457
1458 /**
1459 * The Memory Object Control state for depth and stencil buffers
1460 *
1461 * Both depth and stencil will get the same MOCS value. The exact format
1462 * of this value depends on hardware generation.
1463 */
1464 uint32_t mocs;
1465
1466 /**
1467 * The HiZ surface or NULL if HiZ is disabled.
1468 */
1469 const struct isl_surf *hiz_surf;
1470 enum isl_aux_usage hiz_usage;
1471 uint64_t hiz_address;
1472
1473 /**
1474 * The depth clear value
1475 */
1476 float depth_clear_value;
1477
1478 /**
1479 * Track stencil aux usage for Gen >= 12
1480 */
1481 enum isl_aux_usage stencil_aux_usage;
1482 };
1483
1484 extern const struct isl_format_layout isl_format_layouts[];
1485
1486 void
1487 isl_device_init(struct isl_device *dev,
1488 const struct gen_device_info *info,
1489 bool has_bit6_swizzling);
1490
1491 isl_sample_count_mask_t ATTRIBUTE_CONST
1492 isl_device_get_sample_counts(struct isl_device *dev);
1493
1494 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1495 isl_format_get_layout(enum isl_format fmt)
1496 {
1497 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1498 assert(fmt < ISL_NUM_FORMATS);
1499 return &isl_format_layouts[fmt];
1500 }
1501
1502 bool isl_format_is_valid(enum isl_format);
1503
1504 static inline const char * ATTRIBUTE_CONST
1505 isl_format_get_name(enum isl_format fmt)
1506 {
1507 return isl_format_get_layout(fmt)->name;
1508 }
1509
1510 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
1511
1512 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1513 enum isl_format format);
1514 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1515 enum isl_format format);
1516 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1517 enum isl_format format);
1518 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1519 enum isl_format format);
1520 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1521 enum isl_format format);
1522 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1523 enum isl_format format);
1524 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1525 enum isl_format format);
1526 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1527 enum isl_format format);
1528 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1529 enum isl_format format);
1530 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1531 enum isl_format format);
1532
1533 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1534 enum isl_format format1,
1535 enum isl_format format2);
1536 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
1537
1538 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1539 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1540 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1541 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1542 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1543 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1544
1545 static inline bool
1546 isl_format_has_normalized_channel(enum isl_format fmt)
1547 {
1548 return isl_format_has_unorm_channel(fmt) ||
1549 isl_format_has_snorm_channel(fmt);
1550 }
1551
1552 static inline bool
1553 isl_format_has_float_channel(enum isl_format fmt)
1554 {
1555 return isl_format_has_ufloat_channel(fmt) ||
1556 isl_format_has_sfloat_channel(fmt);
1557 }
1558
1559 static inline bool
1560 isl_format_has_int_channel(enum isl_format fmt)
1561 {
1562 return isl_format_has_uint_channel(fmt) ||
1563 isl_format_has_sint_channel(fmt);
1564 }
1565
1566 bool isl_format_has_color_component(enum isl_format fmt,
1567 int component) ATTRIBUTE_CONST;
1568
1569 unsigned isl_format_get_num_channels(enum isl_format fmt);
1570
1571 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1572
1573 static inline bool
1574 isl_format_is_compressed(enum isl_format fmt)
1575 {
1576 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1577
1578 return fmtl->txc != ISL_TXC_NONE;
1579 }
1580
1581 static inline bool
1582 isl_format_has_bc_compression(enum isl_format fmt)
1583 {
1584 switch (isl_format_get_layout(fmt)->txc) {
1585 case ISL_TXC_DXT1:
1586 case ISL_TXC_DXT3:
1587 case ISL_TXC_DXT5:
1588 return true;
1589 case ISL_TXC_NONE:
1590 case ISL_TXC_FXT1:
1591 case ISL_TXC_RGTC1:
1592 case ISL_TXC_RGTC2:
1593 case ISL_TXC_BPTC:
1594 case ISL_TXC_ETC1:
1595 case ISL_TXC_ETC2:
1596 case ISL_TXC_ASTC:
1597 return false;
1598
1599 case ISL_TXC_HIZ:
1600 case ISL_TXC_MCS:
1601 case ISL_TXC_CCS:
1602 unreachable("Should not be called on an aux surface");
1603 }
1604
1605 unreachable("bad texture compression mode");
1606 return false;
1607 }
1608
1609 static inline bool
1610 isl_format_is_yuv(enum isl_format fmt)
1611 {
1612 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1613
1614 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1615 }
1616
1617 static inline bool
1618 isl_format_block_is_1x1x1(enum isl_format fmt)
1619 {
1620 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1621
1622 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1623 }
1624
1625 static inline bool
1626 isl_format_is_srgb(enum isl_format fmt)
1627 {
1628 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1629 }
1630
1631 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1632
1633 static inline bool
1634 isl_format_is_rgb(enum isl_format fmt)
1635 {
1636 if (isl_format_is_yuv(fmt))
1637 return false;
1638
1639 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1640
1641 return fmtl->channels.r.bits > 0 &&
1642 fmtl->channels.g.bits > 0 &&
1643 fmtl->channels.b.bits > 0 &&
1644 fmtl->channels.a.bits == 0;
1645 }
1646
1647 static inline bool
1648 isl_format_is_rgbx(enum isl_format fmt)
1649 {
1650 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1651
1652 return fmtl->channels.r.bits > 0 &&
1653 fmtl->channels.g.bits > 0 &&
1654 fmtl->channels.b.bits > 0 &&
1655 fmtl->channels.a.bits > 0 &&
1656 fmtl->channels.a.type == ISL_VOID;
1657 }
1658
1659 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1660 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1661 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1662
1663 void isl_color_value_pack(const union isl_color_value *value,
1664 enum isl_format format,
1665 uint32_t *data_out);
1666 void isl_color_value_unpack(union isl_color_value *value,
1667 enum isl_format format,
1668 const uint32_t *data_in);
1669
1670 bool isl_is_storage_image_format(enum isl_format fmt);
1671
1672 enum isl_format
1673 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1674 enum isl_format fmt);
1675
1676 /* Returns true if this hardware supports typed load/store on a format with
1677 * the same size as the given format.
1678 */
1679 bool
1680 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1681 enum isl_format fmt);
1682
1683 static inline enum isl_tiling
1684 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
1685 {
1686 assert(__builtin_popcount(flag) == 1);
1687 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
1688 }
1689
1690 static inline bool
1691 isl_tiling_is_any_y(enum isl_tiling tiling)
1692 {
1693 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1694 }
1695
1696 static inline bool
1697 isl_tiling_is_std_y(enum isl_tiling tiling)
1698 {
1699 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1700 }
1701
1702 uint32_t
1703 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1704
1705 enum isl_tiling
1706 isl_tiling_from_i915_tiling(uint32_t tiling);
1707
1708 /**
1709 * Return an isl_aux_op needed to enable an access to occur in an
1710 * isl_aux_state suitable for the isl_aux_usage.
1711 *
1712 * NOTE: If the access will invalidate the main surface, this function should
1713 * not be called and the isl_aux_op of NONE should be used instead.
1714 * Otherwise, an extra (but still lossless) ambiguate may occur.
1715 *
1716 * @invariant initial_state is possible with an isl_aux_usage compatible with
1717 * the given usage. Two usages are compatible if it's possible to
1718 * switch between them (e.g. CCS_E <-> CCS_D).
1719 * @invariant fast_clear is false if the aux doesn't support fast clears.
1720 */
1721 enum isl_aux_op
1722 isl_aux_prepare_access(enum isl_aux_state initial_state,
1723 enum isl_aux_usage usage,
1724 bool fast_clear_supported);
1725
1726 /**
1727 * Return the isl_aux_state entered after performing an isl_aux_op.
1728 *
1729 * @invariant initial_state is possible with the given usage.
1730 * @invariant op is possible with the given usage.
1731 * @invariant op must not cause HW to read from an invalid aux.
1732 */
1733 enum isl_aux_state
1734 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
1735 enum isl_aux_usage usage,
1736 enum isl_aux_op op);
1737
1738 /**
1739 * Return the isl_aux_state entered after performing a write.
1740 *
1741 * NOTE: full_surface should be true if the write covers the entire
1742 * slice. Setting it to false in this case will still result in a
1743 * correct (but imprecise) aux state.
1744 *
1745 * @invariant if usage is not ISL_AUX_USAGE_NONE, then initial_state is
1746 * possible with the given usage.
1747 * @invariant usage can be ISL_AUX_USAGE_NONE iff:
1748 * * the main surface is valid, or
1749 * * the main surface is being invalidated/replaced.
1750 */
1751 enum isl_aux_state
1752 isl_aux_state_transition_write(enum isl_aux_state initial_state,
1753 enum isl_aux_usage usage,
1754 bool full_surface);
1755
1756 bool
1757 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
1758
1759 static inline bool
1760 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
1761 {
1762 return usage == ISL_AUX_USAGE_HIZ ||
1763 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
1764 usage == ISL_AUX_USAGE_HIZ_CCS;
1765 }
1766
1767 static inline bool
1768 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
1769 {
1770 return usage == ISL_AUX_USAGE_MCS ||
1771 usage == ISL_AUX_USAGE_MCS_CCS;
1772 }
1773
1774 static inline bool
1775 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
1776 {
1777 return usage == ISL_AUX_USAGE_CCS_D ||
1778 usage == ISL_AUX_USAGE_CCS_E ||
1779 usage == ISL_AUX_USAGE_MC ||
1780 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
1781 usage == ISL_AUX_USAGE_HIZ_CCS ||
1782 usage == ISL_AUX_USAGE_MCS_CCS;
1783 }
1784
1785 static inline bool
1786 isl_aux_state_has_valid_primary(enum isl_aux_state state)
1787 {
1788 return state == ISL_AUX_STATE_RESOLVED ||
1789 state == ISL_AUX_STATE_PASS_THROUGH ||
1790 state == ISL_AUX_STATE_AUX_INVALID;
1791 }
1792
1793 static inline bool
1794 isl_aux_state_has_valid_aux(enum isl_aux_state state)
1795 {
1796 return state != ISL_AUX_STATE_AUX_INVALID;
1797 }
1798
1799 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1800 isl_drm_modifier_get_info(uint64_t modifier);
1801
1802 static inline bool
1803 isl_drm_modifier_has_aux(uint64_t modifier)
1804 {
1805 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1806 }
1807
1808 /** Returns the default isl_aux_state for the given modifier.
1809 *
1810 * If we have a modifier which supports compression, then the auxiliary data
1811 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1812 * can be in any of the following:
1813 *
1814 * - ISL_AUX_STATE_CLEAR
1815 * - ISL_AUX_STATE_PARTIAL_CLEAR
1816 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1817 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1818 * - ISL_AUX_STATE_RESOLVED
1819 * - ISL_AUX_STATE_PASS_THROUGH
1820 *
1821 * If the modifier does not support fast-clears, then we are guaranteed
1822 * that the surface is at least partially resolved and the first three not
1823 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1824 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1825 * because they are the least common denominator of the set of possible aux
1826 * states and will yield a valid interpretation of the aux data.
1827 *
1828 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1829 */
1830 static inline enum isl_aux_state
1831 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1832 {
1833 const struct isl_drm_modifier_info *mod_info =
1834 isl_drm_modifier_get_info(modifier);
1835
1836 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1837 return ISL_AUX_STATE_AUX_INVALID;
1838
1839 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1840 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1841 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1842 }
1843
1844 struct isl_extent2d ATTRIBUTE_CONST
1845 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1846
1847 static inline bool
1848 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1849 {
1850 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1851 }
1852
1853 static inline bool
1854 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1855 {
1856 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1857 }
1858
1859 static inline bool
1860 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1861 {
1862 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1863 }
1864
1865 static inline bool
1866 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1867 {
1868 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1869 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1870 }
1871
1872 static inline bool
1873 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1874 {
1875 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1876 }
1877
1878 static inline bool
1879 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1880 {
1881 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1882 (info->format == ISL_FORMAT_R16_UNORM);
1883 }
1884
1885 static inline bool
1886 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1887 {
1888 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1889 (info->format == ISL_FORMAT_R32_FLOAT);
1890 }
1891
1892 static inline struct isl_extent2d
1893 isl_extent2d(uint32_t width, uint32_t height)
1894 {
1895 struct isl_extent2d e = { { 0 } };
1896
1897 e.width = width;
1898 e.height = height;
1899
1900 return e;
1901 }
1902
1903 static inline struct isl_extent3d
1904 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1905 {
1906 struct isl_extent3d e = { { 0 } };
1907
1908 e.width = width;
1909 e.height = height;
1910 e.depth = depth;
1911
1912 return e;
1913 }
1914
1915 static inline struct isl_extent4d
1916 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1917 uint32_t array_len)
1918 {
1919 struct isl_extent4d e = { { 0 } };
1920
1921 e.width = width;
1922 e.height = height;
1923 e.depth = depth;
1924 e.array_len = array_len;
1925
1926 return e;
1927 }
1928
1929 bool isl_color_value_is_zero(union isl_color_value value,
1930 enum isl_format format);
1931
1932 bool isl_color_value_is_zero_one(union isl_color_value value,
1933 enum isl_format format);
1934
1935 static inline bool
1936 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1937 {
1938 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1939 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1940 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1941 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1942 }
1943
1944 bool
1945 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1946 struct isl_swizzle swizzle);
1947
1948 struct isl_swizzle
1949 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
1950 struct isl_swizzle
1951 isl_swizzle_invert(struct isl_swizzle swizzle);
1952
1953 #define isl_surf_init(dev, surf, ...) \
1954 isl_surf_init_s((dev), (surf), \
1955 &(struct isl_surf_init_info) { __VA_ARGS__ });
1956
1957 bool
1958 isl_surf_init_s(const struct isl_device *dev,
1959 struct isl_surf *surf,
1960 const struct isl_surf_init_info *restrict info);
1961
1962 void
1963 isl_surf_get_tile_info(const struct isl_surf *surf,
1964 struct isl_tile_info *tile_info);
1965
1966 bool
1967 isl_surf_get_hiz_surf(const struct isl_device *dev,
1968 const struct isl_surf *surf,
1969 struct isl_surf *hiz_surf);
1970
1971 bool
1972 isl_surf_get_mcs_surf(const struct isl_device *dev,
1973 const struct isl_surf *surf,
1974 struct isl_surf *mcs_surf);
1975
1976 bool
1977 isl_surf_get_ccs_surf(const struct isl_device *dev,
1978 const struct isl_surf *surf,
1979 struct isl_surf *aux_surf,
1980 struct isl_surf *extra_aux_surf,
1981 uint32_t row_pitch_B /**< Ignored if 0 */);
1982
1983 #define isl_surf_fill_state(dev, state, ...) \
1984 isl_surf_fill_state_s((dev), (state), \
1985 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1986
1987 void
1988 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1989 const struct isl_surf_fill_state_info *restrict info);
1990
1991 #define isl_buffer_fill_state(dev, state, ...) \
1992 isl_buffer_fill_state_s((dev), (state), \
1993 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1994
1995 void
1996 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1997 const struct isl_buffer_fill_state_info *restrict info);
1998
1999 void
2000 isl_null_fill_state(const struct isl_device *dev, void *state,
2001 struct isl_extent3d size);
2002
2003 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2004 isl_emit_depth_stencil_hiz_s((dev), (batch), \
2005 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2006
2007 void
2008 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
2009 const struct isl_depth_stencil_hiz_emit_info *restrict info);
2010
2011 void
2012 isl_surf_fill_image_param(const struct isl_device *dev,
2013 struct brw_image_param *param,
2014 const struct isl_surf *surf,
2015 const struct isl_view *view);
2016
2017 void
2018 isl_buffer_fill_image_param(const struct isl_device *dev,
2019 struct brw_image_param *param,
2020 enum isl_format format,
2021 uint64_t size);
2022
2023 /**
2024 * Alignment of the upper-left sample of each subimage, in units of surface
2025 * elements.
2026 */
2027 static inline struct isl_extent3d
2028 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
2029 {
2030 return surf->image_alignment_el;
2031 }
2032
2033 /**
2034 * Alignment of the upper-left sample of each subimage, in units of surface
2035 * samples.
2036 */
2037 static inline struct isl_extent3d
2038 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
2039 {
2040 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2041
2042 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
2043 fmtl->bh * surf->image_alignment_el.h,
2044 fmtl->bd * surf->image_alignment_el.d);
2045 }
2046
2047 /**
2048 * Logical extent of level 0 in units of surface elements.
2049 */
2050 static inline struct isl_extent4d
2051 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
2052 {
2053 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2054
2055 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
2056 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
2057 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
2058 surf->logical_level0_px.a);
2059 }
2060
2061 /**
2062 * Physical extent of level 0 in units of surface elements.
2063 */
2064 static inline struct isl_extent4d
2065 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
2066 {
2067 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2068
2069 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
2070 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
2071 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
2072 surf->phys_level0_sa.a);
2073 }
2074
2075 /**
2076 * Pitch between vertically adjacent surface elements, in bytes.
2077 */
2078 static inline uint32_t
2079 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2080 {
2081 return surf->row_pitch_B;
2082 }
2083
2084 /**
2085 * Pitch between vertically adjacent surface elements, in units of surface elements.
2086 */
2087 static inline uint32_t
2088 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2089 {
2090 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2091
2092 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2093 return surf->row_pitch_B / (fmtl->bpb / 8);
2094 }
2095
2096 /**
2097 * Pitch between physical array slices, in rows of surface elements.
2098 */
2099 static inline uint32_t
2100 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2101 {
2102 return surf->array_pitch_el_rows;
2103 }
2104
2105 /**
2106 * Pitch between physical array slices, in units of surface elements.
2107 */
2108 static inline uint32_t
2109 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2110 {
2111 return isl_surf_get_array_pitch_el_rows(surf) *
2112 isl_surf_get_row_pitch_el(surf);
2113 }
2114
2115 /**
2116 * Pitch between physical array slices, in rows of surface samples.
2117 */
2118 static inline uint32_t
2119 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2120 {
2121 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2122 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2123 }
2124
2125 /**
2126 * Pitch between physical array slices, in bytes.
2127 */
2128 static inline uint32_t
2129 isl_surf_get_array_pitch(const struct isl_surf *surf)
2130 {
2131 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2132 }
2133
2134 /**
2135 * Calculate the offset, in units of surface samples, to a subimage in the
2136 * surface.
2137 *
2138 * @invariant level < surface levels
2139 * @invariant logical_array_layer < logical array length of surface
2140 * @invariant logical_z_offset_px < logical depth of surface at level
2141 */
2142 void
2143 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2144 uint32_t level,
2145 uint32_t logical_array_layer,
2146 uint32_t logical_z_offset_px,
2147 uint32_t *x_offset_sa,
2148 uint32_t *y_offset_sa);
2149
2150 /**
2151 * Calculate the offset, in units of surface elements, to a subimage in the
2152 * surface.
2153 *
2154 * @invariant level < surface levels
2155 * @invariant logical_array_layer < logical array length of surface
2156 * @invariant logical_z_offset_px < logical depth of surface at level
2157 */
2158 void
2159 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2160 uint32_t level,
2161 uint32_t logical_array_layer,
2162 uint32_t logical_z_offset_px,
2163 uint32_t *x_offset_el,
2164 uint32_t *y_offset_el);
2165
2166 /**
2167 * Calculate the offset, in bytes and intratile surface samples, to a
2168 * subimage in the surface.
2169 *
2170 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2171 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2172 * offsets to samples.
2173 *
2174 * @invariant level < surface levels
2175 * @invariant logical_array_layer < logical array length of surface
2176 * @invariant logical_z_offset_px < logical depth of surface at level
2177 */
2178 void
2179 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2180 uint32_t level,
2181 uint32_t logical_array_layer,
2182 uint32_t logical_z_offset_px,
2183 uint32_t *offset_B,
2184 uint32_t *x_offset_sa,
2185 uint32_t *y_offset_sa);
2186
2187 /**
2188 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2189 *
2190 * The range returned will be the smallest memory range in which the give
2191 * subimage fits, rounded to even tiles. Intel images do not usually have a
2192 * direct subimage -> range mapping so the range returned may contain data
2193 * from other sub-images. The returned range is a half-open interval where
2194 * all of the addresses within the subimage are < end_tile_B.
2195 *
2196 * @invariant level < surface levels
2197 * @invariant logical_array_layer < logical array length of surface
2198 * @invariant logical_z_offset_px < logical depth of surface at level
2199 */
2200 void
2201 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2202 uint32_t level,
2203 uint32_t logical_array_layer,
2204 uint32_t logical_z_offset_px,
2205 uint32_t *start_tile_B,
2206 uint32_t *end_tile_B);
2207
2208 /**
2209 * Create an isl_surf that represents a particular subimage in the surface.
2210 *
2211 * The newly created surface will have a single miplevel and array slice. The
2212 * surface lives at the returned byte and intratile offsets, in samples.
2213 *
2214 * It is safe to call this function with surf == image_surf.
2215 *
2216 * @invariant level < surface levels
2217 * @invariant logical_array_layer < logical array length of surface
2218 * @invariant logical_z_offset_px < logical depth of surface at level
2219 */
2220 void
2221 isl_surf_get_image_surf(const struct isl_device *dev,
2222 const struct isl_surf *surf,
2223 uint32_t level,
2224 uint32_t logical_array_layer,
2225 uint32_t logical_z_offset_px,
2226 struct isl_surf *image_surf,
2227 uint32_t *offset_B,
2228 uint32_t *x_offset_sa,
2229 uint32_t *y_offset_sa);
2230
2231 /**
2232 * @brief Calculate the intratile offsets to a surface.
2233 *
2234 * In @a base_address_offset return the offset from the base of the surface to
2235 * the base address of the first tile of the subimage. In @a x_offset_B and
2236 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2237 * tile's base to the subimage's first surface element. The x and y offsets
2238 * are intratile offsets; that is, they do not exceed the boundary of the
2239 * surface's tiling format.
2240 */
2241 void
2242 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2243 uint32_t bpb,
2244 uint32_t row_pitch_B,
2245 uint32_t total_x_offset_el,
2246 uint32_t total_y_offset_el,
2247 uint32_t *base_address_offset,
2248 uint32_t *x_offset_el,
2249 uint32_t *y_offset_el);
2250
2251 static inline void
2252 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2253 enum isl_format format,
2254 uint32_t row_pitch_B,
2255 uint32_t total_x_offset_sa,
2256 uint32_t total_y_offset_sa,
2257 uint32_t *base_address_offset,
2258 uint32_t *x_offset_sa,
2259 uint32_t *y_offset_sa)
2260 {
2261 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2262
2263 /* For computing the intratile offsets, we actually want a strange unit
2264 * which is samples for multisampled surfaces but elements for compressed
2265 * surfaces.
2266 */
2267 assert(total_x_offset_sa % fmtl->bw == 0);
2268 assert(total_y_offset_sa % fmtl->bh == 0);
2269 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2270 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2271
2272 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
2273 total_x_offset, total_y_offset,
2274 base_address_offset,
2275 x_offset_sa, y_offset_sa);
2276 *x_offset_sa *= fmtl->bw;
2277 *y_offset_sa *= fmtl->bh;
2278 }
2279
2280 /**
2281 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2282 *
2283 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2284 * @pre surf->format must be a valid format for depth surfaces
2285 */
2286 uint32_t
2287 isl_surf_get_depth_format(const struct isl_device *dev,
2288 const struct isl_surf *surf);
2289
2290 /**
2291 * @brief determines if a surface supports writing through HIZ to the CCS.
2292 */
2293 bool
2294 isl_surf_supports_hiz_ccs_wt(const struct gen_device_info *dev,
2295 const struct isl_surf *surf,
2296 enum isl_aux_usage aux_usage);
2297
2298 /**
2299 * @brief performs a copy from linear to tiled surface
2300 *
2301 */
2302 void
2303 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2304 uint32_t yt1, uint32_t yt2,
2305 char *dst, const char *src,
2306 uint32_t dst_pitch, int32_t src_pitch,
2307 bool has_swizzling,
2308 enum isl_tiling tiling,
2309 isl_memcpy_type copy_type);
2310
2311 /**
2312 * @brief performs a copy from tiled to linear surface
2313 *
2314 */
2315 void
2316 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2317 uint32_t yt1, uint32_t yt2,
2318 char *dst, const char *src,
2319 int32_t dst_pitch, uint32_t src_pitch,
2320 bool has_swizzling,
2321 enum isl_tiling tiling,
2322 isl_memcpy_type copy_type);
2323
2324 #ifdef __cplusplus
2325 }
2326 #endif
2327
2328 #endif /* ISL_H */