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isl: Fix isl_tiling_is_any_y()
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct brw_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
63 #else
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
66 #endif
67
68 #ifndef ISL_DEV_IS_HASWELL
69 /**
70 * @brief Get the hardware generation of isl_device.
71 *
72 * You can define this as a compile-time constant in the CFLAGS. For example,
73 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
74 */
75 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
76 #endif
77
78 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
79 /**
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
82 */
83 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
84 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
85 #else
86 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
87 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
88 #endif
89
90 /**
91 * Hardware enumeration SURFACE_FORMAT.
92 *
93 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
94 * Enumerations: SURFACE_FORMAT.
95 */
96 enum isl_format {
97 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
98 ISL_FORMAT_R32G32B32A32_SINT = 1,
99 ISL_FORMAT_R32G32B32A32_UINT = 2,
100 ISL_FORMAT_R32G32B32A32_UNORM = 3,
101 ISL_FORMAT_R32G32B32A32_SNORM = 4,
102 ISL_FORMAT_R64G64_FLOAT = 5,
103 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
104 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
105 ISL_FORMAT_R32G32B32A32_USCALED = 8,
106 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
107 ISL_FORMAT_R64G64_PASSTHRU = 33,
108 ISL_FORMAT_R32G32B32_FLOAT = 64,
109 ISL_FORMAT_R32G32B32_SINT = 65,
110 ISL_FORMAT_R32G32B32_UINT = 66,
111 ISL_FORMAT_R32G32B32_UNORM = 67,
112 ISL_FORMAT_R32G32B32_SNORM = 68,
113 ISL_FORMAT_R32G32B32_SSCALED = 69,
114 ISL_FORMAT_R32G32B32_USCALED = 70,
115 ISL_FORMAT_R32G32B32_SFIXED = 80,
116 ISL_FORMAT_R16G16B16A16_UNORM = 128,
117 ISL_FORMAT_R16G16B16A16_SNORM = 129,
118 ISL_FORMAT_R16G16B16A16_SINT = 130,
119 ISL_FORMAT_R16G16B16A16_UINT = 131,
120 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
121 ISL_FORMAT_R32G32_FLOAT = 133,
122 ISL_FORMAT_R32G32_SINT = 134,
123 ISL_FORMAT_R32G32_UINT = 135,
124 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
125 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
126 ISL_FORMAT_L32A32_FLOAT = 138,
127 ISL_FORMAT_R32G32_UNORM = 139,
128 ISL_FORMAT_R32G32_SNORM = 140,
129 ISL_FORMAT_R64_FLOAT = 141,
130 ISL_FORMAT_R16G16B16X16_UNORM = 142,
131 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
132 ISL_FORMAT_A32X32_FLOAT = 144,
133 ISL_FORMAT_L32X32_FLOAT = 145,
134 ISL_FORMAT_I32X32_FLOAT = 146,
135 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
136 ISL_FORMAT_R16G16B16A16_USCALED = 148,
137 ISL_FORMAT_R32G32_SSCALED = 149,
138 ISL_FORMAT_R32G32_USCALED = 150,
139 ISL_FORMAT_R32G32_FLOAT_LD = 151,
140 ISL_FORMAT_R32G32_SFIXED = 160,
141 ISL_FORMAT_R64_PASSTHRU = 161,
142 ISL_FORMAT_B8G8R8A8_UNORM = 192,
143 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
144 ISL_FORMAT_R10G10B10A2_UNORM = 194,
145 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
146 ISL_FORMAT_R10G10B10A2_UINT = 196,
147 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
148 ISL_FORMAT_R8G8B8A8_UNORM = 199,
149 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
150 ISL_FORMAT_R8G8B8A8_SNORM = 201,
151 ISL_FORMAT_R8G8B8A8_SINT = 202,
152 ISL_FORMAT_R8G8B8A8_UINT = 203,
153 ISL_FORMAT_R16G16_UNORM = 204,
154 ISL_FORMAT_R16G16_SNORM = 205,
155 ISL_FORMAT_R16G16_SINT = 206,
156 ISL_FORMAT_R16G16_UINT = 207,
157 ISL_FORMAT_R16G16_FLOAT = 208,
158 ISL_FORMAT_B10G10R10A2_UNORM = 209,
159 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
160 ISL_FORMAT_R11G11B10_FLOAT = 211,
161 ISL_FORMAT_R32_SINT = 214,
162 ISL_FORMAT_R32_UINT = 215,
163 ISL_FORMAT_R32_FLOAT = 216,
164 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
165 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
166 ISL_FORMAT_L32_UNORM = 221,
167 ISL_FORMAT_A32_UNORM = 222,
168 ISL_FORMAT_L16A16_UNORM = 223,
169 ISL_FORMAT_I24X8_UNORM = 224,
170 ISL_FORMAT_L24X8_UNORM = 225,
171 ISL_FORMAT_A24X8_UNORM = 226,
172 ISL_FORMAT_I32_FLOAT = 227,
173 ISL_FORMAT_L32_FLOAT = 228,
174 ISL_FORMAT_A32_FLOAT = 229,
175 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
176 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
177 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
178 ISL_FORMAT_B8G8R8X8_UNORM = 233,
179 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
180 ISL_FORMAT_R8G8B8X8_UNORM = 235,
181 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
182 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
183 ISL_FORMAT_B10G10R10X2_UNORM = 238,
184 ISL_FORMAT_L16A16_FLOAT = 240,
185 ISL_FORMAT_R32_UNORM = 241,
186 ISL_FORMAT_R32_SNORM = 242,
187 ISL_FORMAT_R10G10B10X2_USCALED = 243,
188 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
189 ISL_FORMAT_R8G8B8A8_USCALED = 245,
190 ISL_FORMAT_R16G16_SSCALED = 246,
191 ISL_FORMAT_R16G16_USCALED = 247,
192 ISL_FORMAT_R32_SSCALED = 248,
193 ISL_FORMAT_R32_USCALED = 249,
194 ISL_FORMAT_B5G6R5_UNORM = 256,
195 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
196 ISL_FORMAT_B5G5R5A1_UNORM = 258,
197 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
198 ISL_FORMAT_B4G4R4A4_UNORM = 260,
199 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
200 ISL_FORMAT_R8G8_UNORM = 262,
201 ISL_FORMAT_R8G8_SNORM = 263,
202 ISL_FORMAT_R8G8_SINT = 264,
203 ISL_FORMAT_R8G8_UINT = 265,
204 ISL_FORMAT_R16_UNORM = 266,
205 ISL_FORMAT_R16_SNORM = 267,
206 ISL_FORMAT_R16_SINT = 268,
207 ISL_FORMAT_R16_UINT = 269,
208 ISL_FORMAT_R16_FLOAT = 270,
209 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
210 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
211 ISL_FORMAT_I16_UNORM = 273,
212 ISL_FORMAT_L16_UNORM = 274,
213 ISL_FORMAT_A16_UNORM = 275,
214 ISL_FORMAT_L8A8_UNORM = 276,
215 ISL_FORMAT_I16_FLOAT = 277,
216 ISL_FORMAT_L16_FLOAT = 278,
217 ISL_FORMAT_A16_FLOAT = 279,
218 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
219 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
220 ISL_FORMAT_B5G5R5X1_UNORM = 282,
221 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
222 ISL_FORMAT_R8G8_SSCALED = 284,
223 ISL_FORMAT_R8G8_USCALED = 285,
224 ISL_FORMAT_R16_SSCALED = 286,
225 ISL_FORMAT_R16_USCALED = 287,
226 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
227 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
228 ISL_FORMAT_A1B5G5R5_UNORM = 292,
229 ISL_FORMAT_A4B4G4R4_UNORM = 293,
230 ISL_FORMAT_L8A8_UINT = 294,
231 ISL_FORMAT_L8A8_SINT = 295,
232 ISL_FORMAT_R8_UNORM = 320,
233 ISL_FORMAT_R8_SNORM = 321,
234 ISL_FORMAT_R8_SINT = 322,
235 ISL_FORMAT_R8_UINT = 323,
236 ISL_FORMAT_A8_UNORM = 324,
237 ISL_FORMAT_I8_UNORM = 325,
238 ISL_FORMAT_L8_UNORM = 326,
239 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
240 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
241 ISL_FORMAT_R8_SSCALED = 329,
242 ISL_FORMAT_R8_USCALED = 330,
243 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
244 ISL_FORMAT_L8_UNORM_SRGB = 332,
245 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
246 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
247 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
248 ISL_FORMAT_Y8_UNORM = 336,
249 ISL_FORMAT_L8_UINT = 338,
250 ISL_FORMAT_L8_SINT = 339,
251 ISL_FORMAT_I8_UINT = 340,
252 ISL_FORMAT_I8_SINT = 341,
253 ISL_FORMAT_DXT1_RGB_SRGB = 384,
254 ISL_FORMAT_R1_UNORM = 385,
255 ISL_FORMAT_YCRCB_NORMAL = 386,
256 ISL_FORMAT_YCRCB_SWAPUVY = 387,
257 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
258 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
259 ISL_FORMAT_BC1_UNORM = 390,
260 ISL_FORMAT_BC2_UNORM = 391,
261 ISL_FORMAT_BC3_UNORM = 392,
262 ISL_FORMAT_BC4_UNORM = 393,
263 ISL_FORMAT_BC5_UNORM = 394,
264 ISL_FORMAT_BC1_UNORM_SRGB = 395,
265 ISL_FORMAT_BC2_UNORM_SRGB = 396,
266 ISL_FORMAT_BC3_UNORM_SRGB = 397,
267 ISL_FORMAT_MONO8 = 398,
268 ISL_FORMAT_YCRCB_SWAPUV = 399,
269 ISL_FORMAT_YCRCB_SWAPY = 400,
270 ISL_FORMAT_DXT1_RGB = 401,
271 ISL_FORMAT_FXT1 = 402,
272 ISL_FORMAT_R8G8B8_UNORM = 403,
273 ISL_FORMAT_R8G8B8_SNORM = 404,
274 ISL_FORMAT_R8G8B8_SSCALED = 405,
275 ISL_FORMAT_R8G8B8_USCALED = 406,
276 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
277 ISL_FORMAT_R64G64B64_FLOAT = 408,
278 ISL_FORMAT_BC4_SNORM = 409,
279 ISL_FORMAT_BC5_SNORM = 410,
280 ISL_FORMAT_R16G16B16_FLOAT = 411,
281 ISL_FORMAT_R16G16B16_UNORM = 412,
282 ISL_FORMAT_R16G16B16_SNORM = 413,
283 ISL_FORMAT_R16G16B16_SSCALED = 414,
284 ISL_FORMAT_R16G16B16_USCALED = 415,
285 ISL_FORMAT_BC6H_SF16 = 417,
286 ISL_FORMAT_BC7_UNORM = 418,
287 ISL_FORMAT_BC7_UNORM_SRGB = 419,
288 ISL_FORMAT_BC6H_UF16 = 420,
289 ISL_FORMAT_PLANAR_420_8 = 421,
290 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
291 ISL_FORMAT_ETC1_RGB8 = 425,
292 ISL_FORMAT_ETC2_RGB8 = 426,
293 ISL_FORMAT_EAC_R11 = 427,
294 ISL_FORMAT_EAC_RG11 = 428,
295 ISL_FORMAT_EAC_SIGNED_R11 = 429,
296 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
297 ISL_FORMAT_ETC2_SRGB8 = 431,
298 ISL_FORMAT_R16G16B16_UINT = 432,
299 ISL_FORMAT_R16G16B16_SINT = 433,
300 ISL_FORMAT_R32_SFIXED = 434,
301 ISL_FORMAT_R10G10B10A2_SNORM = 435,
302 ISL_FORMAT_R10G10B10A2_USCALED = 436,
303 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
304 ISL_FORMAT_R10G10B10A2_SINT = 438,
305 ISL_FORMAT_B10G10R10A2_SNORM = 439,
306 ISL_FORMAT_B10G10R10A2_USCALED = 440,
307 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
308 ISL_FORMAT_B10G10R10A2_UINT = 442,
309 ISL_FORMAT_B10G10R10A2_SINT = 443,
310 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
311 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
312 ISL_FORMAT_ETC2_RGB8_PTA = 448,
313 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
314 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
315 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
316 ISL_FORMAT_R8G8B8_UINT = 456,
317 ISL_FORMAT_R8G8B8_SINT = 457,
318 ISL_FORMAT_RAW = 511,
319 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
320 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
321 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
322 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
323 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
324 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
325 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
326 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
327 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
328 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
329 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
330 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
331 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
332 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
347
348 /* The formats that follow are internal to ISL and as such don't have an
349 * explicit number. We'll just let the C compiler assign it for us. Any
350 * actual hardware formats *must* come before these in the list.
351 */
352
353 /* Formats for color compression surfaces */
354 ISL_FORMAT_HIZ,
355 ISL_FORMAT_MCS_2X,
356 ISL_FORMAT_MCS_4X,
357 ISL_FORMAT_MCS_8X,
358 ISL_FORMAT_MCS_16X,
359 ISL_FORMAT_GEN7_CCS_32BPP_X,
360 ISL_FORMAT_GEN7_CCS_64BPP_X,
361 ISL_FORMAT_GEN7_CCS_128BPP_X,
362 ISL_FORMAT_GEN7_CCS_32BPP_Y,
363 ISL_FORMAT_GEN7_CCS_64BPP_Y,
364 ISL_FORMAT_GEN7_CCS_128BPP_Y,
365 ISL_FORMAT_GEN9_CCS_32BPP,
366 ISL_FORMAT_GEN9_CCS_64BPP,
367 ISL_FORMAT_GEN9_CCS_128BPP,
368
369 /* Hardware doesn't understand this out-of-band value */
370 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
371 };
372
373 /**
374 * Numerical base type for channels of isl_format.
375 */
376 enum isl_base_type {
377 ISL_VOID,
378 ISL_RAW,
379 ISL_UNORM,
380 ISL_SNORM,
381 ISL_UFLOAT,
382 ISL_SFLOAT,
383 ISL_UFIXED,
384 ISL_SFIXED,
385 ISL_UINT,
386 ISL_SINT,
387 ISL_USCALED,
388 ISL_SSCALED,
389 };
390
391 /**
392 * Colorspace of isl_format.
393 */
394 enum isl_colorspace {
395 ISL_COLORSPACE_NONE = 0,
396 ISL_COLORSPACE_LINEAR,
397 ISL_COLORSPACE_SRGB,
398 ISL_COLORSPACE_YUV,
399 };
400
401 /**
402 * Texture compression mode of isl_format.
403 */
404 enum isl_txc {
405 ISL_TXC_NONE = 0,
406 ISL_TXC_DXT1,
407 ISL_TXC_DXT3,
408 ISL_TXC_DXT5,
409 ISL_TXC_FXT1,
410 ISL_TXC_RGTC1,
411 ISL_TXC_RGTC2,
412 ISL_TXC_BPTC,
413 ISL_TXC_ETC1,
414 ISL_TXC_ETC2,
415 ISL_TXC_ASTC,
416
417 /* Used for auxiliary surface formats */
418 ISL_TXC_HIZ,
419 ISL_TXC_MCS,
420 ISL_TXC_CCS,
421 };
422
423 /**
424 * @brief Hardware tile mode
425 *
426 * WARNING: These values differ from the hardware enum values, which are
427 * unstable across hardware generations.
428 *
429 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
430 * clearly distinguish it from Yf and Ys.
431 */
432 enum isl_tiling {
433 ISL_TILING_LINEAR = 0,
434 ISL_TILING_W,
435 ISL_TILING_X,
436 ISL_TILING_Y0, /**< Legacy Y tiling */
437 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
438 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
439 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
440 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
441 };
442
443 /**
444 * @defgroup Tiling Flags
445 * @{
446 */
447 typedef uint32_t isl_tiling_flags_t;
448 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
449 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
450 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
451 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
452 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
453 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
454 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
455 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
456 #define ISL_TILING_ANY_MASK (~0u)
457 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
458
459 /** Any Y tiling, including legacy Y tiling. */
460 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
461 ISL_TILING_Yf_BIT | \
462 ISL_TILING_Ys_BIT)
463
464 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
465 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
466 ISL_TILING_Ys_BIT)
467 /** @} */
468
469 /**
470 * @brief Logical dimension of surface.
471 *
472 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
473 * as 2D array surfaces.
474 */
475 enum isl_surf_dim {
476 ISL_SURF_DIM_1D,
477 ISL_SURF_DIM_2D,
478 ISL_SURF_DIM_3D,
479 };
480
481 /**
482 * @brief Physical layout of the surface's dimensions.
483 */
484 enum isl_dim_layout {
485 /**
486 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
487 * 6.17.3: 2D Surfaces.
488 *
489 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
490 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
491 *
492 * One-dimensional surfaces are identical to 2D surfaces with height of
493 * one.
494 *
495 * @invariant isl_surf::phys_level0_sa::depth == 1
496 */
497 ISL_DIM_LAYOUT_GEN4_2D,
498
499 /**
500 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
501 * 6.17.5: 3D Surfaces.
502 *
503 * @invariant isl_surf::phys_level0_sa::array_len == 1
504 */
505 ISL_DIM_LAYOUT_GEN4_3D,
506
507 /**
508 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
509 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
510 */
511 ISL_DIM_LAYOUT_GEN9_1D,
512 };
513
514 enum isl_aux_usage {
515 /** No Auxiliary surface is used */
516 ISL_AUX_USAGE_NONE,
517
518 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
519 ISL_AUX_USAGE_HIZ,
520
521 /** The auxiliary surface is an MCS
522 *
523 * @invariant isl_surf::samples > 1
524 */
525 ISL_AUX_USAGE_MCS,
526
527 /** The auxiliary surface is a fast-clear-only compression surface
528 *
529 * @invariant isl_surf::samples == 1
530 */
531 ISL_AUX_USAGE_CCS_D,
532
533 /** The auxiliary surface provides full lossless color compression
534 *
535 * @invariant isl_surf::samples == 1
536 */
537 ISL_AUX_USAGE_CCS_E,
538 };
539
540 /* TODO(chadv): Explain */
541 enum isl_array_pitch_span {
542 ISL_ARRAY_PITCH_SPAN_FULL,
543 ISL_ARRAY_PITCH_SPAN_COMPACT,
544 };
545
546 /**
547 * @defgroup Surface Usage
548 * @{
549 */
550 typedef uint64_t isl_surf_usage_flags_t;
551 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
552 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
553 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
554 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
555 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
556 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
557 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
558 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
559 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
560 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
561 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
562 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
563 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
564 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
565 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
566 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
567 /** @} */
568
569 /**
570 * @brief A channel select (also known as texture swizzle) value
571 */
572 enum isl_channel_select {
573 ISL_CHANNEL_SELECT_ZERO = 0,
574 ISL_CHANNEL_SELECT_ONE = 1,
575 ISL_CHANNEL_SELECT_RED = 4,
576 ISL_CHANNEL_SELECT_GREEN = 5,
577 ISL_CHANNEL_SELECT_BLUE = 6,
578 ISL_CHANNEL_SELECT_ALPHA = 7,
579 };
580
581 /**
582 * Identical to VkSampleCountFlagBits.
583 */
584 enum isl_sample_count {
585 ISL_SAMPLE_COUNT_1_BIT = 1u,
586 ISL_SAMPLE_COUNT_2_BIT = 2u,
587 ISL_SAMPLE_COUNT_4_BIT = 4u,
588 ISL_SAMPLE_COUNT_8_BIT = 8u,
589 ISL_SAMPLE_COUNT_16_BIT = 16u,
590 };
591 typedef uint32_t isl_sample_count_mask_t;
592
593 /**
594 * @brief Multisample Format
595 */
596 enum isl_msaa_layout {
597 /**
598 * @brief Suface is single-sampled.
599 */
600 ISL_MSAA_LAYOUT_NONE,
601
602 /**
603 * @brief [SNB+] Interleaved Multisample Format
604 *
605 * In this format, multiple samples are interleaved into each cacheline.
606 * In other words, the sample index is swizzled into the low 6 bits of the
607 * surface's virtual address space.
608 *
609 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
610 * and its pixel format is 32bpp. Then the first cacheline is arranged
611 * thus:
612 *
613 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
614 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
615 *
616 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
617 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
618 *
619 * The hardware docs refer to this format with multiple terms. In
620 * Sandybridge, this is the only multisample format; so no term is used.
621 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
622 * Multisample Surface). Later hardware docs additionally refer to this
623 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
624 * color surfaces).
625 *
626 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
627 * Surface Behavior".
628 *
629 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
630 * Multisampled Surfaces".
631 */
632 ISL_MSAA_LAYOUT_INTERLEAVED,
633
634 /**
635 * @brief [IVB+] Array Multisample Format
636 *
637 * In this format, the surface's physical layout resembles that of a
638 * 2D array surface.
639 *
640 * Suppose the multisample surface's logical extent is (w, h) and its
641 * sample count is N. Then surface's physical extent is the same as
642 * a singlesample 2D surface whose logical extent is (w, h) and array
643 * length is N. Array slice `i` contains the pixel values for sample
644 * index `i`.
645 *
646 * The Ivybridge docs refer to surfaces in this format as UMS
647 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
648 * Surface). The Broadwell docs additionally refer to this format as
649 * MSFMT_MSS (MSS=Multisample Surface Storage).
650 *
651 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
652 * Multisample Surfaces".
653 *
654 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
655 * Multisample Surfaces".
656 */
657 ISL_MSAA_LAYOUT_ARRAY,
658 };
659
660
661 struct isl_device {
662 const struct brw_device_info *info;
663 bool use_separate_stencil;
664 bool has_bit6_swizzling;
665 };
666
667 struct isl_extent2d {
668 union { uint32_t w, width; };
669 union { uint32_t h, height; };
670 };
671
672 struct isl_extent3d {
673 union { uint32_t w, width; };
674 union { uint32_t h, height; };
675 union { uint32_t d, depth; };
676 };
677
678 struct isl_extent4d {
679 union { uint32_t w, width; };
680 union { uint32_t h, height; };
681 union { uint32_t d, depth; };
682 union { uint32_t a, array_len; };
683 };
684
685 struct isl_channel_layout {
686 enum isl_base_type type;
687 uint8_t bits; /**< Size in bits */
688 };
689
690 /**
691 * Each format has 3D block extent (width, height, depth). The block extent of
692 * compressed formats is that of the format's compression block. For example,
693 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
694 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
695 * is (w=1, h=1, d=1).
696 */
697 struct isl_format_layout {
698 enum isl_format format;
699 const char *name;
700
701 uint16_t bpb; /**< Bits per block */
702 uint8_t bw; /**< Block width, in pixels */
703 uint8_t bh; /**< Block height, in pixels */
704 uint8_t bd; /**< Block depth, in pixels */
705
706 struct {
707 struct isl_channel_layout r; /**< Red channel */
708 struct isl_channel_layout g; /**< Green channel */
709 struct isl_channel_layout b; /**< Blue channel */
710 struct isl_channel_layout a; /**< Alpha channel */
711 struct isl_channel_layout l; /**< Luminance channel */
712 struct isl_channel_layout i; /**< Intensity channel */
713 struct isl_channel_layout p; /**< Palette channel */
714 } channels;
715
716 enum isl_colorspace colorspace;
717 enum isl_txc txc;
718 };
719
720 struct isl_tile_info {
721 enum isl_tiling tiling;
722
723 /** The logical size of the tile in units of surface elements
724 *
725 * This field determines how a given surface is cut up into tiles. It is
726 * used to compute the size of a surface in tiles and can be used to
727 * determine the location of the tile containing any given surface element.
728 * The exact value of this field depends heavily on the bits-per-block of
729 * the format being used.
730 */
731 struct isl_extent2d logical_extent_el;
732
733 /** The physical size of the tile in bytes and rows of bytes
734 *
735 * This field determines how the tiles of a surface are physically layed
736 * out in memory. The logical and physical tile extent are frequently the
737 * same but this is not always the case. For instance, a W-tile (which is
738 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
739 * its physical size is 128B x 32rows, the same as a Y-tile.
740 *
741 * @see isl_surf::row_pitch
742 */
743 struct isl_extent2d phys_extent_B;
744 };
745
746 /**
747 * @brief Input to surface initialization
748 *
749 * @invariant width >= 1
750 * @invariant height >= 1
751 * @invariant depth >= 1
752 * @invariant levels >= 1
753 * @invariant samples >= 1
754 * @invariant array_len >= 1
755 *
756 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
757 * @invariant if 2D then depth == 1
758 * @invariant if 3D then array_len == 1 and samples == 1
759 */
760 struct isl_surf_init_info {
761 enum isl_surf_dim dim;
762 enum isl_format format;
763
764 uint32_t width;
765 uint32_t height;
766 uint32_t depth;
767 uint32_t levels;
768 uint32_t array_len;
769 uint32_t samples;
770
771 /** Lower bound for isl_surf::alignment, in bytes. */
772 uint32_t min_alignment;
773
774 /** Lower bound for isl_surf::pitch, in bytes. */
775 uint32_t min_pitch;
776
777 isl_surf_usage_flags_t usage;
778
779 /** Flags that alter how ISL selects isl_surf::tiling. */
780 isl_tiling_flags_t tiling_flags;
781 };
782
783 struct isl_surf {
784 enum isl_surf_dim dim;
785 enum isl_dim_layout dim_layout;
786 enum isl_msaa_layout msaa_layout;
787 enum isl_tiling tiling;
788 enum isl_format format;
789
790 /**
791 * Alignment of the upper-left sample of each subimage, in units of surface
792 * elements.
793 */
794 struct isl_extent3d image_alignment_el;
795
796 /**
797 * Logical extent of the surface's base level, in units of pixels. This is
798 * identical to the extent defined in isl_surf_init_info.
799 */
800 struct isl_extent4d logical_level0_px;
801
802 /**
803 * Physical extent of the surface's base level, in units of physical
804 * surface samples and aligned to the format's compression block.
805 *
806 * Consider isl_dim_layout as an operator that transforms a logical surface
807 * layout to a physical surface layout. Then
808 *
809 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
810 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
811 */
812 struct isl_extent4d phys_level0_sa;
813
814 uint32_t levels;
815 uint32_t samples;
816
817 /** Total size of the surface, in bytes. */
818 uint32_t size;
819
820 /** Required alignment for the surface's base address. */
821 uint32_t alignment;
822
823 /**
824 * The interpretation of this field depends on the value of
825 * isl_tile_info::physical_extent_B. In particular, the width of the
826 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
827 * and the distance in bytes between vertically adjacent tiles in the image
828 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
829 *
830 * For linear images where isl_tile_info::physical_extent_B.height == 1,
831 * this cleanly reduces to being the distance, in bytes, between vertically
832 * adjacent surface elements.
833 *
834 * @see isl_tile_info::phys_extent_B;
835 */
836 uint32_t row_pitch;
837
838 /**
839 * Pitch between physical array slices, in rows of surface elements.
840 */
841 uint32_t array_pitch_el_rows;
842
843 enum isl_array_pitch_span array_pitch_span;
844
845 /** Copy of isl_surf_init_info::usage. */
846 isl_surf_usage_flags_t usage;
847 };
848
849 struct isl_view {
850 /**
851 * Indicates the usage of the particular view
852 *
853 * Normally, this is one bit. However, for a cube map texture, it
854 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
855 */
856 isl_surf_usage_flags_t usage;
857
858 /**
859 * The format to use in the view
860 *
861 * This may differ from the format of the actual isl_surf but must have
862 * the same block size.
863 */
864 enum isl_format format;
865
866 uint32_t base_level;
867 uint32_t levels;
868
869 /**
870 * Base array layer
871 *
872 * For cube maps, both base_array_layer and array_len should be
873 * specified in terms of 2-D layers and must be a multiple of 6.
874 */
875 uint32_t base_array_layer;
876 uint32_t array_len;
877
878 enum isl_channel_select channel_select[4];
879 };
880
881 union isl_color_value {
882 float f32[4];
883 uint32_t u32[4];
884 int32_t i32[4];
885 };
886
887 struct isl_surf_fill_state_info {
888 const struct isl_surf *surf;
889 const struct isl_view *view;
890
891 /**
892 * The address of the surface in GPU memory.
893 */
894 uint64_t address;
895
896 /**
897 * The Memory Object Control state for the filled surface state.
898 *
899 * The exact format of this value depends on hardware generation.
900 */
901 uint32_t mocs;
902
903 /**
904 * The auxilary surface or NULL if no auxilary surface is to be used.
905 */
906 const struct isl_surf *aux_surf;
907 enum isl_aux_usage aux_usage;
908 uint64_t aux_address;
909
910 /**
911 * The clear color for this surface
912 *
913 * Valid values depend on hardware generation.
914 */
915 union isl_color_value clear_color;
916 };
917
918 struct isl_buffer_fill_state_info {
919 /**
920 * The address of the surface in GPU memory.
921 */
922 uint64_t address;
923
924 /**
925 * The size of the buffer
926 */
927 uint64_t size;
928
929 /**
930 * The Memory Object Control state for the filled surface state.
931 *
932 * The exact format of this value depends on hardware generation.
933 */
934 uint32_t mocs;
935
936 /**
937 * The format to use in the surface state
938 *
939 * This may differ from the format of the actual isl_surf but have the
940 * same block size.
941 */
942 enum isl_format format;
943
944 uint32_t stride;
945 };
946
947 extern const struct isl_format_layout isl_format_layouts[];
948
949 void
950 isl_device_init(struct isl_device *dev,
951 const struct brw_device_info *info,
952 bool has_bit6_swizzling);
953
954 isl_sample_count_mask_t ATTRIBUTE_CONST
955 isl_device_get_sample_counts(struct isl_device *dev);
956
957 static inline const struct isl_format_layout * ATTRIBUTE_CONST
958 isl_format_get_layout(enum isl_format fmt)
959 {
960 return &isl_format_layouts[fmt];
961 }
962
963 static inline const char * ATTRIBUTE_CONST
964 isl_format_get_name(enum isl_format fmt)
965 {
966 return isl_format_layouts[fmt].name;
967 }
968
969 bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
970 enum isl_format format);
971 bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
972 enum isl_format format);
973 bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
974 enum isl_format format);
975 bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
976 enum isl_format format);
977 bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
978 enum isl_format format);
979 bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
980 enum isl_format format);
981
982 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
983 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
984 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
985 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
986 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
987 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
988
989 static inline bool
990 isl_format_has_normalized_channel(enum isl_format fmt)
991 {
992 return isl_format_has_unorm_channel(fmt) ||
993 isl_format_has_snorm_channel(fmt);
994 }
995
996 static inline bool
997 isl_format_has_float_channel(enum isl_format fmt)
998 {
999 return isl_format_has_ufloat_channel(fmt) ||
1000 isl_format_has_sfloat_channel(fmt);
1001 }
1002
1003 static inline bool
1004 isl_format_has_int_channel(enum isl_format fmt)
1005 {
1006 return isl_format_has_uint_channel(fmt) ||
1007 isl_format_has_sint_channel(fmt);
1008 }
1009
1010 unsigned isl_format_get_num_channels(enum isl_format fmt);
1011
1012 static inline bool
1013 isl_format_is_compressed(enum isl_format fmt)
1014 {
1015 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1016
1017 return fmtl->txc != ISL_TXC_NONE;
1018 }
1019
1020 static inline bool
1021 isl_format_has_bc_compression(enum isl_format fmt)
1022 {
1023 switch (isl_format_get_layout(fmt)->txc) {
1024 case ISL_TXC_DXT1:
1025 case ISL_TXC_DXT3:
1026 case ISL_TXC_DXT5:
1027 return true;
1028 case ISL_TXC_NONE:
1029 case ISL_TXC_FXT1:
1030 case ISL_TXC_RGTC1:
1031 case ISL_TXC_RGTC2:
1032 case ISL_TXC_BPTC:
1033 case ISL_TXC_ETC1:
1034 case ISL_TXC_ETC2:
1035 case ISL_TXC_ASTC:
1036 return false;
1037
1038 case ISL_TXC_HIZ:
1039 case ISL_TXC_MCS:
1040 case ISL_TXC_CCS:
1041 unreachable("Should not be called on an aux surface");
1042 }
1043
1044 unreachable("bad texture compression mode");
1045 return false;
1046 }
1047
1048 static inline bool
1049 isl_format_is_yuv(enum isl_format fmt)
1050 {
1051 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1052
1053 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1054 }
1055
1056 static inline bool
1057 isl_format_block_is_1x1x1(enum isl_format fmt)
1058 {
1059 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1060
1061 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1062 }
1063
1064 static inline bool
1065 isl_format_is_rgb(enum isl_format fmt)
1066 {
1067 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1068 isl_format_layouts[fmt].channels.g.bits > 0 &&
1069 isl_format_layouts[fmt].channels.b.bits > 0 &&
1070 isl_format_layouts[fmt].channels.a.bits == 0;
1071 }
1072
1073 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1074 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1075
1076 bool isl_is_storage_image_format(enum isl_format fmt);
1077
1078 enum isl_format
1079 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
1080 enum isl_format fmt);
1081
1082 /* Returns true if this hardware supports typed load/store on a format with
1083 * the same size as the given format.
1084 */
1085 bool
1086 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
1087 enum isl_format fmt);
1088
1089 static inline bool
1090 isl_tiling_is_any_y(enum isl_tiling tiling)
1091 {
1092 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1093 }
1094
1095 static inline bool
1096 isl_tiling_is_std_y(enum isl_tiling tiling)
1097 {
1098 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1099 }
1100
1101 bool
1102 isl_tiling_get_info(const struct isl_device *dev,
1103 enum isl_tiling tiling,
1104 uint32_t format_bpb,
1105 struct isl_tile_info *info);
1106 bool
1107 isl_surf_choose_tiling(const struct isl_device *dev,
1108 const struct isl_surf_init_info *restrict info,
1109 enum isl_tiling *tiling);
1110
1111 static inline bool
1112 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1113 {
1114 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1115 }
1116
1117 static inline bool
1118 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1119 {
1120 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1121 }
1122
1123 static inline bool
1124 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1125 {
1126 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1127 }
1128
1129 static inline bool
1130 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1131 {
1132 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1133 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1134 }
1135
1136 static inline bool
1137 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1138 {
1139 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1140 }
1141
1142 static inline bool
1143 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1144 {
1145 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1146 (info->format == ISL_FORMAT_R16_UNORM);
1147 }
1148
1149 static inline bool
1150 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1151 {
1152 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1153 (info->format == ISL_FORMAT_R32_FLOAT);
1154 }
1155
1156 static inline struct isl_extent2d
1157 isl_extent2d(uint32_t width, uint32_t height)
1158 {
1159 struct isl_extent2d e = { { 0 } };
1160
1161 e.width = width;
1162 e.height = height;
1163
1164 return e;
1165 }
1166
1167 static inline struct isl_extent3d
1168 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1169 {
1170 struct isl_extent3d e = { { 0 } };
1171
1172 e.width = width;
1173 e.height = height;
1174 e.depth = depth;
1175
1176 return e;
1177 }
1178
1179 static inline struct isl_extent4d
1180 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1181 uint32_t array_len)
1182 {
1183 struct isl_extent4d e = { { 0 } };
1184
1185 e.width = width;
1186 e.height = height;
1187 e.depth = depth;
1188 e.array_len = array_len;
1189
1190 return e;
1191 }
1192
1193 #define isl_surf_init(dev, surf, ...) \
1194 isl_surf_init_s((dev), (surf), \
1195 &(struct isl_surf_init_info) { __VA_ARGS__ });
1196
1197 bool
1198 isl_surf_init_s(const struct isl_device *dev,
1199 struct isl_surf *surf,
1200 const struct isl_surf_init_info *restrict info);
1201
1202 void
1203 isl_surf_get_tile_info(const struct isl_device *dev,
1204 const struct isl_surf *surf,
1205 struct isl_tile_info *tile_info);
1206
1207 #define isl_surf_fill_state(dev, state, ...) \
1208 isl_surf_fill_state_s((dev), (state), \
1209 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1210
1211 void
1212 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1213 const struct isl_surf_fill_state_info *restrict info);
1214
1215 #define isl_buffer_fill_state(dev, state, ...) \
1216 isl_buffer_fill_state_s((dev), (state), \
1217 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1218
1219 void
1220 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1221 const struct isl_buffer_fill_state_info *restrict info);
1222
1223 void
1224 isl_surf_fill_image_param(const struct isl_device *dev,
1225 struct brw_image_param *param,
1226 const struct isl_surf *surf,
1227 const struct isl_view *view);
1228
1229 void
1230 isl_buffer_fill_image_param(const struct isl_device *dev,
1231 struct brw_image_param *param,
1232 enum isl_format format,
1233 uint64_t size);
1234
1235 /**
1236 * Alignment of the upper-left sample of each subimage, in units of surface
1237 * elements.
1238 */
1239 static inline struct isl_extent3d
1240 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1241 {
1242 return surf->image_alignment_el;
1243 }
1244
1245 /**
1246 * Alignment of the upper-left sample of each subimage, in units of surface
1247 * samples.
1248 */
1249 static inline struct isl_extent3d
1250 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1251 {
1252 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1253
1254 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1255 fmtl->bh * surf->image_alignment_el.h,
1256 fmtl->bd * surf->image_alignment_el.d);
1257 }
1258
1259 /**
1260 * Pitch between vertically adjacent surface elements, in bytes.
1261 */
1262 static inline uint32_t
1263 isl_surf_get_row_pitch(const struct isl_surf *surf)
1264 {
1265 return surf->row_pitch;
1266 }
1267
1268 /**
1269 * Pitch between vertically adjacent surface elements, in units of surface elements.
1270 */
1271 static inline uint32_t
1272 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1273 {
1274 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1275
1276 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1277 return surf->row_pitch / (fmtl->bpb / 8);
1278 }
1279
1280 /**
1281 * Pitch between physical array slices, in rows of surface elements.
1282 */
1283 static inline uint32_t
1284 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1285 {
1286 return surf->array_pitch_el_rows;
1287 }
1288
1289 /**
1290 * Pitch between physical array slices, in units of surface elements.
1291 */
1292 static inline uint32_t
1293 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1294 {
1295 return isl_surf_get_array_pitch_el_rows(surf) *
1296 isl_surf_get_row_pitch_el(surf);
1297 }
1298
1299 /**
1300 * Pitch between physical array slices, in rows of surface samples.
1301 */
1302 static inline uint32_t
1303 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1304 {
1305 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1306 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1307 }
1308
1309 /**
1310 * Pitch between physical array slices, in bytes.
1311 */
1312 static inline uint32_t
1313 isl_surf_get_array_pitch(const struct isl_surf *surf)
1314 {
1315 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1316 }
1317
1318 /**
1319 * Calculate the offset, in units of surface elements, to a subimage in the
1320 * surface.
1321 *
1322 * @invariant level < surface levels
1323 * @invariant logical_array_layer < logical array length of surface
1324 * @invariant logical_z_offset_px < logical depth of surface at level
1325 */
1326 void
1327 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1328 uint32_t level,
1329 uint32_t logical_array_layer,
1330 uint32_t logical_z_offset_px,
1331 uint32_t *x_offset_el,
1332 uint32_t *y_offset_el);
1333
1334 /**
1335 * @brief Calculate the intratile offsets to a surface.
1336 *
1337 * In @a base_address_offset return the offset from the base of the surface to
1338 * the base address of the first tile of the subimage. In @a x_offset_B and
1339 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1340 * tile's base to the subimage's first surface element. The x and y offsets
1341 * are intratile offsets; that is, they do not exceed the boundary of the
1342 * surface's tiling format.
1343 */
1344 void
1345 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1346 enum isl_tiling tiling,
1347 uint8_t bs,
1348 uint32_t row_pitch,
1349 uint32_t total_x_offset_B,
1350 uint32_t total_y_offset_rows,
1351 uint32_t *base_address_offset,
1352 uint32_t *x_offset_B,
1353 uint32_t *y_offset_rows);
1354
1355 /**
1356 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1357 *
1358 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1359 * @pre surf->format must be a valid format for depth surfaces
1360 */
1361 uint32_t
1362 isl_surf_get_depth_format(const struct isl_device *dev,
1363 const struct isl_surf *surf);
1364
1365 #ifdef __cplusplus
1366 }
1367 #endif