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isl: Add the ISL_FORMAT_R32G32_FLOAT_LD format
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct brw_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #endif
63
64 #ifndef ISL_DEV_IS_HASWELL
65 /**
66 * @brief Get the hardware generation of isl_device.
67 *
68 * You can define this as a compile-time constant in the CFLAGS. For example,
69 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
70 */
71 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
72 #endif
73
74 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
75 /**
76 * You can define this as a compile-time constant in the CFLAGS. For example,
77 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
78 */
79 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
80 #endif
81
82 /**
83 * Hardware enumeration SURFACE_FORMAT.
84 *
85 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
86 * Enumerations: SURFACE_FORMAT.
87 */
88 enum isl_format {
89 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
90 ISL_FORMAT_R32G32B32A32_SINT = 1,
91 ISL_FORMAT_R32G32B32A32_UINT = 2,
92 ISL_FORMAT_R32G32B32A32_UNORM = 3,
93 ISL_FORMAT_R32G32B32A32_SNORM = 4,
94 ISL_FORMAT_R64G64_FLOAT = 5,
95 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
96 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
97 ISL_FORMAT_R32G32B32A32_USCALED = 8,
98 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
99 ISL_FORMAT_R64G64_PASSTHRU = 33,
100 ISL_FORMAT_R32G32B32_FLOAT = 64,
101 ISL_FORMAT_R32G32B32_SINT = 65,
102 ISL_FORMAT_R32G32B32_UINT = 66,
103 ISL_FORMAT_R32G32B32_UNORM = 67,
104 ISL_FORMAT_R32G32B32_SNORM = 68,
105 ISL_FORMAT_R32G32B32_SSCALED = 69,
106 ISL_FORMAT_R32G32B32_USCALED = 70,
107 ISL_FORMAT_R32G32B32_SFIXED = 80,
108 ISL_FORMAT_R16G16B16A16_UNORM = 128,
109 ISL_FORMAT_R16G16B16A16_SNORM = 129,
110 ISL_FORMAT_R16G16B16A16_SINT = 130,
111 ISL_FORMAT_R16G16B16A16_UINT = 131,
112 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
113 ISL_FORMAT_R32G32_FLOAT = 133,
114 ISL_FORMAT_R32G32_SINT = 134,
115 ISL_FORMAT_R32G32_UINT = 135,
116 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
117 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
118 ISL_FORMAT_L32A32_FLOAT = 138,
119 ISL_FORMAT_R32G32_UNORM = 139,
120 ISL_FORMAT_R32G32_SNORM = 140,
121 ISL_FORMAT_R64_FLOAT = 141,
122 ISL_FORMAT_R16G16B16X16_UNORM = 142,
123 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
124 ISL_FORMAT_A32X32_FLOAT = 144,
125 ISL_FORMAT_L32X32_FLOAT = 145,
126 ISL_FORMAT_I32X32_FLOAT = 146,
127 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
128 ISL_FORMAT_R16G16B16A16_USCALED = 148,
129 ISL_FORMAT_R32G32_SSCALED = 149,
130 ISL_FORMAT_R32G32_USCALED = 150,
131 ISL_FORMAT_R32G32_FLOAT_LD = 151,
132 ISL_FORMAT_R32G32_SFIXED = 160,
133 ISL_FORMAT_R64_PASSTHRU = 161,
134 ISL_FORMAT_B8G8R8A8_UNORM = 192,
135 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
136 ISL_FORMAT_R10G10B10A2_UNORM = 194,
137 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
138 ISL_FORMAT_R10G10B10A2_UINT = 196,
139 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
140 ISL_FORMAT_R8G8B8A8_UNORM = 199,
141 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
142 ISL_FORMAT_R8G8B8A8_SNORM = 201,
143 ISL_FORMAT_R8G8B8A8_SINT = 202,
144 ISL_FORMAT_R8G8B8A8_UINT = 203,
145 ISL_FORMAT_R16G16_UNORM = 204,
146 ISL_FORMAT_R16G16_SNORM = 205,
147 ISL_FORMAT_R16G16_SINT = 206,
148 ISL_FORMAT_R16G16_UINT = 207,
149 ISL_FORMAT_R16G16_FLOAT = 208,
150 ISL_FORMAT_B10G10R10A2_UNORM = 209,
151 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
152 ISL_FORMAT_R11G11B10_FLOAT = 211,
153 ISL_FORMAT_R32_SINT = 214,
154 ISL_FORMAT_R32_UINT = 215,
155 ISL_FORMAT_R32_FLOAT = 216,
156 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
157 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
158 ISL_FORMAT_L32_UNORM = 221,
159 ISL_FORMAT_A32_UNORM = 222,
160 ISL_FORMAT_L16A16_UNORM = 223,
161 ISL_FORMAT_I24X8_UNORM = 224,
162 ISL_FORMAT_L24X8_UNORM = 225,
163 ISL_FORMAT_A24X8_UNORM = 226,
164 ISL_FORMAT_I32_FLOAT = 227,
165 ISL_FORMAT_L32_FLOAT = 228,
166 ISL_FORMAT_A32_FLOAT = 229,
167 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
168 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
169 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
170 ISL_FORMAT_B8G8R8X8_UNORM = 233,
171 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
172 ISL_FORMAT_R8G8B8X8_UNORM = 235,
173 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
174 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
175 ISL_FORMAT_B10G10R10X2_UNORM = 238,
176 ISL_FORMAT_L16A16_FLOAT = 240,
177 ISL_FORMAT_R32_UNORM = 241,
178 ISL_FORMAT_R32_SNORM = 242,
179 ISL_FORMAT_R10G10B10X2_USCALED = 243,
180 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
181 ISL_FORMAT_R8G8B8A8_USCALED = 245,
182 ISL_FORMAT_R16G16_SSCALED = 246,
183 ISL_FORMAT_R16G16_USCALED = 247,
184 ISL_FORMAT_R32_SSCALED = 248,
185 ISL_FORMAT_R32_USCALED = 249,
186 ISL_FORMAT_B5G6R5_UNORM = 256,
187 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
188 ISL_FORMAT_B5G5R5A1_UNORM = 258,
189 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
190 ISL_FORMAT_B4G4R4A4_UNORM = 260,
191 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
192 ISL_FORMAT_R8G8_UNORM = 262,
193 ISL_FORMAT_R8G8_SNORM = 263,
194 ISL_FORMAT_R8G8_SINT = 264,
195 ISL_FORMAT_R8G8_UINT = 265,
196 ISL_FORMAT_R16_UNORM = 266,
197 ISL_FORMAT_R16_SNORM = 267,
198 ISL_FORMAT_R16_SINT = 268,
199 ISL_FORMAT_R16_UINT = 269,
200 ISL_FORMAT_R16_FLOAT = 270,
201 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
202 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
203 ISL_FORMAT_I16_UNORM = 273,
204 ISL_FORMAT_L16_UNORM = 274,
205 ISL_FORMAT_A16_UNORM = 275,
206 ISL_FORMAT_L8A8_UNORM = 276,
207 ISL_FORMAT_I16_FLOAT = 277,
208 ISL_FORMAT_L16_FLOAT = 278,
209 ISL_FORMAT_A16_FLOAT = 279,
210 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
211 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
212 ISL_FORMAT_B5G5R5X1_UNORM = 282,
213 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
214 ISL_FORMAT_R8G8_SSCALED = 284,
215 ISL_FORMAT_R8G8_USCALED = 285,
216 ISL_FORMAT_R16_SSCALED = 286,
217 ISL_FORMAT_R16_USCALED = 287,
218 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
219 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
220 ISL_FORMAT_A1B5G5R5_UNORM = 292,
221 ISL_FORMAT_A4B4G4R4_UNORM = 293,
222 ISL_FORMAT_L8A8_UINT = 294,
223 ISL_FORMAT_L8A8_SINT = 295,
224 ISL_FORMAT_R8_UNORM = 320,
225 ISL_FORMAT_R8_SNORM = 321,
226 ISL_FORMAT_R8_SINT = 322,
227 ISL_FORMAT_R8_UINT = 323,
228 ISL_FORMAT_A8_UNORM = 324,
229 ISL_FORMAT_I8_UNORM = 325,
230 ISL_FORMAT_L8_UNORM = 326,
231 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
232 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
233 ISL_FORMAT_R8_SSCALED = 329,
234 ISL_FORMAT_R8_USCALED = 330,
235 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
236 ISL_FORMAT_L8_UNORM_SRGB = 332,
237 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
238 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
239 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
240 ISL_FORMAT_Y8_UNORM = 336,
241 ISL_FORMAT_L8_UINT = 338,
242 ISL_FORMAT_L8_SINT = 339,
243 ISL_FORMAT_I8_UINT = 340,
244 ISL_FORMAT_I8_SINT = 341,
245 ISL_FORMAT_DXT1_RGB_SRGB = 384,
246 ISL_FORMAT_R1_UNORM = 385,
247 ISL_FORMAT_YCRCB_NORMAL = 386,
248 ISL_FORMAT_YCRCB_SWAPUVY = 387,
249 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
250 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
251 ISL_FORMAT_BC1_UNORM = 390,
252 ISL_FORMAT_BC2_UNORM = 391,
253 ISL_FORMAT_BC3_UNORM = 392,
254 ISL_FORMAT_BC4_UNORM = 393,
255 ISL_FORMAT_BC5_UNORM = 394,
256 ISL_FORMAT_BC1_UNORM_SRGB = 395,
257 ISL_FORMAT_BC2_UNORM_SRGB = 396,
258 ISL_FORMAT_BC3_UNORM_SRGB = 397,
259 ISL_FORMAT_MONO8 = 398,
260 ISL_FORMAT_YCRCB_SWAPUV = 399,
261 ISL_FORMAT_YCRCB_SWAPY = 400,
262 ISL_FORMAT_DXT1_RGB = 401,
263 ISL_FORMAT_FXT1 = 402,
264 ISL_FORMAT_R8G8B8_UNORM = 403,
265 ISL_FORMAT_R8G8B8_SNORM = 404,
266 ISL_FORMAT_R8G8B8_SSCALED = 405,
267 ISL_FORMAT_R8G8B8_USCALED = 406,
268 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
269 ISL_FORMAT_R64G64B64_FLOAT = 408,
270 ISL_FORMAT_BC4_SNORM = 409,
271 ISL_FORMAT_BC5_SNORM = 410,
272 ISL_FORMAT_R16G16B16_FLOAT = 411,
273 ISL_FORMAT_R16G16B16_UNORM = 412,
274 ISL_FORMAT_R16G16B16_SNORM = 413,
275 ISL_FORMAT_R16G16B16_SSCALED = 414,
276 ISL_FORMAT_R16G16B16_USCALED = 415,
277 ISL_FORMAT_BC6H_SF16 = 417,
278 ISL_FORMAT_BC7_UNORM = 418,
279 ISL_FORMAT_BC7_UNORM_SRGB = 419,
280 ISL_FORMAT_BC6H_UF16 = 420,
281 ISL_FORMAT_PLANAR_420_8 = 421,
282 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
283 ISL_FORMAT_ETC1_RGB8 = 425,
284 ISL_FORMAT_ETC2_RGB8 = 426,
285 ISL_FORMAT_EAC_R11 = 427,
286 ISL_FORMAT_EAC_RG11 = 428,
287 ISL_FORMAT_EAC_SIGNED_R11 = 429,
288 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
289 ISL_FORMAT_ETC2_SRGB8 = 431,
290 ISL_FORMAT_R16G16B16_UINT = 432,
291 ISL_FORMAT_R16G16B16_SINT = 433,
292 ISL_FORMAT_R32_SFIXED = 434,
293 ISL_FORMAT_R10G10B10A2_SNORM = 435,
294 ISL_FORMAT_R10G10B10A2_USCALED = 436,
295 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
296 ISL_FORMAT_R10G10B10A2_SINT = 438,
297 ISL_FORMAT_B10G10R10A2_SNORM = 439,
298 ISL_FORMAT_B10G10R10A2_USCALED = 440,
299 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
300 ISL_FORMAT_B10G10R10A2_UINT = 442,
301 ISL_FORMAT_B10G10R10A2_SINT = 443,
302 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
303 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
304 ISL_FORMAT_ETC2_RGB8_PTA = 448,
305 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
306 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
307 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
308 ISL_FORMAT_R8G8B8_UINT = 456,
309 ISL_FORMAT_R8G8B8_SINT = 457,
310 ISL_FORMAT_RAW = 511,
311 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
312 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
313 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
314 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
315 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
316 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
317 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
318 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
319 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
320 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
321 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
322 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
323 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
324 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
325 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
326 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
327 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
328 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
329 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
330 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
331 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
332 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
333 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
334 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
335 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
336 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
337 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
338 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
339
340 /* Hardware doesn't understand this out-of-band value */
341 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
342 };
343
344 /**
345 * Numerical base type for channels of isl_format.
346 */
347 enum isl_base_type {
348 ISL_VOID,
349 ISL_RAW,
350 ISL_UNORM,
351 ISL_SNORM,
352 ISL_UFLOAT,
353 ISL_SFLOAT,
354 ISL_UFIXED,
355 ISL_SFIXED,
356 ISL_UINT,
357 ISL_SINT,
358 ISL_USCALED,
359 ISL_SSCALED,
360 };
361
362 /**
363 * Colorspace of isl_format.
364 */
365 enum isl_colorspace {
366 ISL_COLORSPACE_NONE = 0,
367 ISL_COLORSPACE_LINEAR,
368 ISL_COLORSPACE_SRGB,
369 ISL_COLORSPACE_YUV,
370 };
371
372 /**
373 * Texture compression mode of isl_format.
374 */
375 enum isl_txc {
376 ISL_TXC_NONE = 0,
377 ISL_TXC_DXT1,
378 ISL_TXC_DXT3,
379 ISL_TXC_DXT5,
380 ISL_TXC_FXT1,
381 ISL_TXC_RGTC1,
382 ISL_TXC_RGTC2,
383 ISL_TXC_BPTC,
384 ISL_TXC_ETC1,
385 ISL_TXC_ETC2,
386 ISL_TXC_ASTC,
387 };
388
389 /**
390 * @brief Hardware tile mode
391 *
392 * WARNING: These values differ from the hardware enum values, which are
393 * unstable across hardware generations.
394 *
395 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
396 * clearly distinguish it from Yf and Ys.
397 */
398 enum isl_tiling {
399 ISL_TILING_LINEAR = 0,
400 ISL_TILING_W,
401 ISL_TILING_X,
402 ISL_TILING_Y0, /**< Legacy Y tiling */
403 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
404 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
405 };
406
407 /**
408 * @defgroup Tiling Flags
409 * @{
410 */
411 typedef uint32_t isl_tiling_flags_t;
412 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
413 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
414 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
415 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
416 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
417 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
418 #define ISL_TILING_ANY_MASK (~0u)
419 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
420
421 /** Any Y tiling, including legacy Y tiling. */
422 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
423 ISL_TILING_Yf_BIT | \
424 ISL_TILING_Ys_BIT)
425
426 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
427 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
428 ISL_TILING_Ys_BIT)
429 /** @} */
430
431 /**
432 * @brief Logical dimension of surface.
433 *
434 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
435 * as 2D array surfaces.
436 */
437 enum isl_surf_dim {
438 ISL_SURF_DIM_1D,
439 ISL_SURF_DIM_2D,
440 ISL_SURF_DIM_3D,
441 };
442
443 /**
444 * @brief Physical layout of the surface's dimensions.
445 */
446 enum isl_dim_layout {
447 /**
448 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
449 * 6.17.3: 2D Surfaces.
450 *
451 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
452 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
453 *
454 * One-dimensional surfaces are identical to 2D surfaces with height of
455 * one.
456 *
457 * @invariant isl_surf::phys_level0_sa::depth == 1
458 */
459 ISL_DIM_LAYOUT_GEN4_2D,
460
461 /**
462 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
463 * 6.17.5: 3D Surfaces.
464 *
465 * @invariant isl_surf::phys_level0_sa::array_len == 1
466 */
467 ISL_DIM_LAYOUT_GEN4_3D,
468
469 /**
470 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
471 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
472 */
473 ISL_DIM_LAYOUT_GEN9_1D,
474 };
475
476 /* TODO(chadv): Explain */
477 enum isl_array_pitch_span {
478 ISL_ARRAY_PITCH_SPAN_FULL,
479 ISL_ARRAY_PITCH_SPAN_COMPACT,
480 };
481
482 /**
483 * @defgroup Surface Usage
484 * @{
485 */
486 typedef uint64_t isl_surf_usage_flags_t;
487 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
488 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
489 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
490 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
491 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
492 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
493 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
494 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
495 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
496 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
497 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
498 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
499 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
500 /** @} */
501
502 /**
503 * @brief A channel select (also known as texture swizzle) value
504 */
505 enum isl_channel_select {
506 ISL_CHANNEL_SELECT_ZERO = 0,
507 ISL_CHANNEL_SELECT_ONE = 1,
508 ISL_CHANNEL_SELECT_RED = 4,
509 ISL_CHANNEL_SELECT_GREEN = 5,
510 ISL_CHANNEL_SELECT_BLUE = 6,
511 ISL_CHANNEL_SELECT_ALPHA = 7,
512 };
513
514 /**
515 * Identical to VkSampleCountFlagBits.
516 */
517 enum isl_sample_count {
518 ISL_SAMPLE_COUNT_1_BIT = 1u,
519 ISL_SAMPLE_COUNT_2_BIT = 2u,
520 ISL_SAMPLE_COUNT_4_BIT = 4u,
521 ISL_SAMPLE_COUNT_8_BIT = 8u,
522 ISL_SAMPLE_COUNT_16_BIT = 16u,
523 };
524 typedef uint32_t isl_sample_count_mask_t;
525
526 /**
527 * @brief Multisample Format
528 */
529 enum isl_msaa_layout {
530 /**
531 * @brief Suface is single-sampled.
532 */
533 ISL_MSAA_LAYOUT_NONE,
534
535 /**
536 * @brief [SNB+] Interleaved Multisample Format
537 *
538 * In this format, multiple samples are interleaved into each cacheline.
539 * In other words, the sample index is swizzled into the low 6 bits of the
540 * surface's virtual address space.
541 *
542 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
543 * and its pixel format is 32bpp. Then the first cacheline is arranged
544 * thus:
545 *
546 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
547 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
548 *
549 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
550 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
551 *
552 * The hardware docs refer to this format with multiple terms. In
553 * Sandybridge, this is the only multisample format; so no term is used.
554 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
555 * Multisample Surface). Later hardware docs additionally refer to this
556 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
557 * color surfaces).
558 *
559 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
560 * Surface Behavior".
561 *
562 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
563 * Multisampled Surfaces".
564 */
565 ISL_MSAA_LAYOUT_INTERLEAVED,
566
567 /**
568 * @brief [IVB+] Array Multisample Format
569 *
570 * In this format, the surface's physical layout resembles that of a
571 * 2D array surface.
572 *
573 * Suppose the multisample surface's logical extent is (w, h) and its
574 * sample count is N. Then surface's physical extent is the same as
575 * a singlesample 2D surface whose logical extent is (w, h) and array
576 * length is N. Array slice `i` contains the pixel values for sample
577 * index `i`.
578 *
579 * The Ivybridge docs refer to surfaces in this format as UMS
580 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
581 * Surface). The Broadwell docs additionally refer to this format as
582 * MSFMT_MSS (MSS=Multisample Surface Storage).
583 *
584 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
585 * Multisample Surfaces".
586 *
587 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
588 * Multisample Surfaces".
589 */
590 ISL_MSAA_LAYOUT_ARRAY,
591 };
592
593
594 struct isl_device {
595 const struct brw_device_info *info;
596 bool use_separate_stencil;
597 bool has_bit6_swizzling;
598 };
599
600 struct isl_extent2d {
601 union { uint32_t w, width; };
602 union { uint32_t h, height; };
603 };
604
605 struct isl_extent3d {
606 union { uint32_t w, width; };
607 union { uint32_t h, height; };
608 union { uint32_t d, depth; };
609 };
610
611 struct isl_extent4d {
612 union { uint32_t w, width; };
613 union { uint32_t h, height; };
614 union { uint32_t d, depth; };
615 union { uint32_t a, array_len; };
616 };
617
618 struct isl_channel_layout {
619 enum isl_base_type type;
620 uint8_t bits; /**< Size in bits */
621 };
622
623 /**
624 * Each format has 3D block extent (width, height, depth). The block extent of
625 * compressed formats is that of the format's compression block. For example,
626 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
627 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
628 * is (w=1, h=1, d=1).
629 */
630 struct isl_format_layout {
631 enum isl_format format;
632 const char *name;
633
634 uint8_t bs; /**< Block size, in bytes, rounded towards 0 */
635 uint8_t bw; /**< Block width, in pixels */
636 uint8_t bh; /**< Block height, in pixels */
637 uint8_t bd; /**< Block depth, in pixels */
638
639 struct {
640 struct isl_channel_layout r; /**< Red channel */
641 struct isl_channel_layout g; /**< Green channel */
642 struct isl_channel_layout b; /**< Blue channel */
643 struct isl_channel_layout a; /**< Alpha channel */
644 struct isl_channel_layout l; /**< Luminance channel */
645 struct isl_channel_layout i; /**< Intensity channel */
646 struct isl_channel_layout p; /**< Palette channel */
647 } channels;
648
649 enum isl_colorspace colorspace;
650 enum isl_txc txc;
651 };
652
653 struct isl_tile_info {
654 enum isl_tiling tiling;
655 uint32_t width; /**< in bytes */
656 uint32_t height; /**< in rows of memory */
657 uint32_t size; /**< in bytes */
658 };
659
660 /**
661 * @brief Input to surface initialization
662 *
663 * @invariant width >= 1
664 * @invariant height >= 1
665 * @invariant depth >= 1
666 * @invariant levels >= 1
667 * @invariant samples >= 1
668 * @invariant array_len >= 1
669 *
670 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
671 * @invariant if 2D then depth == 1
672 * @invariant if 3D then array_len == 1 and samples == 1
673 */
674 struct isl_surf_init_info {
675 enum isl_surf_dim dim;
676 enum isl_format format;
677
678 uint32_t width;
679 uint32_t height;
680 uint32_t depth;
681 uint32_t levels;
682 uint32_t array_len;
683 uint32_t samples;
684
685 /** Lower bound for isl_surf::alignment, in bytes. */
686 uint32_t min_alignment;
687
688 /** Lower bound for isl_surf::pitch, in bytes. */
689 uint32_t min_pitch;
690
691 isl_surf_usage_flags_t usage;
692
693 /** Flags that alter how ISL selects isl_surf::tiling. */
694 isl_tiling_flags_t tiling_flags;
695 };
696
697 struct isl_surf {
698 enum isl_surf_dim dim;
699 enum isl_dim_layout dim_layout;
700 enum isl_msaa_layout msaa_layout;
701 enum isl_tiling tiling;
702 enum isl_format format;
703
704 /**
705 * Alignment of the upper-left sample of each subimage, in units of surface
706 * elements.
707 */
708 struct isl_extent3d image_alignment_el;
709
710 /**
711 * Logical extent of the surface's base level, in units of pixels. This is
712 * identical to the extent defined in isl_surf_init_info.
713 */
714 struct isl_extent4d logical_level0_px;
715
716 /**
717 * Physical extent of the surface's base level, in units of physical
718 * surface samples and aligned to the format's compression block.
719 *
720 * Consider isl_dim_layout as an operator that transforms a logical surface
721 * layout to a physical surface layout. Then
722 *
723 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
724 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
725 */
726 struct isl_extent4d phys_level0_sa;
727
728 uint32_t levels;
729 uint32_t samples;
730
731 /** Total size of the surface, in bytes. */
732 uint32_t size;
733
734 /** Required alignment for the surface's base address. */
735 uint32_t alignment;
736
737 /**
738 * Pitch between vertically adjacent surface elements, in bytes.
739 */
740 uint32_t row_pitch;
741
742 /**
743 * Pitch between physical array slices, in rows of surface elements.
744 */
745 uint32_t array_pitch_el_rows;
746
747 enum isl_array_pitch_span array_pitch_span;
748
749 /** Copy of isl_surf_init_info::usage. */
750 isl_surf_usage_flags_t usage;
751 };
752
753 struct isl_view {
754 /**
755 * Indicates the usage of the particular view
756 *
757 * Normally, this is one bit. However, for a cube map texture, it
758 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
759 */
760 isl_surf_usage_flags_t usage;
761
762 /**
763 * The format to use in the view
764 *
765 * This may differ from the format of the actual isl_surf but must have
766 * the same block size.
767 */
768 enum isl_format format;
769
770 uint32_t base_level;
771 uint32_t levels;
772
773 /**
774 * Base array layer
775 *
776 * For cube maps, both base_array_layer and array_len should be
777 * specified in terms of 2-D layers and must be a multiple of 6.
778 */
779 uint32_t base_array_layer;
780 uint32_t array_len;
781
782 enum isl_channel_select channel_select[4];
783 };
784
785 union isl_color_value {
786 float f32[4];
787 uint32_t u32[4];
788 int32_t i32[4];
789 };
790
791 struct isl_surf_fill_state_info {
792 const struct isl_surf *surf;
793 const struct isl_view *view;
794
795 /**
796 * The address of the surface in GPU memory.
797 */
798 uint64_t address;
799
800 /**
801 * The Memory Object Control state for the filled surface state.
802 *
803 * The exact format of this value depends on hardware generation.
804 */
805 uint32_t mocs;
806
807 /**
808 * The clear color for this surface
809 *
810 * Valid values depend on hardware generation.
811 */
812 union isl_color_value clear_color;
813 };
814
815 struct isl_buffer_fill_state_info {
816 /**
817 * The address of the surface in GPU memory.
818 */
819 uint64_t address;
820
821 /**
822 * The size of the buffer
823 */
824 uint64_t size;
825
826 /**
827 * The Memory Object Control state for the filled surface state.
828 *
829 * The exact format of this value depends on hardware generation.
830 */
831 uint32_t mocs;
832
833 /**
834 * The format to use in the surface state
835 *
836 * This may differ from the format of the actual isl_surf but have the
837 * same block size.
838 */
839 enum isl_format format;
840
841 uint32_t stride;
842 };
843
844 extern const struct isl_format_layout isl_format_layouts[];
845
846 void
847 isl_device_init(struct isl_device *dev,
848 const struct brw_device_info *info,
849 bool has_bit6_swizzling);
850
851 isl_sample_count_mask_t ATTRIBUTE_CONST
852 isl_device_get_sample_counts(struct isl_device *dev);
853
854 static inline const struct isl_format_layout * ATTRIBUTE_CONST
855 isl_format_get_layout(enum isl_format fmt)
856 {
857 return &isl_format_layouts[fmt];
858 }
859
860 static inline const char * ATTRIBUTE_CONST
861 isl_format_get_name(enum isl_format fmt)
862 {
863 return isl_format_layouts[fmt].name;
864 }
865
866 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
867 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
868 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
869 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
870 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
871 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
872
873 static inline bool
874 isl_format_has_normalized_channel(enum isl_format fmt)
875 {
876 return isl_format_has_unorm_channel(fmt) ||
877 isl_format_has_snorm_channel(fmt);
878 }
879
880 static inline bool
881 isl_format_has_float_channel(enum isl_format fmt)
882 {
883 return isl_format_has_ufloat_channel(fmt) ||
884 isl_format_has_sfloat_channel(fmt);
885 }
886
887 static inline bool
888 isl_format_has_int_channel(enum isl_format fmt)
889 {
890 return isl_format_has_uint_channel(fmt) ||
891 isl_format_has_sint_channel(fmt);
892 }
893
894 unsigned isl_format_get_num_channels(enum isl_format fmt);
895
896 static inline bool
897 isl_format_is_compressed(enum isl_format fmt)
898 {
899 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
900
901 return fmtl->txc != ISL_TXC_NONE;
902 }
903
904 static inline bool
905 isl_format_has_bc_compression(enum isl_format fmt)
906 {
907 switch (isl_format_get_layout(fmt)->txc) {
908 case ISL_TXC_DXT1:
909 case ISL_TXC_DXT3:
910 case ISL_TXC_DXT5:
911 return true;
912 case ISL_TXC_NONE:
913 case ISL_TXC_FXT1:
914 case ISL_TXC_RGTC1:
915 case ISL_TXC_RGTC2:
916 case ISL_TXC_BPTC:
917 case ISL_TXC_ETC1:
918 case ISL_TXC_ETC2:
919 case ISL_TXC_ASTC:
920 return false;
921 }
922
923 unreachable("bad texture compression mode");
924 return false;
925 }
926
927 static inline bool
928 isl_format_is_yuv(enum isl_format fmt)
929 {
930 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
931
932 return fmtl->colorspace == ISL_COLORSPACE_YUV;
933 }
934
935 static inline bool
936 isl_format_block_is_1x1x1(enum isl_format fmt)
937 {
938 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
939
940 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
941 }
942
943 static inline bool
944 isl_format_is_rgb(enum isl_format fmt)
945 {
946 return isl_format_layouts[fmt].channels.r.bits > 0 &&
947 isl_format_layouts[fmt].channels.g.bits > 0 &&
948 isl_format_layouts[fmt].channels.b.bits > 0 &&
949 isl_format_layouts[fmt].channels.a.bits == 0;
950 }
951
952 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
953 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
954
955 bool isl_is_storage_image_format(enum isl_format fmt);
956
957 enum isl_format
958 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
959 enum isl_format fmt);
960
961 /* Returns true if this hardware supports typed load/store on a format with
962 * the same size as the given format.
963 */
964 bool
965 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
966 enum isl_format fmt);
967
968 static inline bool
969 isl_tiling_is_any_y(enum isl_tiling tiling)
970 {
971 return (1u << tiling) & ISL_TILING_ANY_MASK;
972 }
973
974 static inline bool
975 isl_tiling_is_std_y(enum isl_tiling tiling)
976 {
977 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
978 }
979
980 bool
981 isl_tiling_get_info(const struct isl_device *dev,
982 enum isl_tiling tiling,
983 uint32_t format_block_size,
984 struct isl_tile_info *info);
985
986 void
987 isl_tiling_get_extent(const struct isl_device *dev,
988 enum isl_tiling tiling,
989 uint32_t format_block_size,
990 struct isl_extent2d *e);
991 bool
992 isl_surf_choose_tiling(const struct isl_device *dev,
993 const struct isl_surf_init_info *restrict info,
994 enum isl_tiling *tiling);
995
996 static inline bool
997 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
998 {
999 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1000 }
1001
1002 static inline bool
1003 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1004 {
1005 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1006 }
1007
1008 static inline bool
1009 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1010 {
1011 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1012 }
1013
1014 static inline bool
1015 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1016 {
1017 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1018 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1019 }
1020
1021 static inline bool
1022 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1023 {
1024 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1025 }
1026
1027 static inline bool
1028 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1029 {
1030 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1031 (info->format == ISL_FORMAT_R16_UNORM);
1032 }
1033
1034 static inline bool
1035 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1036 {
1037 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1038 (info->format == ISL_FORMAT_R32_FLOAT);
1039 }
1040
1041 static inline struct isl_extent2d
1042 isl_extent2d(uint32_t width, uint32_t height)
1043 {
1044 struct isl_extent2d e = { { 0 } };
1045
1046 e.width = width;
1047 e.height = height;
1048
1049 return e;
1050 }
1051
1052 static inline struct isl_extent3d
1053 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1054 {
1055 struct isl_extent3d e = { { 0 } };
1056
1057 e.width = width;
1058 e.height = height;
1059 e.depth = depth;
1060
1061 return e;
1062 }
1063
1064 static inline struct isl_extent4d
1065 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1066 uint32_t array_len)
1067 {
1068 struct isl_extent4d e = { { 0 } };
1069
1070 e.width = width;
1071 e.height = height;
1072 e.depth = depth;
1073 e.array_len = array_len;
1074
1075 return e;
1076 }
1077
1078 #define isl_surf_init(dev, surf, ...) \
1079 isl_surf_init_s((dev), (surf), \
1080 &(struct isl_surf_init_info) { __VA_ARGS__ });
1081
1082 bool
1083 isl_surf_init_s(const struct isl_device *dev,
1084 struct isl_surf *surf,
1085 const struct isl_surf_init_info *restrict info);
1086
1087 void
1088 isl_surf_get_tile_info(const struct isl_device *dev,
1089 const struct isl_surf *surf,
1090 struct isl_tile_info *tile_info);
1091
1092 #define isl_surf_fill_state(dev, state, ...) \
1093 isl_surf_fill_state_s((dev), (state), \
1094 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1095
1096 void
1097 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1098 const struct isl_surf_fill_state_info *restrict info);
1099
1100 #define isl_buffer_fill_state(dev, state, ...) \
1101 isl_buffer_fill_state_s((dev), (state), \
1102 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1103
1104 void
1105 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1106 const struct isl_buffer_fill_state_info *restrict info);
1107
1108 void
1109 isl_surf_fill_image_param(const struct isl_device *dev,
1110 struct brw_image_param *param,
1111 const struct isl_surf *surf,
1112 const struct isl_view *view);
1113
1114 void
1115 isl_buffer_fill_image_param(const struct isl_device *dev,
1116 struct brw_image_param *param,
1117 enum isl_format format,
1118 uint64_t size);
1119
1120 /**
1121 * Alignment of the upper-left sample of each subimage, in units of surface
1122 * elements.
1123 */
1124 static inline struct isl_extent3d
1125 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1126 {
1127 return surf->image_alignment_el;
1128 }
1129
1130 /**
1131 * Alignment of the upper-left sample of each subimage, in units of surface
1132 * samples.
1133 */
1134 static inline struct isl_extent3d
1135 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1136 {
1137 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1138
1139 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1140 fmtl->bh * surf->image_alignment_el.h,
1141 fmtl->bd * surf->image_alignment_el.d);
1142 }
1143
1144 /**
1145 * Pitch between vertically adjacent surface elements, in bytes.
1146 */
1147 static inline uint32_t
1148 isl_surf_get_row_pitch(const struct isl_surf *surf)
1149 {
1150 return surf->row_pitch;
1151 }
1152
1153 /**
1154 * Pitch between vertically adjacent surface elements, in units of surface elements.
1155 */
1156 static inline uint32_t
1157 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1158 {
1159 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1160
1161 assert(surf->row_pitch % fmtl->bs == 0);
1162 return surf->row_pitch / fmtl->bs;
1163 }
1164
1165 /**
1166 * Pitch between physical array slices, in rows of surface elements.
1167 */
1168 static inline uint32_t
1169 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1170 {
1171 return surf->array_pitch_el_rows;
1172 }
1173
1174 /**
1175 * Pitch between physical array slices, in units of surface elements.
1176 */
1177 static inline uint32_t
1178 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1179 {
1180 return isl_surf_get_array_pitch_el_rows(surf) *
1181 isl_surf_get_row_pitch_el(surf);
1182 }
1183
1184 /**
1185 * Pitch between physical array slices, in rows of surface samples.
1186 */
1187 static inline uint32_t
1188 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1189 {
1190 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1191 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1192 }
1193
1194 /**
1195 * Pitch between physical array slices, in bytes.
1196 */
1197 static inline uint32_t
1198 isl_surf_get_array_pitch(const struct isl_surf *surf)
1199 {
1200 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1201 }
1202
1203 /**
1204 * Calculate the offset, in units of surface elements, to a subimage in the
1205 * surface.
1206 *
1207 * @invariant level < surface levels
1208 * @invariant logical_array_layer < logical array length of surface
1209 * @invariant logical_z_offset_px < logical depth of surface at level
1210 */
1211 void
1212 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1213 uint32_t level,
1214 uint32_t logical_array_layer,
1215 uint32_t logical_z_offset_px,
1216 uint32_t *x_offset_el,
1217 uint32_t *y_offset_el);
1218
1219 /**
1220 * @brief Calculate the intratile offsets to a surface.
1221 *
1222 * In @a base_address_offset return the offset from the base of the surface to
1223 * the base address of the first tile of the subimage. In @a x_offset_B and
1224 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1225 * tile's base to the subimage's first surface element. The x and y offsets
1226 * are intratile offsets; that is, they do not exceed the boundary of the
1227 * surface's tiling format.
1228 */
1229 void
1230 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1231 enum isl_tiling tiling,
1232 uint8_t bs,
1233 uint32_t row_pitch,
1234 uint32_t total_x_offset_B,
1235 uint32_t total_y_offset_rows,
1236 uint32_t *base_address_offset,
1237 uint32_t *x_offset_B,
1238 uint32_t *y_offset_rows);
1239
1240 /**
1241 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1242 *
1243 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1244 * @pre surf->format must be a valid format for depth surfaces
1245 */
1246 uint32_t
1247 isl_surf_get_depth_format(const struct isl_device *dev,
1248 const struct isl_surf *surf);
1249
1250 #ifdef __cplusplus
1251 }
1252 #endif