2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
45 #include "c99_compat.h"
46 #include "util/macros.h"
52 struct gen_device_info
;
53 struct brw_image_param
;
57 * @brief Get the hardware generation of isl_device.
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
73 #ifndef ISL_DEV_IS_HASWELL
75 * @brief Get the hardware generation of isl_device.
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 * Hardware enumeration SURFACE_FORMAT.
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
106 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
107 ISL_FORMAT_R32G32B32A32_SINT
= 1,
108 ISL_FORMAT_R32G32B32A32_UINT
= 2,
109 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
110 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
111 ISL_FORMAT_R64G64_FLOAT
= 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
114 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
116 ISL_FORMAT_R64G64_PASSTHRU
= 33,
117 ISL_FORMAT_R32G32B32_FLOAT
= 64,
118 ISL_FORMAT_R32G32B32_SINT
= 65,
119 ISL_FORMAT_R32G32B32_UINT
= 66,
120 ISL_FORMAT_R32G32B32_UNORM
= 67,
121 ISL_FORMAT_R32G32B32_SNORM
= 68,
122 ISL_FORMAT_R32G32B32_SSCALED
= 69,
123 ISL_FORMAT_R32G32B32_USCALED
= 70,
124 ISL_FORMAT_R32G32B32_SFIXED
= 80,
125 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
126 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
127 ISL_FORMAT_R16G16B16A16_SINT
= 130,
128 ISL_FORMAT_R16G16B16A16_UINT
= 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
130 ISL_FORMAT_R32G32_FLOAT
= 133,
131 ISL_FORMAT_R32G32_SINT
= 134,
132 ISL_FORMAT_R32G32_UINT
= 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
135 ISL_FORMAT_L32A32_FLOAT
= 138,
136 ISL_FORMAT_R32G32_UNORM
= 139,
137 ISL_FORMAT_R32G32_SNORM
= 140,
138 ISL_FORMAT_R64_FLOAT
= 141,
139 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
141 ISL_FORMAT_A32X32_FLOAT
= 144,
142 ISL_FORMAT_L32X32_FLOAT
= 145,
143 ISL_FORMAT_I32X32_FLOAT
= 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
145 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
146 ISL_FORMAT_R32G32_SSCALED
= 149,
147 ISL_FORMAT_R32G32_USCALED
= 150,
148 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
149 ISL_FORMAT_R32G32_SFIXED
= 160,
150 ISL_FORMAT_R64_PASSTHRU
= 161,
151 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
153 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
155 ISL_FORMAT_R10G10B10A2_UINT
= 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
157 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
159 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
160 ISL_FORMAT_R8G8B8A8_SINT
= 202,
161 ISL_FORMAT_R8G8B8A8_UINT
= 203,
162 ISL_FORMAT_R16G16_UNORM
= 204,
163 ISL_FORMAT_R16G16_SNORM
= 205,
164 ISL_FORMAT_R16G16_SINT
= 206,
165 ISL_FORMAT_R16G16_UINT
= 207,
166 ISL_FORMAT_R16G16_FLOAT
= 208,
167 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
169 ISL_FORMAT_R11G11B10_FLOAT
= 211,
170 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM
= 213,
171 ISL_FORMAT_R32_SINT
= 214,
172 ISL_FORMAT_R32_UINT
= 215,
173 ISL_FORMAT_R32_FLOAT
= 216,
174 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
175 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
176 ISL_FORMAT_L32_UNORM
= 221,
177 ISL_FORMAT_A32_UNORM
= 222,
178 ISL_FORMAT_L16A16_UNORM
= 223,
179 ISL_FORMAT_I24X8_UNORM
= 224,
180 ISL_FORMAT_L24X8_UNORM
= 225,
181 ISL_FORMAT_A24X8_UNORM
= 226,
182 ISL_FORMAT_I32_FLOAT
= 227,
183 ISL_FORMAT_L32_FLOAT
= 228,
184 ISL_FORMAT_A32_FLOAT
= 229,
185 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
186 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
187 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
188 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
189 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
190 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
191 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
192 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
193 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
194 ISL_FORMAT_L16A16_FLOAT
= 240,
195 ISL_FORMAT_R32_UNORM
= 241,
196 ISL_FORMAT_R32_SNORM
= 242,
197 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
198 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
199 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
200 ISL_FORMAT_R16G16_SSCALED
= 246,
201 ISL_FORMAT_R16G16_USCALED
= 247,
202 ISL_FORMAT_R32_SSCALED
= 248,
203 ISL_FORMAT_R32_USCALED
= 249,
204 ISL_FORMAT_B5G6R5_UNORM
= 256,
205 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
206 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
207 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
208 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
209 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
210 ISL_FORMAT_R8G8_UNORM
= 262,
211 ISL_FORMAT_R8G8_SNORM
= 263,
212 ISL_FORMAT_R8G8_SINT
= 264,
213 ISL_FORMAT_R8G8_UINT
= 265,
214 ISL_FORMAT_R16_UNORM
= 266,
215 ISL_FORMAT_R16_SNORM
= 267,
216 ISL_FORMAT_R16_SINT
= 268,
217 ISL_FORMAT_R16_UINT
= 269,
218 ISL_FORMAT_R16_FLOAT
= 270,
219 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
220 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
221 ISL_FORMAT_I16_UNORM
= 273,
222 ISL_FORMAT_L16_UNORM
= 274,
223 ISL_FORMAT_A16_UNORM
= 275,
224 ISL_FORMAT_L8A8_UNORM
= 276,
225 ISL_FORMAT_I16_FLOAT
= 277,
226 ISL_FORMAT_L16_FLOAT
= 278,
227 ISL_FORMAT_A16_FLOAT
= 279,
228 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
229 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
230 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
231 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
232 ISL_FORMAT_R8G8_SSCALED
= 284,
233 ISL_FORMAT_R8G8_USCALED
= 285,
234 ISL_FORMAT_R16_SSCALED
= 286,
235 ISL_FORMAT_R16_USCALED
= 287,
236 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
237 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
238 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
239 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
240 ISL_FORMAT_L8A8_UINT
= 294,
241 ISL_FORMAT_L8A8_SINT
= 295,
242 ISL_FORMAT_R8_UNORM
= 320,
243 ISL_FORMAT_R8_SNORM
= 321,
244 ISL_FORMAT_R8_SINT
= 322,
245 ISL_FORMAT_R8_UINT
= 323,
246 ISL_FORMAT_A8_UNORM
= 324,
247 ISL_FORMAT_I8_UNORM
= 325,
248 ISL_FORMAT_L8_UNORM
= 326,
249 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
250 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
251 ISL_FORMAT_R8_SSCALED
= 329,
252 ISL_FORMAT_R8_USCALED
= 330,
253 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
254 ISL_FORMAT_L8_UNORM_SRGB
= 332,
255 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
256 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
257 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
258 ISL_FORMAT_Y8_UNORM
= 336,
259 ISL_FORMAT_L8_UINT
= 338,
260 ISL_FORMAT_L8_SINT
= 339,
261 ISL_FORMAT_I8_UINT
= 340,
262 ISL_FORMAT_I8_SINT
= 341,
263 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
264 ISL_FORMAT_R1_UNORM
= 385,
265 ISL_FORMAT_YCRCB_NORMAL
= 386,
266 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
267 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
268 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
269 ISL_FORMAT_BC1_UNORM
= 390,
270 ISL_FORMAT_BC2_UNORM
= 391,
271 ISL_FORMAT_BC3_UNORM
= 392,
272 ISL_FORMAT_BC4_UNORM
= 393,
273 ISL_FORMAT_BC5_UNORM
= 394,
274 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
275 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
276 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
277 ISL_FORMAT_MONO8
= 398,
278 ISL_FORMAT_YCRCB_SWAPUV
= 399,
279 ISL_FORMAT_YCRCB_SWAPY
= 400,
280 ISL_FORMAT_DXT1_RGB
= 401,
281 ISL_FORMAT_FXT1
= 402,
282 ISL_FORMAT_R8G8B8_UNORM
= 403,
283 ISL_FORMAT_R8G8B8_SNORM
= 404,
284 ISL_FORMAT_R8G8B8_SSCALED
= 405,
285 ISL_FORMAT_R8G8B8_USCALED
= 406,
286 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
287 ISL_FORMAT_R64G64B64_FLOAT
= 408,
288 ISL_FORMAT_BC4_SNORM
= 409,
289 ISL_FORMAT_BC5_SNORM
= 410,
290 ISL_FORMAT_R16G16B16_FLOAT
= 411,
291 ISL_FORMAT_R16G16B16_UNORM
= 412,
292 ISL_FORMAT_R16G16B16_SNORM
= 413,
293 ISL_FORMAT_R16G16B16_SSCALED
= 414,
294 ISL_FORMAT_R16G16B16_USCALED
= 415,
295 ISL_FORMAT_BC6H_SF16
= 417,
296 ISL_FORMAT_BC7_UNORM
= 418,
297 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
298 ISL_FORMAT_BC6H_UF16
= 420,
299 ISL_FORMAT_PLANAR_420_8
= 421,
300 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
301 ISL_FORMAT_ETC1_RGB8
= 425,
302 ISL_FORMAT_ETC2_RGB8
= 426,
303 ISL_FORMAT_EAC_R11
= 427,
304 ISL_FORMAT_EAC_RG11
= 428,
305 ISL_FORMAT_EAC_SIGNED_R11
= 429,
306 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
307 ISL_FORMAT_ETC2_SRGB8
= 431,
308 ISL_FORMAT_R16G16B16_UINT
= 432,
309 ISL_FORMAT_R16G16B16_SINT
= 433,
310 ISL_FORMAT_R32_SFIXED
= 434,
311 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
312 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
313 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
314 ISL_FORMAT_R10G10B10A2_SINT
= 438,
315 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
316 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
317 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
318 ISL_FORMAT_B10G10R10A2_UINT
= 442,
319 ISL_FORMAT_B10G10R10A2_SINT
= 443,
320 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
321 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
322 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
323 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
324 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
325 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
326 ISL_FORMAT_R8G8B8_UINT
= 456,
327 ISL_FORMAT_R8G8B8_SINT
= 457,
328 ISL_FORMAT_RAW
= 511,
329 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
330 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
331 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
332 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
333 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
334 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
335 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
336 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
337 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
338 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
339 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
340 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
341 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
342 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
343 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
344 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
345 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
346 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
347 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
348 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
349 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
350 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
351 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
352 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
353 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
354 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
355 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
356 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
357 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16
= 832,
358 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16
= 840,
359 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16
= 841,
360 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16
= 849,
361 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16
= 850,
362 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16
= 865,
363 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16
= 866,
364 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16
= 868,
365 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16
= 881,
366 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16
= 882,
367 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16
= 884,
368 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16
= 886,
369 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16
= 894,
370 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16
= 895,
372 /* The formats that follow are internal to ISL and as such don't have an
373 * explicit number. We'll just let the C compiler assign it for us. Any
374 * actual hardware formats *must* come before these in the list.
377 /* Formats for auxiliary surfaces */
383 ISL_FORMAT_GEN7_CCS_32BPP_X
,
384 ISL_FORMAT_GEN7_CCS_64BPP_X
,
385 ISL_FORMAT_GEN7_CCS_128BPP_X
,
386 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
387 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
388 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
389 ISL_FORMAT_GEN9_CCS_32BPP
,
390 ISL_FORMAT_GEN9_CCS_64BPP
,
391 ISL_FORMAT_GEN9_CCS_128BPP
,
392 ISL_FORMAT_GEN12_CCS_8BPP_Y0
,
393 ISL_FORMAT_GEN12_CCS_16BPP_Y0
,
394 ISL_FORMAT_GEN12_CCS_32BPP_Y0
,
395 ISL_FORMAT_GEN12_CCS_64BPP_Y0
,
396 ISL_FORMAT_GEN12_CCS_128BPP_Y0
,
398 /* An upper bound on the supported format enumerations */
401 /* Hardware doesn't understand this out-of-band value */
402 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
406 * Numerical base type for channels of isl_format.
424 * Colorspace of isl_format.
426 enum isl_colorspace
{
427 ISL_COLORSPACE_NONE
= 0,
428 ISL_COLORSPACE_LINEAR
,
434 * Texture compression mode of isl_format.
449 /* Used for auxiliary surface formats */
456 * @brief Hardware tile mode
458 * WARNING: These values differ from the hardware enum values, which are
459 * unstable across hardware generations.
461 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
462 * clearly distinguish it from Yf and Ys.
465 ISL_TILING_LINEAR
= 0,
468 ISL_TILING_Y0
, /**< Legacy Y tiling */
469 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
470 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
471 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
472 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
473 ISL_TILING_GEN12_CCS
, /**< Tiling format for Gen12 CCS surfaces */
477 * @defgroup Tiling Flags
480 typedef uint32_t isl_tiling_flags_t
;
481 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
482 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
483 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
484 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
485 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
486 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
487 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
488 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
489 #define ISL_TILING_GEN12_CCS_BIT (1u << ISL_TILING_GEN12_CCS)
490 #define ISL_TILING_ANY_MASK (~0u)
491 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
493 /** Any Y tiling, including legacy Y tiling. */
494 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
495 ISL_TILING_Yf_BIT | \
498 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
499 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
504 * @brief Logical dimension of surface.
506 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
507 * as 2D array surfaces.
516 * @brief Physical layout of the surface's dimensions.
518 enum isl_dim_layout
{
520 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
521 * 6.17.3: 2D Surfaces.
523 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
524 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
526 * One-dimensional surfaces are identical to 2D surfaces with height of
529 * @invariant isl_surf::phys_level0_sa::depth == 1
531 ISL_DIM_LAYOUT_GEN4_2D
,
534 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
535 * 6.17.5: 3D Surfaces.
537 * @invariant isl_surf::phys_level0_sa::array_len == 1
539 ISL_DIM_LAYOUT_GEN4_3D
,
542 * Special layout used for HiZ and stencil on Sandy Bridge to work around
543 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
544 * work the same as on gen7+ except that they don't technically support
545 * mipmapping. That does not, however, stop us from doing it. As far as
546 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
547 * single miplevel 2D (possibly array) image. The dimensions of that image
550 * In order to implement HiZ and stencil on Sandy Bridge, we create one
551 * full-sized 2D (possibly array) image for every LOD with every image
552 * aligned to a page boundary. When the surface is used with the stencil
553 * or HiZ hardware, we manually offset to the image for the given LOD.
555 * As a memory saving measure, we pretend that the width of each miplevel
556 * is minified and we place LOD1 and above below LOD0 but horizontally
557 * adjacent to each other. When considered as full-sized images, LOD1 and
558 * above technically overlap. However, since we only write to part of that
559 * image, the hardware will never notice the overlap.
561 * This layout looks something like this:
579 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
,
582 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
583 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
585 ISL_DIM_LAYOUT_GEN9_1D
,
589 /** No Auxiliary surface is used */
592 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
595 /** The auxiliary surface is an MCS
597 * @invariant isl_surf::samples > 1
601 /** The auxiliary surface is a fast-clear-only compression surface
603 * @invariant isl_surf::samples == 1
607 /** The auxiliary surface provides full lossless color compression
609 * @invariant isl_surf::samples == 1
613 /** The auxiliary surface provides full lossless media color compression
615 * @invariant isl_surf::samples == 1
619 /** The auxiliary surface is a HiZ surface and CCS is also enabled */
620 ISL_AUX_USAGE_HIZ_CCS
,
622 /** The auxiliary surface is an MCS and CCS is also enabled
624 * @invariant isl_surf::samples > 1
626 ISL_AUX_USAGE_MCS_CCS
,
630 * Enum for keeping track of the state an auxiliary compressed surface.
632 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
633 * given slice (lod + array layer) can be in one of the six states described
634 * by this enum. Draw and resolve operations may cause the slice to change
635 * from one state to another. The six valid states are:
637 * 1) Clear: In this state, each block in the auxiliary surface contains a
638 * magic value that indicates that the block is in the clear state. If
639 * a block is in the clear state, it's values in the primary surface are
640 * ignored and the color of the samples in the block is taken either the
641 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
642 * depth. Since neither the primary surface nor the auxiliary surface
643 * contains the clear value, the surface can be cleared to a different
644 * color by simply changing the clear color without modifying either
647 * 2) Partial Clear: In this state, each block in the auxiliary surface
648 * contains either the magic clear or pass-through value. See Clear and
649 * Pass-through for more details.
651 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
652 * nor the primary surface has a complete representation of the data.
653 * Instead, both surfaces must be used together or else rendering
654 * corruption may occur. Depending on the auxiliary compression format
655 * and the data, any given block in the primary surface may contain all,
656 * some, or none of the data required to reconstruct the actual sample
657 * values. Blocks may also be in the clear state (see Clear) and have
658 * their value taken from outside the surface.
660 * 4) Compressed w/o Clear: This state is identical to the state above
661 * except that no blocks are in the clear state. In this state, all of
662 * the data required to reconstruct the final sample values is contained
663 * in the auxiliary and primary surface and the clear value is not
666 * 5) Resolved: In this state, the primary surface contains 100% of the
667 * data. The auxiliary surface is also valid so the surface can be
668 * validly used with or without aux enabled. The auxiliary surface may,
669 * however, contain non-trivial data and any update to the primary
670 * surface with aux disabled will cause the two to get out of sync.
672 * 6) Pass-through: In this state, the primary surface contains 100% of the
673 * data and every block in the auxiliary surface contains a magic value
674 * which indicates that the auxiliary surface should be ignored and the
675 * only the primary surface should be considered. Updating the primary
676 * surface without aux works fine and can be done repeatedly in this
677 * mode. Writing to a surface in pass-through mode with aux enabled may
678 * cause the auxiliary buffer to contain non-trivial data and no longer
679 * be in the pass-through state.
681 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
682 * data and the auxiliary surface is completely bogus. Any attempt to
683 * use the auxiliary surface is liable to result in rendering
684 * corruption. The only thing that one can do to re-enable aux once
685 * this state is reached is to use an ambiguate pass to transition into
686 * the pass-through state.
688 * Drawing with or without aux enabled may implicitly cause the surface to
689 * transition between these states. There are also four types of auxiliary
690 * compression operations which cause an explicit transition which are
691 * described by the isl_aux_op enum below.
693 * Not all operations are valid or useful in all states. The diagram below
694 * contains a complete description of the states and all valid and useful
695 * transitions except clear.
700 * | +-------------+ Draw w/ Aux +-------------+
701 * +------>| Compressed |<-------------------| Clear |
702 * | w/ Clear |----->----+ | |
703 * +-------------+ | +-------------+
706 * | | +------<-----+ | Draw w/
708 * | | Full | | +----------+
709 * Partial | | Resolve | \|/ | |
710 * Resolve | | | +-------------+ |
711 * | | | | Partial |<------+
712 * | | | | Clear |<----------+
713 * | | | +-------------+ |
715 * | | +------>---------+ Full |
717 * Draw w/ aux | | Partial Fast Clear | |
718 * +----------+ | +--------------------------+ | |
720 * | +-------------+ Full Resolve +-------------+ |
721 * +------>| Compressed |------------------->| Resolved | |
722 * | w/o Clear |<-------------------| | |
723 * +-------------+ Draw w/ Aux +-------------+ |
726 * | w/ Aux | | w/o Aux |
728 * | +--------------------------+ | |
729 * Draw w/o Aux | | | Draw w/o Aux |
730 * +----------+ | | | +----------+ |
731 * | | | \|/ \|/ | | |
732 * | +-------------+ Ambiguate +-------------+ | |
733 * +------>| Pass- |<-------------------| Aux |<------+ |
734 * +------>| through | | Invalid | |
735 * | +-------------+ +-------------+ |
737 * +----------+ +-----------------------------------------------------+
738 * Draw w/ Partial Fast Clear
742 * While the above general theory applies to all forms of auxiliary
743 * compression on Intel hardware, not all states and operations are available
744 * on all compression types. However, each of the auxiliary states and
745 * operations can be fairly easily mapped onto the above diagram:
747 * HiZ: Hierarchical depth compression is capable of being in any of the
748 * states above. Hardware provides three HiZ operations: "Depth
749 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
750 * Clear", "Full Resolve", and "Ambiguate" respectively. The
751 * hardware provides no HiZ partial resolve operation so the only way
752 * to get into the "Compressed w/o Clear" state is to render with HiZ
753 * when the surface is in the resolved or pass-through states.
755 * MCS: Multisample compression is technically capable of being in any of
756 * the states above except that most of them aren't useful. Both the
757 * render engine and the sampler support MCS compression and, apart
758 * from clear color, MCS is format-unaware so we leave the surface
759 * compressed 100% of the time. The hardware provides no MCS
762 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
763 * the simplest forms of compression since they don't do anything
764 * beyond clear color tracking. They really only support three of
765 * the six states: Clear, Partial Clear, and Pass-through. The
766 * only CCS_D operation is "Resolve" which maps to a full resolve
767 * followed by an ambiguate.
769 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
770 * is capable of being in almost all of the above states. THe only
771 * exception is that it does not have separate resolved and pass-
772 * through states. Instead, the CCS_E full resolve operation does
773 * both a resolve and an ambiguate so it goes directly into the
774 * pass-through state. CCS_E also provides fast clear and partial
775 * resolve operations which work as described above.
777 * While it is technically possible to perform a CCS_E ambiguate, it
778 * is not provided by Sky Lake hardware so we choose to avoid the aux
779 * invalid state. If the aux invalid state were determined to be
780 * useful, a CCS ambiguate could be done by carefully rendering to
781 * the CCS and filling it with zeros.
784 ISL_AUX_STATE_CLEAR
= 0,
785 ISL_AUX_STATE_PARTIAL_CLEAR
,
786 ISL_AUX_STATE_COMPRESSED_CLEAR
,
787 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
,
788 ISL_AUX_STATE_RESOLVED
,
789 ISL_AUX_STATE_PASS_THROUGH
,
790 ISL_AUX_STATE_AUX_INVALID
,
794 * Enum which describes explicit aux transition operations.
801 * This operation writes the magic "clear" value to the auxiliary surface.
802 * This operation will safely transition any slice of a surface from any
803 * state to the clear state so long as the entire slice is fast cleared at
804 * once. A fast clear that only covers part of a slice of a surface is
805 * called a partial fast clear.
807 ISL_AUX_OP_FAST_CLEAR
,
811 * This operation combines the auxiliary surface data with the primary
812 * surface data and writes the result to the primary. For HiZ, the docs
813 * call this a depth resolve. For CCS, the hardware full resolve operation
814 * does both a full resolve and an ambiguate so it actually takes you all
815 * the way to the pass-through state.
817 ISL_AUX_OP_FULL_RESOLVE
,
821 * This operation considers blocks which are in the "clear" state and
822 * writes the clear value directly into the primary or auxiliary surface.
823 * Once this operation completes, the surface is still compressed but no
824 * longer references the clear color. This operation is only available
827 ISL_AUX_OP_PARTIAL_RESOLVE
,
831 * This operation throws away the current auxiliary data and replaces it
832 * with the magic pass-through value. If an ambiguate operation is
833 * performed when the primary surface does not contain 100% of the data,
834 * data will be lost. This operation is only implemented in hardware for
835 * depth where it is called a HiZ resolve.
837 ISL_AUX_OP_AMBIGUATE
,
840 /* TODO(chadv): Explain */
841 enum isl_array_pitch_span
{
842 ISL_ARRAY_PITCH_SPAN_FULL
,
843 ISL_ARRAY_PITCH_SPAN_COMPACT
,
847 * @defgroup Surface Usage
850 typedef uint64_t isl_surf_usage_flags_t
;
851 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
852 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
853 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
854 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
855 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
856 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
857 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
858 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
859 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
860 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
861 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
862 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
863 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
864 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
865 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
866 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
870 * @defgroup Channel Mask
872 * These #define values are chosen to match the values of
873 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
877 typedef uint8_t isl_channel_mask_t
;
878 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
879 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
880 #define ISL_CHANNEL_RED_BIT (1 << 2)
881 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
885 * @brief A channel select (also known as texture swizzle) value
887 enum PACKED isl_channel_select
{
888 ISL_CHANNEL_SELECT_ZERO
= 0,
889 ISL_CHANNEL_SELECT_ONE
= 1,
890 ISL_CHANNEL_SELECT_RED
= 4,
891 ISL_CHANNEL_SELECT_GREEN
= 5,
892 ISL_CHANNEL_SELECT_BLUE
= 6,
893 ISL_CHANNEL_SELECT_ALPHA
= 7,
897 * Identical to VkSampleCountFlagBits.
899 enum isl_sample_count
{
900 ISL_SAMPLE_COUNT_1_BIT
= 1u,
901 ISL_SAMPLE_COUNT_2_BIT
= 2u,
902 ISL_SAMPLE_COUNT_4_BIT
= 4u,
903 ISL_SAMPLE_COUNT_8_BIT
= 8u,
904 ISL_SAMPLE_COUNT_16_BIT
= 16u,
906 typedef uint32_t isl_sample_count_mask_t
;
909 * @brief Multisample Format
911 enum isl_msaa_layout
{
913 * @brief Suface is single-sampled.
915 ISL_MSAA_LAYOUT_NONE
,
918 * @brief [SNB+] Interleaved Multisample Format
920 * In this format, multiple samples are interleaved into each cacheline.
921 * In other words, the sample index is swizzled into the low 6 bits of the
922 * surface's virtual address space.
924 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
925 * and its pixel format is 32bpp. Then the first cacheline is arranged
928 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
929 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
931 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
932 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
934 * The hardware docs refer to this format with multiple terms. In
935 * Sandybridge, this is the only multisample format; so no term is used.
936 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
937 * Multisample Surface). Later hardware docs additionally refer to this
938 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
941 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
944 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
945 * Multisampled Surfaces".
947 ISL_MSAA_LAYOUT_INTERLEAVED
,
950 * @brief [IVB+] Array Multisample Format
952 * In this format, the surface's physical layout resembles that of a
955 * Suppose the multisample surface's logical extent is (w, h) and its
956 * sample count is N. Then surface's physical extent is the same as
957 * a singlesample 2D surface whose logical extent is (w, h) and array
958 * length is N. Array slice `i` contains the pixel values for sample
961 * The Ivybridge docs refer to surfaces in this format as UMS
962 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
963 * Surface). The Broadwell docs additionally refer to this format as
964 * MSFMT_MSS (MSS=Multisample Surface Storage).
966 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
967 * Multisample Surfaces".
969 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
970 * Multisample Surfaces".
972 ISL_MSAA_LAYOUT_ARRAY
,
978 ISL_MEMCPY_STREAMING_LOAD
,
983 const struct gen_device_info
*info
;
984 bool use_separate_stencil
;
985 bool has_bit6_swizzling
;
988 * Describes the layout of a RENDER_SURFACE_STATE structure for the
995 uint8_t aux_addr_offset
;
997 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
999 /* size of the state buffer used to store the clear color + extra
1000 * additional space used by the hardware */
1001 uint8_t clear_color_state_size
;
1002 uint8_t clear_color_state_offset
;
1003 /* size of the clear color itself - used to copy it to/from a BO */
1004 uint8_t clear_value_size
;
1005 uint8_t clear_value_offset
;
1009 * Describes the layout of the depth/stencil/hiz commands as emitted by
1010 * isl_emit_depth_stencil_hiz.
1014 uint8_t depth_offset
;
1015 uint8_t stencil_offset
;
1025 struct isl_extent2d
{
1026 union { uint32_t w
, width
; };
1027 union { uint32_t h
, height
; };
1030 struct isl_extent3d
{
1031 union { uint32_t w
, width
; };
1032 union { uint32_t h
, height
; };
1033 union { uint32_t d
, depth
; };
1036 struct isl_extent4d
{
1037 union { uint32_t w
, width
; };
1038 union { uint32_t h
, height
; };
1039 union { uint32_t d
, depth
; };
1040 union { uint32_t a
, array_len
; };
1043 struct isl_channel_layout
{
1044 enum isl_base_type type
;
1045 uint8_t start_bit
; /**< Bit at which this channel starts */
1046 uint8_t bits
; /**< Size in bits */
1050 * Each format has 3D block extent (width, height, depth). The block extent of
1051 * compressed formats is that of the format's compression block. For example,
1052 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1053 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1054 * is (w=1, h=1, d=1).
1056 struct isl_format_layout
{
1057 enum isl_format format
;
1060 uint16_t bpb
; /**< Bits per block */
1061 uint8_t bw
; /**< Block width, in pixels */
1062 uint8_t bh
; /**< Block height, in pixels */
1063 uint8_t bd
; /**< Block depth, in pixels */
1067 struct isl_channel_layout r
; /**< Red channel */
1068 struct isl_channel_layout g
; /**< Green channel */
1069 struct isl_channel_layout b
; /**< Blue channel */
1070 struct isl_channel_layout a
; /**< Alpha channel */
1071 struct isl_channel_layout l
; /**< Luminance channel */
1072 struct isl_channel_layout i
; /**< Intensity channel */
1073 struct isl_channel_layout p
; /**< Palette channel */
1075 struct isl_channel_layout channels_array
[7];
1078 enum isl_colorspace colorspace
;
1082 struct isl_tile_info
{
1083 enum isl_tiling tiling
;
1085 /* The size (in bits per block) of a single surface element
1087 * For surfaces with power-of-two formats, this is the same as
1088 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1089 * The logical_extent_el field is in terms of elements of this size.
1091 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1092 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1093 * of the tiling formats can actually hold an integer number of 96-bit
1094 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1095 * 32-bit element size. It is the responsibility of the caller to
1096 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1097 * the width of a surface in tiles, you would do:
1099 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1100 * tile_info.logical_extent_el.width);
1102 uint32_t format_bpb
;
1104 /** The logical size of the tile in units of format_bpb size elements
1106 * This field determines how a given surface is cut up into tiles. It is
1107 * used to compute the size of a surface in tiles and can be used to
1108 * determine the location of the tile containing any given surface element.
1109 * The exact value of this field depends heavily on the bits-per-block of
1110 * the format being used.
1112 struct isl_extent2d logical_extent_el
;
1114 /** The physical size of the tile in bytes and rows of bytes
1116 * This field determines how the tiles of a surface are physically layed
1117 * out in memory. The logical and physical tile extent are frequently the
1118 * same but this is not always the case. For instance, a W-tile (which is
1119 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1120 * its physical size is 128B x 32rows, the same as a Y-tile.
1122 * @see isl_surf::row_pitch_B
1124 struct isl_extent2d phys_extent_B
;
1128 * Metadata about a DRM format modifier.
1130 struct isl_drm_modifier_info
{
1133 /** Text name of the modifier */
1136 /** ISL tiling implied by this modifier */
1137 enum isl_tiling tiling
;
1139 /** ISL aux usage implied by this modifier */
1140 enum isl_aux_usage aux_usage
;
1142 /** Whether or not this modifier supports clear color */
1143 bool supports_clear_color
;
1147 * @brief Input to surface initialization
1149 * @invariant width >= 1
1150 * @invariant height >= 1
1151 * @invariant depth >= 1
1152 * @invariant levels >= 1
1153 * @invariant samples >= 1
1154 * @invariant array_len >= 1
1156 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1157 * @invariant if 2D then depth == 1
1158 * @invariant if 3D then array_len == 1 and samples == 1
1160 struct isl_surf_init_info
{
1161 enum isl_surf_dim dim
;
1162 enum isl_format format
;
1171 /** Lower bound for isl_surf::alignment, in bytes. */
1172 uint32_t min_alignment_B
;
1175 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1176 * will fail if this is misaligned or out of bounds.
1178 uint32_t row_pitch_B
;
1180 isl_surf_usage_flags_t usage
;
1182 /** Flags that alter how ISL selects isl_surf::tiling. */
1183 isl_tiling_flags_t tiling_flags
;
1187 enum isl_surf_dim dim
;
1188 enum isl_dim_layout dim_layout
;
1189 enum isl_msaa_layout msaa_layout
;
1190 enum isl_tiling tiling
;
1191 enum isl_format format
;
1194 * Alignment of the upper-left sample of each subimage, in units of surface
1197 struct isl_extent3d image_alignment_el
;
1200 * Logical extent of the surface's base level, in units of pixels. This is
1201 * identical to the extent defined in isl_surf_init_info.
1203 struct isl_extent4d logical_level0_px
;
1206 * Physical extent of the surface's base level, in units of physical
1209 * Consider isl_dim_layout as an operator that transforms a logical surface
1210 * layout to a physical surface layout. Then
1212 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1213 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1215 struct isl_extent4d phys_level0_sa
;
1220 /** Total size of the surface, in bytes. */
1223 /** Required alignment for the surface's base address. */
1224 uint32_t alignment_B
;
1227 * The interpretation of this field depends on the value of
1228 * isl_tile_info::physical_extent_B. In particular, the width of the
1229 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1230 * and the distance in bytes between vertically adjacent tiles in the image
1231 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1233 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1234 * this cleanly reduces to being the distance, in bytes, between vertically
1235 * adjacent surface elements.
1237 * @see isl_tile_info::phys_extent_B;
1239 uint32_t row_pitch_B
;
1242 * Pitch between physical array slices, in rows of surface elements.
1244 uint32_t array_pitch_el_rows
;
1246 enum isl_array_pitch_span array_pitch_span
;
1248 /** Copy of isl_surf_init_info::usage. */
1249 isl_surf_usage_flags_t usage
;
1252 struct isl_swizzle
{
1253 enum isl_channel_select r
:4;
1254 enum isl_channel_select g
:4;
1255 enum isl_channel_select b
:4;
1256 enum isl_channel_select a
:4;
1259 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1260 .r = ISL_CHANNEL_SELECT_##R, \
1261 .g = ISL_CHANNEL_SELECT_##G, \
1262 .b = ISL_CHANNEL_SELECT_##B, \
1263 .a = ISL_CHANNEL_SELECT_##A, \
1266 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1270 * Indicates the usage of the particular view
1272 * Normally, this is one bit. However, for a cube map texture, it
1273 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1275 isl_surf_usage_flags_t usage
;
1278 * The format to use in the view
1280 * This may differ from the format of the actual isl_surf but must have
1281 * the same block size.
1283 enum isl_format format
;
1285 uint32_t base_level
;
1291 * For cube maps, both base_array_layer and array_len should be
1292 * specified in terms of 2-D layers and must be a multiple of 6.
1294 * 3-D textures are effectively treated as 2-D arrays when used as a
1295 * storage image or render target. If `usage` contains
1296 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1297 * base_array_layer and array_len are applied. If the surface is only used
1298 * for texturing, they are ignored.
1300 uint32_t base_array_layer
;
1305 * Indicates the number of array elements starting at Base Array Layer.
1309 struct isl_swizzle swizzle
;
1312 union isl_color_value
{
1318 struct isl_surf_fill_state_info
{
1319 const struct isl_surf
*surf
;
1320 const struct isl_view
*view
;
1323 * The address of the surface in GPU memory.
1328 * The Memory Object Control state for the filled surface state.
1330 * The exact format of this value depends on hardware generation.
1335 * The auxilary surface or NULL if no auxilary surface is to be used.
1337 const struct isl_surf
*aux_surf
;
1338 enum isl_aux_usage aux_usage
;
1339 uint64_t aux_address
;
1342 * The clear color for this surface
1344 * Valid values depend on hardware generation.
1346 union isl_color_value clear_color
;
1349 * Send only the clear value address
1351 * If set, we only pass the clear address to the GPU and it will fetch it
1352 * from wherever it is.
1354 bool use_clear_address
;
1355 uint64_t clear_address
;
1358 * Surface write disables for gen4-5
1360 isl_channel_mask_t write_disables
;
1362 /* Intra-tile offset */
1363 uint16_t x_offset_sa
, y_offset_sa
;
1366 struct isl_buffer_fill_state_info
{
1368 * The address of the surface in GPU memory.
1373 * The size of the buffer
1378 * The Memory Object Control state for the filled surface state.
1380 * The exact format of this value depends on hardware generation.
1385 * The format to use in the surface state
1387 * This may differ from the format of the actual isl_surf but have the
1390 enum isl_format format
;
1393 * The swizzle to use in the surface state
1395 struct isl_swizzle swizzle
;
1400 struct isl_depth_stencil_hiz_emit_info
{
1404 const struct isl_surf
*depth_surf
;
1407 * The stencil surface
1409 * If separate stencil is not available, this must point to the same
1410 * isl_surf as depth_surf.
1412 const struct isl_surf
*stencil_surf
;
1415 * The view into the depth and stencil surfaces.
1417 * This view applies to both surfaces simultaneously.
1419 const struct isl_view
*view
;
1422 * The address of the depth surface in GPU memory
1424 uint64_t depth_address
;
1427 * The address of the stencil surface in GPU memory
1429 * If separate stencil is not available, this must have the same value as
1432 uint64_t stencil_address
;
1435 * The Memory Object Control state for depth and stencil buffers
1437 * Both depth and stencil will get the same MOCS value. The exact format
1438 * of this value depends on hardware generation.
1443 * The HiZ surface or NULL if HiZ is disabled.
1445 const struct isl_surf
*hiz_surf
;
1446 enum isl_aux_usage hiz_usage
;
1447 uint64_t hiz_address
;
1450 * The depth clear value
1452 float depth_clear_value
;
1455 * Track stencil aux usage for Gen >= 12
1457 enum isl_aux_usage stencil_aux_usage
;
1460 extern const struct isl_format_layout isl_format_layouts
[];
1463 isl_device_init(struct isl_device
*dev
,
1464 const struct gen_device_info
*info
,
1465 bool has_bit6_swizzling
);
1467 isl_sample_count_mask_t ATTRIBUTE_CONST
1468 isl_device_get_sample_counts(struct isl_device
*dev
);
1470 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
1471 isl_format_get_layout(enum isl_format fmt
)
1473 assert(fmt
!= ISL_FORMAT_UNSUPPORTED
);
1474 assert(fmt
< ISL_NUM_FORMATS
);
1475 return &isl_format_layouts
[fmt
];
1478 bool isl_format_is_valid(enum isl_format
);
1480 static inline const char * ATTRIBUTE_CONST
1481 isl_format_get_name(enum isl_format fmt
)
1483 return isl_format_get_layout(fmt
)->name
;
1486 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
1487 enum isl_format format
);
1488 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
1489 enum isl_format format
);
1490 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
1491 enum isl_format format
);
1492 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
1493 enum isl_format format
);
1494 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
1495 enum isl_format format
);
1496 bool isl_format_supports_typed_writes(const struct gen_device_info
*devinfo
,
1497 enum isl_format format
);
1498 bool isl_format_supports_typed_reads(const struct gen_device_info
*devinfo
,
1499 enum isl_format format
);
1500 bool isl_format_supports_ccs_d(const struct gen_device_info
*devinfo
,
1501 enum isl_format format
);
1502 bool isl_format_supports_ccs_e(const struct gen_device_info
*devinfo
,
1503 enum isl_format format
);
1504 bool isl_format_supports_multisampling(const struct gen_device_info
*devinfo
,
1505 enum isl_format format
);
1507 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info
*devinfo
,
1508 enum isl_format format1
,
1509 enum isl_format format2
);
1511 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1512 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1513 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1514 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1515 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1516 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1519 isl_format_has_normalized_channel(enum isl_format fmt
)
1521 return isl_format_has_unorm_channel(fmt
) ||
1522 isl_format_has_snorm_channel(fmt
);
1526 isl_format_has_float_channel(enum isl_format fmt
)
1528 return isl_format_has_ufloat_channel(fmt
) ||
1529 isl_format_has_sfloat_channel(fmt
);
1533 isl_format_has_int_channel(enum isl_format fmt
)
1535 return isl_format_has_uint_channel(fmt
) ||
1536 isl_format_has_sint_channel(fmt
);
1539 bool isl_format_has_color_component(enum isl_format fmt
,
1540 int component
) ATTRIBUTE_CONST
;
1542 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1544 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1547 isl_format_is_compressed(enum isl_format fmt
)
1549 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1551 return fmtl
->txc
!= ISL_TXC_NONE
;
1555 isl_format_has_bc_compression(enum isl_format fmt
)
1557 switch (isl_format_get_layout(fmt
)->txc
) {
1575 unreachable("Should not be called on an aux surface");
1578 unreachable("bad texture compression mode");
1583 isl_format_is_yuv(enum isl_format fmt
)
1585 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1587 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1591 isl_format_block_is_1x1x1(enum isl_format fmt
)
1593 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1595 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1599 isl_format_is_srgb(enum isl_format fmt
)
1601 return isl_format_get_layout(fmt
)->colorspace
== ISL_COLORSPACE_SRGB
;
1604 enum isl_format
isl_format_srgb_to_linear(enum isl_format fmt
);
1607 isl_format_is_rgb(enum isl_format fmt
)
1609 if (isl_format_is_yuv(fmt
))
1612 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1614 return fmtl
->channels
.r
.bits
> 0 &&
1615 fmtl
->channels
.g
.bits
> 0 &&
1616 fmtl
->channels
.b
.bits
> 0 &&
1617 fmtl
->channels
.a
.bits
== 0;
1621 isl_format_is_rgbx(enum isl_format fmt
)
1623 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1625 return fmtl
->channels
.r
.bits
> 0 &&
1626 fmtl
->channels
.g
.bits
> 0 &&
1627 fmtl
->channels
.b
.bits
> 0 &&
1628 fmtl
->channels
.a
.bits
> 0 &&
1629 fmtl
->channels
.a
.type
== ISL_VOID
;
1632 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1633 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1634 enum isl_format
isl_format_rgbx_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1636 void isl_color_value_pack(const union isl_color_value
*value
,
1637 enum isl_format format
,
1638 uint32_t *data_out
);
1639 void isl_color_value_unpack(union isl_color_value
*value
,
1640 enum isl_format format
,
1641 const uint32_t *data_in
);
1643 bool isl_is_storage_image_format(enum isl_format fmt
);
1646 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1647 enum isl_format fmt
);
1649 /* Returns true if this hardware supports typed load/store on a format with
1650 * the same size as the given format.
1653 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1654 enum isl_format fmt
);
1656 static inline enum isl_tiling
1657 isl_tiling_flag_to_enum(isl_tiling_flags_t flag
)
1659 assert(__builtin_popcount(flag
) == 1);
1660 return (enum isl_tiling
) (__builtin_ffs(flag
) - 1);
1664 isl_tiling_is_any_y(enum isl_tiling tiling
)
1666 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1670 isl_tiling_is_std_y(enum isl_tiling tiling
)
1672 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1676 isl_tiling_to_i915_tiling(enum isl_tiling tiling
);
1679 isl_tiling_from_i915_tiling(uint32_t tiling
);
1682 isl_aux_usage_has_hiz(enum isl_aux_usage usage
)
1684 return usage
== ISL_AUX_USAGE_HIZ
||
1685 usage
== ISL_AUX_USAGE_HIZ_CCS
;
1689 isl_aux_usage_has_mcs(enum isl_aux_usage usage
)
1691 return usage
== ISL_AUX_USAGE_MCS
||
1692 usage
== ISL_AUX_USAGE_MCS_CCS
;
1696 isl_aux_usage_has_ccs(enum isl_aux_usage usage
)
1698 return usage
== ISL_AUX_USAGE_CCS_D
||
1699 usage
== ISL_AUX_USAGE_CCS_E
||
1700 usage
== ISL_AUX_USAGE_MC
||
1701 usage
== ISL_AUX_USAGE_HIZ_CCS
||
1702 usage
== ISL_AUX_USAGE_MCS_CCS
;
1705 const struct isl_drm_modifier_info
* ATTRIBUTE_CONST
1706 isl_drm_modifier_get_info(uint64_t modifier
);
1709 isl_drm_modifier_has_aux(uint64_t modifier
)
1711 return isl_drm_modifier_get_info(modifier
)->aux_usage
!= ISL_AUX_USAGE_NONE
;
1714 /** Returns the default isl_aux_state for the given modifier.
1716 * If we have a modifier which supports compression, then the auxiliary data
1717 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1718 * can be in any of the following:
1720 * - ISL_AUX_STATE_CLEAR
1721 * - ISL_AUX_STATE_PARTIAL_CLEAR
1722 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1723 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1724 * - ISL_AUX_STATE_RESOLVED
1725 * - ISL_AUX_STATE_PASS_THROUGH
1727 * If the modifier does not support fast-clears, then we are guaranteed
1728 * that the surface is at least partially resolved and the first three not
1729 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1730 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1731 * because they are the least common denominator of the set of possible aux
1732 * states and will yield a valid interpretation of the aux data.
1734 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1736 static inline enum isl_aux_state
1737 isl_drm_modifier_get_default_aux_state(uint64_t modifier
)
1739 const struct isl_drm_modifier_info
*mod_info
=
1740 isl_drm_modifier_get_info(modifier
);
1742 if (!mod_info
|| mod_info
->aux_usage
== ISL_AUX_USAGE_NONE
)
1743 return ISL_AUX_STATE_AUX_INVALID
;
1745 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1746 return mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1747 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1750 struct isl_extent2d ATTRIBUTE_CONST
1751 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
);
1754 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1756 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1760 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1762 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1766 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1768 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1772 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1774 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1775 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1779 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1781 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1785 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1787 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1788 (info
->format
== ISL_FORMAT_R16_UNORM
);
1792 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1794 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1795 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1798 static inline struct isl_extent2d
1799 isl_extent2d(uint32_t width
, uint32_t height
)
1801 struct isl_extent2d e
= { { 0 } };
1809 static inline struct isl_extent3d
1810 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1812 struct isl_extent3d e
= { { 0 } };
1821 static inline struct isl_extent4d
1822 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1825 struct isl_extent4d e
= { { 0 } };
1830 e
.array_len
= array_len
;
1835 bool isl_color_value_is_zero(union isl_color_value value
,
1836 enum isl_format format
);
1838 bool isl_color_value_is_zero_one(union isl_color_value value
,
1839 enum isl_format format
);
1842 isl_swizzle_is_identity(struct isl_swizzle swizzle
)
1844 return swizzle
.r
== ISL_CHANNEL_SELECT_RED
&&
1845 swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
&&
1846 swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
&&
1847 swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
;
1851 isl_swizzle_supports_rendering(const struct gen_device_info
*devinfo
,
1852 struct isl_swizzle swizzle
);
1855 isl_swizzle_compose(struct isl_swizzle first
, struct isl_swizzle second
);
1857 isl_swizzle_invert(struct isl_swizzle swizzle
);
1859 #define isl_surf_init(dev, surf, ...) \
1860 isl_surf_init_s((dev), (surf), \
1861 &(struct isl_surf_init_info) { __VA_ARGS__ });
1864 isl_surf_init_s(const struct isl_device
*dev
,
1865 struct isl_surf
*surf
,
1866 const struct isl_surf_init_info
*restrict info
);
1869 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1870 struct isl_tile_info
*tile_info
);
1873 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1874 const struct isl_surf
*surf
,
1875 struct isl_surf
*hiz_surf
);
1878 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1879 const struct isl_surf
*surf
,
1880 struct isl_surf
*mcs_surf
);
1883 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1884 const struct isl_surf
*surf
,
1885 struct isl_surf
*aux_surf
,
1886 struct isl_surf
*extra_aux_surf
,
1887 uint32_t row_pitch_B
/**< Ignored if 0 */);
1889 #define isl_surf_fill_state(dev, state, ...) \
1890 isl_surf_fill_state_s((dev), (state), \
1891 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1894 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1895 const struct isl_surf_fill_state_info
*restrict info
);
1897 #define isl_buffer_fill_state(dev, state, ...) \
1898 isl_buffer_fill_state_s((dev), (state), \
1899 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1902 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1903 const struct isl_buffer_fill_state_info
*restrict info
);
1906 isl_null_fill_state(const struct isl_device
*dev
, void *state
,
1907 struct isl_extent3d size
);
1909 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1910 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1911 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1914 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1915 const struct isl_depth_stencil_hiz_emit_info
*restrict info
);
1918 isl_surf_fill_image_param(const struct isl_device
*dev
,
1919 struct brw_image_param
*param
,
1920 const struct isl_surf
*surf
,
1921 const struct isl_view
*view
);
1924 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1925 struct brw_image_param
*param
,
1926 enum isl_format format
,
1930 * Alignment of the upper-left sample of each subimage, in units of surface
1933 static inline struct isl_extent3d
1934 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1936 return surf
->image_alignment_el
;
1940 * Alignment of the upper-left sample of each subimage, in units of surface
1943 static inline struct isl_extent3d
1944 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1946 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1948 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1949 fmtl
->bh
* surf
->image_alignment_el
.h
,
1950 fmtl
->bd
* surf
->image_alignment_el
.d
);
1954 * Logical extent of level 0 in units of surface elements.
1956 static inline struct isl_extent4d
1957 isl_surf_get_logical_level0_el(const struct isl_surf
*surf
)
1959 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1961 return isl_extent4d(DIV_ROUND_UP(surf
->logical_level0_px
.w
, fmtl
->bw
),
1962 DIV_ROUND_UP(surf
->logical_level0_px
.h
, fmtl
->bh
),
1963 DIV_ROUND_UP(surf
->logical_level0_px
.d
, fmtl
->bd
),
1964 surf
->logical_level0_px
.a
);
1968 * Physical extent of level 0 in units of surface elements.
1970 static inline struct isl_extent4d
1971 isl_surf_get_phys_level0_el(const struct isl_surf
*surf
)
1973 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1975 return isl_extent4d(DIV_ROUND_UP(surf
->phys_level0_sa
.w
, fmtl
->bw
),
1976 DIV_ROUND_UP(surf
->phys_level0_sa
.h
, fmtl
->bh
),
1977 DIV_ROUND_UP(surf
->phys_level0_sa
.d
, fmtl
->bd
),
1978 surf
->phys_level0_sa
.a
);
1982 * Pitch between vertically adjacent surface elements, in bytes.
1984 static inline uint32_t
1985 isl_surf_get_row_pitch_B(const struct isl_surf
*surf
)
1987 return surf
->row_pitch_B
;
1991 * Pitch between vertically adjacent surface elements, in units of surface elements.
1993 static inline uint32_t
1994 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1996 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1998 assert(surf
->row_pitch_B
% (fmtl
->bpb
/ 8) == 0);
1999 return surf
->row_pitch_B
/ (fmtl
->bpb
/ 8);
2003 * Pitch between physical array slices, in rows of surface elements.
2005 static inline uint32_t
2006 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
2008 return surf
->array_pitch_el_rows
;
2012 * Pitch between physical array slices, in units of surface elements.
2014 static inline uint32_t
2015 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
2017 return isl_surf_get_array_pitch_el_rows(surf
) *
2018 isl_surf_get_row_pitch_el(surf
);
2022 * Pitch between physical array slices, in rows of surface samples.
2024 static inline uint32_t
2025 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
2027 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
2028 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
2032 * Pitch between physical array slices, in bytes.
2034 static inline uint32_t
2035 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
2037 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch_B
;
2041 * Calculate the offset, in units of surface samples, to a subimage in the
2044 * @invariant level < surface levels
2045 * @invariant logical_array_layer < logical array length of surface
2046 * @invariant logical_z_offset_px < logical depth of surface at level
2049 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
2051 uint32_t logical_array_layer
,
2052 uint32_t logical_z_offset_px
,
2053 uint32_t *x_offset_sa
,
2054 uint32_t *y_offset_sa
);
2057 * Calculate the offset, in units of surface elements, to a subimage in the
2060 * @invariant level < surface levels
2061 * @invariant logical_array_layer < logical array length of surface
2062 * @invariant logical_z_offset_px < logical depth of surface at level
2065 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
2067 uint32_t logical_array_layer
,
2068 uint32_t logical_z_offset_px
,
2069 uint32_t *x_offset_el
,
2070 uint32_t *y_offset_el
);
2073 * Calculate the offset, in bytes and intratile surface samples, to a
2074 * subimage in the surface.
2076 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2077 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2078 * offsets to samples.
2080 * @invariant level < surface levels
2081 * @invariant logical_array_layer < logical array length of surface
2082 * @invariant logical_z_offset_px < logical depth of surface at level
2085 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
2087 uint32_t logical_array_layer
,
2088 uint32_t logical_z_offset_px
,
2090 uint32_t *x_offset_sa
,
2091 uint32_t *y_offset_sa
);
2094 * Create an isl_surf that represents a particular subimage in the surface.
2096 * The newly created surface will have a single miplevel and array slice. The
2097 * surface lives at the returned byte and intratile offsets, in samples.
2099 * It is safe to call this function with surf == image_surf.
2101 * @invariant level < surface levels
2102 * @invariant logical_array_layer < logical array length of surface
2103 * @invariant logical_z_offset_px < logical depth of surface at level
2106 isl_surf_get_image_surf(const struct isl_device
*dev
,
2107 const struct isl_surf
*surf
,
2109 uint32_t logical_array_layer
,
2110 uint32_t logical_z_offset_px
,
2111 struct isl_surf
*image_surf
,
2113 uint32_t *x_offset_sa
,
2114 uint32_t *y_offset_sa
);
2117 * @brief Calculate the intratile offsets to a surface.
2119 * In @a base_address_offset return the offset from the base of the surface to
2120 * the base address of the first tile of the subimage. In @a x_offset_B and
2121 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2122 * tile's base to the subimage's first surface element. The x and y offsets
2123 * are intratile offsets; that is, they do not exceed the boundary of the
2124 * surface's tiling format.
2127 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
2129 uint32_t row_pitch_B
,
2130 uint32_t total_x_offset_el
,
2131 uint32_t total_y_offset_el
,
2132 uint32_t *base_address_offset
,
2133 uint32_t *x_offset_el
,
2134 uint32_t *y_offset_el
);
2137 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling
,
2138 enum isl_format format
,
2139 uint32_t row_pitch_B
,
2140 uint32_t total_x_offset_sa
,
2141 uint32_t total_y_offset_sa
,
2142 uint32_t *base_address_offset
,
2143 uint32_t *x_offset_sa
,
2144 uint32_t *y_offset_sa
)
2146 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
2148 /* For computing the intratile offsets, we actually want a strange unit
2149 * which is samples for multisampled surfaces but elements for compressed
2152 assert(total_x_offset_sa
% fmtl
->bw
== 0);
2153 assert(total_y_offset_sa
% fmtl
->bh
== 0);
2154 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
2155 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
2157 isl_tiling_get_intratile_offset_el(tiling
, fmtl
->bpb
, row_pitch_B
,
2158 total_x_offset
, total_y_offset
,
2159 base_address_offset
,
2160 x_offset_sa
, y_offset_sa
);
2161 *x_offset_sa
*= fmtl
->bw
;
2162 *y_offset_sa
*= fmtl
->bh
;
2166 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2168 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2169 * @pre surf->format must be a valid format for depth surfaces
2172 isl_surf_get_depth_format(const struct isl_device
*dev
,
2173 const struct isl_surf
*surf
);
2176 * @brief determines if a surface supports writing through HIZ to the CCS.
2179 isl_surf_supports_hiz_ccs_wt(const struct gen_device_info
*dev
,
2180 const struct isl_surf
*surf
,
2181 enum isl_aux_usage aux_usage
);
2184 * @brief performs a copy from linear to tiled surface
2188 isl_memcpy_linear_to_tiled(uint32_t xt1
, uint32_t xt2
,
2189 uint32_t yt1
, uint32_t yt2
,
2190 char *dst
, const char *src
,
2191 uint32_t dst_pitch
, int32_t src_pitch
,
2193 enum isl_tiling tiling
,
2194 isl_memcpy_type copy_type
);
2197 * @brief performs a copy from tiled to linear surface
2201 isl_memcpy_tiled_to_linear(uint32_t xt1
, uint32_t xt2
,
2202 uint32_t yt1
, uint32_t yt2
,
2203 char *dst
, const char *src
,
2204 int32_t dst_pitch
, uint32_t src_pitch
,
2206 enum isl_tiling tiling
,
2207 isl_memcpy_type copy_type
);