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isl: Add support for HiZ surfaces
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct brw_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
63 #else
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
66 #endif
67
68 #ifndef ISL_DEV_IS_HASWELL
69 /**
70 * @brief Get the hardware generation of isl_device.
71 *
72 * You can define this as a compile-time constant in the CFLAGS. For example,
73 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
74 */
75 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
76 #endif
77
78 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
79 /**
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
82 */
83 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
84 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
85 #else
86 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
87 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
88 #endif
89
90 /**
91 * Hardware enumeration SURFACE_FORMAT.
92 *
93 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
94 * Enumerations: SURFACE_FORMAT.
95 */
96 enum isl_format {
97 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
98 ISL_FORMAT_R32G32B32A32_SINT = 1,
99 ISL_FORMAT_R32G32B32A32_UINT = 2,
100 ISL_FORMAT_R32G32B32A32_UNORM = 3,
101 ISL_FORMAT_R32G32B32A32_SNORM = 4,
102 ISL_FORMAT_R64G64_FLOAT = 5,
103 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
104 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
105 ISL_FORMAT_R32G32B32A32_USCALED = 8,
106 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
107 ISL_FORMAT_R64G64_PASSTHRU = 33,
108 ISL_FORMAT_R32G32B32_FLOAT = 64,
109 ISL_FORMAT_R32G32B32_SINT = 65,
110 ISL_FORMAT_R32G32B32_UINT = 66,
111 ISL_FORMAT_R32G32B32_UNORM = 67,
112 ISL_FORMAT_R32G32B32_SNORM = 68,
113 ISL_FORMAT_R32G32B32_SSCALED = 69,
114 ISL_FORMAT_R32G32B32_USCALED = 70,
115 ISL_FORMAT_R32G32B32_SFIXED = 80,
116 ISL_FORMAT_R16G16B16A16_UNORM = 128,
117 ISL_FORMAT_R16G16B16A16_SNORM = 129,
118 ISL_FORMAT_R16G16B16A16_SINT = 130,
119 ISL_FORMAT_R16G16B16A16_UINT = 131,
120 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
121 ISL_FORMAT_R32G32_FLOAT = 133,
122 ISL_FORMAT_R32G32_SINT = 134,
123 ISL_FORMAT_R32G32_UINT = 135,
124 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
125 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
126 ISL_FORMAT_L32A32_FLOAT = 138,
127 ISL_FORMAT_R32G32_UNORM = 139,
128 ISL_FORMAT_R32G32_SNORM = 140,
129 ISL_FORMAT_R64_FLOAT = 141,
130 ISL_FORMAT_R16G16B16X16_UNORM = 142,
131 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
132 ISL_FORMAT_A32X32_FLOAT = 144,
133 ISL_FORMAT_L32X32_FLOAT = 145,
134 ISL_FORMAT_I32X32_FLOAT = 146,
135 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
136 ISL_FORMAT_R16G16B16A16_USCALED = 148,
137 ISL_FORMAT_R32G32_SSCALED = 149,
138 ISL_FORMAT_R32G32_USCALED = 150,
139 ISL_FORMAT_R32G32_FLOAT_LD = 151,
140 ISL_FORMAT_R32G32_SFIXED = 160,
141 ISL_FORMAT_R64_PASSTHRU = 161,
142 ISL_FORMAT_B8G8R8A8_UNORM = 192,
143 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
144 ISL_FORMAT_R10G10B10A2_UNORM = 194,
145 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
146 ISL_FORMAT_R10G10B10A2_UINT = 196,
147 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
148 ISL_FORMAT_R8G8B8A8_UNORM = 199,
149 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
150 ISL_FORMAT_R8G8B8A8_SNORM = 201,
151 ISL_FORMAT_R8G8B8A8_SINT = 202,
152 ISL_FORMAT_R8G8B8A8_UINT = 203,
153 ISL_FORMAT_R16G16_UNORM = 204,
154 ISL_FORMAT_R16G16_SNORM = 205,
155 ISL_FORMAT_R16G16_SINT = 206,
156 ISL_FORMAT_R16G16_UINT = 207,
157 ISL_FORMAT_R16G16_FLOAT = 208,
158 ISL_FORMAT_B10G10R10A2_UNORM = 209,
159 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
160 ISL_FORMAT_R11G11B10_FLOAT = 211,
161 ISL_FORMAT_R32_SINT = 214,
162 ISL_FORMAT_R32_UINT = 215,
163 ISL_FORMAT_R32_FLOAT = 216,
164 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
165 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
166 ISL_FORMAT_L32_UNORM = 221,
167 ISL_FORMAT_A32_UNORM = 222,
168 ISL_FORMAT_L16A16_UNORM = 223,
169 ISL_FORMAT_I24X8_UNORM = 224,
170 ISL_FORMAT_L24X8_UNORM = 225,
171 ISL_FORMAT_A24X8_UNORM = 226,
172 ISL_FORMAT_I32_FLOAT = 227,
173 ISL_FORMAT_L32_FLOAT = 228,
174 ISL_FORMAT_A32_FLOAT = 229,
175 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
176 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
177 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
178 ISL_FORMAT_B8G8R8X8_UNORM = 233,
179 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
180 ISL_FORMAT_R8G8B8X8_UNORM = 235,
181 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
182 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
183 ISL_FORMAT_B10G10R10X2_UNORM = 238,
184 ISL_FORMAT_L16A16_FLOAT = 240,
185 ISL_FORMAT_R32_UNORM = 241,
186 ISL_FORMAT_R32_SNORM = 242,
187 ISL_FORMAT_R10G10B10X2_USCALED = 243,
188 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
189 ISL_FORMAT_R8G8B8A8_USCALED = 245,
190 ISL_FORMAT_R16G16_SSCALED = 246,
191 ISL_FORMAT_R16G16_USCALED = 247,
192 ISL_FORMAT_R32_SSCALED = 248,
193 ISL_FORMAT_R32_USCALED = 249,
194 ISL_FORMAT_B5G6R5_UNORM = 256,
195 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
196 ISL_FORMAT_B5G5R5A1_UNORM = 258,
197 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
198 ISL_FORMAT_B4G4R4A4_UNORM = 260,
199 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
200 ISL_FORMAT_R8G8_UNORM = 262,
201 ISL_FORMAT_R8G8_SNORM = 263,
202 ISL_FORMAT_R8G8_SINT = 264,
203 ISL_FORMAT_R8G8_UINT = 265,
204 ISL_FORMAT_R16_UNORM = 266,
205 ISL_FORMAT_R16_SNORM = 267,
206 ISL_FORMAT_R16_SINT = 268,
207 ISL_FORMAT_R16_UINT = 269,
208 ISL_FORMAT_R16_FLOAT = 270,
209 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
210 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
211 ISL_FORMAT_I16_UNORM = 273,
212 ISL_FORMAT_L16_UNORM = 274,
213 ISL_FORMAT_A16_UNORM = 275,
214 ISL_FORMAT_L8A8_UNORM = 276,
215 ISL_FORMAT_I16_FLOAT = 277,
216 ISL_FORMAT_L16_FLOAT = 278,
217 ISL_FORMAT_A16_FLOAT = 279,
218 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
219 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
220 ISL_FORMAT_B5G5R5X1_UNORM = 282,
221 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
222 ISL_FORMAT_R8G8_SSCALED = 284,
223 ISL_FORMAT_R8G8_USCALED = 285,
224 ISL_FORMAT_R16_SSCALED = 286,
225 ISL_FORMAT_R16_USCALED = 287,
226 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
227 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
228 ISL_FORMAT_A1B5G5R5_UNORM = 292,
229 ISL_FORMAT_A4B4G4R4_UNORM = 293,
230 ISL_FORMAT_L8A8_UINT = 294,
231 ISL_FORMAT_L8A8_SINT = 295,
232 ISL_FORMAT_R8_UNORM = 320,
233 ISL_FORMAT_R8_SNORM = 321,
234 ISL_FORMAT_R8_SINT = 322,
235 ISL_FORMAT_R8_UINT = 323,
236 ISL_FORMAT_A8_UNORM = 324,
237 ISL_FORMAT_I8_UNORM = 325,
238 ISL_FORMAT_L8_UNORM = 326,
239 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
240 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
241 ISL_FORMAT_R8_SSCALED = 329,
242 ISL_FORMAT_R8_USCALED = 330,
243 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
244 ISL_FORMAT_L8_UNORM_SRGB = 332,
245 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
246 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
247 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
248 ISL_FORMAT_Y8_UNORM = 336,
249 ISL_FORMAT_L8_UINT = 338,
250 ISL_FORMAT_L8_SINT = 339,
251 ISL_FORMAT_I8_UINT = 340,
252 ISL_FORMAT_I8_SINT = 341,
253 ISL_FORMAT_DXT1_RGB_SRGB = 384,
254 ISL_FORMAT_R1_UNORM = 385,
255 ISL_FORMAT_YCRCB_NORMAL = 386,
256 ISL_FORMAT_YCRCB_SWAPUVY = 387,
257 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
258 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
259 ISL_FORMAT_BC1_UNORM = 390,
260 ISL_FORMAT_BC2_UNORM = 391,
261 ISL_FORMAT_BC3_UNORM = 392,
262 ISL_FORMAT_BC4_UNORM = 393,
263 ISL_FORMAT_BC5_UNORM = 394,
264 ISL_FORMAT_BC1_UNORM_SRGB = 395,
265 ISL_FORMAT_BC2_UNORM_SRGB = 396,
266 ISL_FORMAT_BC3_UNORM_SRGB = 397,
267 ISL_FORMAT_MONO8 = 398,
268 ISL_FORMAT_YCRCB_SWAPUV = 399,
269 ISL_FORMAT_YCRCB_SWAPY = 400,
270 ISL_FORMAT_DXT1_RGB = 401,
271 ISL_FORMAT_FXT1 = 402,
272 ISL_FORMAT_R8G8B8_UNORM = 403,
273 ISL_FORMAT_R8G8B8_SNORM = 404,
274 ISL_FORMAT_R8G8B8_SSCALED = 405,
275 ISL_FORMAT_R8G8B8_USCALED = 406,
276 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
277 ISL_FORMAT_R64G64B64_FLOAT = 408,
278 ISL_FORMAT_BC4_SNORM = 409,
279 ISL_FORMAT_BC5_SNORM = 410,
280 ISL_FORMAT_R16G16B16_FLOAT = 411,
281 ISL_FORMAT_R16G16B16_UNORM = 412,
282 ISL_FORMAT_R16G16B16_SNORM = 413,
283 ISL_FORMAT_R16G16B16_SSCALED = 414,
284 ISL_FORMAT_R16G16B16_USCALED = 415,
285 ISL_FORMAT_BC6H_SF16 = 417,
286 ISL_FORMAT_BC7_UNORM = 418,
287 ISL_FORMAT_BC7_UNORM_SRGB = 419,
288 ISL_FORMAT_BC6H_UF16 = 420,
289 ISL_FORMAT_PLANAR_420_8 = 421,
290 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
291 ISL_FORMAT_ETC1_RGB8 = 425,
292 ISL_FORMAT_ETC2_RGB8 = 426,
293 ISL_FORMAT_EAC_R11 = 427,
294 ISL_FORMAT_EAC_RG11 = 428,
295 ISL_FORMAT_EAC_SIGNED_R11 = 429,
296 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
297 ISL_FORMAT_ETC2_SRGB8 = 431,
298 ISL_FORMAT_R16G16B16_UINT = 432,
299 ISL_FORMAT_R16G16B16_SINT = 433,
300 ISL_FORMAT_R32_SFIXED = 434,
301 ISL_FORMAT_R10G10B10A2_SNORM = 435,
302 ISL_FORMAT_R10G10B10A2_USCALED = 436,
303 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
304 ISL_FORMAT_R10G10B10A2_SINT = 438,
305 ISL_FORMAT_B10G10R10A2_SNORM = 439,
306 ISL_FORMAT_B10G10R10A2_USCALED = 440,
307 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
308 ISL_FORMAT_B10G10R10A2_UINT = 442,
309 ISL_FORMAT_B10G10R10A2_SINT = 443,
310 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
311 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
312 ISL_FORMAT_ETC2_RGB8_PTA = 448,
313 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
314 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
315 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
316 ISL_FORMAT_R8G8B8_UINT = 456,
317 ISL_FORMAT_R8G8B8_SINT = 457,
318 ISL_FORMAT_RAW = 511,
319 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
320 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
321 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
322 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
323 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
324 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
325 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
326 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
327 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
328 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
329 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
330 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
331 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
332 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
347
348 /* The formats that follow are internal to ISL and as such don't have an
349 * explicit number. We'll just let the C compiler assign it for us. Any
350 * actual hardware formats *must* come before these in the list.
351 */
352
353 /* Formats for color compression surfaces */
354 ISL_FORMAT_HIZ,
355
356 /* Hardware doesn't understand this out-of-band value */
357 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
358 };
359
360 /**
361 * Numerical base type for channels of isl_format.
362 */
363 enum isl_base_type {
364 ISL_VOID,
365 ISL_RAW,
366 ISL_UNORM,
367 ISL_SNORM,
368 ISL_UFLOAT,
369 ISL_SFLOAT,
370 ISL_UFIXED,
371 ISL_SFIXED,
372 ISL_UINT,
373 ISL_SINT,
374 ISL_USCALED,
375 ISL_SSCALED,
376 };
377
378 /**
379 * Colorspace of isl_format.
380 */
381 enum isl_colorspace {
382 ISL_COLORSPACE_NONE = 0,
383 ISL_COLORSPACE_LINEAR,
384 ISL_COLORSPACE_SRGB,
385 ISL_COLORSPACE_YUV,
386 };
387
388 /**
389 * Texture compression mode of isl_format.
390 */
391 enum isl_txc {
392 ISL_TXC_NONE = 0,
393 ISL_TXC_DXT1,
394 ISL_TXC_DXT3,
395 ISL_TXC_DXT5,
396 ISL_TXC_FXT1,
397 ISL_TXC_RGTC1,
398 ISL_TXC_RGTC2,
399 ISL_TXC_BPTC,
400 ISL_TXC_ETC1,
401 ISL_TXC_ETC2,
402 ISL_TXC_ASTC,
403
404 /* Used for auxiliary surface formats */
405 ISL_TXC_HIZ,
406 };
407
408 /**
409 * @brief Hardware tile mode
410 *
411 * WARNING: These values differ from the hardware enum values, which are
412 * unstable across hardware generations.
413 *
414 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
415 * clearly distinguish it from Yf and Ys.
416 */
417 enum isl_tiling {
418 ISL_TILING_LINEAR = 0,
419 ISL_TILING_W,
420 ISL_TILING_X,
421 ISL_TILING_Y0, /**< Legacy Y tiling */
422 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
423 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
424 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
425 };
426
427 /**
428 * @defgroup Tiling Flags
429 * @{
430 */
431 typedef uint32_t isl_tiling_flags_t;
432 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
433 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
434 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
435 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
436 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
437 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
438 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
439 #define ISL_TILING_ANY_MASK (~0u)
440 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
441
442 /** Any Y tiling, including legacy Y tiling. */
443 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
444 ISL_TILING_Yf_BIT | \
445 ISL_TILING_Ys_BIT)
446
447 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
448 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
449 ISL_TILING_Ys_BIT)
450 /** @} */
451
452 /**
453 * @brief Logical dimension of surface.
454 *
455 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
456 * as 2D array surfaces.
457 */
458 enum isl_surf_dim {
459 ISL_SURF_DIM_1D,
460 ISL_SURF_DIM_2D,
461 ISL_SURF_DIM_3D,
462 };
463
464 /**
465 * @brief Physical layout of the surface's dimensions.
466 */
467 enum isl_dim_layout {
468 /**
469 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
470 * 6.17.3: 2D Surfaces.
471 *
472 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
473 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
474 *
475 * One-dimensional surfaces are identical to 2D surfaces with height of
476 * one.
477 *
478 * @invariant isl_surf::phys_level0_sa::depth == 1
479 */
480 ISL_DIM_LAYOUT_GEN4_2D,
481
482 /**
483 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
484 * 6.17.5: 3D Surfaces.
485 *
486 * @invariant isl_surf::phys_level0_sa::array_len == 1
487 */
488 ISL_DIM_LAYOUT_GEN4_3D,
489
490 /**
491 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
492 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
493 */
494 ISL_DIM_LAYOUT_GEN9_1D,
495 };
496
497 /* TODO(chadv): Explain */
498 enum isl_array_pitch_span {
499 ISL_ARRAY_PITCH_SPAN_FULL,
500 ISL_ARRAY_PITCH_SPAN_COMPACT,
501 };
502
503 /**
504 * @defgroup Surface Usage
505 * @{
506 */
507 typedef uint64_t isl_surf_usage_flags_t;
508 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
509 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
510 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
511 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
512 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
513 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
514 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
515 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
516 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
517 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
518 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
519 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
520 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
521 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
522 /** @} */
523
524 /**
525 * @brief A channel select (also known as texture swizzle) value
526 */
527 enum isl_channel_select {
528 ISL_CHANNEL_SELECT_ZERO = 0,
529 ISL_CHANNEL_SELECT_ONE = 1,
530 ISL_CHANNEL_SELECT_RED = 4,
531 ISL_CHANNEL_SELECT_GREEN = 5,
532 ISL_CHANNEL_SELECT_BLUE = 6,
533 ISL_CHANNEL_SELECT_ALPHA = 7,
534 };
535
536 /**
537 * Identical to VkSampleCountFlagBits.
538 */
539 enum isl_sample_count {
540 ISL_SAMPLE_COUNT_1_BIT = 1u,
541 ISL_SAMPLE_COUNT_2_BIT = 2u,
542 ISL_SAMPLE_COUNT_4_BIT = 4u,
543 ISL_SAMPLE_COUNT_8_BIT = 8u,
544 ISL_SAMPLE_COUNT_16_BIT = 16u,
545 };
546 typedef uint32_t isl_sample_count_mask_t;
547
548 /**
549 * @brief Multisample Format
550 */
551 enum isl_msaa_layout {
552 /**
553 * @brief Suface is single-sampled.
554 */
555 ISL_MSAA_LAYOUT_NONE,
556
557 /**
558 * @brief [SNB+] Interleaved Multisample Format
559 *
560 * In this format, multiple samples are interleaved into each cacheline.
561 * In other words, the sample index is swizzled into the low 6 bits of the
562 * surface's virtual address space.
563 *
564 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
565 * and its pixel format is 32bpp. Then the first cacheline is arranged
566 * thus:
567 *
568 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
569 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
570 *
571 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
572 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
573 *
574 * The hardware docs refer to this format with multiple terms. In
575 * Sandybridge, this is the only multisample format; so no term is used.
576 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
577 * Multisample Surface). Later hardware docs additionally refer to this
578 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
579 * color surfaces).
580 *
581 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
582 * Surface Behavior".
583 *
584 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
585 * Multisampled Surfaces".
586 */
587 ISL_MSAA_LAYOUT_INTERLEAVED,
588
589 /**
590 * @brief [IVB+] Array Multisample Format
591 *
592 * In this format, the surface's physical layout resembles that of a
593 * 2D array surface.
594 *
595 * Suppose the multisample surface's logical extent is (w, h) and its
596 * sample count is N. Then surface's physical extent is the same as
597 * a singlesample 2D surface whose logical extent is (w, h) and array
598 * length is N. Array slice `i` contains the pixel values for sample
599 * index `i`.
600 *
601 * The Ivybridge docs refer to surfaces in this format as UMS
602 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
603 * Surface). The Broadwell docs additionally refer to this format as
604 * MSFMT_MSS (MSS=Multisample Surface Storage).
605 *
606 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
607 * Multisample Surfaces".
608 *
609 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
610 * Multisample Surfaces".
611 */
612 ISL_MSAA_LAYOUT_ARRAY,
613 };
614
615
616 struct isl_device {
617 const struct brw_device_info *info;
618 bool use_separate_stencil;
619 bool has_bit6_swizzling;
620 };
621
622 struct isl_extent2d {
623 union { uint32_t w, width; };
624 union { uint32_t h, height; };
625 };
626
627 struct isl_extent3d {
628 union { uint32_t w, width; };
629 union { uint32_t h, height; };
630 union { uint32_t d, depth; };
631 };
632
633 struct isl_extent4d {
634 union { uint32_t w, width; };
635 union { uint32_t h, height; };
636 union { uint32_t d, depth; };
637 union { uint32_t a, array_len; };
638 };
639
640 struct isl_channel_layout {
641 enum isl_base_type type;
642 uint8_t bits; /**< Size in bits */
643 };
644
645 /**
646 * Each format has 3D block extent (width, height, depth). The block extent of
647 * compressed formats is that of the format's compression block. For example,
648 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
649 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
650 * is (w=1, h=1, d=1).
651 */
652 struct isl_format_layout {
653 enum isl_format format;
654 const char *name;
655
656 uint16_t bpb; /**< Bits per block */
657 uint8_t bw; /**< Block width, in pixels */
658 uint8_t bh; /**< Block height, in pixels */
659 uint8_t bd; /**< Block depth, in pixels */
660
661 struct {
662 struct isl_channel_layout r; /**< Red channel */
663 struct isl_channel_layout g; /**< Green channel */
664 struct isl_channel_layout b; /**< Blue channel */
665 struct isl_channel_layout a; /**< Alpha channel */
666 struct isl_channel_layout l; /**< Luminance channel */
667 struct isl_channel_layout i; /**< Intensity channel */
668 struct isl_channel_layout p; /**< Palette channel */
669 } channels;
670
671 enum isl_colorspace colorspace;
672 enum isl_txc txc;
673 };
674
675 struct isl_tile_info {
676 enum isl_tiling tiling;
677
678 /** The logical size of the tile in units of surface elements
679 *
680 * This field determines how a given surface is cut up into tiles. It is
681 * used to compute the size of a surface in tiles and can be used to
682 * determine the location of the tile containing any given surface element.
683 * The exact value of this field depends heavily on the bits-per-block of
684 * the format being used.
685 */
686 struct isl_extent2d logical_extent_el;
687
688 /** The physical size of the tile in bytes and rows of bytes
689 *
690 * This field determines how the tiles of a surface are physically layed
691 * out in memory. The logical and physical tile extent are frequently the
692 * same but this is not always the case. For instance, a W-tile (which is
693 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
694 * its physical size is 128B x 32rows, the same as a Y-tile.
695 *
696 * @see isl_surf::row_pitch
697 */
698 struct isl_extent2d phys_extent_B;
699 };
700
701 /**
702 * @brief Input to surface initialization
703 *
704 * @invariant width >= 1
705 * @invariant height >= 1
706 * @invariant depth >= 1
707 * @invariant levels >= 1
708 * @invariant samples >= 1
709 * @invariant array_len >= 1
710 *
711 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
712 * @invariant if 2D then depth == 1
713 * @invariant if 3D then array_len == 1 and samples == 1
714 */
715 struct isl_surf_init_info {
716 enum isl_surf_dim dim;
717 enum isl_format format;
718
719 uint32_t width;
720 uint32_t height;
721 uint32_t depth;
722 uint32_t levels;
723 uint32_t array_len;
724 uint32_t samples;
725
726 /** Lower bound for isl_surf::alignment, in bytes. */
727 uint32_t min_alignment;
728
729 /** Lower bound for isl_surf::pitch, in bytes. */
730 uint32_t min_pitch;
731
732 isl_surf_usage_flags_t usage;
733
734 /** Flags that alter how ISL selects isl_surf::tiling. */
735 isl_tiling_flags_t tiling_flags;
736 };
737
738 struct isl_surf {
739 enum isl_surf_dim dim;
740 enum isl_dim_layout dim_layout;
741 enum isl_msaa_layout msaa_layout;
742 enum isl_tiling tiling;
743 enum isl_format format;
744
745 /**
746 * Alignment of the upper-left sample of each subimage, in units of surface
747 * elements.
748 */
749 struct isl_extent3d image_alignment_el;
750
751 /**
752 * Logical extent of the surface's base level, in units of pixels. This is
753 * identical to the extent defined in isl_surf_init_info.
754 */
755 struct isl_extent4d logical_level0_px;
756
757 /**
758 * Physical extent of the surface's base level, in units of physical
759 * surface samples and aligned to the format's compression block.
760 *
761 * Consider isl_dim_layout as an operator that transforms a logical surface
762 * layout to a physical surface layout. Then
763 *
764 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
765 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
766 */
767 struct isl_extent4d phys_level0_sa;
768
769 uint32_t levels;
770 uint32_t samples;
771
772 /** Total size of the surface, in bytes. */
773 uint32_t size;
774
775 /** Required alignment for the surface's base address. */
776 uint32_t alignment;
777
778 /**
779 * The interpretation of this field depends on the value of
780 * isl_tile_info::physical_extent_B. In particular, the width of the
781 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
782 * and the distance in bytes between vertically adjacent tiles in the image
783 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
784 *
785 * For linear images where isl_tile_info::physical_extent_B.height == 1,
786 * this cleanly reduces to being the distance, in bytes, between vertically
787 * adjacent surface elements.
788 *
789 * @see isl_tile_info::phys_extent_B;
790 */
791 uint32_t row_pitch;
792
793 /**
794 * Pitch between physical array slices, in rows of surface elements.
795 */
796 uint32_t array_pitch_el_rows;
797
798 enum isl_array_pitch_span array_pitch_span;
799
800 /** Copy of isl_surf_init_info::usage. */
801 isl_surf_usage_flags_t usage;
802 };
803
804 struct isl_view {
805 /**
806 * Indicates the usage of the particular view
807 *
808 * Normally, this is one bit. However, for a cube map texture, it
809 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
810 */
811 isl_surf_usage_flags_t usage;
812
813 /**
814 * The format to use in the view
815 *
816 * This may differ from the format of the actual isl_surf but must have
817 * the same block size.
818 */
819 enum isl_format format;
820
821 uint32_t base_level;
822 uint32_t levels;
823
824 /**
825 * Base array layer
826 *
827 * For cube maps, both base_array_layer and array_len should be
828 * specified in terms of 2-D layers and must be a multiple of 6.
829 */
830 uint32_t base_array_layer;
831 uint32_t array_len;
832
833 enum isl_channel_select channel_select[4];
834 };
835
836 union isl_color_value {
837 float f32[4];
838 uint32_t u32[4];
839 int32_t i32[4];
840 };
841
842 struct isl_surf_fill_state_info {
843 const struct isl_surf *surf;
844 const struct isl_view *view;
845
846 /**
847 * The address of the surface in GPU memory.
848 */
849 uint64_t address;
850
851 /**
852 * The Memory Object Control state for the filled surface state.
853 *
854 * The exact format of this value depends on hardware generation.
855 */
856 uint32_t mocs;
857
858 /**
859 * The clear color for this surface
860 *
861 * Valid values depend on hardware generation.
862 */
863 union isl_color_value clear_color;
864 };
865
866 struct isl_buffer_fill_state_info {
867 /**
868 * The address of the surface in GPU memory.
869 */
870 uint64_t address;
871
872 /**
873 * The size of the buffer
874 */
875 uint64_t size;
876
877 /**
878 * The Memory Object Control state for the filled surface state.
879 *
880 * The exact format of this value depends on hardware generation.
881 */
882 uint32_t mocs;
883
884 /**
885 * The format to use in the surface state
886 *
887 * This may differ from the format of the actual isl_surf but have the
888 * same block size.
889 */
890 enum isl_format format;
891
892 uint32_t stride;
893 };
894
895 extern const struct isl_format_layout isl_format_layouts[];
896
897 void
898 isl_device_init(struct isl_device *dev,
899 const struct brw_device_info *info,
900 bool has_bit6_swizzling);
901
902 isl_sample_count_mask_t ATTRIBUTE_CONST
903 isl_device_get_sample_counts(struct isl_device *dev);
904
905 static inline const struct isl_format_layout * ATTRIBUTE_CONST
906 isl_format_get_layout(enum isl_format fmt)
907 {
908 return &isl_format_layouts[fmt];
909 }
910
911 static inline const char * ATTRIBUTE_CONST
912 isl_format_get_name(enum isl_format fmt)
913 {
914 return isl_format_layouts[fmt].name;
915 }
916
917 bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
918 enum isl_format format);
919 bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
920 enum isl_format format);
921 bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
922 enum isl_format format);
923 bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
924 enum isl_format format);
925 bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
926 enum isl_format format);
927 bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
928 enum isl_format format);
929
930 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
931 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
932 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
933 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
934 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
935 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
936
937 static inline bool
938 isl_format_has_normalized_channel(enum isl_format fmt)
939 {
940 return isl_format_has_unorm_channel(fmt) ||
941 isl_format_has_snorm_channel(fmt);
942 }
943
944 static inline bool
945 isl_format_has_float_channel(enum isl_format fmt)
946 {
947 return isl_format_has_ufloat_channel(fmt) ||
948 isl_format_has_sfloat_channel(fmt);
949 }
950
951 static inline bool
952 isl_format_has_int_channel(enum isl_format fmt)
953 {
954 return isl_format_has_uint_channel(fmt) ||
955 isl_format_has_sint_channel(fmt);
956 }
957
958 unsigned isl_format_get_num_channels(enum isl_format fmt);
959
960 static inline bool
961 isl_format_is_compressed(enum isl_format fmt)
962 {
963 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
964
965 return fmtl->txc != ISL_TXC_NONE;
966 }
967
968 static inline bool
969 isl_format_has_bc_compression(enum isl_format fmt)
970 {
971 switch (isl_format_get_layout(fmt)->txc) {
972 case ISL_TXC_DXT1:
973 case ISL_TXC_DXT3:
974 case ISL_TXC_DXT5:
975 return true;
976 case ISL_TXC_NONE:
977 case ISL_TXC_FXT1:
978 case ISL_TXC_RGTC1:
979 case ISL_TXC_RGTC2:
980 case ISL_TXC_BPTC:
981 case ISL_TXC_ETC1:
982 case ISL_TXC_ETC2:
983 case ISL_TXC_ASTC:
984 return false;
985
986 case ISL_TXC_HIZ:
987 unreachable("Should not be called on an aux surface");
988 }
989
990 unreachable("bad texture compression mode");
991 return false;
992 }
993
994 static inline bool
995 isl_format_is_yuv(enum isl_format fmt)
996 {
997 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
998
999 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1000 }
1001
1002 static inline bool
1003 isl_format_block_is_1x1x1(enum isl_format fmt)
1004 {
1005 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1006
1007 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1008 }
1009
1010 static inline bool
1011 isl_format_is_rgb(enum isl_format fmt)
1012 {
1013 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1014 isl_format_layouts[fmt].channels.g.bits > 0 &&
1015 isl_format_layouts[fmt].channels.b.bits > 0 &&
1016 isl_format_layouts[fmt].channels.a.bits == 0;
1017 }
1018
1019 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1020 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1021
1022 bool isl_is_storage_image_format(enum isl_format fmt);
1023
1024 enum isl_format
1025 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
1026 enum isl_format fmt);
1027
1028 /* Returns true if this hardware supports typed load/store on a format with
1029 * the same size as the given format.
1030 */
1031 bool
1032 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
1033 enum isl_format fmt);
1034
1035 static inline bool
1036 isl_tiling_is_any_y(enum isl_tiling tiling)
1037 {
1038 return (1u << tiling) & ISL_TILING_ANY_MASK;
1039 }
1040
1041 static inline bool
1042 isl_tiling_is_std_y(enum isl_tiling tiling)
1043 {
1044 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1045 }
1046
1047 bool
1048 isl_tiling_get_info(const struct isl_device *dev,
1049 enum isl_tiling tiling,
1050 uint32_t format_bpb,
1051 struct isl_tile_info *info);
1052 bool
1053 isl_surf_choose_tiling(const struct isl_device *dev,
1054 const struct isl_surf_init_info *restrict info,
1055 enum isl_tiling *tiling);
1056
1057 static inline bool
1058 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1059 {
1060 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1061 }
1062
1063 static inline bool
1064 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1065 {
1066 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1067 }
1068
1069 static inline bool
1070 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1071 {
1072 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1073 }
1074
1075 static inline bool
1076 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1077 {
1078 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1079 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1080 }
1081
1082 static inline bool
1083 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1084 {
1085 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1086 }
1087
1088 static inline bool
1089 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1090 {
1091 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1092 (info->format == ISL_FORMAT_R16_UNORM);
1093 }
1094
1095 static inline bool
1096 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1097 {
1098 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1099 (info->format == ISL_FORMAT_R32_FLOAT);
1100 }
1101
1102 static inline struct isl_extent2d
1103 isl_extent2d(uint32_t width, uint32_t height)
1104 {
1105 struct isl_extent2d e = { { 0 } };
1106
1107 e.width = width;
1108 e.height = height;
1109
1110 return e;
1111 }
1112
1113 static inline struct isl_extent3d
1114 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1115 {
1116 struct isl_extent3d e = { { 0 } };
1117
1118 e.width = width;
1119 e.height = height;
1120 e.depth = depth;
1121
1122 return e;
1123 }
1124
1125 static inline struct isl_extent4d
1126 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1127 uint32_t array_len)
1128 {
1129 struct isl_extent4d e = { { 0 } };
1130
1131 e.width = width;
1132 e.height = height;
1133 e.depth = depth;
1134 e.array_len = array_len;
1135
1136 return e;
1137 }
1138
1139 #define isl_surf_init(dev, surf, ...) \
1140 isl_surf_init_s((dev), (surf), \
1141 &(struct isl_surf_init_info) { __VA_ARGS__ });
1142
1143 bool
1144 isl_surf_init_s(const struct isl_device *dev,
1145 struct isl_surf *surf,
1146 const struct isl_surf_init_info *restrict info);
1147
1148 void
1149 isl_surf_get_tile_info(const struct isl_device *dev,
1150 const struct isl_surf *surf,
1151 struct isl_tile_info *tile_info);
1152
1153 #define isl_surf_fill_state(dev, state, ...) \
1154 isl_surf_fill_state_s((dev), (state), \
1155 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1156
1157 void
1158 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1159 const struct isl_surf_fill_state_info *restrict info);
1160
1161 #define isl_buffer_fill_state(dev, state, ...) \
1162 isl_buffer_fill_state_s((dev), (state), \
1163 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1164
1165 void
1166 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1167 const struct isl_buffer_fill_state_info *restrict info);
1168
1169 void
1170 isl_surf_fill_image_param(const struct isl_device *dev,
1171 struct brw_image_param *param,
1172 const struct isl_surf *surf,
1173 const struct isl_view *view);
1174
1175 void
1176 isl_buffer_fill_image_param(const struct isl_device *dev,
1177 struct brw_image_param *param,
1178 enum isl_format format,
1179 uint64_t size);
1180
1181 /**
1182 * Alignment of the upper-left sample of each subimage, in units of surface
1183 * elements.
1184 */
1185 static inline struct isl_extent3d
1186 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1187 {
1188 return surf->image_alignment_el;
1189 }
1190
1191 /**
1192 * Alignment of the upper-left sample of each subimage, in units of surface
1193 * samples.
1194 */
1195 static inline struct isl_extent3d
1196 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1197 {
1198 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1199
1200 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1201 fmtl->bh * surf->image_alignment_el.h,
1202 fmtl->bd * surf->image_alignment_el.d);
1203 }
1204
1205 /**
1206 * Pitch between vertically adjacent surface elements, in bytes.
1207 */
1208 static inline uint32_t
1209 isl_surf_get_row_pitch(const struct isl_surf *surf)
1210 {
1211 return surf->row_pitch;
1212 }
1213
1214 /**
1215 * Pitch between vertically adjacent surface elements, in units of surface elements.
1216 */
1217 static inline uint32_t
1218 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1219 {
1220 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1221
1222 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1223 return surf->row_pitch / (fmtl->bpb / 8);
1224 }
1225
1226 /**
1227 * Pitch between physical array slices, in rows of surface elements.
1228 */
1229 static inline uint32_t
1230 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1231 {
1232 return surf->array_pitch_el_rows;
1233 }
1234
1235 /**
1236 * Pitch between physical array slices, in units of surface elements.
1237 */
1238 static inline uint32_t
1239 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1240 {
1241 return isl_surf_get_array_pitch_el_rows(surf) *
1242 isl_surf_get_row_pitch_el(surf);
1243 }
1244
1245 /**
1246 * Pitch between physical array slices, in rows of surface samples.
1247 */
1248 static inline uint32_t
1249 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1250 {
1251 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1252 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1253 }
1254
1255 /**
1256 * Pitch between physical array slices, in bytes.
1257 */
1258 static inline uint32_t
1259 isl_surf_get_array_pitch(const struct isl_surf *surf)
1260 {
1261 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1262 }
1263
1264 /**
1265 * Calculate the offset, in units of surface elements, to a subimage in the
1266 * surface.
1267 *
1268 * @invariant level < surface levels
1269 * @invariant logical_array_layer < logical array length of surface
1270 * @invariant logical_z_offset_px < logical depth of surface at level
1271 */
1272 void
1273 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1274 uint32_t level,
1275 uint32_t logical_array_layer,
1276 uint32_t logical_z_offset_px,
1277 uint32_t *x_offset_el,
1278 uint32_t *y_offset_el);
1279
1280 /**
1281 * @brief Calculate the intratile offsets to a surface.
1282 *
1283 * In @a base_address_offset return the offset from the base of the surface to
1284 * the base address of the first tile of the subimage. In @a x_offset_B and
1285 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1286 * tile's base to the subimage's first surface element. The x and y offsets
1287 * are intratile offsets; that is, they do not exceed the boundary of the
1288 * surface's tiling format.
1289 */
1290 void
1291 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1292 enum isl_tiling tiling,
1293 uint8_t bs,
1294 uint32_t row_pitch,
1295 uint32_t total_x_offset_B,
1296 uint32_t total_y_offset_rows,
1297 uint32_t *base_address_offset,
1298 uint32_t *x_offset_B,
1299 uint32_t *y_offset_rows);
1300
1301 /**
1302 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1303 *
1304 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1305 * @pre surf->format must be a valid format for depth surfaces
1306 */
1307 uint32_t
1308 isl_surf_get_depth_format(const struct isl_device *dev,
1309 const struct isl_surf *surf);
1310
1311 #ifdef __cplusplus
1312 }
1313 #endif