2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
44 #include "c99_compat.h"
45 #include "util/macros.h"
51 struct brw_device_info
;
52 struct brw_image_param
;
56 * @brief Get the hardware generation of isl_device.
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
64 #ifndef ISL_DEV_IS_HASWELL
66 * @brief Get the hardware generation of isl_device.
68 * You can define this as a compile-time constant in the CFLAGS. For example,
69 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
71 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
74 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
76 * You can define this as a compile-time constant in the CFLAGS. For example,
77 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
79 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
83 * Hardware enumeration SURFACE_FORMAT.
85 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
86 * Enumerations: SURFACE_FORMAT.
89 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
90 ISL_FORMAT_R32G32B32A32_SINT
= 1,
91 ISL_FORMAT_R32G32B32A32_UINT
= 2,
92 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
93 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
94 ISL_FORMAT_R64G64_FLOAT
= 5,
95 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
96 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
97 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
98 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
99 ISL_FORMAT_R64G64_PASSTHRU
= 33,
100 ISL_FORMAT_R32G32B32_FLOAT
= 64,
101 ISL_FORMAT_R32G32B32_SINT
= 65,
102 ISL_FORMAT_R32G32B32_UINT
= 66,
103 ISL_FORMAT_R32G32B32_UNORM
= 67,
104 ISL_FORMAT_R32G32B32_SNORM
= 68,
105 ISL_FORMAT_R32G32B32_SSCALED
= 69,
106 ISL_FORMAT_R32G32B32_USCALED
= 70,
107 ISL_FORMAT_R32G32B32_SFIXED
= 80,
108 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
109 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
110 ISL_FORMAT_R16G16B16A16_SINT
= 130,
111 ISL_FORMAT_R16G16B16A16_UINT
= 131,
112 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
113 ISL_FORMAT_R32G32_FLOAT
= 133,
114 ISL_FORMAT_R32G32_SINT
= 134,
115 ISL_FORMAT_R32G32_UINT
= 135,
116 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
117 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
118 ISL_FORMAT_L32A32_FLOAT
= 138,
119 ISL_FORMAT_R32G32_UNORM
= 139,
120 ISL_FORMAT_R32G32_SNORM
= 140,
121 ISL_FORMAT_R64_FLOAT
= 141,
122 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
123 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
124 ISL_FORMAT_A32X32_FLOAT
= 144,
125 ISL_FORMAT_L32X32_FLOAT
= 145,
126 ISL_FORMAT_I32X32_FLOAT
= 146,
127 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
128 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
129 ISL_FORMAT_R32G32_SSCALED
= 149,
130 ISL_FORMAT_R32G32_USCALED
= 150,
131 ISL_FORMAT_R32G32_SFIXED
= 160,
132 ISL_FORMAT_R64_PASSTHRU
= 161,
133 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
134 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
135 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
136 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
137 ISL_FORMAT_R10G10B10A2_UINT
= 196,
138 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
139 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
140 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
141 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
142 ISL_FORMAT_R8G8B8A8_SINT
= 202,
143 ISL_FORMAT_R8G8B8A8_UINT
= 203,
144 ISL_FORMAT_R16G16_UNORM
= 204,
145 ISL_FORMAT_R16G16_SNORM
= 205,
146 ISL_FORMAT_R16G16_SINT
= 206,
147 ISL_FORMAT_R16G16_UINT
= 207,
148 ISL_FORMAT_R16G16_FLOAT
= 208,
149 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
150 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
151 ISL_FORMAT_R11G11B10_FLOAT
= 211,
152 ISL_FORMAT_R32_SINT
= 214,
153 ISL_FORMAT_R32_UINT
= 215,
154 ISL_FORMAT_R32_FLOAT
= 216,
155 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
156 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
157 ISL_FORMAT_L32_UNORM
= 221,
158 ISL_FORMAT_A32_UNORM
= 222,
159 ISL_FORMAT_L16A16_UNORM
= 223,
160 ISL_FORMAT_I24X8_UNORM
= 224,
161 ISL_FORMAT_L24X8_UNORM
= 225,
162 ISL_FORMAT_A24X8_UNORM
= 226,
163 ISL_FORMAT_I32_FLOAT
= 227,
164 ISL_FORMAT_L32_FLOAT
= 228,
165 ISL_FORMAT_A32_FLOAT
= 229,
166 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
167 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
168 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
169 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
170 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
171 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
172 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
173 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
174 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
175 ISL_FORMAT_L16A16_FLOAT
= 240,
176 ISL_FORMAT_R32_UNORM
= 241,
177 ISL_FORMAT_R32_SNORM
= 242,
178 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
179 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
180 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
181 ISL_FORMAT_R16G16_SSCALED
= 246,
182 ISL_FORMAT_R16G16_USCALED
= 247,
183 ISL_FORMAT_R32_SSCALED
= 248,
184 ISL_FORMAT_R32_USCALED
= 249,
185 ISL_FORMAT_B5G6R5_UNORM
= 256,
186 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
187 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
188 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
189 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
190 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
191 ISL_FORMAT_R8G8_UNORM
= 262,
192 ISL_FORMAT_R8G8_SNORM
= 263,
193 ISL_FORMAT_R8G8_SINT
= 264,
194 ISL_FORMAT_R8G8_UINT
= 265,
195 ISL_FORMAT_R16_UNORM
= 266,
196 ISL_FORMAT_R16_SNORM
= 267,
197 ISL_FORMAT_R16_SINT
= 268,
198 ISL_FORMAT_R16_UINT
= 269,
199 ISL_FORMAT_R16_FLOAT
= 270,
200 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
201 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
202 ISL_FORMAT_I16_UNORM
= 273,
203 ISL_FORMAT_L16_UNORM
= 274,
204 ISL_FORMAT_A16_UNORM
= 275,
205 ISL_FORMAT_L8A8_UNORM
= 276,
206 ISL_FORMAT_I16_FLOAT
= 277,
207 ISL_FORMAT_L16_FLOAT
= 278,
208 ISL_FORMAT_A16_FLOAT
= 279,
209 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
210 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
211 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
212 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
213 ISL_FORMAT_R8G8_SSCALED
= 284,
214 ISL_FORMAT_R8G8_USCALED
= 285,
215 ISL_FORMAT_R16_SSCALED
= 286,
216 ISL_FORMAT_R16_USCALED
= 287,
217 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
218 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
219 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
220 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
221 ISL_FORMAT_L8A8_UINT
= 294,
222 ISL_FORMAT_L8A8_SINT
= 295,
223 ISL_FORMAT_R8_UNORM
= 320,
224 ISL_FORMAT_R8_SNORM
= 321,
225 ISL_FORMAT_R8_SINT
= 322,
226 ISL_FORMAT_R8_UINT
= 323,
227 ISL_FORMAT_A8_UNORM
= 324,
228 ISL_FORMAT_I8_UNORM
= 325,
229 ISL_FORMAT_L8_UNORM
= 326,
230 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
231 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
232 ISL_FORMAT_R8_SSCALED
= 329,
233 ISL_FORMAT_R8_USCALED
= 330,
234 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
235 ISL_FORMAT_L8_UNORM_SRGB
= 332,
236 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
237 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
238 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
239 ISL_FORMAT_Y8_UNORM
= 336,
240 ISL_FORMAT_L8_UINT
= 338,
241 ISL_FORMAT_L8_SINT
= 339,
242 ISL_FORMAT_I8_UINT
= 340,
243 ISL_FORMAT_I8_SINT
= 341,
244 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
245 ISL_FORMAT_R1_UNORM
= 385,
246 ISL_FORMAT_YCRCB_NORMAL
= 386,
247 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
248 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
249 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
250 ISL_FORMAT_BC1_UNORM
= 390,
251 ISL_FORMAT_BC2_UNORM
= 391,
252 ISL_FORMAT_BC3_UNORM
= 392,
253 ISL_FORMAT_BC4_UNORM
= 393,
254 ISL_FORMAT_BC5_UNORM
= 394,
255 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
256 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
257 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
258 ISL_FORMAT_MONO8
= 398,
259 ISL_FORMAT_YCRCB_SWAPUV
= 399,
260 ISL_FORMAT_YCRCB_SWAPY
= 400,
261 ISL_FORMAT_DXT1_RGB
= 401,
262 ISL_FORMAT_FXT1
= 402,
263 ISL_FORMAT_R8G8B8_UNORM
= 403,
264 ISL_FORMAT_R8G8B8_SNORM
= 404,
265 ISL_FORMAT_R8G8B8_SSCALED
= 405,
266 ISL_FORMAT_R8G8B8_USCALED
= 406,
267 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
268 ISL_FORMAT_R64G64B64_FLOAT
= 408,
269 ISL_FORMAT_BC4_SNORM
= 409,
270 ISL_FORMAT_BC5_SNORM
= 410,
271 ISL_FORMAT_R16G16B16_FLOAT
= 411,
272 ISL_FORMAT_R16G16B16_UNORM
= 412,
273 ISL_FORMAT_R16G16B16_SNORM
= 413,
274 ISL_FORMAT_R16G16B16_SSCALED
= 414,
275 ISL_FORMAT_R16G16B16_USCALED
= 415,
276 ISL_FORMAT_BC6H_SF16
= 417,
277 ISL_FORMAT_BC7_UNORM
= 418,
278 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
279 ISL_FORMAT_BC6H_UF16
= 420,
280 ISL_FORMAT_PLANAR_420_8
= 421,
281 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
282 ISL_FORMAT_ETC1_RGB8
= 425,
283 ISL_FORMAT_ETC2_RGB8
= 426,
284 ISL_FORMAT_EAC_R11
= 427,
285 ISL_FORMAT_EAC_RG11
= 428,
286 ISL_FORMAT_EAC_SIGNED_R11
= 429,
287 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
288 ISL_FORMAT_ETC2_SRGB8
= 431,
289 ISL_FORMAT_R16G16B16_UINT
= 432,
290 ISL_FORMAT_R16G16B16_SINT
= 433,
291 ISL_FORMAT_R32_SFIXED
= 434,
292 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
293 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
294 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
295 ISL_FORMAT_R10G10B10A2_SINT
= 438,
296 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
297 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
298 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
299 ISL_FORMAT_B10G10R10A2_UINT
= 442,
300 ISL_FORMAT_B10G10R10A2_SINT
= 443,
301 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
302 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
303 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
304 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
305 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
306 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
307 ISL_FORMAT_R8G8B8_UINT
= 456,
308 ISL_FORMAT_R8G8B8_SINT
= 457,
309 ISL_FORMAT_RAW
= 511,
311 /* Hardware doesn't understand this out-of-band value */
312 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
316 * Numerical base type for channels of isl_format.
334 * Colorspace of isl_format.
336 enum isl_colorspace
{
337 ISL_COLORSPACE_NONE
= 0,
338 ISL_COLORSPACE_LINEAR
,
344 * Texture compression mode of isl_format.
360 * @brief Hardware tile mode
362 * WARNING: These values differ from the hardware enum values, which are
363 * unstable across hardware generations.
365 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
366 * clearly distinguish it from Yf and Ys.
369 ISL_TILING_LINEAR
= 0,
372 ISL_TILING_Y0
, /**< Legacy Y tiling */
373 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
374 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
378 * @defgroup Tiling Flags
381 typedef uint32_t isl_tiling_flags_t
;
382 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
383 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
384 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
385 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
386 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
387 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
388 #define ISL_TILING_ANY_MASK (~0u)
389 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
391 /** Any Y tiling, including legacy Y tiling. */
392 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
393 ISL_TILING_Yf_BIT | \
396 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
397 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
402 * @brief Logical dimension of surface.
404 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
405 * as 2D array surfaces.
414 * @brief Physical layout of the surface's dimensions.
416 enum isl_dim_layout
{
418 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
419 * 6.17.3: 2D Surfaces.
421 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
422 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
424 * One-dimensional surfaces are identical to 2D surfaces with height of
427 * @invariant isl_surf::phys_level0_sa::depth == 1
429 ISL_DIM_LAYOUT_GEN4_2D
,
432 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
433 * 6.17.5: 3D Surfaces.
435 * @invariant isl_surf::phys_level0_sa::array_len == 1
437 ISL_DIM_LAYOUT_GEN4_3D
,
440 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
441 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
443 ISL_DIM_LAYOUT_GEN9_1D
,
446 /* TODO(chadv): Explain */
447 enum isl_array_pitch_span
{
448 ISL_ARRAY_PITCH_SPAN_FULL
,
449 ISL_ARRAY_PITCH_SPAN_COMPACT
,
453 * @defgroup Surface Usage
456 typedef uint64_t isl_surf_usage_flags_t
;
457 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
458 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
459 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
460 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
461 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
462 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
463 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
464 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
465 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
466 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
467 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
468 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
469 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
473 * @brief A channel select (also known as texture swizzle) value
475 enum isl_channel_select
{
476 ISL_CHANNEL_SELECT_ZERO
= 0,
477 ISL_CHANNEL_SELECT_ONE
= 1,
478 ISL_CHANNEL_SELECT_RED
= 4,
479 ISL_CHANNEL_SELECT_GREEN
= 5,
480 ISL_CHANNEL_SELECT_BLUE
= 6,
481 ISL_CHANNEL_SELECT_ALPHA
= 7,
485 * Identical to VkSampleCountFlagBits.
487 enum isl_sample_count
{
488 ISL_SAMPLE_COUNT_1_BIT
= 1u,
489 ISL_SAMPLE_COUNT_2_BIT
= 2u,
490 ISL_SAMPLE_COUNT_4_BIT
= 4u,
491 ISL_SAMPLE_COUNT_8_BIT
= 8u,
492 ISL_SAMPLE_COUNT_16_BIT
= 16u,
494 typedef uint32_t isl_sample_count_mask_t
;
497 * @brief Multisample Format
499 enum isl_msaa_layout
{
501 * @brief Suface is single-sampled.
503 ISL_MSAA_LAYOUT_NONE
,
506 * @brief [SNB+] Interleaved Multisample Format
508 * In this format, multiple samples are interleaved into each cacheline.
509 * In other words, the sample index is swizzled into the low 6 bits of the
510 * surface's virtual address space.
512 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
513 * and its pixel format is 32bpp. Then the first cacheline is arranged
516 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
517 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
519 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
520 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
522 * The hardware docs refer to this format with multiple terms. In
523 * Sandybridge, this is the only multisample format; so no term is used.
524 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
525 * Multisample Surface). Later hardware docs additionally refer to this
526 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
529 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
532 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
533 * Multisampled Surfaces".
535 ISL_MSAA_LAYOUT_INTERLEAVED
,
538 * @brief [IVB+] Array Multisample Format
540 * In this format, the surface's physical layout resembles that of a
543 * Suppose the multisample surface's logical extent is (w, h) and its
544 * sample count is N. Then surface's physical extent is the same as
545 * a singlesample 2D surface whose logical extent is (w, h) and array
546 * length is N. Array slice `i` contains the pixel values for sample
549 * The Ivybridge docs refer to surfaces in this format as UMS
550 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
551 * Surface). The Broadwell docs additionally refer to this format as
552 * MSFMT_MSS (MSS=Multisample Surface Storage).
554 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
555 * Multisample Surfaces".
557 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
558 * Multisample Surfaces".
560 ISL_MSAA_LAYOUT_ARRAY
,
565 const struct brw_device_info
*info
;
566 bool use_separate_stencil
;
567 bool has_bit6_swizzling
;
570 struct isl_extent2d
{
571 union { uint32_t w
, width
; };
572 union { uint32_t h
, height
; };
575 struct isl_extent3d
{
576 union { uint32_t w
, width
; };
577 union { uint32_t h
, height
; };
578 union { uint32_t d
, depth
; };
581 struct isl_extent4d
{
582 union { uint32_t w
, width
; };
583 union { uint32_t h
, height
; };
584 union { uint32_t d
, depth
; };
585 union { uint32_t a
, array_len
; };
588 struct isl_channel_layout
{
589 enum isl_base_type type
;
590 uint8_t bits
; /**< Size in bits */
594 * Each format has 3D block extent (width, height, depth). The block extent of
595 * compressed formats is that of the format's compression block. For example,
596 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
597 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
598 * is (w=1, h=1, d=1).
600 struct isl_format_layout
{
601 enum isl_format format
;
603 uint8_t bs
; /**< Block size, in bytes, rounded towards 0 */
604 uint8_t bw
; /**< Block width, in pixels */
605 uint8_t bh
; /**< Block height, in pixels */
606 uint8_t bd
; /**< Block depth, in pixels */
609 struct isl_channel_layout r
; /**< Red channel */
610 struct isl_channel_layout g
; /**< Green channel */
611 struct isl_channel_layout b
; /**< Blue channel */
612 struct isl_channel_layout a
; /**< Alpha channel */
613 struct isl_channel_layout l
; /**< Luminance channel */
614 struct isl_channel_layout i
; /**< Intensity channel */
615 struct isl_channel_layout p
; /**< Palette channel */
618 enum isl_colorspace colorspace
;
622 struct isl_tile_info
{
623 enum isl_tiling tiling
;
624 uint32_t width
; /**< in bytes */
625 uint32_t height
; /**< in rows of memory */
626 uint32_t size
; /**< in bytes */
630 * @brief Input to surface initialization
632 * @invariant width >= 1
633 * @invariant height >= 1
634 * @invariant depth >= 1
635 * @invariant levels >= 1
636 * @invariant samples >= 1
637 * @invariant array_len >= 1
639 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
640 * @invariant if 2D then depth == 1
641 * @invariant if 3D then array_len == 1 and samples == 1
643 struct isl_surf_init_info
{
644 enum isl_surf_dim dim
;
645 enum isl_format format
;
654 /** Lower bound for isl_surf::alignment, in bytes. */
655 uint32_t min_alignment
;
657 /** Lower bound for isl_surf::pitch, in bytes. */
660 isl_surf_usage_flags_t usage
;
662 /** Flags that alter how ISL selects isl_surf::tiling. */
663 isl_tiling_flags_t tiling_flags
;
667 enum isl_surf_dim dim
;
668 enum isl_dim_layout dim_layout
;
669 enum isl_msaa_layout msaa_layout
;
670 enum isl_tiling tiling
;
671 enum isl_format format
;
674 * Alignment of the upper-left sample of each subimage, in units of surface
677 struct isl_extent3d image_alignment_el
;
680 * Logical extent of the surface's base level, in units of pixels. This is
681 * identical to the extent defined in isl_surf_init_info.
683 struct isl_extent4d logical_level0_px
;
686 * Physical extent of the surface's base level, in units of physical
687 * surface samples and aligned to the format's compression block.
689 * Consider isl_dim_layout as an operator that transforms a logical surface
690 * layout to a physical surface layout. Then
692 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
693 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
695 struct isl_extent4d phys_level0_sa
;
700 /** Total size of the surface, in bytes. */
703 /** Required alignment for the surface's base address. */
707 * Pitch between vertically adjacent surface elements, in bytes.
712 * Pitch between physical array slices, in rows of surface elements.
714 uint32_t array_pitch_el_rows
;
716 enum isl_array_pitch_span array_pitch_span
;
718 /** Copy of isl_surf_init_info::usage. */
719 isl_surf_usage_flags_t usage
;
724 * Indicates the usage of the particular view
726 * Normally, this is one bit. However, for a cube map texture, it
727 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
729 isl_surf_usage_flags_t usage
;
732 * The format to use in the view
734 * This may differ from the format of the actual isl_surf but must have
735 * the same block size.
737 enum isl_format format
;
745 * For cube maps, both base_array_layer and array_len should be
746 * specified in terms of 2-D layers and must be a multiple of 6.
748 uint32_t base_array_layer
;
751 enum isl_channel_select channel_select
[4];
754 union isl_color_value
{
760 struct isl_surf_fill_state_info
{
761 const struct isl_surf
*surf
;
762 const struct isl_view
*view
;
765 * The address of the surface in GPU memory.
770 * The Memory Object Control state for the filled surface state.
772 * The exact format of this value depends on hardware generation.
777 * The clear color for this surface
779 * Valid values depend on hardware generation.
781 union isl_color_value clear_color
;
784 struct isl_buffer_fill_state_info
{
786 * The address of the surface in GPU memory.
791 * The size of the buffer
796 * The Memory Object Control state for the filled surface state.
798 * The exact format of this value depends on hardware generation.
803 * The format to use in the surface state
805 * This may differ from the format of the actual isl_surf but have the
808 enum isl_format format
;
813 extern const struct isl_format_layout isl_format_layouts
[];
816 isl_device_init(struct isl_device
*dev
,
817 const struct brw_device_info
*info
,
818 bool has_bit6_swizzling
);
820 isl_sample_count_mask_t ATTRIBUTE_CONST
821 isl_device_get_sample_counts(struct isl_device
*dev
);
823 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
824 isl_format_get_layout(enum isl_format fmt
)
826 return &isl_format_layouts
[fmt
];
830 isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
833 isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
836 isl_format_has_int_channel(enum isl_format fmt
)
838 return isl_format_has_uint_channel(fmt
) ||
839 isl_format_has_sint_channel(fmt
);
843 isl_format_is_compressed(enum isl_format fmt
)
845 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
847 return fmtl
->txc
!= ISL_TXC_NONE
;
851 isl_format_has_bc_compression(enum isl_format fmt
)
853 switch (isl_format_get_layout(fmt
)->txc
) {
868 unreachable("bad texture compression mode");
873 isl_format_is_yuv(enum isl_format fmt
)
875 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
877 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
881 isl_format_block_is_1x1x1(enum isl_format fmt
)
883 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
885 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
889 isl_format_is_rgb(enum isl_format fmt
)
891 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
892 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
893 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
894 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
897 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
898 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
900 bool isl_is_storage_image_format(enum isl_format fmt
);
903 isl_lower_storage_image_format(const struct isl_device
*dev
,
904 enum isl_format fmt
);
907 isl_tiling_is_any_y(enum isl_tiling tiling
)
909 return (1u << tiling
) & ISL_TILING_ANY_MASK
;
913 isl_tiling_is_std_y(enum isl_tiling tiling
)
915 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
919 isl_tiling_get_info(const struct isl_device
*dev
,
920 enum isl_tiling tiling
,
921 uint32_t format_block_size
,
922 struct isl_tile_info
*info
);
925 isl_tiling_get_extent(const struct isl_device
*dev
,
926 enum isl_tiling tiling
,
927 uint32_t format_block_size
,
928 struct isl_extent2d
*e
);
930 isl_surf_choose_tiling(const struct isl_device
*dev
,
931 const struct isl_surf_init_info
*restrict info
,
932 enum isl_tiling
*tiling
);
935 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
937 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
941 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
943 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
947 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
949 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
953 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
955 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
956 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
960 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
962 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
966 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
968 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
969 (info
->format
== ISL_FORMAT_R16_UNORM
);
973 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
975 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
976 (info
->format
== ISL_FORMAT_R32_FLOAT
);
979 static inline struct isl_extent2d
980 isl_extent2d(uint32_t width
, uint32_t height
)
982 struct isl_extent2d e
= { { 0 } };
990 static inline struct isl_extent3d
991 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
993 struct isl_extent3d e
= { { 0 } };
1002 static inline struct isl_extent4d
1003 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1006 struct isl_extent4d e
= { { 0 } };
1011 e
.array_len
= array_len
;
1016 #define isl_surf_init(dev, surf, ...) \
1017 isl_surf_init_s((dev), (surf), \
1018 &(struct isl_surf_init_info) { __VA_ARGS__ });
1021 isl_surf_init_s(const struct isl_device
*dev
,
1022 struct isl_surf
*surf
,
1023 const struct isl_surf_init_info
*restrict info
);
1026 isl_surf_get_tile_info(const struct isl_device
*dev
,
1027 const struct isl_surf
*surf
,
1028 struct isl_tile_info
*tile_info
);
1030 #define isl_surf_fill_state(dev, state, ...) \
1031 isl_surf_fill_state_s((dev), (state), \
1032 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1035 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1036 const struct isl_surf_fill_state_info
*restrict info
);
1038 #define isl_buffer_fill_state(dev, state, ...) \
1039 isl_buffer_fill_state_s((dev), (state), \
1040 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1043 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1044 const struct isl_buffer_fill_state_info
*restrict info
);
1047 isl_surf_fill_image_param(const struct isl_device
*dev
,
1048 struct brw_image_param
*param
,
1049 const struct isl_surf
*surf
,
1050 const struct isl_view
*view
);
1053 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1054 struct brw_image_param
*param
,
1055 enum isl_format format
,
1059 * Alignment of the upper-left sample of each subimage, in units of surface
1062 static inline struct isl_extent3d
1063 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1065 return surf
->image_alignment_el
;
1069 * Alignment of the upper-left sample of each subimage, in units of surface
1072 static inline struct isl_extent3d
1073 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1075 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1077 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1078 fmtl
->bh
* surf
->image_alignment_el
.h
,
1079 fmtl
->bd
* surf
->image_alignment_el
.d
);
1083 * Pitch between vertically adjacent surface elements, in bytes.
1085 static inline uint32_t
1086 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
1088 return surf
->row_pitch
;
1092 * Pitch between vertically adjacent surface elements, in units of surface elements.
1094 static inline uint32_t
1095 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1097 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1099 assert(surf
->row_pitch
% fmtl
->bs
== 0);
1100 return surf
->row_pitch
/ fmtl
->bs
;
1104 * Pitch between physical array slices, in rows of surface elements.
1106 static inline uint32_t
1107 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1109 return surf
->array_pitch_el_rows
;
1113 * Pitch between physical array slices, in units of surface elements.
1115 static inline uint32_t
1116 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1118 return isl_surf_get_array_pitch_el_rows(surf
) *
1119 isl_surf_get_row_pitch_el(surf
);
1123 * Pitch between physical array slices, in rows of surface samples.
1125 static inline uint32_t
1126 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1128 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1129 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1133 * Pitch between physical array slices, in bytes.
1135 static inline uint32_t
1136 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1138 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
1142 * Calculate the offset, in units of surface elements, to a subimage in the
1145 * @invariant level < surface levels
1146 * @invariant logical_array_layer < logical array length of surface
1147 * @invariant logical_z_offset_px < logical depth of surface at level
1150 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1152 uint32_t logical_array_layer
,
1153 uint32_t logical_z_offset_px
,
1154 uint32_t *x_offset_el
,
1155 uint32_t *y_offset_el
);
1158 * @brief Calculate the intratile offsets to a surface.
1160 * In @a base_address_offset return the offset from the base of the surface to
1161 * the base address of the first tile of the subimage. In @a x_offset_B and
1162 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1163 * tile's base to the subimage's first surface element. The x and y offsets
1164 * are intratile offsets; that is, they do not exceed the boundary of the
1165 * surface's tiling format.
1168 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1169 enum isl_tiling tiling
,
1172 uint32_t total_x_offset_B
,
1173 uint32_t total_y_offset_rows
,
1174 uint32_t *base_address_offset
,
1175 uint32_t *x_offset_B
,
1176 uint32_t *y_offset_rows
);
1179 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1181 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1182 * @pre surf->format must be a valid format for depth surfaces
1185 isl_surf_get_depth_format(const struct isl_device
*dev
,
1186 const struct isl_surf
*surf
);