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isl/state: Add support for OffsetX/Y in surface state
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct brw_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
63 #else
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
66 #endif
67
68 #ifndef ISL_DEV_IS_G4X
69 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
70 #endif
71
72 #ifndef ISL_DEV_IS_HASWELL
73 /**
74 * @brief Get the hardware generation of isl_device.
75 *
76 * You can define this as a compile-time constant in the CFLAGS. For example,
77 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
78 */
79 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
80 #endif
81
82 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
83 /**
84 * You can define this as a compile-time constant in the CFLAGS. For example,
85 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
86 */
87 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
88 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
89 #else
90 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
91 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
92 #endif
93
94 /**
95 * Hardware enumeration SURFACE_FORMAT.
96 *
97 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
98 * Enumerations: SURFACE_FORMAT.
99 */
100 enum isl_format {
101 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
102 ISL_FORMAT_R32G32B32A32_SINT = 1,
103 ISL_FORMAT_R32G32B32A32_UINT = 2,
104 ISL_FORMAT_R32G32B32A32_UNORM = 3,
105 ISL_FORMAT_R32G32B32A32_SNORM = 4,
106 ISL_FORMAT_R64G64_FLOAT = 5,
107 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
108 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
109 ISL_FORMAT_R32G32B32A32_USCALED = 8,
110 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
111 ISL_FORMAT_R64G64_PASSTHRU = 33,
112 ISL_FORMAT_R32G32B32_FLOAT = 64,
113 ISL_FORMAT_R32G32B32_SINT = 65,
114 ISL_FORMAT_R32G32B32_UINT = 66,
115 ISL_FORMAT_R32G32B32_UNORM = 67,
116 ISL_FORMAT_R32G32B32_SNORM = 68,
117 ISL_FORMAT_R32G32B32_SSCALED = 69,
118 ISL_FORMAT_R32G32B32_USCALED = 70,
119 ISL_FORMAT_R32G32B32_SFIXED = 80,
120 ISL_FORMAT_R16G16B16A16_UNORM = 128,
121 ISL_FORMAT_R16G16B16A16_SNORM = 129,
122 ISL_FORMAT_R16G16B16A16_SINT = 130,
123 ISL_FORMAT_R16G16B16A16_UINT = 131,
124 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
125 ISL_FORMAT_R32G32_FLOAT = 133,
126 ISL_FORMAT_R32G32_SINT = 134,
127 ISL_FORMAT_R32G32_UINT = 135,
128 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
129 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
130 ISL_FORMAT_L32A32_FLOAT = 138,
131 ISL_FORMAT_R32G32_UNORM = 139,
132 ISL_FORMAT_R32G32_SNORM = 140,
133 ISL_FORMAT_R64_FLOAT = 141,
134 ISL_FORMAT_R16G16B16X16_UNORM = 142,
135 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
136 ISL_FORMAT_A32X32_FLOAT = 144,
137 ISL_FORMAT_L32X32_FLOAT = 145,
138 ISL_FORMAT_I32X32_FLOAT = 146,
139 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
140 ISL_FORMAT_R16G16B16A16_USCALED = 148,
141 ISL_FORMAT_R32G32_SSCALED = 149,
142 ISL_FORMAT_R32G32_USCALED = 150,
143 ISL_FORMAT_R32G32_FLOAT_LD = 151,
144 ISL_FORMAT_R32G32_SFIXED = 160,
145 ISL_FORMAT_R64_PASSTHRU = 161,
146 ISL_FORMAT_B8G8R8A8_UNORM = 192,
147 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
148 ISL_FORMAT_R10G10B10A2_UNORM = 194,
149 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
150 ISL_FORMAT_R10G10B10A2_UINT = 196,
151 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
152 ISL_FORMAT_R8G8B8A8_UNORM = 199,
153 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
154 ISL_FORMAT_R8G8B8A8_SNORM = 201,
155 ISL_FORMAT_R8G8B8A8_SINT = 202,
156 ISL_FORMAT_R8G8B8A8_UINT = 203,
157 ISL_FORMAT_R16G16_UNORM = 204,
158 ISL_FORMAT_R16G16_SNORM = 205,
159 ISL_FORMAT_R16G16_SINT = 206,
160 ISL_FORMAT_R16G16_UINT = 207,
161 ISL_FORMAT_R16G16_FLOAT = 208,
162 ISL_FORMAT_B10G10R10A2_UNORM = 209,
163 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
164 ISL_FORMAT_R11G11B10_FLOAT = 211,
165 ISL_FORMAT_R32_SINT = 214,
166 ISL_FORMAT_R32_UINT = 215,
167 ISL_FORMAT_R32_FLOAT = 216,
168 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
169 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
170 ISL_FORMAT_L32_UNORM = 221,
171 ISL_FORMAT_A32_UNORM = 222,
172 ISL_FORMAT_L16A16_UNORM = 223,
173 ISL_FORMAT_I24X8_UNORM = 224,
174 ISL_FORMAT_L24X8_UNORM = 225,
175 ISL_FORMAT_A24X8_UNORM = 226,
176 ISL_FORMAT_I32_FLOAT = 227,
177 ISL_FORMAT_L32_FLOAT = 228,
178 ISL_FORMAT_A32_FLOAT = 229,
179 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
180 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
181 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
182 ISL_FORMAT_B8G8R8X8_UNORM = 233,
183 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
184 ISL_FORMAT_R8G8B8X8_UNORM = 235,
185 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
186 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
187 ISL_FORMAT_B10G10R10X2_UNORM = 238,
188 ISL_FORMAT_L16A16_FLOAT = 240,
189 ISL_FORMAT_R32_UNORM = 241,
190 ISL_FORMAT_R32_SNORM = 242,
191 ISL_FORMAT_R10G10B10X2_USCALED = 243,
192 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
193 ISL_FORMAT_R8G8B8A8_USCALED = 245,
194 ISL_FORMAT_R16G16_SSCALED = 246,
195 ISL_FORMAT_R16G16_USCALED = 247,
196 ISL_FORMAT_R32_SSCALED = 248,
197 ISL_FORMAT_R32_USCALED = 249,
198 ISL_FORMAT_B5G6R5_UNORM = 256,
199 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
200 ISL_FORMAT_B5G5R5A1_UNORM = 258,
201 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
202 ISL_FORMAT_B4G4R4A4_UNORM = 260,
203 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
204 ISL_FORMAT_R8G8_UNORM = 262,
205 ISL_FORMAT_R8G8_SNORM = 263,
206 ISL_FORMAT_R8G8_SINT = 264,
207 ISL_FORMAT_R8G8_UINT = 265,
208 ISL_FORMAT_R16_UNORM = 266,
209 ISL_FORMAT_R16_SNORM = 267,
210 ISL_FORMAT_R16_SINT = 268,
211 ISL_FORMAT_R16_UINT = 269,
212 ISL_FORMAT_R16_FLOAT = 270,
213 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
214 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
215 ISL_FORMAT_I16_UNORM = 273,
216 ISL_FORMAT_L16_UNORM = 274,
217 ISL_FORMAT_A16_UNORM = 275,
218 ISL_FORMAT_L8A8_UNORM = 276,
219 ISL_FORMAT_I16_FLOAT = 277,
220 ISL_FORMAT_L16_FLOAT = 278,
221 ISL_FORMAT_A16_FLOAT = 279,
222 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
223 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
224 ISL_FORMAT_B5G5R5X1_UNORM = 282,
225 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
226 ISL_FORMAT_R8G8_SSCALED = 284,
227 ISL_FORMAT_R8G8_USCALED = 285,
228 ISL_FORMAT_R16_SSCALED = 286,
229 ISL_FORMAT_R16_USCALED = 287,
230 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
231 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
232 ISL_FORMAT_A1B5G5R5_UNORM = 292,
233 ISL_FORMAT_A4B4G4R4_UNORM = 293,
234 ISL_FORMAT_L8A8_UINT = 294,
235 ISL_FORMAT_L8A8_SINT = 295,
236 ISL_FORMAT_R8_UNORM = 320,
237 ISL_FORMAT_R8_SNORM = 321,
238 ISL_FORMAT_R8_SINT = 322,
239 ISL_FORMAT_R8_UINT = 323,
240 ISL_FORMAT_A8_UNORM = 324,
241 ISL_FORMAT_I8_UNORM = 325,
242 ISL_FORMAT_L8_UNORM = 326,
243 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
244 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
245 ISL_FORMAT_R8_SSCALED = 329,
246 ISL_FORMAT_R8_USCALED = 330,
247 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
248 ISL_FORMAT_L8_UNORM_SRGB = 332,
249 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
250 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
251 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
252 ISL_FORMAT_Y8_UNORM = 336,
253 ISL_FORMAT_L8_UINT = 338,
254 ISL_FORMAT_L8_SINT = 339,
255 ISL_FORMAT_I8_UINT = 340,
256 ISL_FORMAT_I8_SINT = 341,
257 ISL_FORMAT_DXT1_RGB_SRGB = 384,
258 ISL_FORMAT_R1_UNORM = 385,
259 ISL_FORMAT_YCRCB_NORMAL = 386,
260 ISL_FORMAT_YCRCB_SWAPUVY = 387,
261 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
262 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
263 ISL_FORMAT_BC1_UNORM = 390,
264 ISL_FORMAT_BC2_UNORM = 391,
265 ISL_FORMAT_BC3_UNORM = 392,
266 ISL_FORMAT_BC4_UNORM = 393,
267 ISL_FORMAT_BC5_UNORM = 394,
268 ISL_FORMAT_BC1_UNORM_SRGB = 395,
269 ISL_FORMAT_BC2_UNORM_SRGB = 396,
270 ISL_FORMAT_BC3_UNORM_SRGB = 397,
271 ISL_FORMAT_MONO8 = 398,
272 ISL_FORMAT_YCRCB_SWAPUV = 399,
273 ISL_FORMAT_YCRCB_SWAPY = 400,
274 ISL_FORMAT_DXT1_RGB = 401,
275 ISL_FORMAT_FXT1 = 402,
276 ISL_FORMAT_R8G8B8_UNORM = 403,
277 ISL_FORMAT_R8G8B8_SNORM = 404,
278 ISL_FORMAT_R8G8B8_SSCALED = 405,
279 ISL_FORMAT_R8G8B8_USCALED = 406,
280 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
281 ISL_FORMAT_R64G64B64_FLOAT = 408,
282 ISL_FORMAT_BC4_SNORM = 409,
283 ISL_FORMAT_BC5_SNORM = 410,
284 ISL_FORMAT_R16G16B16_FLOAT = 411,
285 ISL_FORMAT_R16G16B16_UNORM = 412,
286 ISL_FORMAT_R16G16B16_SNORM = 413,
287 ISL_FORMAT_R16G16B16_SSCALED = 414,
288 ISL_FORMAT_R16G16B16_USCALED = 415,
289 ISL_FORMAT_BC6H_SF16 = 417,
290 ISL_FORMAT_BC7_UNORM = 418,
291 ISL_FORMAT_BC7_UNORM_SRGB = 419,
292 ISL_FORMAT_BC6H_UF16 = 420,
293 ISL_FORMAT_PLANAR_420_8 = 421,
294 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
295 ISL_FORMAT_ETC1_RGB8 = 425,
296 ISL_FORMAT_ETC2_RGB8 = 426,
297 ISL_FORMAT_EAC_R11 = 427,
298 ISL_FORMAT_EAC_RG11 = 428,
299 ISL_FORMAT_EAC_SIGNED_R11 = 429,
300 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
301 ISL_FORMAT_ETC2_SRGB8 = 431,
302 ISL_FORMAT_R16G16B16_UINT = 432,
303 ISL_FORMAT_R16G16B16_SINT = 433,
304 ISL_FORMAT_R32_SFIXED = 434,
305 ISL_FORMAT_R10G10B10A2_SNORM = 435,
306 ISL_FORMAT_R10G10B10A2_USCALED = 436,
307 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
308 ISL_FORMAT_R10G10B10A2_SINT = 438,
309 ISL_FORMAT_B10G10R10A2_SNORM = 439,
310 ISL_FORMAT_B10G10R10A2_USCALED = 440,
311 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
312 ISL_FORMAT_B10G10R10A2_UINT = 442,
313 ISL_FORMAT_B10G10R10A2_SINT = 443,
314 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
315 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
316 ISL_FORMAT_ETC2_RGB8_PTA = 448,
317 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
318 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
319 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
320 ISL_FORMAT_R8G8B8_UINT = 456,
321 ISL_FORMAT_R8G8B8_SINT = 457,
322 ISL_FORMAT_RAW = 511,
323 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
324 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
325 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
326 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
327 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
328 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
329 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
330 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
331 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
332 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
333 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
334 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
335 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
336 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
337 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
338 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
339 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
340 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
341 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
342 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
343 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
344 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
345 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
346 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
347 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
348 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
349 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
350 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
351
352 /* The formats that follow are internal to ISL and as such don't have an
353 * explicit number. We'll just let the C compiler assign it for us. Any
354 * actual hardware formats *must* come before these in the list.
355 */
356
357 /* Formats for color compression surfaces */
358 ISL_FORMAT_HIZ,
359 ISL_FORMAT_MCS_2X,
360 ISL_FORMAT_MCS_4X,
361 ISL_FORMAT_MCS_8X,
362 ISL_FORMAT_MCS_16X,
363 ISL_FORMAT_GEN7_CCS_32BPP_X,
364 ISL_FORMAT_GEN7_CCS_64BPP_X,
365 ISL_FORMAT_GEN7_CCS_128BPP_X,
366 ISL_FORMAT_GEN7_CCS_32BPP_Y,
367 ISL_FORMAT_GEN7_CCS_64BPP_Y,
368 ISL_FORMAT_GEN7_CCS_128BPP_Y,
369 ISL_FORMAT_GEN9_CCS_32BPP,
370 ISL_FORMAT_GEN9_CCS_64BPP,
371 ISL_FORMAT_GEN9_CCS_128BPP,
372
373 /* Hardware doesn't understand this out-of-band value */
374 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
375 };
376
377 /**
378 * Numerical base type for channels of isl_format.
379 */
380 enum isl_base_type {
381 ISL_VOID,
382 ISL_RAW,
383 ISL_UNORM,
384 ISL_SNORM,
385 ISL_UFLOAT,
386 ISL_SFLOAT,
387 ISL_UFIXED,
388 ISL_SFIXED,
389 ISL_UINT,
390 ISL_SINT,
391 ISL_USCALED,
392 ISL_SSCALED,
393 };
394
395 /**
396 * Colorspace of isl_format.
397 */
398 enum isl_colorspace {
399 ISL_COLORSPACE_NONE = 0,
400 ISL_COLORSPACE_LINEAR,
401 ISL_COLORSPACE_SRGB,
402 ISL_COLORSPACE_YUV,
403 };
404
405 /**
406 * Texture compression mode of isl_format.
407 */
408 enum isl_txc {
409 ISL_TXC_NONE = 0,
410 ISL_TXC_DXT1,
411 ISL_TXC_DXT3,
412 ISL_TXC_DXT5,
413 ISL_TXC_FXT1,
414 ISL_TXC_RGTC1,
415 ISL_TXC_RGTC2,
416 ISL_TXC_BPTC,
417 ISL_TXC_ETC1,
418 ISL_TXC_ETC2,
419 ISL_TXC_ASTC,
420
421 /* Used for auxiliary surface formats */
422 ISL_TXC_HIZ,
423 ISL_TXC_MCS,
424 ISL_TXC_CCS,
425 };
426
427 /**
428 * @brief Hardware tile mode
429 *
430 * WARNING: These values differ from the hardware enum values, which are
431 * unstable across hardware generations.
432 *
433 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
434 * clearly distinguish it from Yf and Ys.
435 */
436 enum isl_tiling {
437 ISL_TILING_LINEAR = 0,
438 ISL_TILING_W,
439 ISL_TILING_X,
440 ISL_TILING_Y0, /**< Legacy Y tiling */
441 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
442 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
443 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
444 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
445 };
446
447 /**
448 * @defgroup Tiling Flags
449 * @{
450 */
451 typedef uint32_t isl_tiling_flags_t;
452 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
453 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
454 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
455 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
456 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
457 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
458 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
459 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
460 #define ISL_TILING_ANY_MASK (~0u)
461 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
462
463 /** Any Y tiling, including legacy Y tiling. */
464 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
465 ISL_TILING_Yf_BIT | \
466 ISL_TILING_Ys_BIT)
467
468 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
469 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
470 ISL_TILING_Ys_BIT)
471 /** @} */
472
473 /**
474 * @brief Logical dimension of surface.
475 *
476 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
477 * as 2D array surfaces.
478 */
479 enum isl_surf_dim {
480 ISL_SURF_DIM_1D,
481 ISL_SURF_DIM_2D,
482 ISL_SURF_DIM_3D,
483 };
484
485 /**
486 * @brief Physical layout of the surface's dimensions.
487 */
488 enum isl_dim_layout {
489 /**
490 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
491 * 6.17.3: 2D Surfaces.
492 *
493 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
494 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
495 *
496 * One-dimensional surfaces are identical to 2D surfaces with height of
497 * one.
498 *
499 * @invariant isl_surf::phys_level0_sa::depth == 1
500 */
501 ISL_DIM_LAYOUT_GEN4_2D,
502
503 /**
504 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
505 * 6.17.5: 3D Surfaces.
506 *
507 * @invariant isl_surf::phys_level0_sa::array_len == 1
508 */
509 ISL_DIM_LAYOUT_GEN4_3D,
510
511 /**
512 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
513 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
514 */
515 ISL_DIM_LAYOUT_GEN9_1D,
516 };
517
518 enum isl_aux_usage {
519 /** No Auxiliary surface is used */
520 ISL_AUX_USAGE_NONE,
521
522 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
523 ISL_AUX_USAGE_HIZ,
524
525 /** The auxiliary surface is an MCS
526 *
527 * @invariant isl_surf::samples > 1
528 */
529 ISL_AUX_USAGE_MCS,
530
531 /** The auxiliary surface is a fast-clear-only compression surface
532 *
533 * @invariant isl_surf::samples == 1
534 */
535 ISL_AUX_USAGE_CCS_D,
536
537 /** The auxiliary surface provides full lossless color compression
538 *
539 * @invariant isl_surf::samples == 1
540 */
541 ISL_AUX_USAGE_CCS_E,
542 };
543
544 /* TODO(chadv): Explain */
545 enum isl_array_pitch_span {
546 ISL_ARRAY_PITCH_SPAN_FULL,
547 ISL_ARRAY_PITCH_SPAN_COMPACT,
548 };
549
550 /**
551 * @defgroup Surface Usage
552 * @{
553 */
554 typedef uint64_t isl_surf_usage_flags_t;
555 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
556 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
557 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
558 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
559 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
560 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
561 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
562 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
563 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
564 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
565 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
566 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
567 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
568 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
569 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
570 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
571 /** @} */
572
573 /**
574 * @brief A channel select (also known as texture swizzle) value
575 */
576 enum isl_channel_select {
577 ISL_CHANNEL_SELECT_ZERO = 0,
578 ISL_CHANNEL_SELECT_ONE = 1,
579 ISL_CHANNEL_SELECT_RED = 4,
580 ISL_CHANNEL_SELECT_GREEN = 5,
581 ISL_CHANNEL_SELECT_BLUE = 6,
582 ISL_CHANNEL_SELECT_ALPHA = 7,
583 };
584
585 /**
586 * Identical to VkSampleCountFlagBits.
587 */
588 enum isl_sample_count {
589 ISL_SAMPLE_COUNT_1_BIT = 1u,
590 ISL_SAMPLE_COUNT_2_BIT = 2u,
591 ISL_SAMPLE_COUNT_4_BIT = 4u,
592 ISL_SAMPLE_COUNT_8_BIT = 8u,
593 ISL_SAMPLE_COUNT_16_BIT = 16u,
594 };
595 typedef uint32_t isl_sample_count_mask_t;
596
597 /**
598 * @brief Multisample Format
599 */
600 enum isl_msaa_layout {
601 /**
602 * @brief Suface is single-sampled.
603 */
604 ISL_MSAA_LAYOUT_NONE,
605
606 /**
607 * @brief [SNB+] Interleaved Multisample Format
608 *
609 * In this format, multiple samples are interleaved into each cacheline.
610 * In other words, the sample index is swizzled into the low 6 bits of the
611 * surface's virtual address space.
612 *
613 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
614 * and its pixel format is 32bpp. Then the first cacheline is arranged
615 * thus:
616 *
617 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
618 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
619 *
620 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
621 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
622 *
623 * The hardware docs refer to this format with multiple terms. In
624 * Sandybridge, this is the only multisample format; so no term is used.
625 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
626 * Multisample Surface). Later hardware docs additionally refer to this
627 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
628 * color surfaces).
629 *
630 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
631 * Surface Behavior".
632 *
633 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
634 * Multisampled Surfaces".
635 */
636 ISL_MSAA_LAYOUT_INTERLEAVED,
637
638 /**
639 * @brief [IVB+] Array Multisample Format
640 *
641 * In this format, the surface's physical layout resembles that of a
642 * 2D array surface.
643 *
644 * Suppose the multisample surface's logical extent is (w, h) and its
645 * sample count is N. Then surface's physical extent is the same as
646 * a singlesample 2D surface whose logical extent is (w, h) and array
647 * length is N. Array slice `i` contains the pixel values for sample
648 * index `i`.
649 *
650 * The Ivybridge docs refer to surfaces in this format as UMS
651 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
652 * Surface). The Broadwell docs additionally refer to this format as
653 * MSFMT_MSS (MSS=Multisample Surface Storage).
654 *
655 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
656 * Multisample Surfaces".
657 *
658 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
659 * Multisample Surfaces".
660 */
661 ISL_MSAA_LAYOUT_ARRAY,
662 };
663
664
665 struct isl_device {
666 const struct brw_device_info *info;
667 bool use_separate_stencil;
668 bool has_bit6_swizzling;
669 };
670
671 struct isl_extent2d {
672 union { uint32_t w, width; };
673 union { uint32_t h, height; };
674 };
675
676 struct isl_extent3d {
677 union { uint32_t w, width; };
678 union { uint32_t h, height; };
679 union { uint32_t d, depth; };
680 };
681
682 struct isl_extent4d {
683 union { uint32_t w, width; };
684 union { uint32_t h, height; };
685 union { uint32_t d, depth; };
686 union { uint32_t a, array_len; };
687 };
688
689 struct isl_channel_layout {
690 enum isl_base_type type;
691 uint8_t bits; /**< Size in bits */
692 };
693
694 /**
695 * Each format has 3D block extent (width, height, depth). The block extent of
696 * compressed formats is that of the format's compression block. For example,
697 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
698 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
699 * is (w=1, h=1, d=1).
700 */
701 struct isl_format_layout {
702 enum isl_format format;
703 const char *name;
704
705 uint16_t bpb; /**< Bits per block */
706 uint8_t bw; /**< Block width, in pixels */
707 uint8_t bh; /**< Block height, in pixels */
708 uint8_t bd; /**< Block depth, in pixels */
709
710 struct {
711 struct isl_channel_layout r; /**< Red channel */
712 struct isl_channel_layout g; /**< Green channel */
713 struct isl_channel_layout b; /**< Blue channel */
714 struct isl_channel_layout a; /**< Alpha channel */
715 struct isl_channel_layout l; /**< Luminance channel */
716 struct isl_channel_layout i; /**< Intensity channel */
717 struct isl_channel_layout p; /**< Palette channel */
718 } channels;
719
720 enum isl_colorspace colorspace;
721 enum isl_txc txc;
722 };
723
724 struct isl_tile_info {
725 enum isl_tiling tiling;
726
727 /** The logical size of the tile in units of surface elements
728 *
729 * This field determines how a given surface is cut up into tiles. It is
730 * used to compute the size of a surface in tiles and can be used to
731 * determine the location of the tile containing any given surface element.
732 * The exact value of this field depends heavily on the bits-per-block of
733 * the format being used.
734 */
735 struct isl_extent2d logical_extent_el;
736
737 /** The physical size of the tile in bytes and rows of bytes
738 *
739 * This field determines how the tiles of a surface are physically layed
740 * out in memory. The logical and physical tile extent are frequently the
741 * same but this is not always the case. For instance, a W-tile (which is
742 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
743 * its physical size is 128B x 32rows, the same as a Y-tile.
744 *
745 * @see isl_surf::row_pitch
746 */
747 struct isl_extent2d phys_extent_B;
748 };
749
750 /**
751 * @brief Input to surface initialization
752 *
753 * @invariant width >= 1
754 * @invariant height >= 1
755 * @invariant depth >= 1
756 * @invariant levels >= 1
757 * @invariant samples >= 1
758 * @invariant array_len >= 1
759 *
760 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
761 * @invariant if 2D then depth == 1
762 * @invariant if 3D then array_len == 1 and samples == 1
763 */
764 struct isl_surf_init_info {
765 enum isl_surf_dim dim;
766 enum isl_format format;
767
768 uint32_t width;
769 uint32_t height;
770 uint32_t depth;
771 uint32_t levels;
772 uint32_t array_len;
773 uint32_t samples;
774
775 /** Lower bound for isl_surf::alignment, in bytes. */
776 uint32_t min_alignment;
777
778 /** Lower bound for isl_surf::pitch, in bytes. */
779 uint32_t min_pitch;
780
781 isl_surf_usage_flags_t usage;
782
783 /** Flags that alter how ISL selects isl_surf::tiling. */
784 isl_tiling_flags_t tiling_flags;
785 };
786
787 struct isl_surf {
788 enum isl_surf_dim dim;
789 enum isl_dim_layout dim_layout;
790 enum isl_msaa_layout msaa_layout;
791 enum isl_tiling tiling;
792 enum isl_format format;
793
794 /**
795 * Alignment of the upper-left sample of each subimage, in units of surface
796 * elements.
797 */
798 struct isl_extent3d image_alignment_el;
799
800 /**
801 * Logical extent of the surface's base level, in units of pixels. This is
802 * identical to the extent defined in isl_surf_init_info.
803 */
804 struct isl_extent4d logical_level0_px;
805
806 /**
807 * Physical extent of the surface's base level, in units of physical
808 * surface samples and aligned to the format's compression block.
809 *
810 * Consider isl_dim_layout as an operator that transforms a logical surface
811 * layout to a physical surface layout. Then
812 *
813 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
814 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
815 */
816 struct isl_extent4d phys_level0_sa;
817
818 uint32_t levels;
819 uint32_t samples;
820
821 /** Total size of the surface, in bytes. */
822 uint32_t size;
823
824 /** Required alignment for the surface's base address. */
825 uint32_t alignment;
826
827 /**
828 * The interpretation of this field depends on the value of
829 * isl_tile_info::physical_extent_B. In particular, the width of the
830 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
831 * and the distance in bytes between vertically adjacent tiles in the image
832 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
833 *
834 * For linear images where isl_tile_info::physical_extent_B.height == 1,
835 * this cleanly reduces to being the distance, in bytes, between vertically
836 * adjacent surface elements.
837 *
838 * @see isl_tile_info::phys_extent_B;
839 */
840 uint32_t row_pitch;
841
842 /**
843 * Pitch between physical array slices, in rows of surface elements.
844 */
845 uint32_t array_pitch_el_rows;
846
847 enum isl_array_pitch_span array_pitch_span;
848
849 /** Copy of isl_surf_init_info::usage. */
850 isl_surf_usage_flags_t usage;
851 };
852
853 struct isl_view {
854 /**
855 * Indicates the usage of the particular view
856 *
857 * Normally, this is one bit. However, for a cube map texture, it
858 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
859 */
860 isl_surf_usage_flags_t usage;
861
862 /**
863 * The format to use in the view
864 *
865 * This may differ from the format of the actual isl_surf but must have
866 * the same block size.
867 */
868 enum isl_format format;
869
870 uint32_t base_level;
871 uint32_t levels;
872
873 /**
874 * Base array layer
875 *
876 * For cube maps, both base_array_layer and array_len should be
877 * specified in terms of 2-D layers and must be a multiple of 6.
878 */
879 uint32_t base_array_layer;
880 uint32_t array_len;
881
882 enum isl_channel_select channel_select[4];
883 };
884
885 union isl_color_value {
886 float f32[4];
887 uint32_t u32[4];
888 int32_t i32[4];
889 };
890
891 struct isl_surf_fill_state_info {
892 const struct isl_surf *surf;
893 const struct isl_view *view;
894
895 /**
896 * The address of the surface in GPU memory.
897 */
898 uint64_t address;
899
900 /**
901 * The Memory Object Control state for the filled surface state.
902 *
903 * The exact format of this value depends on hardware generation.
904 */
905 uint32_t mocs;
906
907 /**
908 * The auxilary surface or NULL if no auxilary surface is to be used.
909 */
910 const struct isl_surf *aux_surf;
911 enum isl_aux_usage aux_usage;
912 uint64_t aux_address;
913
914 /**
915 * The clear color for this surface
916 *
917 * Valid values depend on hardware generation.
918 */
919 union isl_color_value clear_color;
920
921 /* Intra-tile offset */
922 uint16_t x_offset_sa, y_offset_sa;
923 };
924
925 struct isl_buffer_fill_state_info {
926 /**
927 * The address of the surface in GPU memory.
928 */
929 uint64_t address;
930
931 /**
932 * The size of the buffer
933 */
934 uint64_t size;
935
936 /**
937 * The Memory Object Control state for the filled surface state.
938 *
939 * The exact format of this value depends on hardware generation.
940 */
941 uint32_t mocs;
942
943 /**
944 * The format to use in the surface state
945 *
946 * This may differ from the format of the actual isl_surf but have the
947 * same block size.
948 */
949 enum isl_format format;
950
951 uint32_t stride;
952 };
953
954 extern const struct isl_format_layout isl_format_layouts[];
955
956 void
957 isl_device_init(struct isl_device *dev,
958 const struct brw_device_info *info,
959 bool has_bit6_swizzling);
960
961 isl_sample_count_mask_t ATTRIBUTE_CONST
962 isl_device_get_sample_counts(struct isl_device *dev);
963
964 static inline const struct isl_format_layout * ATTRIBUTE_CONST
965 isl_format_get_layout(enum isl_format fmt)
966 {
967 return &isl_format_layouts[fmt];
968 }
969
970 static inline const char * ATTRIBUTE_CONST
971 isl_format_get_name(enum isl_format fmt)
972 {
973 return isl_format_layouts[fmt].name;
974 }
975
976 bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
977 enum isl_format format);
978 bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
979 enum isl_format format);
980 bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
981 enum isl_format format);
982 bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
983 enum isl_format format);
984 bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
985 enum isl_format format);
986 bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
987 enum isl_format format);
988
989 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
990 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
991 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
992 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
993 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
994 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
995
996 static inline bool
997 isl_format_has_normalized_channel(enum isl_format fmt)
998 {
999 return isl_format_has_unorm_channel(fmt) ||
1000 isl_format_has_snorm_channel(fmt);
1001 }
1002
1003 static inline bool
1004 isl_format_has_float_channel(enum isl_format fmt)
1005 {
1006 return isl_format_has_ufloat_channel(fmt) ||
1007 isl_format_has_sfloat_channel(fmt);
1008 }
1009
1010 static inline bool
1011 isl_format_has_int_channel(enum isl_format fmt)
1012 {
1013 return isl_format_has_uint_channel(fmt) ||
1014 isl_format_has_sint_channel(fmt);
1015 }
1016
1017 unsigned isl_format_get_num_channels(enum isl_format fmt);
1018
1019 static inline bool
1020 isl_format_is_compressed(enum isl_format fmt)
1021 {
1022 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1023
1024 return fmtl->txc != ISL_TXC_NONE;
1025 }
1026
1027 static inline bool
1028 isl_format_has_bc_compression(enum isl_format fmt)
1029 {
1030 switch (isl_format_get_layout(fmt)->txc) {
1031 case ISL_TXC_DXT1:
1032 case ISL_TXC_DXT3:
1033 case ISL_TXC_DXT5:
1034 return true;
1035 case ISL_TXC_NONE:
1036 case ISL_TXC_FXT1:
1037 case ISL_TXC_RGTC1:
1038 case ISL_TXC_RGTC2:
1039 case ISL_TXC_BPTC:
1040 case ISL_TXC_ETC1:
1041 case ISL_TXC_ETC2:
1042 case ISL_TXC_ASTC:
1043 return false;
1044
1045 case ISL_TXC_HIZ:
1046 case ISL_TXC_MCS:
1047 case ISL_TXC_CCS:
1048 unreachable("Should not be called on an aux surface");
1049 }
1050
1051 unreachable("bad texture compression mode");
1052 return false;
1053 }
1054
1055 static inline bool
1056 isl_format_is_yuv(enum isl_format fmt)
1057 {
1058 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1059
1060 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1061 }
1062
1063 static inline bool
1064 isl_format_block_is_1x1x1(enum isl_format fmt)
1065 {
1066 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1067
1068 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1069 }
1070
1071 static inline bool
1072 isl_format_is_rgb(enum isl_format fmt)
1073 {
1074 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1075 isl_format_layouts[fmt].channels.g.bits > 0 &&
1076 isl_format_layouts[fmt].channels.b.bits > 0 &&
1077 isl_format_layouts[fmt].channels.a.bits == 0;
1078 }
1079
1080 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1081 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1082
1083 bool isl_is_storage_image_format(enum isl_format fmt);
1084
1085 enum isl_format
1086 isl_lower_storage_image_format(const struct brw_device_info *devinfo,
1087 enum isl_format fmt);
1088
1089 /* Returns true if this hardware supports typed load/store on a format with
1090 * the same size as the given format.
1091 */
1092 bool
1093 isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
1094 enum isl_format fmt);
1095
1096 static inline bool
1097 isl_tiling_is_any_y(enum isl_tiling tiling)
1098 {
1099 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1100 }
1101
1102 static inline bool
1103 isl_tiling_is_std_y(enum isl_tiling tiling)
1104 {
1105 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1106 }
1107
1108 bool
1109 isl_tiling_get_info(const struct isl_device *dev,
1110 enum isl_tiling tiling,
1111 uint32_t format_bpb,
1112 struct isl_tile_info *info);
1113 bool
1114 isl_surf_choose_tiling(const struct isl_device *dev,
1115 const struct isl_surf_init_info *restrict info,
1116 enum isl_tiling *tiling);
1117
1118 static inline bool
1119 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1120 {
1121 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1122 }
1123
1124 static inline bool
1125 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1126 {
1127 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1128 }
1129
1130 static inline bool
1131 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1132 {
1133 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1134 }
1135
1136 static inline bool
1137 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1138 {
1139 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1140 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1141 }
1142
1143 static inline bool
1144 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1145 {
1146 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1147 }
1148
1149 static inline bool
1150 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1151 {
1152 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1153 (info->format == ISL_FORMAT_R16_UNORM);
1154 }
1155
1156 static inline bool
1157 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1158 {
1159 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1160 (info->format == ISL_FORMAT_R32_FLOAT);
1161 }
1162
1163 static inline struct isl_extent2d
1164 isl_extent2d(uint32_t width, uint32_t height)
1165 {
1166 struct isl_extent2d e = { { 0 } };
1167
1168 e.width = width;
1169 e.height = height;
1170
1171 return e;
1172 }
1173
1174 static inline struct isl_extent3d
1175 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1176 {
1177 struct isl_extent3d e = { { 0 } };
1178
1179 e.width = width;
1180 e.height = height;
1181 e.depth = depth;
1182
1183 return e;
1184 }
1185
1186 static inline struct isl_extent4d
1187 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1188 uint32_t array_len)
1189 {
1190 struct isl_extent4d e = { { 0 } };
1191
1192 e.width = width;
1193 e.height = height;
1194 e.depth = depth;
1195 e.array_len = array_len;
1196
1197 return e;
1198 }
1199
1200 #define isl_surf_init(dev, surf, ...) \
1201 isl_surf_init_s((dev), (surf), \
1202 &(struct isl_surf_init_info) { __VA_ARGS__ });
1203
1204 bool
1205 isl_surf_init_s(const struct isl_device *dev,
1206 struct isl_surf *surf,
1207 const struct isl_surf_init_info *restrict info);
1208
1209 void
1210 isl_surf_get_tile_info(const struct isl_device *dev,
1211 const struct isl_surf *surf,
1212 struct isl_tile_info *tile_info);
1213
1214 #define isl_surf_fill_state(dev, state, ...) \
1215 isl_surf_fill_state_s((dev), (state), \
1216 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1217
1218 void
1219 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1220 const struct isl_surf_fill_state_info *restrict info);
1221
1222 #define isl_buffer_fill_state(dev, state, ...) \
1223 isl_buffer_fill_state_s((dev), (state), \
1224 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1225
1226 void
1227 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1228 const struct isl_buffer_fill_state_info *restrict info);
1229
1230 void
1231 isl_surf_fill_image_param(const struct isl_device *dev,
1232 struct brw_image_param *param,
1233 const struct isl_surf *surf,
1234 const struct isl_view *view);
1235
1236 void
1237 isl_buffer_fill_image_param(const struct isl_device *dev,
1238 struct brw_image_param *param,
1239 enum isl_format format,
1240 uint64_t size);
1241
1242 /**
1243 * Alignment of the upper-left sample of each subimage, in units of surface
1244 * elements.
1245 */
1246 static inline struct isl_extent3d
1247 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1248 {
1249 return surf->image_alignment_el;
1250 }
1251
1252 /**
1253 * Alignment of the upper-left sample of each subimage, in units of surface
1254 * samples.
1255 */
1256 static inline struct isl_extent3d
1257 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1258 {
1259 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1260
1261 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1262 fmtl->bh * surf->image_alignment_el.h,
1263 fmtl->bd * surf->image_alignment_el.d);
1264 }
1265
1266 /**
1267 * Pitch between vertically adjacent surface elements, in bytes.
1268 */
1269 static inline uint32_t
1270 isl_surf_get_row_pitch(const struct isl_surf *surf)
1271 {
1272 return surf->row_pitch;
1273 }
1274
1275 /**
1276 * Pitch between vertically adjacent surface elements, in units of surface elements.
1277 */
1278 static inline uint32_t
1279 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1280 {
1281 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1282
1283 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1284 return surf->row_pitch / (fmtl->bpb / 8);
1285 }
1286
1287 /**
1288 * Pitch between physical array slices, in rows of surface elements.
1289 */
1290 static inline uint32_t
1291 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1292 {
1293 return surf->array_pitch_el_rows;
1294 }
1295
1296 /**
1297 * Pitch between physical array slices, in units of surface elements.
1298 */
1299 static inline uint32_t
1300 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1301 {
1302 return isl_surf_get_array_pitch_el_rows(surf) *
1303 isl_surf_get_row_pitch_el(surf);
1304 }
1305
1306 /**
1307 * Pitch between physical array slices, in rows of surface samples.
1308 */
1309 static inline uint32_t
1310 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1311 {
1312 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1313 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1314 }
1315
1316 /**
1317 * Pitch between physical array slices, in bytes.
1318 */
1319 static inline uint32_t
1320 isl_surf_get_array_pitch(const struct isl_surf *surf)
1321 {
1322 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1323 }
1324
1325 /**
1326 * Calculate the offset, in units of surface elements, to a subimage in the
1327 * surface.
1328 *
1329 * @invariant level < surface levels
1330 * @invariant logical_array_layer < logical array length of surface
1331 * @invariant logical_z_offset_px < logical depth of surface at level
1332 */
1333 void
1334 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1335 uint32_t level,
1336 uint32_t logical_array_layer,
1337 uint32_t logical_z_offset_px,
1338 uint32_t *x_offset_el,
1339 uint32_t *y_offset_el);
1340
1341 /**
1342 * @brief Calculate the intratile offsets to a surface.
1343 *
1344 * In @a base_address_offset return the offset from the base of the surface to
1345 * the base address of the first tile of the subimage. In @a x_offset_B and
1346 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1347 * tile's base to the subimage's first surface element. The x and y offsets
1348 * are intratile offsets; that is, they do not exceed the boundary of the
1349 * surface's tiling format.
1350 */
1351 void
1352 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1353 enum isl_tiling tiling,
1354 uint8_t bs,
1355 uint32_t row_pitch,
1356 uint32_t total_x_offset_B,
1357 uint32_t total_y_offset_rows,
1358 uint32_t *base_address_offset,
1359 uint32_t *x_offset_B,
1360 uint32_t *y_offset_rows);
1361
1362 /**
1363 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1364 *
1365 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1366 * @pre surf->format must be a valid format for depth surfaces
1367 */
1368 uint32_t
1369 isl_surf_get_depth_format(const struct isl_device *dev,
1370 const struct isl_surf *surf);
1371
1372 #ifdef __cplusplus
1373 }
1374 #endif