2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
44 #include "c99_compat.h"
45 #include "util/macros.h"
51 struct gen_device_info
;
52 struct brw_image_param
;
56 * @brief Get the hardware generation of isl_device.
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
68 #ifndef ISL_DEV_IS_G4X
69 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
72 #ifndef ISL_DEV_IS_HASWELL
74 * @brief Get the hardware generation of isl_device.
76 * You can define this as a compile-time constant in the CFLAGS. For example,
77 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
82 #ifndef ISL_DEV_IS_BAYTRAIL
83 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
86 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 * You can define this as a compile-time constant in the CFLAGS. For example,
89 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
92 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
95 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
99 * Hardware enumeration SURFACE_FORMAT.
101 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
102 * Enumerations: SURFACE_FORMAT.
105 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
106 ISL_FORMAT_R32G32B32A32_SINT
= 1,
107 ISL_FORMAT_R32G32B32A32_UINT
= 2,
108 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
109 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
110 ISL_FORMAT_R64G64_FLOAT
= 5,
111 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
112 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
113 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
114 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
115 ISL_FORMAT_R64G64_PASSTHRU
= 33,
116 ISL_FORMAT_R32G32B32_FLOAT
= 64,
117 ISL_FORMAT_R32G32B32_SINT
= 65,
118 ISL_FORMAT_R32G32B32_UINT
= 66,
119 ISL_FORMAT_R32G32B32_UNORM
= 67,
120 ISL_FORMAT_R32G32B32_SNORM
= 68,
121 ISL_FORMAT_R32G32B32_SSCALED
= 69,
122 ISL_FORMAT_R32G32B32_USCALED
= 70,
123 ISL_FORMAT_R32G32B32_SFIXED
= 80,
124 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
125 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
126 ISL_FORMAT_R16G16B16A16_SINT
= 130,
127 ISL_FORMAT_R16G16B16A16_UINT
= 131,
128 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
129 ISL_FORMAT_R32G32_FLOAT
= 133,
130 ISL_FORMAT_R32G32_SINT
= 134,
131 ISL_FORMAT_R32G32_UINT
= 135,
132 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
133 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
134 ISL_FORMAT_L32A32_FLOAT
= 138,
135 ISL_FORMAT_R32G32_UNORM
= 139,
136 ISL_FORMAT_R32G32_SNORM
= 140,
137 ISL_FORMAT_R64_FLOAT
= 141,
138 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
139 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
140 ISL_FORMAT_A32X32_FLOAT
= 144,
141 ISL_FORMAT_L32X32_FLOAT
= 145,
142 ISL_FORMAT_I32X32_FLOAT
= 146,
143 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
144 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
145 ISL_FORMAT_R32G32_SSCALED
= 149,
146 ISL_FORMAT_R32G32_USCALED
= 150,
147 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
148 ISL_FORMAT_R32G32_SFIXED
= 160,
149 ISL_FORMAT_R64_PASSTHRU
= 161,
150 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
151 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
152 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
153 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
154 ISL_FORMAT_R10G10B10A2_UINT
= 196,
155 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
156 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
157 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
158 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
159 ISL_FORMAT_R8G8B8A8_SINT
= 202,
160 ISL_FORMAT_R8G8B8A8_UINT
= 203,
161 ISL_FORMAT_R16G16_UNORM
= 204,
162 ISL_FORMAT_R16G16_SNORM
= 205,
163 ISL_FORMAT_R16G16_SINT
= 206,
164 ISL_FORMAT_R16G16_UINT
= 207,
165 ISL_FORMAT_R16G16_FLOAT
= 208,
166 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
167 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
168 ISL_FORMAT_R11G11B10_FLOAT
= 211,
169 ISL_FORMAT_R32_SINT
= 214,
170 ISL_FORMAT_R32_UINT
= 215,
171 ISL_FORMAT_R32_FLOAT
= 216,
172 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
173 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
174 ISL_FORMAT_L32_UNORM
= 221,
175 ISL_FORMAT_A32_UNORM
= 222,
176 ISL_FORMAT_L16A16_UNORM
= 223,
177 ISL_FORMAT_I24X8_UNORM
= 224,
178 ISL_FORMAT_L24X8_UNORM
= 225,
179 ISL_FORMAT_A24X8_UNORM
= 226,
180 ISL_FORMAT_I32_FLOAT
= 227,
181 ISL_FORMAT_L32_FLOAT
= 228,
182 ISL_FORMAT_A32_FLOAT
= 229,
183 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
184 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
185 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
186 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
187 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
188 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
189 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
190 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
191 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
192 ISL_FORMAT_L16A16_FLOAT
= 240,
193 ISL_FORMAT_R32_UNORM
= 241,
194 ISL_FORMAT_R32_SNORM
= 242,
195 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
196 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
197 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
198 ISL_FORMAT_R16G16_SSCALED
= 246,
199 ISL_FORMAT_R16G16_USCALED
= 247,
200 ISL_FORMAT_R32_SSCALED
= 248,
201 ISL_FORMAT_R32_USCALED
= 249,
202 ISL_FORMAT_B5G6R5_UNORM
= 256,
203 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
204 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
205 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
206 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
207 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
208 ISL_FORMAT_R8G8_UNORM
= 262,
209 ISL_FORMAT_R8G8_SNORM
= 263,
210 ISL_FORMAT_R8G8_SINT
= 264,
211 ISL_FORMAT_R8G8_UINT
= 265,
212 ISL_FORMAT_R16_UNORM
= 266,
213 ISL_FORMAT_R16_SNORM
= 267,
214 ISL_FORMAT_R16_SINT
= 268,
215 ISL_FORMAT_R16_UINT
= 269,
216 ISL_FORMAT_R16_FLOAT
= 270,
217 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
218 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
219 ISL_FORMAT_I16_UNORM
= 273,
220 ISL_FORMAT_L16_UNORM
= 274,
221 ISL_FORMAT_A16_UNORM
= 275,
222 ISL_FORMAT_L8A8_UNORM
= 276,
223 ISL_FORMAT_I16_FLOAT
= 277,
224 ISL_FORMAT_L16_FLOAT
= 278,
225 ISL_FORMAT_A16_FLOAT
= 279,
226 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
227 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
228 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
229 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
230 ISL_FORMAT_R8G8_SSCALED
= 284,
231 ISL_FORMAT_R8G8_USCALED
= 285,
232 ISL_FORMAT_R16_SSCALED
= 286,
233 ISL_FORMAT_R16_USCALED
= 287,
234 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
235 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
236 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
237 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
238 ISL_FORMAT_L8A8_UINT
= 294,
239 ISL_FORMAT_L8A8_SINT
= 295,
240 ISL_FORMAT_R8_UNORM
= 320,
241 ISL_FORMAT_R8_SNORM
= 321,
242 ISL_FORMAT_R8_SINT
= 322,
243 ISL_FORMAT_R8_UINT
= 323,
244 ISL_FORMAT_A8_UNORM
= 324,
245 ISL_FORMAT_I8_UNORM
= 325,
246 ISL_FORMAT_L8_UNORM
= 326,
247 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
248 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
249 ISL_FORMAT_R8_SSCALED
= 329,
250 ISL_FORMAT_R8_USCALED
= 330,
251 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
252 ISL_FORMAT_L8_UNORM_SRGB
= 332,
253 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
254 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
255 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
256 ISL_FORMAT_Y8_UNORM
= 336,
257 ISL_FORMAT_L8_UINT
= 338,
258 ISL_FORMAT_L8_SINT
= 339,
259 ISL_FORMAT_I8_UINT
= 340,
260 ISL_FORMAT_I8_SINT
= 341,
261 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
262 ISL_FORMAT_R1_UNORM
= 385,
263 ISL_FORMAT_YCRCB_NORMAL
= 386,
264 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
265 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
266 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
267 ISL_FORMAT_BC1_UNORM
= 390,
268 ISL_FORMAT_BC2_UNORM
= 391,
269 ISL_FORMAT_BC3_UNORM
= 392,
270 ISL_FORMAT_BC4_UNORM
= 393,
271 ISL_FORMAT_BC5_UNORM
= 394,
272 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
273 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
274 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
275 ISL_FORMAT_MONO8
= 398,
276 ISL_FORMAT_YCRCB_SWAPUV
= 399,
277 ISL_FORMAT_YCRCB_SWAPY
= 400,
278 ISL_FORMAT_DXT1_RGB
= 401,
279 ISL_FORMAT_FXT1
= 402,
280 ISL_FORMAT_R8G8B8_UNORM
= 403,
281 ISL_FORMAT_R8G8B8_SNORM
= 404,
282 ISL_FORMAT_R8G8B8_SSCALED
= 405,
283 ISL_FORMAT_R8G8B8_USCALED
= 406,
284 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
285 ISL_FORMAT_R64G64B64_FLOAT
= 408,
286 ISL_FORMAT_BC4_SNORM
= 409,
287 ISL_FORMAT_BC5_SNORM
= 410,
288 ISL_FORMAT_R16G16B16_FLOAT
= 411,
289 ISL_FORMAT_R16G16B16_UNORM
= 412,
290 ISL_FORMAT_R16G16B16_SNORM
= 413,
291 ISL_FORMAT_R16G16B16_SSCALED
= 414,
292 ISL_FORMAT_R16G16B16_USCALED
= 415,
293 ISL_FORMAT_BC6H_SF16
= 417,
294 ISL_FORMAT_BC7_UNORM
= 418,
295 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
296 ISL_FORMAT_BC6H_UF16
= 420,
297 ISL_FORMAT_PLANAR_420_8
= 421,
298 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
299 ISL_FORMAT_ETC1_RGB8
= 425,
300 ISL_FORMAT_ETC2_RGB8
= 426,
301 ISL_FORMAT_EAC_R11
= 427,
302 ISL_FORMAT_EAC_RG11
= 428,
303 ISL_FORMAT_EAC_SIGNED_R11
= 429,
304 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
305 ISL_FORMAT_ETC2_SRGB8
= 431,
306 ISL_FORMAT_R16G16B16_UINT
= 432,
307 ISL_FORMAT_R16G16B16_SINT
= 433,
308 ISL_FORMAT_R32_SFIXED
= 434,
309 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
310 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
311 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
312 ISL_FORMAT_R10G10B10A2_SINT
= 438,
313 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
314 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
315 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
316 ISL_FORMAT_B10G10R10A2_UINT
= 442,
317 ISL_FORMAT_B10G10R10A2_SINT
= 443,
318 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
319 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
320 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
321 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
322 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
323 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
324 ISL_FORMAT_R8G8B8_UINT
= 456,
325 ISL_FORMAT_R8G8B8_SINT
= 457,
326 ISL_FORMAT_RAW
= 511,
327 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
328 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
329 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
330 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
331 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
332 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
333 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
334 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
335 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
336 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
337 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
338 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
339 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
340 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
341 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
342 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
343 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
344 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
345 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
346 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
347 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
348 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
349 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
350 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
351 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
352 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
353 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
354 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
356 /* The formats that follow are internal to ISL and as such don't have an
357 * explicit number. We'll just let the C compiler assign it for us. Any
358 * actual hardware formats *must* come before these in the list.
361 /* Formats for color compression surfaces */
367 ISL_FORMAT_GEN7_CCS_32BPP_X
,
368 ISL_FORMAT_GEN7_CCS_64BPP_X
,
369 ISL_FORMAT_GEN7_CCS_128BPP_X
,
370 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
371 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
372 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
373 ISL_FORMAT_GEN9_CCS_32BPP
,
374 ISL_FORMAT_GEN9_CCS_64BPP
,
375 ISL_FORMAT_GEN9_CCS_128BPP
,
377 /* Hardware doesn't understand this out-of-band value */
378 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
382 * Numerical base type for channels of isl_format.
400 * Colorspace of isl_format.
402 enum isl_colorspace
{
403 ISL_COLORSPACE_NONE
= 0,
404 ISL_COLORSPACE_LINEAR
,
410 * Texture compression mode of isl_format.
425 /* Used for auxiliary surface formats */
432 * @brief Hardware tile mode
434 * WARNING: These values differ from the hardware enum values, which are
435 * unstable across hardware generations.
437 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
438 * clearly distinguish it from Yf and Ys.
441 ISL_TILING_LINEAR
= 0,
444 ISL_TILING_Y0
, /**< Legacy Y tiling */
445 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
446 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
447 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
448 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
452 * @defgroup Tiling Flags
455 typedef uint32_t isl_tiling_flags_t
;
456 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
457 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
458 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
459 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
460 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
461 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
462 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
463 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
464 #define ISL_TILING_ANY_MASK (~0u)
465 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
467 /** Any Y tiling, including legacy Y tiling. */
468 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
469 ISL_TILING_Yf_BIT | \
472 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
473 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
478 * @brief Logical dimension of surface.
480 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
481 * as 2D array surfaces.
490 * @brief Physical layout of the surface's dimensions.
492 enum isl_dim_layout
{
494 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
495 * 6.17.3: 2D Surfaces.
497 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
498 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
500 * One-dimensional surfaces are identical to 2D surfaces with height of
503 * @invariant isl_surf::phys_level0_sa::depth == 1
505 ISL_DIM_LAYOUT_GEN4_2D
,
508 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
509 * 6.17.5: 3D Surfaces.
511 * @invariant isl_surf::phys_level0_sa::array_len == 1
513 ISL_DIM_LAYOUT_GEN4_3D
,
516 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
517 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
519 ISL_DIM_LAYOUT_GEN9_1D
,
523 /** No Auxiliary surface is used */
526 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
529 /** The auxiliary surface is an MCS
531 * @invariant isl_surf::samples > 1
535 /** The auxiliary surface is a fast-clear-only compression surface
537 * @invariant isl_surf::samples == 1
541 /** The auxiliary surface provides full lossless color compression
543 * @invariant isl_surf::samples == 1
548 /* TODO(chadv): Explain */
549 enum isl_array_pitch_span
{
550 ISL_ARRAY_PITCH_SPAN_FULL
,
551 ISL_ARRAY_PITCH_SPAN_COMPACT
,
555 * @defgroup Surface Usage
558 typedef uint64_t isl_surf_usage_flags_t
;
559 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
560 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
561 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
562 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
563 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
564 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
565 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
566 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
567 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
568 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
569 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
570 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
571 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
572 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
573 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
574 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
578 * @brief A channel select (also known as texture swizzle) value
580 enum isl_channel_select
{
581 ISL_CHANNEL_SELECT_ZERO
= 0,
582 ISL_CHANNEL_SELECT_ONE
= 1,
583 ISL_CHANNEL_SELECT_RED
= 4,
584 ISL_CHANNEL_SELECT_GREEN
= 5,
585 ISL_CHANNEL_SELECT_BLUE
= 6,
586 ISL_CHANNEL_SELECT_ALPHA
= 7,
590 * Identical to VkSampleCountFlagBits.
592 enum isl_sample_count
{
593 ISL_SAMPLE_COUNT_1_BIT
= 1u,
594 ISL_SAMPLE_COUNT_2_BIT
= 2u,
595 ISL_SAMPLE_COUNT_4_BIT
= 4u,
596 ISL_SAMPLE_COUNT_8_BIT
= 8u,
597 ISL_SAMPLE_COUNT_16_BIT
= 16u,
599 typedef uint32_t isl_sample_count_mask_t
;
602 * @brief Multisample Format
604 enum isl_msaa_layout
{
606 * @brief Suface is single-sampled.
608 ISL_MSAA_LAYOUT_NONE
,
611 * @brief [SNB+] Interleaved Multisample Format
613 * In this format, multiple samples are interleaved into each cacheline.
614 * In other words, the sample index is swizzled into the low 6 bits of the
615 * surface's virtual address space.
617 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
618 * and its pixel format is 32bpp. Then the first cacheline is arranged
621 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
622 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
624 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
625 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
627 * The hardware docs refer to this format with multiple terms. In
628 * Sandybridge, this is the only multisample format; so no term is used.
629 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
630 * Multisample Surface). Later hardware docs additionally refer to this
631 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
634 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
637 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
638 * Multisampled Surfaces".
640 ISL_MSAA_LAYOUT_INTERLEAVED
,
643 * @brief [IVB+] Array Multisample Format
645 * In this format, the surface's physical layout resembles that of a
648 * Suppose the multisample surface's logical extent is (w, h) and its
649 * sample count is N. Then surface's physical extent is the same as
650 * a singlesample 2D surface whose logical extent is (w, h) and array
651 * length is N. Array slice `i` contains the pixel values for sample
654 * The Ivybridge docs refer to surfaces in this format as UMS
655 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
656 * Surface). The Broadwell docs additionally refer to this format as
657 * MSFMT_MSS (MSS=Multisample Surface Storage).
659 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
660 * Multisample Surfaces".
662 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
663 * Multisample Surfaces".
665 ISL_MSAA_LAYOUT_ARRAY
,
670 const struct gen_device_info
*info
;
671 bool use_separate_stencil
;
672 bool has_bit6_swizzling
;
675 struct isl_extent2d
{
676 union { uint32_t w
, width
; };
677 union { uint32_t h
, height
; };
680 struct isl_extent3d
{
681 union { uint32_t w
, width
; };
682 union { uint32_t h
, height
; };
683 union { uint32_t d
, depth
; };
686 struct isl_extent4d
{
687 union { uint32_t w
, width
; };
688 union { uint32_t h
, height
; };
689 union { uint32_t d
, depth
; };
690 union { uint32_t a
, array_len
; };
693 struct isl_channel_layout
{
694 enum isl_base_type type
;
695 uint8_t bits
; /**< Size in bits */
699 * Each format has 3D block extent (width, height, depth). The block extent of
700 * compressed formats is that of the format's compression block. For example,
701 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
702 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
703 * is (w=1, h=1, d=1).
705 struct isl_format_layout
{
706 enum isl_format format
;
709 uint16_t bpb
; /**< Bits per block */
710 uint8_t bw
; /**< Block width, in pixels */
711 uint8_t bh
; /**< Block height, in pixels */
712 uint8_t bd
; /**< Block depth, in pixels */
715 struct isl_channel_layout r
; /**< Red channel */
716 struct isl_channel_layout g
; /**< Green channel */
717 struct isl_channel_layout b
; /**< Blue channel */
718 struct isl_channel_layout a
; /**< Alpha channel */
719 struct isl_channel_layout l
; /**< Luminance channel */
720 struct isl_channel_layout i
; /**< Intensity channel */
721 struct isl_channel_layout p
; /**< Palette channel */
724 enum isl_colorspace colorspace
;
728 struct isl_tile_info
{
729 enum isl_tiling tiling
;
731 /** The logical size of the tile in units of surface elements
733 * This field determines how a given surface is cut up into tiles. It is
734 * used to compute the size of a surface in tiles and can be used to
735 * determine the location of the tile containing any given surface element.
736 * The exact value of this field depends heavily on the bits-per-block of
737 * the format being used.
739 struct isl_extent2d logical_extent_el
;
741 /** The physical size of the tile in bytes and rows of bytes
743 * This field determines how the tiles of a surface are physically layed
744 * out in memory. The logical and physical tile extent are frequently the
745 * same but this is not always the case. For instance, a W-tile (which is
746 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
747 * its physical size is 128B x 32rows, the same as a Y-tile.
749 * @see isl_surf::row_pitch
751 struct isl_extent2d phys_extent_B
;
755 * @brief Input to surface initialization
757 * @invariant width >= 1
758 * @invariant height >= 1
759 * @invariant depth >= 1
760 * @invariant levels >= 1
761 * @invariant samples >= 1
762 * @invariant array_len >= 1
764 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
765 * @invariant if 2D then depth == 1
766 * @invariant if 3D then array_len == 1 and samples == 1
768 struct isl_surf_init_info
{
769 enum isl_surf_dim dim
;
770 enum isl_format format
;
779 /** Lower bound for isl_surf::alignment, in bytes. */
780 uint32_t min_alignment
;
782 /** Lower bound for isl_surf::pitch, in bytes. */
785 isl_surf_usage_flags_t usage
;
787 /** Flags that alter how ISL selects isl_surf::tiling. */
788 isl_tiling_flags_t tiling_flags
;
792 enum isl_surf_dim dim
;
793 enum isl_dim_layout dim_layout
;
794 enum isl_msaa_layout msaa_layout
;
795 enum isl_tiling tiling
;
796 enum isl_format format
;
799 * Alignment of the upper-left sample of each subimage, in units of surface
802 struct isl_extent3d image_alignment_el
;
805 * Logical extent of the surface's base level, in units of pixels. This is
806 * identical to the extent defined in isl_surf_init_info.
808 struct isl_extent4d logical_level0_px
;
811 * Physical extent of the surface's base level, in units of physical
812 * surface samples and aligned to the format's compression block.
814 * Consider isl_dim_layout as an operator that transforms a logical surface
815 * layout to a physical surface layout. Then
817 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
818 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
820 struct isl_extent4d phys_level0_sa
;
825 /** Total size of the surface, in bytes. */
828 /** Required alignment for the surface's base address. */
832 * The interpretation of this field depends on the value of
833 * isl_tile_info::physical_extent_B. In particular, the width of the
834 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
835 * and the distance in bytes between vertically adjacent tiles in the image
836 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
838 * For linear images where isl_tile_info::physical_extent_B.height == 1,
839 * this cleanly reduces to being the distance, in bytes, between vertically
840 * adjacent surface elements.
842 * @see isl_tile_info::phys_extent_B;
847 * Pitch between physical array slices, in rows of surface elements.
849 uint32_t array_pitch_el_rows
;
851 enum isl_array_pitch_span array_pitch_span
;
853 /** Copy of isl_surf_init_info::usage. */
854 isl_surf_usage_flags_t usage
;
859 * Indicates the usage of the particular view
861 * Normally, this is one bit. However, for a cube map texture, it
862 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
864 isl_surf_usage_flags_t usage
;
867 * The format to use in the view
869 * This may differ from the format of the actual isl_surf but must have
870 * the same block size.
872 enum isl_format format
;
880 * For cube maps, both base_array_layer and array_len should be
881 * specified in terms of 2-D layers and must be a multiple of 6.
883 uint32_t base_array_layer
;
886 enum isl_channel_select channel_select
[4];
889 union isl_color_value
{
895 struct isl_surf_fill_state_info
{
896 const struct isl_surf
*surf
;
897 const struct isl_view
*view
;
900 * The address of the surface in GPU memory.
905 * The Memory Object Control state for the filled surface state.
907 * The exact format of this value depends on hardware generation.
912 * The auxilary surface or NULL if no auxilary surface is to be used.
914 const struct isl_surf
*aux_surf
;
915 enum isl_aux_usage aux_usage
;
916 uint64_t aux_address
;
919 * The clear color for this surface
921 * Valid values depend on hardware generation.
923 union isl_color_value clear_color
;
925 /* Intra-tile offset */
926 uint16_t x_offset_sa
, y_offset_sa
;
929 struct isl_buffer_fill_state_info
{
931 * The address of the surface in GPU memory.
936 * The size of the buffer
941 * The Memory Object Control state for the filled surface state.
943 * The exact format of this value depends on hardware generation.
948 * The format to use in the surface state
950 * This may differ from the format of the actual isl_surf but have the
953 enum isl_format format
;
958 extern const struct isl_format_layout isl_format_layouts
[];
961 isl_device_init(struct isl_device
*dev
,
962 const struct gen_device_info
*info
,
963 bool has_bit6_swizzling
);
965 isl_sample_count_mask_t ATTRIBUTE_CONST
966 isl_device_get_sample_counts(struct isl_device
*dev
);
968 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
969 isl_format_get_layout(enum isl_format fmt
)
971 return &isl_format_layouts
[fmt
];
974 static inline const char * ATTRIBUTE_CONST
975 isl_format_get_name(enum isl_format fmt
)
977 return isl_format_layouts
[fmt
].name
;
980 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
981 enum isl_format format
);
982 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
983 enum isl_format format
);
984 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
985 enum isl_format format
);
986 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
987 enum isl_format format
);
988 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
989 enum isl_format format
);
990 bool isl_format_supports_lossless_compression(const struct gen_device_info
*devinfo
,
991 enum isl_format format
);
993 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
994 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
995 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
996 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
997 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
998 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1001 isl_format_has_normalized_channel(enum isl_format fmt
)
1003 return isl_format_has_unorm_channel(fmt
) ||
1004 isl_format_has_snorm_channel(fmt
);
1008 isl_format_has_float_channel(enum isl_format fmt
)
1010 return isl_format_has_ufloat_channel(fmt
) ||
1011 isl_format_has_sfloat_channel(fmt
);
1015 isl_format_has_int_channel(enum isl_format fmt
)
1017 return isl_format_has_uint_channel(fmt
) ||
1018 isl_format_has_sint_channel(fmt
);
1021 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1023 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1026 isl_format_is_compressed(enum isl_format fmt
)
1028 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1030 return fmtl
->txc
!= ISL_TXC_NONE
;
1034 isl_format_has_bc_compression(enum isl_format fmt
)
1036 switch (isl_format_get_layout(fmt
)->txc
) {
1054 unreachable("Should not be called on an aux surface");
1057 unreachable("bad texture compression mode");
1062 isl_format_is_yuv(enum isl_format fmt
)
1064 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1066 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1070 isl_format_block_is_1x1x1(enum isl_format fmt
)
1072 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1074 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1078 isl_format_is_rgb(enum isl_format fmt
)
1080 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
1081 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
1082 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
1083 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
1086 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1087 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1089 bool isl_is_storage_image_format(enum isl_format fmt
);
1092 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1093 enum isl_format fmt
);
1095 /* Returns true if this hardware supports typed load/store on a format with
1096 * the same size as the given format.
1099 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1100 enum isl_format fmt
);
1103 isl_tiling_is_any_y(enum isl_tiling tiling
)
1105 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1109 isl_tiling_is_std_y(enum isl_tiling tiling
)
1111 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1115 isl_tiling_get_info(const struct isl_device
*dev
,
1116 enum isl_tiling tiling
,
1117 uint32_t format_bpb
,
1118 struct isl_tile_info
*info
);
1120 isl_surf_choose_tiling(const struct isl_device
*dev
,
1121 const struct isl_surf_init_info
*restrict info
,
1122 enum isl_tiling
*tiling
);
1125 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1127 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1131 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1133 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1137 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1139 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1143 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1145 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1146 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1150 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1152 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1156 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1158 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1159 (info
->format
== ISL_FORMAT_R16_UNORM
);
1163 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1165 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1166 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1169 static inline struct isl_extent2d
1170 isl_extent2d(uint32_t width
, uint32_t height
)
1172 struct isl_extent2d e
= { { 0 } };
1180 static inline struct isl_extent3d
1181 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1183 struct isl_extent3d e
= { { 0 } };
1192 static inline struct isl_extent4d
1193 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1196 struct isl_extent4d e
= { { 0 } };
1201 e
.array_len
= array_len
;
1206 #define isl_surf_init(dev, surf, ...) \
1207 isl_surf_init_s((dev), (surf), \
1208 &(struct isl_surf_init_info) { __VA_ARGS__ });
1211 isl_surf_init_s(const struct isl_device
*dev
,
1212 struct isl_surf
*surf
,
1213 const struct isl_surf_init_info
*restrict info
);
1216 isl_surf_get_tile_info(const struct isl_device
*dev
,
1217 const struct isl_surf
*surf
,
1218 struct isl_tile_info
*tile_info
);
1221 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1222 const struct isl_surf
*surf
,
1223 struct isl_surf
*hiz_surf
);
1226 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1227 const struct isl_surf
*surf
,
1228 struct isl_surf
*mcs_surf
);
1231 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1232 const struct isl_surf
*surf
,
1233 struct isl_surf
*ccs_surf
);
1235 #define isl_surf_fill_state(dev, state, ...) \
1236 isl_surf_fill_state_s((dev), (state), \
1237 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1240 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1241 const struct isl_surf_fill_state_info
*restrict info
);
1243 #define isl_buffer_fill_state(dev, state, ...) \
1244 isl_buffer_fill_state_s((dev), (state), \
1245 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1248 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1249 const struct isl_buffer_fill_state_info
*restrict info
);
1252 isl_surf_fill_image_param(const struct isl_device
*dev
,
1253 struct brw_image_param
*param
,
1254 const struct isl_surf
*surf
,
1255 const struct isl_view
*view
);
1258 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1259 struct brw_image_param
*param
,
1260 enum isl_format format
,
1264 * Alignment of the upper-left sample of each subimage, in units of surface
1267 static inline struct isl_extent3d
1268 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1270 return surf
->image_alignment_el
;
1274 * Alignment of the upper-left sample of each subimage, in units of surface
1277 static inline struct isl_extent3d
1278 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1280 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1282 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1283 fmtl
->bh
* surf
->image_alignment_el
.h
,
1284 fmtl
->bd
* surf
->image_alignment_el
.d
);
1288 * Pitch between vertically adjacent surface elements, in bytes.
1290 static inline uint32_t
1291 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
1293 return surf
->row_pitch
;
1297 * Pitch between vertically adjacent surface elements, in units of surface elements.
1299 static inline uint32_t
1300 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1302 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1304 assert(surf
->row_pitch
% (fmtl
->bpb
/ 8) == 0);
1305 return surf
->row_pitch
/ (fmtl
->bpb
/ 8);
1309 * Pitch between physical array slices, in rows of surface elements.
1311 static inline uint32_t
1312 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1314 return surf
->array_pitch_el_rows
;
1318 * Pitch between physical array slices, in units of surface elements.
1320 static inline uint32_t
1321 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1323 return isl_surf_get_array_pitch_el_rows(surf
) *
1324 isl_surf_get_row_pitch_el(surf
);
1328 * Pitch between physical array slices, in rows of surface samples.
1330 static inline uint32_t
1331 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1333 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1334 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1338 * Pitch between physical array slices, in bytes.
1340 static inline uint32_t
1341 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1343 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
1347 * Calculate the offset, in units of surface samples, to a subimage in the
1350 * @invariant level < surface levels
1351 * @invariant logical_array_layer < logical array length of surface
1352 * @invariant logical_z_offset_px < logical depth of surface at level
1355 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1357 uint32_t logical_array_layer
,
1358 uint32_t logical_z_offset_px
,
1359 uint32_t *x_offset_sa
,
1360 uint32_t *y_offset_sa
);
1363 * Calculate the offset, in units of surface elements, to a subimage in the
1366 * @invariant level < surface levels
1367 * @invariant logical_array_layer < logical array length of surface
1368 * @invariant logical_z_offset_px < logical depth of surface at level
1371 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1373 uint32_t logical_array_layer
,
1374 uint32_t logical_z_offset_px
,
1375 uint32_t *x_offset_el
,
1376 uint32_t *y_offset_el
);
1379 * @brief Calculate the intratile offsets to a surface.
1381 * In @a base_address_offset return the offset from the base of the surface to
1382 * the base address of the first tile of the subimage. In @a x_offset_B and
1383 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1384 * tile's base to the subimage's first surface element. The x and y offsets
1385 * are intratile offsets; that is, they do not exceed the boundary of the
1386 * surface's tiling format.
1389 isl_tiling_get_intratile_offset_el(const struct isl_device
*dev
,
1390 enum isl_tiling tiling
,
1393 uint32_t total_x_offset_el
,
1394 uint32_t total_y_offset_el
,
1395 uint32_t *base_address_offset
,
1396 uint32_t *x_offset_el
,
1397 uint32_t *y_offset_el
);
1400 isl_tiling_get_intratile_offset_sa(const struct isl_device
*dev
,
1401 enum isl_tiling tiling
,
1402 enum isl_format format
,
1404 uint32_t total_x_offset_sa
,
1405 uint32_t total_y_offset_sa
,
1406 uint32_t *base_address_offset
,
1407 uint32_t *x_offset_sa
,
1408 uint32_t *y_offset_sa
)
1410 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1412 assert(fmtl
->bpb
% 8 == 0);
1414 /* For computing the intratile offsets, we actually want a strange unit
1415 * which is samples for multisampled surfaces but elements for compressed
1418 assert(total_x_offset_sa
% fmtl
->bw
== 0);
1419 assert(total_y_offset_sa
% fmtl
->bw
== 0);
1420 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
1421 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
1423 isl_tiling_get_intratile_offset_el(dev
, tiling
, fmtl
->bpb
/ 8, row_pitch
,
1424 total_x_offset
, total_y_offset
,
1425 base_address_offset
,
1426 x_offset_sa
, y_offset_sa
);
1427 *x_offset_sa
*= fmtl
->bw
;
1428 *y_offset_sa
*= fmtl
->bh
;
1432 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1434 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1435 * @pre surf->format must be a valid format for depth surfaces
1438 isl_surf_get_depth_format(const struct isl_device
*dev
,
1439 const struct isl_surf
*surf
);