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intel/isl: Add an isl_swizzle structure and use it for isl_view swizzles
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #pragma once
39
40 #include <assert.h>
41 #include <stdbool.h>
42 #include <stdint.h>
43
44 #include "c99_compat.h"
45 #include "util/macros.h"
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 struct gen_device_info;
52 struct brw_image_param;
53
54 #ifndef ISL_DEV_GEN
55 /**
56 * @brief Get the hardware generation of isl_device.
57 *
58 * You can define this as a compile-time constant in the CFLAGS. For example,
59 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
60 */
61 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
62 #define ISL_DEV_GEN_SANITIZE(__dev)
63 #else
64 #define ISL_DEV_GEN_SANITIZE(__dev) \
65 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
66 #endif
67
68 #ifndef ISL_DEV_IS_G4X
69 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
70 #endif
71
72 #ifndef ISL_DEV_IS_HASWELL
73 /**
74 * @brief Get the hardware generation of isl_device.
75 *
76 * You can define this as a compile-time constant in the CFLAGS. For example,
77 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
78 */
79 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
80 #endif
81
82 #ifndef ISL_DEV_IS_BAYTRAIL
83 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
84 #endif
85
86 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
87 /**
88 * You can define this as a compile-time constant in the CFLAGS. For example,
89 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
90 */
91 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
92 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
93 #else
94 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
95 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
96 #endif
97
98 /**
99 * Hardware enumeration SURFACE_FORMAT.
100 *
101 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
102 * Enumerations: SURFACE_FORMAT.
103 */
104 enum isl_format {
105 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
106 ISL_FORMAT_R32G32B32A32_SINT = 1,
107 ISL_FORMAT_R32G32B32A32_UINT = 2,
108 ISL_FORMAT_R32G32B32A32_UNORM = 3,
109 ISL_FORMAT_R32G32B32A32_SNORM = 4,
110 ISL_FORMAT_R64G64_FLOAT = 5,
111 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
112 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
113 ISL_FORMAT_R32G32B32A32_USCALED = 8,
114 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
115 ISL_FORMAT_R64G64_PASSTHRU = 33,
116 ISL_FORMAT_R32G32B32_FLOAT = 64,
117 ISL_FORMAT_R32G32B32_SINT = 65,
118 ISL_FORMAT_R32G32B32_UINT = 66,
119 ISL_FORMAT_R32G32B32_UNORM = 67,
120 ISL_FORMAT_R32G32B32_SNORM = 68,
121 ISL_FORMAT_R32G32B32_SSCALED = 69,
122 ISL_FORMAT_R32G32B32_USCALED = 70,
123 ISL_FORMAT_R32G32B32_SFIXED = 80,
124 ISL_FORMAT_R16G16B16A16_UNORM = 128,
125 ISL_FORMAT_R16G16B16A16_SNORM = 129,
126 ISL_FORMAT_R16G16B16A16_SINT = 130,
127 ISL_FORMAT_R16G16B16A16_UINT = 131,
128 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
129 ISL_FORMAT_R32G32_FLOAT = 133,
130 ISL_FORMAT_R32G32_SINT = 134,
131 ISL_FORMAT_R32G32_UINT = 135,
132 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
133 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
134 ISL_FORMAT_L32A32_FLOAT = 138,
135 ISL_FORMAT_R32G32_UNORM = 139,
136 ISL_FORMAT_R32G32_SNORM = 140,
137 ISL_FORMAT_R64_FLOAT = 141,
138 ISL_FORMAT_R16G16B16X16_UNORM = 142,
139 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
140 ISL_FORMAT_A32X32_FLOAT = 144,
141 ISL_FORMAT_L32X32_FLOAT = 145,
142 ISL_FORMAT_I32X32_FLOAT = 146,
143 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
144 ISL_FORMAT_R16G16B16A16_USCALED = 148,
145 ISL_FORMAT_R32G32_SSCALED = 149,
146 ISL_FORMAT_R32G32_USCALED = 150,
147 ISL_FORMAT_R32G32_FLOAT_LD = 151,
148 ISL_FORMAT_R32G32_SFIXED = 160,
149 ISL_FORMAT_R64_PASSTHRU = 161,
150 ISL_FORMAT_B8G8R8A8_UNORM = 192,
151 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
152 ISL_FORMAT_R10G10B10A2_UNORM = 194,
153 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
154 ISL_FORMAT_R10G10B10A2_UINT = 196,
155 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
156 ISL_FORMAT_R8G8B8A8_UNORM = 199,
157 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
158 ISL_FORMAT_R8G8B8A8_SNORM = 201,
159 ISL_FORMAT_R8G8B8A8_SINT = 202,
160 ISL_FORMAT_R8G8B8A8_UINT = 203,
161 ISL_FORMAT_R16G16_UNORM = 204,
162 ISL_FORMAT_R16G16_SNORM = 205,
163 ISL_FORMAT_R16G16_SINT = 206,
164 ISL_FORMAT_R16G16_UINT = 207,
165 ISL_FORMAT_R16G16_FLOAT = 208,
166 ISL_FORMAT_B10G10R10A2_UNORM = 209,
167 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
168 ISL_FORMAT_R11G11B10_FLOAT = 211,
169 ISL_FORMAT_R32_SINT = 214,
170 ISL_FORMAT_R32_UINT = 215,
171 ISL_FORMAT_R32_FLOAT = 216,
172 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
173 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
174 ISL_FORMAT_L32_UNORM = 221,
175 ISL_FORMAT_A32_UNORM = 222,
176 ISL_FORMAT_L16A16_UNORM = 223,
177 ISL_FORMAT_I24X8_UNORM = 224,
178 ISL_FORMAT_L24X8_UNORM = 225,
179 ISL_FORMAT_A24X8_UNORM = 226,
180 ISL_FORMAT_I32_FLOAT = 227,
181 ISL_FORMAT_L32_FLOAT = 228,
182 ISL_FORMAT_A32_FLOAT = 229,
183 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
184 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
185 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
186 ISL_FORMAT_B8G8R8X8_UNORM = 233,
187 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
188 ISL_FORMAT_R8G8B8X8_UNORM = 235,
189 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
190 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
191 ISL_FORMAT_B10G10R10X2_UNORM = 238,
192 ISL_FORMAT_L16A16_FLOAT = 240,
193 ISL_FORMAT_R32_UNORM = 241,
194 ISL_FORMAT_R32_SNORM = 242,
195 ISL_FORMAT_R10G10B10X2_USCALED = 243,
196 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
197 ISL_FORMAT_R8G8B8A8_USCALED = 245,
198 ISL_FORMAT_R16G16_SSCALED = 246,
199 ISL_FORMAT_R16G16_USCALED = 247,
200 ISL_FORMAT_R32_SSCALED = 248,
201 ISL_FORMAT_R32_USCALED = 249,
202 ISL_FORMAT_B5G6R5_UNORM = 256,
203 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
204 ISL_FORMAT_B5G5R5A1_UNORM = 258,
205 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
206 ISL_FORMAT_B4G4R4A4_UNORM = 260,
207 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
208 ISL_FORMAT_R8G8_UNORM = 262,
209 ISL_FORMAT_R8G8_SNORM = 263,
210 ISL_FORMAT_R8G8_SINT = 264,
211 ISL_FORMAT_R8G8_UINT = 265,
212 ISL_FORMAT_R16_UNORM = 266,
213 ISL_FORMAT_R16_SNORM = 267,
214 ISL_FORMAT_R16_SINT = 268,
215 ISL_FORMAT_R16_UINT = 269,
216 ISL_FORMAT_R16_FLOAT = 270,
217 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
218 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
219 ISL_FORMAT_I16_UNORM = 273,
220 ISL_FORMAT_L16_UNORM = 274,
221 ISL_FORMAT_A16_UNORM = 275,
222 ISL_FORMAT_L8A8_UNORM = 276,
223 ISL_FORMAT_I16_FLOAT = 277,
224 ISL_FORMAT_L16_FLOAT = 278,
225 ISL_FORMAT_A16_FLOAT = 279,
226 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
227 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
228 ISL_FORMAT_B5G5R5X1_UNORM = 282,
229 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
230 ISL_FORMAT_R8G8_SSCALED = 284,
231 ISL_FORMAT_R8G8_USCALED = 285,
232 ISL_FORMAT_R16_SSCALED = 286,
233 ISL_FORMAT_R16_USCALED = 287,
234 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
235 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
236 ISL_FORMAT_A1B5G5R5_UNORM = 292,
237 ISL_FORMAT_A4B4G4R4_UNORM = 293,
238 ISL_FORMAT_L8A8_UINT = 294,
239 ISL_FORMAT_L8A8_SINT = 295,
240 ISL_FORMAT_R8_UNORM = 320,
241 ISL_FORMAT_R8_SNORM = 321,
242 ISL_FORMAT_R8_SINT = 322,
243 ISL_FORMAT_R8_UINT = 323,
244 ISL_FORMAT_A8_UNORM = 324,
245 ISL_FORMAT_I8_UNORM = 325,
246 ISL_FORMAT_L8_UNORM = 326,
247 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
248 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
249 ISL_FORMAT_R8_SSCALED = 329,
250 ISL_FORMAT_R8_USCALED = 330,
251 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
252 ISL_FORMAT_L8_UNORM_SRGB = 332,
253 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
254 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
255 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
256 ISL_FORMAT_Y8_UNORM = 336,
257 ISL_FORMAT_L8_UINT = 338,
258 ISL_FORMAT_L8_SINT = 339,
259 ISL_FORMAT_I8_UINT = 340,
260 ISL_FORMAT_I8_SINT = 341,
261 ISL_FORMAT_DXT1_RGB_SRGB = 384,
262 ISL_FORMAT_R1_UNORM = 385,
263 ISL_FORMAT_YCRCB_NORMAL = 386,
264 ISL_FORMAT_YCRCB_SWAPUVY = 387,
265 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
266 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
267 ISL_FORMAT_BC1_UNORM = 390,
268 ISL_FORMAT_BC2_UNORM = 391,
269 ISL_FORMAT_BC3_UNORM = 392,
270 ISL_FORMAT_BC4_UNORM = 393,
271 ISL_FORMAT_BC5_UNORM = 394,
272 ISL_FORMAT_BC1_UNORM_SRGB = 395,
273 ISL_FORMAT_BC2_UNORM_SRGB = 396,
274 ISL_FORMAT_BC3_UNORM_SRGB = 397,
275 ISL_FORMAT_MONO8 = 398,
276 ISL_FORMAT_YCRCB_SWAPUV = 399,
277 ISL_FORMAT_YCRCB_SWAPY = 400,
278 ISL_FORMAT_DXT1_RGB = 401,
279 ISL_FORMAT_FXT1 = 402,
280 ISL_FORMAT_R8G8B8_UNORM = 403,
281 ISL_FORMAT_R8G8B8_SNORM = 404,
282 ISL_FORMAT_R8G8B8_SSCALED = 405,
283 ISL_FORMAT_R8G8B8_USCALED = 406,
284 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
285 ISL_FORMAT_R64G64B64_FLOAT = 408,
286 ISL_FORMAT_BC4_SNORM = 409,
287 ISL_FORMAT_BC5_SNORM = 410,
288 ISL_FORMAT_R16G16B16_FLOAT = 411,
289 ISL_FORMAT_R16G16B16_UNORM = 412,
290 ISL_FORMAT_R16G16B16_SNORM = 413,
291 ISL_FORMAT_R16G16B16_SSCALED = 414,
292 ISL_FORMAT_R16G16B16_USCALED = 415,
293 ISL_FORMAT_BC6H_SF16 = 417,
294 ISL_FORMAT_BC7_UNORM = 418,
295 ISL_FORMAT_BC7_UNORM_SRGB = 419,
296 ISL_FORMAT_BC6H_UF16 = 420,
297 ISL_FORMAT_PLANAR_420_8 = 421,
298 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
299 ISL_FORMAT_ETC1_RGB8 = 425,
300 ISL_FORMAT_ETC2_RGB8 = 426,
301 ISL_FORMAT_EAC_R11 = 427,
302 ISL_FORMAT_EAC_RG11 = 428,
303 ISL_FORMAT_EAC_SIGNED_R11 = 429,
304 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
305 ISL_FORMAT_ETC2_SRGB8 = 431,
306 ISL_FORMAT_R16G16B16_UINT = 432,
307 ISL_FORMAT_R16G16B16_SINT = 433,
308 ISL_FORMAT_R32_SFIXED = 434,
309 ISL_FORMAT_R10G10B10A2_SNORM = 435,
310 ISL_FORMAT_R10G10B10A2_USCALED = 436,
311 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
312 ISL_FORMAT_R10G10B10A2_SINT = 438,
313 ISL_FORMAT_B10G10R10A2_SNORM = 439,
314 ISL_FORMAT_B10G10R10A2_USCALED = 440,
315 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
316 ISL_FORMAT_B10G10R10A2_UINT = 442,
317 ISL_FORMAT_B10G10R10A2_SINT = 443,
318 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
319 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
320 ISL_FORMAT_ETC2_RGB8_PTA = 448,
321 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
322 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
323 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
324 ISL_FORMAT_R8G8B8_UINT = 456,
325 ISL_FORMAT_R8G8B8_SINT = 457,
326 ISL_FORMAT_RAW = 511,
327 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
328 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
329 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
330 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
331 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
332 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
333 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
334 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
335 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
336 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
337 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
338 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
339 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
340 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
341 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
342 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
343 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
344 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
345 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
346 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
347 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
348 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
349 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
350 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
351 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
352 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
353 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
354 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
355
356 /* The formats that follow are internal to ISL and as such don't have an
357 * explicit number. We'll just let the C compiler assign it for us. Any
358 * actual hardware formats *must* come before these in the list.
359 */
360
361 /* Formats for color compression surfaces */
362 ISL_FORMAT_HIZ,
363 ISL_FORMAT_MCS_2X,
364 ISL_FORMAT_MCS_4X,
365 ISL_FORMAT_MCS_8X,
366 ISL_FORMAT_MCS_16X,
367 ISL_FORMAT_GEN7_CCS_32BPP_X,
368 ISL_FORMAT_GEN7_CCS_64BPP_X,
369 ISL_FORMAT_GEN7_CCS_128BPP_X,
370 ISL_FORMAT_GEN7_CCS_32BPP_Y,
371 ISL_FORMAT_GEN7_CCS_64BPP_Y,
372 ISL_FORMAT_GEN7_CCS_128BPP_Y,
373 ISL_FORMAT_GEN9_CCS_32BPP,
374 ISL_FORMAT_GEN9_CCS_64BPP,
375 ISL_FORMAT_GEN9_CCS_128BPP,
376
377 /* Hardware doesn't understand this out-of-band value */
378 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
379 };
380
381 /**
382 * Numerical base type for channels of isl_format.
383 */
384 enum isl_base_type {
385 ISL_VOID,
386 ISL_RAW,
387 ISL_UNORM,
388 ISL_SNORM,
389 ISL_UFLOAT,
390 ISL_SFLOAT,
391 ISL_UFIXED,
392 ISL_SFIXED,
393 ISL_UINT,
394 ISL_SINT,
395 ISL_USCALED,
396 ISL_SSCALED,
397 };
398
399 /**
400 * Colorspace of isl_format.
401 */
402 enum isl_colorspace {
403 ISL_COLORSPACE_NONE = 0,
404 ISL_COLORSPACE_LINEAR,
405 ISL_COLORSPACE_SRGB,
406 ISL_COLORSPACE_YUV,
407 };
408
409 /**
410 * Texture compression mode of isl_format.
411 */
412 enum isl_txc {
413 ISL_TXC_NONE = 0,
414 ISL_TXC_DXT1,
415 ISL_TXC_DXT3,
416 ISL_TXC_DXT5,
417 ISL_TXC_FXT1,
418 ISL_TXC_RGTC1,
419 ISL_TXC_RGTC2,
420 ISL_TXC_BPTC,
421 ISL_TXC_ETC1,
422 ISL_TXC_ETC2,
423 ISL_TXC_ASTC,
424
425 /* Used for auxiliary surface formats */
426 ISL_TXC_HIZ,
427 ISL_TXC_MCS,
428 ISL_TXC_CCS,
429 };
430
431 /**
432 * @brief Hardware tile mode
433 *
434 * WARNING: These values differ from the hardware enum values, which are
435 * unstable across hardware generations.
436 *
437 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
438 * clearly distinguish it from Yf and Ys.
439 */
440 enum isl_tiling {
441 ISL_TILING_LINEAR = 0,
442 ISL_TILING_W,
443 ISL_TILING_X,
444 ISL_TILING_Y0, /**< Legacy Y tiling */
445 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
446 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
447 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
448 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
449 };
450
451 /**
452 * @defgroup Tiling Flags
453 * @{
454 */
455 typedef uint32_t isl_tiling_flags_t;
456 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
457 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
458 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
459 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
460 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
461 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
462 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
463 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
464 #define ISL_TILING_ANY_MASK (~0u)
465 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
466
467 /** Any Y tiling, including legacy Y tiling. */
468 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
469 ISL_TILING_Yf_BIT | \
470 ISL_TILING_Ys_BIT)
471
472 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
473 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
474 ISL_TILING_Ys_BIT)
475 /** @} */
476
477 /**
478 * @brief Logical dimension of surface.
479 *
480 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
481 * as 2D array surfaces.
482 */
483 enum isl_surf_dim {
484 ISL_SURF_DIM_1D,
485 ISL_SURF_DIM_2D,
486 ISL_SURF_DIM_3D,
487 };
488
489 /**
490 * @brief Physical layout of the surface's dimensions.
491 */
492 enum isl_dim_layout {
493 /**
494 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
495 * 6.17.3: 2D Surfaces.
496 *
497 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
498 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
499 *
500 * One-dimensional surfaces are identical to 2D surfaces with height of
501 * one.
502 *
503 * @invariant isl_surf::phys_level0_sa::depth == 1
504 */
505 ISL_DIM_LAYOUT_GEN4_2D,
506
507 /**
508 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
509 * 6.17.5: 3D Surfaces.
510 *
511 * @invariant isl_surf::phys_level0_sa::array_len == 1
512 */
513 ISL_DIM_LAYOUT_GEN4_3D,
514
515 /**
516 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
517 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
518 */
519 ISL_DIM_LAYOUT_GEN9_1D,
520 };
521
522 enum isl_aux_usage {
523 /** No Auxiliary surface is used */
524 ISL_AUX_USAGE_NONE,
525
526 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
527 ISL_AUX_USAGE_HIZ,
528
529 /** The auxiliary surface is an MCS
530 *
531 * @invariant isl_surf::samples > 1
532 */
533 ISL_AUX_USAGE_MCS,
534
535 /** The auxiliary surface is a fast-clear-only compression surface
536 *
537 * @invariant isl_surf::samples == 1
538 */
539 ISL_AUX_USAGE_CCS_D,
540
541 /** The auxiliary surface provides full lossless color compression
542 *
543 * @invariant isl_surf::samples == 1
544 */
545 ISL_AUX_USAGE_CCS_E,
546 };
547
548 /* TODO(chadv): Explain */
549 enum isl_array_pitch_span {
550 ISL_ARRAY_PITCH_SPAN_FULL,
551 ISL_ARRAY_PITCH_SPAN_COMPACT,
552 };
553
554 /**
555 * @defgroup Surface Usage
556 * @{
557 */
558 typedef uint64_t isl_surf_usage_flags_t;
559 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
560 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
561 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
562 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
563 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
564 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
565 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
566 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
567 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
568 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
569 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
570 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
571 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
572 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
573 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
574 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
575 /** @} */
576
577 /**
578 * @brief A channel select (also known as texture swizzle) value
579 */
580 enum isl_channel_select {
581 ISL_CHANNEL_SELECT_ZERO = 0,
582 ISL_CHANNEL_SELECT_ONE = 1,
583 ISL_CHANNEL_SELECT_RED = 4,
584 ISL_CHANNEL_SELECT_GREEN = 5,
585 ISL_CHANNEL_SELECT_BLUE = 6,
586 ISL_CHANNEL_SELECT_ALPHA = 7,
587 };
588
589 /**
590 * Identical to VkSampleCountFlagBits.
591 */
592 enum isl_sample_count {
593 ISL_SAMPLE_COUNT_1_BIT = 1u,
594 ISL_SAMPLE_COUNT_2_BIT = 2u,
595 ISL_SAMPLE_COUNT_4_BIT = 4u,
596 ISL_SAMPLE_COUNT_8_BIT = 8u,
597 ISL_SAMPLE_COUNT_16_BIT = 16u,
598 };
599 typedef uint32_t isl_sample_count_mask_t;
600
601 /**
602 * @brief Multisample Format
603 */
604 enum isl_msaa_layout {
605 /**
606 * @brief Suface is single-sampled.
607 */
608 ISL_MSAA_LAYOUT_NONE,
609
610 /**
611 * @brief [SNB+] Interleaved Multisample Format
612 *
613 * In this format, multiple samples are interleaved into each cacheline.
614 * In other words, the sample index is swizzled into the low 6 bits of the
615 * surface's virtual address space.
616 *
617 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
618 * and its pixel format is 32bpp. Then the first cacheline is arranged
619 * thus:
620 *
621 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
622 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
623 *
624 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
625 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
626 *
627 * The hardware docs refer to this format with multiple terms. In
628 * Sandybridge, this is the only multisample format; so no term is used.
629 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
630 * Multisample Surface). Later hardware docs additionally refer to this
631 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
632 * color surfaces).
633 *
634 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
635 * Surface Behavior".
636 *
637 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
638 * Multisampled Surfaces".
639 */
640 ISL_MSAA_LAYOUT_INTERLEAVED,
641
642 /**
643 * @brief [IVB+] Array Multisample Format
644 *
645 * In this format, the surface's physical layout resembles that of a
646 * 2D array surface.
647 *
648 * Suppose the multisample surface's logical extent is (w, h) and its
649 * sample count is N. Then surface's physical extent is the same as
650 * a singlesample 2D surface whose logical extent is (w, h) and array
651 * length is N. Array slice `i` contains the pixel values for sample
652 * index `i`.
653 *
654 * The Ivybridge docs refer to surfaces in this format as UMS
655 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
656 * Surface). The Broadwell docs additionally refer to this format as
657 * MSFMT_MSS (MSS=Multisample Surface Storage).
658 *
659 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
660 * Multisample Surfaces".
661 *
662 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
663 * Multisample Surfaces".
664 */
665 ISL_MSAA_LAYOUT_ARRAY,
666 };
667
668
669 struct isl_device {
670 const struct gen_device_info *info;
671 bool use_separate_stencil;
672 bool has_bit6_swizzling;
673 };
674
675 struct isl_extent2d {
676 union { uint32_t w, width; };
677 union { uint32_t h, height; };
678 };
679
680 struct isl_extent3d {
681 union { uint32_t w, width; };
682 union { uint32_t h, height; };
683 union { uint32_t d, depth; };
684 };
685
686 struct isl_extent4d {
687 union { uint32_t w, width; };
688 union { uint32_t h, height; };
689 union { uint32_t d, depth; };
690 union { uint32_t a, array_len; };
691 };
692
693 struct isl_channel_layout {
694 enum isl_base_type type;
695 uint8_t bits; /**< Size in bits */
696 };
697
698 /**
699 * Each format has 3D block extent (width, height, depth). The block extent of
700 * compressed formats is that of the format's compression block. For example,
701 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
702 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
703 * is (w=1, h=1, d=1).
704 */
705 struct isl_format_layout {
706 enum isl_format format;
707 const char *name;
708
709 uint16_t bpb; /**< Bits per block */
710 uint8_t bw; /**< Block width, in pixels */
711 uint8_t bh; /**< Block height, in pixels */
712 uint8_t bd; /**< Block depth, in pixels */
713
714 struct {
715 struct isl_channel_layout r; /**< Red channel */
716 struct isl_channel_layout g; /**< Green channel */
717 struct isl_channel_layout b; /**< Blue channel */
718 struct isl_channel_layout a; /**< Alpha channel */
719 struct isl_channel_layout l; /**< Luminance channel */
720 struct isl_channel_layout i; /**< Intensity channel */
721 struct isl_channel_layout p; /**< Palette channel */
722 } channels;
723
724 enum isl_colorspace colorspace;
725 enum isl_txc txc;
726 };
727
728 struct isl_tile_info {
729 enum isl_tiling tiling;
730
731 /** The logical size of the tile in units of surface elements
732 *
733 * This field determines how a given surface is cut up into tiles. It is
734 * used to compute the size of a surface in tiles and can be used to
735 * determine the location of the tile containing any given surface element.
736 * The exact value of this field depends heavily on the bits-per-block of
737 * the format being used.
738 */
739 struct isl_extent2d logical_extent_el;
740
741 /** The physical size of the tile in bytes and rows of bytes
742 *
743 * This field determines how the tiles of a surface are physically layed
744 * out in memory. The logical and physical tile extent are frequently the
745 * same but this is not always the case. For instance, a W-tile (which is
746 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
747 * its physical size is 128B x 32rows, the same as a Y-tile.
748 *
749 * @see isl_surf::row_pitch
750 */
751 struct isl_extent2d phys_extent_B;
752 };
753
754 /**
755 * @brief Input to surface initialization
756 *
757 * @invariant width >= 1
758 * @invariant height >= 1
759 * @invariant depth >= 1
760 * @invariant levels >= 1
761 * @invariant samples >= 1
762 * @invariant array_len >= 1
763 *
764 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
765 * @invariant if 2D then depth == 1
766 * @invariant if 3D then array_len == 1 and samples == 1
767 */
768 struct isl_surf_init_info {
769 enum isl_surf_dim dim;
770 enum isl_format format;
771
772 uint32_t width;
773 uint32_t height;
774 uint32_t depth;
775 uint32_t levels;
776 uint32_t array_len;
777 uint32_t samples;
778
779 /** Lower bound for isl_surf::alignment, in bytes. */
780 uint32_t min_alignment;
781
782 /** Lower bound for isl_surf::pitch, in bytes. */
783 uint32_t min_pitch;
784
785 isl_surf_usage_flags_t usage;
786
787 /** Flags that alter how ISL selects isl_surf::tiling. */
788 isl_tiling_flags_t tiling_flags;
789 };
790
791 struct isl_surf {
792 enum isl_surf_dim dim;
793 enum isl_dim_layout dim_layout;
794 enum isl_msaa_layout msaa_layout;
795 enum isl_tiling tiling;
796 enum isl_format format;
797
798 /**
799 * Alignment of the upper-left sample of each subimage, in units of surface
800 * elements.
801 */
802 struct isl_extent3d image_alignment_el;
803
804 /**
805 * Logical extent of the surface's base level, in units of pixels. This is
806 * identical to the extent defined in isl_surf_init_info.
807 */
808 struct isl_extent4d logical_level0_px;
809
810 /**
811 * Physical extent of the surface's base level, in units of physical
812 * surface samples and aligned to the format's compression block.
813 *
814 * Consider isl_dim_layout as an operator that transforms a logical surface
815 * layout to a physical surface layout. Then
816 *
817 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
818 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
819 */
820 struct isl_extent4d phys_level0_sa;
821
822 uint32_t levels;
823 uint32_t samples;
824
825 /** Total size of the surface, in bytes. */
826 uint32_t size;
827
828 /** Required alignment for the surface's base address. */
829 uint32_t alignment;
830
831 /**
832 * The interpretation of this field depends on the value of
833 * isl_tile_info::physical_extent_B. In particular, the width of the
834 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
835 * and the distance in bytes between vertically adjacent tiles in the image
836 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
837 *
838 * For linear images where isl_tile_info::physical_extent_B.height == 1,
839 * this cleanly reduces to being the distance, in bytes, between vertically
840 * adjacent surface elements.
841 *
842 * @see isl_tile_info::phys_extent_B;
843 */
844 uint32_t row_pitch;
845
846 /**
847 * Pitch between physical array slices, in rows of surface elements.
848 */
849 uint32_t array_pitch_el_rows;
850
851 enum isl_array_pitch_span array_pitch_span;
852
853 /** Copy of isl_surf_init_info::usage. */
854 isl_surf_usage_flags_t usage;
855 };
856
857 struct isl_swizzle {
858 enum isl_channel_select r:4;
859 enum isl_channel_select g:4;
860 enum isl_channel_select b:4;
861 enum isl_channel_select a:4;
862 };
863
864 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
865 .r = ISL_CHANNEL_SELECT_##R, \
866 .g = ISL_CHANNEL_SELECT_##G, \
867 .b = ISL_CHANNEL_SELECT_##B, \
868 .a = ISL_CHANNEL_SELECT_##A, \
869 })
870
871 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
872
873 struct isl_view {
874 /**
875 * Indicates the usage of the particular view
876 *
877 * Normally, this is one bit. However, for a cube map texture, it
878 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
879 */
880 isl_surf_usage_flags_t usage;
881
882 /**
883 * The format to use in the view
884 *
885 * This may differ from the format of the actual isl_surf but must have
886 * the same block size.
887 */
888 enum isl_format format;
889
890 uint32_t base_level;
891 uint32_t levels;
892
893 /**
894 * Base array layer
895 *
896 * For cube maps, both base_array_layer and array_len should be
897 * specified in terms of 2-D layers and must be a multiple of 6.
898 *
899 * 3-D textures are effectively treated as 2-D arrays when used as a
900 * storage image or render target. If `usage` contains
901 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
902 * base_array_layer and array_len are applied. If the surface is only used
903 * for texturing, they are ignored.
904 */
905 uint32_t base_array_layer;
906 uint32_t array_len;
907
908 struct isl_swizzle swizzle;
909 };
910
911 union isl_color_value {
912 float f32[4];
913 uint32_t u32[4];
914 int32_t i32[4];
915 };
916
917 struct isl_surf_fill_state_info {
918 const struct isl_surf *surf;
919 const struct isl_view *view;
920
921 /**
922 * The address of the surface in GPU memory.
923 */
924 uint64_t address;
925
926 /**
927 * The Memory Object Control state for the filled surface state.
928 *
929 * The exact format of this value depends on hardware generation.
930 */
931 uint32_t mocs;
932
933 /**
934 * The auxilary surface or NULL if no auxilary surface is to be used.
935 */
936 const struct isl_surf *aux_surf;
937 enum isl_aux_usage aux_usage;
938 uint64_t aux_address;
939
940 /**
941 * The clear color for this surface
942 *
943 * Valid values depend on hardware generation.
944 */
945 union isl_color_value clear_color;
946
947 /* Intra-tile offset */
948 uint16_t x_offset_sa, y_offset_sa;
949 };
950
951 struct isl_buffer_fill_state_info {
952 /**
953 * The address of the surface in GPU memory.
954 */
955 uint64_t address;
956
957 /**
958 * The size of the buffer
959 */
960 uint64_t size;
961
962 /**
963 * The Memory Object Control state for the filled surface state.
964 *
965 * The exact format of this value depends on hardware generation.
966 */
967 uint32_t mocs;
968
969 /**
970 * The format to use in the surface state
971 *
972 * This may differ from the format of the actual isl_surf but have the
973 * same block size.
974 */
975 enum isl_format format;
976
977 uint32_t stride;
978 };
979
980 extern const struct isl_format_layout isl_format_layouts[];
981
982 void
983 isl_device_init(struct isl_device *dev,
984 const struct gen_device_info *info,
985 bool has_bit6_swizzling);
986
987 isl_sample_count_mask_t ATTRIBUTE_CONST
988 isl_device_get_sample_counts(struct isl_device *dev);
989
990 static inline const struct isl_format_layout * ATTRIBUTE_CONST
991 isl_format_get_layout(enum isl_format fmt)
992 {
993 return &isl_format_layouts[fmt];
994 }
995
996 static inline const char * ATTRIBUTE_CONST
997 isl_format_get_name(enum isl_format fmt)
998 {
999 return isl_format_layouts[fmt].name;
1000 }
1001
1002 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1003 enum isl_format format);
1004 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1005 enum isl_format format);
1006 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1007 enum isl_format format);
1008 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1009 enum isl_format format);
1010 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1011 enum isl_format format);
1012 bool isl_format_supports_lossless_compression(const struct gen_device_info *devinfo,
1013 enum isl_format format);
1014
1015 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1016 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1017 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1018 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1019 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1020 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1021
1022 static inline bool
1023 isl_format_has_normalized_channel(enum isl_format fmt)
1024 {
1025 return isl_format_has_unorm_channel(fmt) ||
1026 isl_format_has_snorm_channel(fmt);
1027 }
1028
1029 static inline bool
1030 isl_format_has_float_channel(enum isl_format fmt)
1031 {
1032 return isl_format_has_ufloat_channel(fmt) ||
1033 isl_format_has_sfloat_channel(fmt);
1034 }
1035
1036 static inline bool
1037 isl_format_has_int_channel(enum isl_format fmt)
1038 {
1039 return isl_format_has_uint_channel(fmt) ||
1040 isl_format_has_sint_channel(fmt);
1041 }
1042
1043 unsigned isl_format_get_num_channels(enum isl_format fmt);
1044
1045 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1046
1047 static inline bool
1048 isl_format_is_compressed(enum isl_format fmt)
1049 {
1050 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1051
1052 return fmtl->txc != ISL_TXC_NONE;
1053 }
1054
1055 static inline bool
1056 isl_format_has_bc_compression(enum isl_format fmt)
1057 {
1058 switch (isl_format_get_layout(fmt)->txc) {
1059 case ISL_TXC_DXT1:
1060 case ISL_TXC_DXT3:
1061 case ISL_TXC_DXT5:
1062 return true;
1063 case ISL_TXC_NONE:
1064 case ISL_TXC_FXT1:
1065 case ISL_TXC_RGTC1:
1066 case ISL_TXC_RGTC2:
1067 case ISL_TXC_BPTC:
1068 case ISL_TXC_ETC1:
1069 case ISL_TXC_ETC2:
1070 case ISL_TXC_ASTC:
1071 return false;
1072
1073 case ISL_TXC_HIZ:
1074 case ISL_TXC_MCS:
1075 case ISL_TXC_CCS:
1076 unreachable("Should not be called on an aux surface");
1077 }
1078
1079 unreachable("bad texture compression mode");
1080 return false;
1081 }
1082
1083 static inline bool
1084 isl_format_is_yuv(enum isl_format fmt)
1085 {
1086 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1087
1088 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1089 }
1090
1091 static inline bool
1092 isl_format_block_is_1x1x1(enum isl_format fmt)
1093 {
1094 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1095
1096 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1097 }
1098
1099 static inline bool
1100 isl_format_is_rgb(enum isl_format fmt)
1101 {
1102 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1103 isl_format_layouts[fmt].channels.g.bits > 0 &&
1104 isl_format_layouts[fmt].channels.b.bits > 0 &&
1105 isl_format_layouts[fmt].channels.a.bits == 0;
1106 }
1107
1108 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1109 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1110
1111 bool isl_is_storage_image_format(enum isl_format fmt);
1112
1113 enum isl_format
1114 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1115 enum isl_format fmt);
1116
1117 /* Returns true if this hardware supports typed load/store on a format with
1118 * the same size as the given format.
1119 */
1120 bool
1121 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1122 enum isl_format fmt);
1123
1124 static inline bool
1125 isl_tiling_is_any_y(enum isl_tiling tiling)
1126 {
1127 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1128 }
1129
1130 static inline bool
1131 isl_tiling_is_std_y(enum isl_tiling tiling)
1132 {
1133 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1134 }
1135
1136 bool
1137 isl_tiling_get_info(const struct isl_device *dev,
1138 enum isl_tiling tiling,
1139 uint32_t format_bpb,
1140 struct isl_tile_info *info);
1141 bool
1142 isl_surf_choose_tiling(const struct isl_device *dev,
1143 const struct isl_surf_init_info *restrict info,
1144 enum isl_tiling *tiling);
1145
1146 static inline bool
1147 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1148 {
1149 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1150 }
1151
1152 static inline bool
1153 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1154 {
1155 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1156 }
1157
1158 static inline bool
1159 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1160 {
1161 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1162 }
1163
1164 static inline bool
1165 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1166 {
1167 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1168 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1169 }
1170
1171 static inline bool
1172 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1173 {
1174 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1175 }
1176
1177 static inline bool
1178 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1179 {
1180 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1181 (info->format == ISL_FORMAT_R16_UNORM);
1182 }
1183
1184 static inline bool
1185 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1186 {
1187 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1188 (info->format == ISL_FORMAT_R32_FLOAT);
1189 }
1190
1191 static inline struct isl_extent2d
1192 isl_extent2d(uint32_t width, uint32_t height)
1193 {
1194 struct isl_extent2d e = { { 0 } };
1195
1196 e.width = width;
1197 e.height = height;
1198
1199 return e;
1200 }
1201
1202 static inline struct isl_extent3d
1203 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1204 {
1205 struct isl_extent3d e = { { 0 } };
1206
1207 e.width = width;
1208 e.height = height;
1209 e.depth = depth;
1210
1211 return e;
1212 }
1213
1214 static inline struct isl_extent4d
1215 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1216 uint32_t array_len)
1217 {
1218 struct isl_extent4d e = { { 0 } };
1219
1220 e.width = width;
1221 e.height = height;
1222 e.depth = depth;
1223 e.array_len = array_len;
1224
1225 return e;
1226 }
1227
1228 #define isl_surf_init(dev, surf, ...) \
1229 isl_surf_init_s((dev), (surf), \
1230 &(struct isl_surf_init_info) { __VA_ARGS__ });
1231
1232 bool
1233 isl_surf_init_s(const struct isl_device *dev,
1234 struct isl_surf *surf,
1235 const struct isl_surf_init_info *restrict info);
1236
1237 void
1238 isl_surf_get_tile_info(const struct isl_device *dev,
1239 const struct isl_surf *surf,
1240 struct isl_tile_info *tile_info);
1241
1242 void
1243 isl_surf_get_hiz_surf(const struct isl_device *dev,
1244 const struct isl_surf *surf,
1245 struct isl_surf *hiz_surf);
1246
1247 void
1248 isl_surf_get_mcs_surf(const struct isl_device *dev,
1249 const struct isl_surf *surf,
1250 struct isl_surf *mcs_surf);
1251
1252 bool
1253 isl_surf_get_ccs_surf(const struct isl_device *dev,
1254 const struct isl_surf *surf,
1255 struct isl_surf *ccs_surf);
1256
1257 #define isl_surf_fill_state(dev, state, ...) \
1258 isl_surf_fill_state_s((dev), (state), \
1259 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1260
1261 void
1262 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1263 const struct isl_surf_fill_state_info *restrict info);
1264
1265 #define isl_buffer_fill_state(dev, state, ...) \
1266 isl_buffer_fill_state_s((dev), (state), \
1267 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1268
1269 void
1270 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1271 const struct isl_buffer_fill_state_info *restrict info);
1272
1273 void
1274 isl_surf_fill_image_param(const struct isl_device *dev,
1275 struct brw_image_param *param,
1276 const struct isl_surf *surf,
1277 const struct isl_view *view);
1278
1279 void
1280 isl_buffer_fill_image_param(const struct isl_device *dev,
1281 struct brw_image_param *param,
1282 enum isl_format format,
1283 uint64_t size);
1284
1285 /**
1286 * Alignment of the upper-left sample of each subimage, in units of surface
1287 * elements.
1288 */
1289 static inline struct isl_extent3d
1290 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1291 {
1292 return surf->image_alignment_el;
1293 }
1294
1295 /**
1296 * Alignment of the upper-left sample of each subimage, in units of surface
1297 * samples.
1298 */
1299 static inline struct isl_extent3d
1300 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1301 {
1302 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1303
1304 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1305 fmtl->bh * surf->image_alignment_el.h,
1306 fmtl->bd * surf->image_alignment_el.d);
1307 }
1308
1309 /**
1310 * Pitch between vertically adjacent surface elements, in bytes.
1311 */
1312 static inline uint32_t
1313 isl_surf_get_row_pitch(const struct isl_surf *surf)
1314 {
1315 return surf->row_pitch;
1316 }
1317
1318 /**
1319 * Pitch between vertically adjacent surface elements, in units of surface elements.
1320 */
1321 static inline uint32_t
1322 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1323 {
1324 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1325
1326 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1327 return surf->row_pitch / (fmtl->bpb / 8);
1328 }
1329
1330 /**
1331 * Pitch between physical array slices, in rows of surface elements.
1332 */
1333 static inline uint32_t
1334 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1335 {
1336 return surf->array_pitch_el_rows;
1337 }
1338
1339 /**
1340 * Pitch between physical array slices, in units of surface elements.
1341 */
1342 static inline uint32_t
1343 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1344 {
1345 return isl_surf_get_array_pitch_el_rows(surf) *
1346 isl_surf_get_row_pitch_el(surf);
1347 }
1348
1349 /**
1350 * Pitch between physical array slices, in rows of surface samples.
1351 */
1352 static inline uint32_t
1353 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1354 {
1355 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1356 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1357 }
1358
1359 /**
1360 * Pitch between physical array slices, in bytes.
1361 */
1362 static inline uint32_t
1363 isl_surf_get_array_pitch(const struct isl_surf *surf)
1364 {
1365 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1366 }
1367
1368 /**
1369 * Calculate the offset, in units of surface samples, to a subimage in the
1370 * surface.
1371 *
1372 * @invariant level < surface levels
1373 * @invariant logical_array_layer < logical array length of surface
1374 * @invariant logical_z_offset_px < logical depth of surface at level
1375 */
1376 void
1377 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1378 uint32_t level,
1379 uint32_t logical_array_layer,
1380 uint32_t logical_z_offset_px,
1381 uint32_t *x_offset_sa,
1382 uint32_t *y_offset_sa);
1383
1384 /**
1385 * Calculate the offset, in units of surface elements, to a subimage in the
1386 * surface.
1387 *
1388 * @invariant level < surface levels
1389 * @invariant logical_array_layer < logical array length of surface
1390 * @invariant logical_z_offset_px < logical depth of surface at level
1391 */
1392 void
1393 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1394 uint32_t level,
1395 uint32_t logical_array_layer,
1396 uint32_t logical_z_offset_px,
1397 uint32_t *x_offset_el,
1398 uint32_t *y_offset_el);
1399
1400 /**
1401 * @brief Calculate the intratile offsets to a surface.
1402 *
1403 * In @a base_address_offset return the offset from the base of the surface to
1404 * the base address of the first tile of the subimage. In @a x_offset_B and
1405 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1406 * tile's base to the subimage's first surface element. The x and y offsets
1407 * are intratile offsets; that is, they do not exceed the boundary of the
1408 * surface's tiling format.
1409 */
1410 void
1411 isl_tiling_get_intratile_offset_el(const struct isl_device *dev,
1412 enum isl_tiling tiling,
1413 uint8_t bs,
1414 uint32_t row_pitch,
1415 uint32_t total_x_offset_el,
1416 uint32_t total_y_offset_el,
1417 uint32_t *base_address_offset,
1418 uint32_t *x_offset_el,
1419 uint32_t *y_offset_el);
1420
1421 static inline void
1422 isl_tiling_get_intratile_offset_sa(const struct isl_device *dev,
1423 enum isl_tiling tiling,
1424 enum isl_format format,
1425 uint32_t row_pitch,
1426 uint32_t total_x_offset_sa,
1427 uint32_t total_y_offset_sa,
1428 uint32_t *base_address_offset,
1429 uint32_t *x_offset_sa,
1430 uint32_t *y_offset_sa)
1431 {
1432 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1433
1434 assert(fmtl->bpb % 8 == 0);
1435
1436 /* For computing the intratile offsets, we actually want a strange unit
1437 * which is samples for multisampled surfaces but elements for compressed
1438 * surfaces.
1439 */
1440 assert(total_x_offset_sa % fmtl->bw == 0);
1441 assert(total_y_offset_sa % fmtl->bw == 0);
1442 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
1443 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
1444
1445 isl_tiling_get_intratile_offset_el(dev, tiling, fmtl->bpb / 8, row_pitch,
1446 total_x_offset, total_y_offset,
1447 base_address_offset,
1448 x_offset_sa, y_offset_sa);
1449 *x_offset_sa *= fmtl->bw;
1450 *y_offset_sa *= fmtl->bh;
1451 }
1452
1453 /**
1454 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1455 *
1456 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1457 * @pre surf->format must be a valid format for depth surfaces
1458 */
1459 uint32_t
1460 isl_surf_get_depth_format(const struct isl_device *dev,
1461 const struct isl_surf *surf);
1462
1463 #ifdef __cplusplus
1464 }
1465 #endif