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intel/isl/format: Add field locations informations to channel_layout
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51
52 struct gen_device_info;
53 struct brw_image_param;
54
55 #ifndef ISL_DEV_GEN
56 /**
57 * @brief Get the hardware generation of isl_device.
58 *
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 */
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #else
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
67 #endif
68
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
71 #endif
72
73 #ifndef ISL_DEV_IS_HASWELL
74 /**
75 * @brief Get the hardware generation of isl_device.
76 *
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 */
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
81 #endif
82
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
85 #endif
86
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 /**
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 */
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #else
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
97 #endif
98
99 /**
100 * Hardware enumeration SURFACE_FORMAT.
101 *
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
104 */
105 enum isl_format {
106 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
107 ISL_FORMAT_R32G32B32A32_SINT = 1,
108 ISL_FORMAT_R32G32B32A32_UINT = 2,
109 ISL_FORMAT_R32G32B32A32_UNORM = 3,
110 ISL_FORMAT_R32G32B32A32_SNORM = 4,
111 ISL_FORMAT_R64G64_FLOAT = 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
114 ISL_FORMAT_R32G32B32A32_USCALED = 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
116 ISL_FORMAT_R64G64_PASSTHRU = 33,
117 ISL_FORMAT_R32G32B32_FLOAT = 64,
118 ISL_FORMAT_R32G32B32_SINT = 65,
119 ISL_FORMAT_R32G32B32_UINT = 66,
120 ISL_FORMAT_R32G32B32_UNORM = 67,
121 ISL_FORMAT_R32G32B32_SNORM = 68,
122 ISL_FORMAT_R32G32B32_SSCALED = 69,
123 ISL_FORMAT_R32G32B32_USCALED = 70,
124 ISL_FORMAT_R32G32B32_SFIXED = 80,
125 ISL_FORMAT_R16G16B16A16_UNORM = 128,
126 ISL_FORMAT_R16G16B16A16_SNORM = 129,
127 ISL_FORMAT_R16G16B16A16_SINT = 130,
128 ISL_FORMAT_R16G16B16A16_UINT = 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
130 ISL_FORMAT_R32G32_FLOAT = 133,
131 ISL_FORMAT_R32G32_SINT = 134,
132 ISL_FORMAT_R32G32_UINT = 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
135 ISL_FORMAT_L32A32_FLOAT = 138,
136 ISL_FORMAT_R32G32_UNORM = 139,
137 ISL_FORMAT_R32G32_SNORM = 140,
138 ISL_FORMAT_R64_FLOAT = 141,
139 ISL_FORMAT_R16G16B16X16_UNORM = 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
141 ISL_FORMAT_A32X32_FLOAT = 144,
142 ISL_FORMAT_L32X32_FLOAT = 145,
143 ISL_FORMAT_I32X32_FLOAT = 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
145 ISL_FORMAT_R16G16B16A16_USCALED = 148,
146 ISL_FORMAT_R32G32_SSCALED = 149,
147 ISL_FORMAT_R32G32_USCALED = 150,
148 ISL_FORMAT_R32G32_FLOAT_LD = 151,
149 ISL_FORMAT_R32G32_SFIXED = 160,
150 ISL_FORMAT_R64_PASSTHRU = 161,
151 ISL_FORMAT_B8G8R8A8_UNORM = 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
153 ISL_FORMAT_R10G10B10A2_UNORM = 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
155 ISL_FORMAT_R10G10B10A2_UINT = 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
157 ISL_FORMAT_R8G8B8A8_UNORM = 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
159 ISL_FORMAT_R8G8B8A8_SNORM = 201,
160 ISL_FORMAT_R8G8B8A8_SINT = 202,
161 ISL_FORMAT_R8G8B8A8_UINT = 203,
162 ISL_FORMAT_R16G16_UNORM = 204,
163 ISL_FORMAT_R16G16_SNORM = 205,
164 ISL_FORMAT_R16G16_SINT = 206,
165 ISL_FORMAT_R16G16_UINT = 207,
166 ISL_FORMAT_R16G16_FLOAT = 208,
167 ISL_FORMAT_B10G10R10A2_UNORM = 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
169 ISL_FORMAT_R11G11B10_FLOAT = 211,
170 ISL_FORMAT_R32_SINT = 214,
171 ISL_FORMAT_R32_UINT = 215,
172 ISL_FORMAT_R32_FLOAT = 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
175 ISL_FORMAT_L32_UNORM = 221,
176 ISL_FORMAT_A32_UNORM = 222,
177 ISL_FORMAT_L16A16_UNORM = 223,
178 ISL_FORMAT_I24X8_UNORM = 224,
179 ISL_FORMAT_L24X8_UNORM = 225,
180 ISL_FORMAT_A24X8_UNORM = 226,
181 ISL_FORMAT_I32_FLOAT = 227,
182 ISL_FORMAT_L32_FLOAT = 228,
183 ISL_FORMAT_A32_FLOAT = 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
187 ISL_FORMAT_B8G8R8X8_UNORM = 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
189 ISL_FORMAT_R8G8B8X8_UNORM = 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
192 ISL_FORMAT_B10G10R10X2_UNORM = 238,
193 ISL_FORMAT_L16A16_FLOAT = 240,
194 ISL_FORMAT_R32_UNORM = 241,
195 ISL_FORMAT_R32_SNORM = 242,
196 ISL_FORMAT_R10G10B10X2_USCALED = 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
198 ISL_FORMAT_R8G8B8A8_USCALED = 245,
199 ISL_FORMAT_R16G16_SSCALED = 246,
200 ISL_FORMAT_R16G16_USCALED = 247,
201 ISL_FORMAT_R32_SSCALED = 248,
202 ISL_FORMAT_R32_USCALED = 249,
203 ISL_FORMAT_B5G6R5_UNORM = 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
205 ISL_FORMAT_B5G5R5A1_UNORM = 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
207 ISL_FORMAT_B4G4R4A4_UNORM = 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
209 ISL_FORMAT_R8G8_UNORM = 262,
210 ISL_FORMAT_R8G8_SNORM = 263,
211 ISL_FORMAT_R8G8_SINT = 264,
212 ISL_FORMAT_R8G8_UINT = 265,
213 ISL_FORMAT_R16_UNORM = 266,
214 ISL_FORMAT_R16_SNORM = 267,
215 ISL_FORMAT_R16_SINT = 268,
216 ISL_FORMAT_R16_UINT = 269,
217 ISL_FORMAT_R16_FLOAT = 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
220 ISL_FORMAT_I16_UNORM = 273,
221 ISL_FORMAT_L16_UNORM = 274,
222 ISL_FORMAT_A16_UNORM = 275,
223 ISL_FORMAT_L8A8_UNORM = 276,
224 ISL_FORMAT_I16_FLOAT = 277,
225 ISL_FORMAT_L16_FLOAT = 278,
226 ISL_FORMAT_A16_FLOAT = 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
229 ISL_FORMAT_B5G5R5X1_UNORM = 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
231 ISL_FORMAT_R8G8_SSCALED = 284,
232 ISL_FORMAT_R8G8_USCALED = 285,
233 ISL_FORMAT_R16_SSCALED = 286,
234 ISL_FORMAT_R16_USCALED = 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
237 ISL_FORMAT_A1B5G5R5_UNORM = 292,
238 ISL_FORMAT_A4B4G4R4_UNORM = 293,
239 ISL_FORMAT_L8A8_UINT = 294,
240 ISL_FORMAT_L8A8_SINT = 295,
241 ISL_FORMAT_R8_UNORM = 320,
242 ISL_FORMAT_R8_SNORM = 321,
243 ISL_FORMAT_R8_SINT = 322,
244 ISL_FORMAT_R8_UINT = 323,
245 ISL_FORMAT_A8_UNORM = 324,
246 ISL_FORMAT_I8_UNORM = 325,
247 ISL_FORMAT_L8_UNORM = 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
250 ISL_FORMAT_R8_SSCALED = 329,
251 ISL_FORMAT_R8_USCALED = 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
253 ISL_FORMAT_L8_UNORM_SRGB = 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
257 ISL_FORMAT_Y8_UNORM = 336,
258 ISL_FORMAT_L8_UINT = 338,
259 ISL_FORMAT_L8_SINT = 339,
260 ISL_FORMAT_I8_UINT = 340,
261 ISL_FORMAT_I8_SINT = 341,
262 ISL_FORMAT_DXT1_RGB_SRGB = 384,
263 ISL_FORMAT_R1_UNORM = 385,
264 ISL_FORMAT_YCRCB_NORMAL = 386,
265 ISL_FORMAT_YCRCB_SWAPUVY = 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
268 ISL_FORMAT_BC1_UNORM = 390,
269 ISL_FORMAT_BC2_UNORM = 391,
270 ISL_FORMAT_BC3_UNORM = 392,
271 ISL_FORMAT_BC4_UNORM = 393,
272 ISL_FORMAT_BC5_UNORM = 394,
273 ISL_FORMAT_BC1_UNORM_SRGB = 395,
274 ISL_FORMAT_BC2_UNORM_SRGB = 396,
275 ISL_FORMAT_BC3_UNORM_SRGB = 397,
276 ISL_FORMAT_MONO8 = 398,
277 ISL_FORMAT_YCRCB_SWAPUV = 399,
278 ISL_FORMAT_YCRCB_SWAPY = 400,
279 ISL_FORMAT_DXT1_RGB = 401,
280 ISL_FORMAT_FXT1 = 402,
281 ISL_FORMAT_R8G8B8_UNORM = 403,
282 ISL_FORMAT_R8G8B8_SNORM = 404,
283 ISL_FORMAT_R8G8B8_SSCALED = 405,
284 ISL_FORMAT_R8G8B8_USCALED = 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
286 ISL_FORMAT_R64G64B64_FLOAT = 408,
287 ISL_FORMAT_BC4_SNORM = 409,
288 ISL_FORMAT_BC5_SNORM = 410,
289 ISL_FORMAT_R16G16B16_FLOAT = 411,
290 ISL_FORMAT_R16G16B16_UNORM = 412,
291 ISL_FORMAT_R16G16B16_SNORM = 413,
292 ISL_FORMAT_R16G16B16_SSCALED = 414,
293 ISL_FORMAT_R16G16B16_USCALED = 415,
294 ISL_FORMAT_BC6H_SF16 = 417,
295 ISL_FORMAT_BC7_UNORM = 418,
296 ISL_FORMAT_BC7_UNORM_SRGB = 419,
297 ISL_FORMAT_BC6H_UF16 = 420,
298 ISL_FORMAT_PLANAR_420_8 = 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
300 ISL_FORMAT_ETC1_RGB8 = 425,
301 ISL_FORMAT_ETC2_RGB8 = 426,
302 ISL_FORMAT_EAC_R11 = 427,
303 ISL_FORMAT_EAC_RG11 = 428,
304 ISL_FORMAT_EAC_SIGNED_R11 = 429,
305 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
306 ISL_FORMAT_ETC2_SRGB8 = 431,
307 ISL_FORMAT_R16G16B16_UINT = 432,
308 ISL_FORMAT_R16G16B16_SINT = 433,
309 ISL_FORMAT_R32_SFIXED = 434,
310 ISL_FORMAT_R10G10B10A2_SNORM = 435,
311 ISL_FORMAT_R10G10B10A2_USCALED = 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
313 ISL_FORMAT_R10G10B10A2_SINT = 438,
314 ISL_FORMAT_B10G10R10A2_SNORM = 439,
315 ISL_FORMAT_B10G10R10A2_USCALED = 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
317 ISL_FORMAT_B10G10R10A2_UINT = 442,
318 ISL_FORMAT_B10G10R10A2_SINT = 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
321 ISL_FORMAT_ETC2_RGB8_PTA = 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
325 ISL_FORMAT_R8G8B8_UINT = 456,
326 ISL_FORMAT_R8G8B8_SINT = 457,
327 ISL_FORMAT_RAW = 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
370
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
374 */
375
376 /* Formats for auxiliary surfaces */
377 ISL_FORMAT_HIZ,
378 ISL_FORMAT_MCS_2X,
379 ISL_FORMAT_MCS_4X,
380 ISL_FORMAT_MCS_8X,
381 ISL_FORMAT_MCS_16X,
382 ISL_FORMAT_GEN7_CCS_32BPP_X,
383 ISL_FORMAT_GEN7_CCS_64BPP_X,
384 ISL_FORMAT_GEN7_CCS_128BPP_X,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y,
388 ISL_FORMAT_GEN9_CCS_32BPP,
389 ISL_FORMAT_GEN9_CCS_64BPP,
390 ISL_FORMAT_GEN9_CCS_128BPP,
391
392 /* Hardware doesn't understand this out-of-band value */
393 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
394 };
395
396 /**
397 * Numerical base type for channels of isl_format.
398 */
399 enum isl_base_type {
400 ISL_VOID,
401 ISL_RAW,
402 ISL_UNORM,
403 ISL_SNORM,
404 ISL_UFLOAT,
405 ISL_SFLOAT,
406 ISL_UFIXED,
407 ISL_SFIXED,
408 ISL_UINT,
409 ISL_SINT,
410 ISL_USCALED,
411 ISL_SSCALED,
412 };
413
414 /**
415 * Colorspace of isl_format.
416 */
417 enum isl_colorspace {
418 ISL_COLORSPACE_NONE = 0,
419 ISL_COLORSPACE_LINEAR,
420 ISL_COLORSPACE_SRGB,
421 ISL_COLORSPACE_YUV,
422 };
423
424 /**
425 * Texture compression mode of isl_format.
426 */
427 enum isl_txc {
428 ISL_TXC_NONE = 0,
429 ISL_TXC_DXT1,
430 ISL_TXC_DXT3,
431 ISL_TXC_DXT5,
432 ISL_TXC_FXT1,
433 ISL_TXC_RGTC1,
434 ISL_TXC_RGTC2,
435 ISL_TXC_BPTC,
436 ISL_TXC_ETC1,
437 ISL_TXC_ETC2,
438 ISL_TXC_ASTC,
439
440 /* Used for auxiliary surface formats */
441 ISL_TXC_HIZ,
442 ISL_TXC_MCS,
443 ISL_TXC_CCS,
444 };
445
446 /**
447 * @brief Hardware tile mode
448 *
449 * WARNING: These values differ from the hardware enum values, which are
450 * unstable across hardware generations.
451 *
452 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
453 * clearly distinguish it from Yf and Ys.
454 */
455 enum isl_tiling {
456 ISL_TILING_LINEAR = 0,
457 ISL_TILING_W,
458 ISL_TILING_X,
459 ISL_TILING_Y0, /**< Legacy Y tiling */
460 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
461 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
462 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
463 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
464 };
465
466 /**
467 * @defgroup Tiling Flags
468 * @{
469 */
470 typedef uint32_t isl_tiling_flags_t;
471 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
472 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
473 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
474 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
475 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
476 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
477 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
478 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
479 #define ISL_TILING_ANY_MASK (~0u)
480 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
481
482 /** Any Y tiling, including legacy Y tiling. */
483 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
484 ISL_TILING_Yf_BIT | \
485 ISL_TILING_Ys_BIT)
486
487 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
488 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
489 ISL_TILING_Ys_BIT)
490 /** @} */
491
492 /**
493 * @brief Logical dimension of surface.
494 *
495 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
496 * as 2D array surfaces.
497 */
498 enum isl_surf_dim {
499 ISL_SURF_DIM_1D,
500 ISL_SURF_DIM_2D,
501 ISL_SURF_DIM_3D,
502 };
503
504 /**
505 * @brief Physical layout of the surface's dimensions.
506 */
507 enum isl_dim_layout {
508 /**
509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
510 * 6.17.3: 2D Surfaces.
511 *
512 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
513 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
514 *
515 * One-dimensional surfaces are identical to 2D surfaces with height of
516 * one.
517 *
518 * @invariant isl_surf::phys_level0_sa::depth == 1
519 */
520 ISL_DIM_LAYOUT_GEN4_2D,
521
522 /**
523 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
524 * 6.17.5: 3D Surfaces.
525 *
526 * @invariant isl_surf::phys_level0_sa::array_len == 1
527 */
528 ISL_DIM_LAYOUT_GEN4_3D,
529
530 /**
531 * Special layout used for HiZ and stencil on Sandy Bridge to work around
532 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
533 * work the same as on gen7+ except that they don't technically support
534 * mipmapping. That does not, however, stop us from doing it. As far as
535 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
536 * single miplevel 2D (possibly array) image. The dimensions of that image
537 * are NOT minified.
538 *
539 * In order to implement HiZ and stencil on Sandy Bridge, we create one
540 * full-sized 2D (possibly array) image for every LOD with every image
541 * aligned to a page boundary. When the surface is used with the stencil
542 * or HiZ hardware, we manually offset to the image for the given LOD.
543 *
544 * As a memory saving measure, we pretend that the width of each miplevel
545 * is minified and we place LOD1 and above below LOD0 but horizontally
546 * adjacent to each other. When considered as full-sized images, LOD1 and
547 * above technically overlap. However, since we only write to part of that
548 * image, the hardware will never notice the overlap.
549 *
550 * This layout looks something like this:
551 *
552 * +---------+
553 * | |
554 * | |
555 * +---------+
556 * | |
557 * | |
558 * +---------+
559 *
560 * +----+ +-+ .
561 * | | +-+
562 * +----+
563 *
564 * +----+ +-+ .
565 * | | +-+
566 * +----+
567 */
568 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
569
570 /**
571 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
572 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
573 */
574 ISL_DIM_LAYOUT_GEN9_1D,
575 };
576
577 enum isl_aux_usage {
578 /** No Auxiliary surface is used */
579 ISL_AUX_USAGE_NONE,
580
581 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
582 ISL_AUX_USAGE_HIZ,
583
584 /** The auxiliary surface is an MCS
585 *
586 * @invariant isl_surf::samples > 1
587 */
588 ISL_AUX_USAGE_MCS,
589
590 /** The auxiliary surface is a fast-clear-only compression surface
591 *
592 * @invariant isl_surf::samples == 1
593 */
594 ISL_AUX_USAGE_CCS_D,
595
596 /** The auxiliary surface provides full lossless color compression
597 *
598 * @invariant isl_surf::samples == 1
599 */
600 ISL_AUX_USAGE_CCS_E,
601 };
602
603 /**
604 * Enum for keeping track of the state an auxiliary compressed surface.
605 *
606 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
607 * given slice (lod + array layer) can be in one of the six states described
608 * by this enum. Draw and resolve operations may cause the slice to change
609 * from one state to another. The six valid states are:
610 *
611 * 1) Clear: In this state, each block in the auxiliary surface contains a
612 * magic value that indicates that the block is in the clear state. If
613 * a block is in the clear state, it's values in the primary surface are
614 * ignored and the color of the samples in the block is taken either the
615 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
616 * depth. Since neither the primary surface nor the auxiliary surface
617 * contains the clear value, the surface can be cleared to a different
618 * color by simply changing the clear color without modifying either
619 * surface.
620 *
621 * 2) Partial Clear: In this state, each block in the auxiliary surface
622 * contains either the magic clear or pass-through value. See Clear and
623 * Pass-through for more details.
624 *
625 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
626 * nor the primary surface has a complete representation of the data.
627 * Instead, both surfaces must be used together or else rendering
628 * corruption may occur. Depending on the auxiliary compression format
629 * and the data, any given block in the primary surface may contain all,
630 * some, or none of the data required to reconstruct the actual sample
631 * values. Blocks may also be in the clear state (see Clear) and have
632 * their value taken from outside the surface.
633 *
634 * 4) Compressed w/o Clear: This state is identical to the state above
635 * except that no blocks are in the clear state. In this state, all of
636 * the data required to reconstruct the final sample values is contained
637 * in the auxiliary and primary surface and the clear value is not
638 * considered.
639 *
640 * 5) Resolved: In this state, the primary surface contains 100% of the
641 * data. The auxiliary surface is also valid so the surface can be
642 * validly used with or without aux enabled. The auxiliary surface may,
643 * however, contain non-trivial data and any update to the primary
644 * surface with aux disabled will cause the two to get out of sync.
645 *
646 * 6) Pass-through: In this state, the primary surface contains 100% of the
647 * data and every block in the auxiliary surface contains a magic value
648 * which indicates that the auxiliary surface should be ignored and the
649 * only the primary surface should be considered. Updating the primary
650 * surface without aux works fine and can be done repeatedly in this
651 * mode. Writing to a surface in pass-through mode with aux enabled may
652 * cause the auxiliary buffer to contain non-trivial data and no longer
653 * be in the pass-through state.
654 *
655 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
656 * data and the auxiliary surface is completely bogus. Any attempt to
657 * use the auxiliary surface is liable to result in rendering
658 * corruption. The only thing that one can do to re-enable aux once
659 * this state is reached is to use an ambiguate pass to transition into
660 * the pass-through state.
661 *
662 * Drawing with or without aux enabled may implicitly cause the surface to
663 * transition between these states. There are also four types of auxiliary
664 * compression operations which cause an explicit transition which are
665 * described by the isl_aux_op enum below.
666 *
667 * Not all operations are valid or useful in all states. The diagram below
668 * contains a complete description of the states and all valid and useful
669 * transitions except clear.
670 *
671 * Draw w/ Aux
672 * +----------+
673 * | |
674 * | +-------------+ Draw w/ Aux +-------------+
675 * +------>| Compressed |<-------------------| Clear |
676 * | w/ Clear |----->----+ | |
677 * +-------------+ | +-------------+
678 * | /|\ | | |
679 * | | | | |
680 * | | +------<-----+ | Draw w/
681 * | | | | Clear Only
682 * | | Full | | +----------+
683 * Partial | | Resolve | \|/ | |
684 * Resolve | | | +-------------+ |
685 * | | | | Partial |<------+
686 * | | | | Clear |<----------+
687 * | | | +-------------+ |
688 * | | | | |
689 * | | +------>---------+ Full |
690 * | | | Resolve |
691 * Draw w/ aux | | Partial Fast Clear | |
692 * +----------+ | +--------------------------+ | |
693 * | | \|/ | \|/ |
694 * | +-------------+ Full Resolve +-------------+ |
695 * +------>| Compressed |------------------->| Resolved | |
696 * | w/o Clear |<-------------------| | |
697 * +-------------+ Draw w/ Aux +-------------+ |
698 * /|\ | | |
699 * | Draw | | Draw |
700 * | w/ Aux | | w/o Aux |
701 * | Ambiguate | | |
702 * | +--------------------------+ | |
703 * Draw w/o Aux | | | Draw w/o Aux |
704 * +----------+ | | | +----------+ |
705 * | | | \|/ \|/ | | |
706 * | +-------------+ Ambiguate +-------------+ | |
707 * +------>| Pass- |<-------------------| Aux |<------+ |
708 * +------>| through | | Invalid | |
709 * | +-------------+ +-------------+ |
710 * | | | |
711 * +----------+ +-----------------------------------------------------+
712 * Draw w/ Partial Fast Clear
713 * Clear Only
714 *
715 *
716 * While the above general theory applies to all forms of auxiliary
717 * compression on Intel hardware, not all states and operations are available
718 * on all compression types. However, each of the auxiliary states and
719 * operations can be fairly easily mapped onto the above diagram:
720 *
721 * HiZ: Hierarchical depth compression is capable of being in any of the
722 * states above. Hardware provides three HiZ operations: "Depth
723 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
724 * Clear", "Full Resolve", and "Ambiguate" respectively. The
725 * hardware provides no HiZ partial resolve operation so the only way
726 * to get into the "Compressed w/o Clear" state is to render with HiZ
727 * when the surface is in the resolved or pass-through states.
728 *
729 * MCS: Multisample compression is technically capable of being in any of
730 * the states above except that most of them aren't useful. Both the
731 * render engine and the sampler support MCS compression and, apart
732 * from clear color, MCS is format-unaware so we leave the surface
733 * compressed 100% of the time. The hardware provides no MCS
734 * operations.
735 *
736 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
737 * the simplest forms of compression since they don't do anything
738 * beyond clear color tracking. They really only support three of
739 * the six states: Clear, Partial Clear, and Pass-through. The
740 * only CCS_D operation is "Resolve" which maps to a full resolve
741 * followed by an ambiguate.
742 *
743 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
744 * is capable of being in almost all of the above states. THe only
745 * exception is that it does not have separate resolved and pass-
746 * through states. Instead, the CCS_E full resolve operation does
747 * both a resolve and an ambiguate so it goes directly into the
748 * pass-through state. CCS_E also provides fast clear and partial
749 * resolve operations which work as described above.
750 *
751 * While it is technically possible to perform a CCS_E ambiguate, it
752 * is not provided by Sky Lake hardware so we choose to avoid the aux
753 * invalid state. If the aux invalid state were determined to be
754 * useful, a CCS ambiguate could be done by carefully rendering to
755 * the CCS and filling it with zeros.
756 */
757 enum isl_aux_state {
758 ISL_AUX_STATE_CLEAR = 0,
759 ISL_AUX_STATE_PARTIAL_CLEAR,
760 ISL_AUX_STATE_COMPRESSED_CLEAR,
761 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
762 ISL_AUX_STATE_RESOLVED,
763 ISL_AUX_STATE_PASS_THROUGH,
764 ISL_AUX_STATE_AUX_INVALID,
765 };
766
767 /**
768 * Enum which describes explicit aux transition operations.
769 */
770 enum isl_aux_op {
771 ISL_AUX_OP_NONE,
772
773 /** Fast Clear
774 *
775 * This operation writes the magic "clear" value to the auxiliary surface.
776 * This operation will safely transition any slice of a surface from any
777 * state to the clear state so long as the entire slice is fast cleared at
778 * once. A fast clear that only covers part of a slice of a surface is
779 * called a partial fast clear.
780 */
781 ISL_AUX_OP_FAST_CLEAR,
782
783 /** Full Resolve
784 *
785 * This operation combines the auxiliary surface data with the primary
786 * surface data and writes the result to the primary. For HiZ, the docs
787 * call this a depth resolve. For CCS, the hardware full resolve operation
788 * does both a full resolve and an ambiguate so it actually takes you all
789 * the way to the pass-through state.
790 */
791 ISL_AUX_OP_FULL_RESOLVE,
792
793 /** Partial Resolve
794 *
795 * This operation considers blocks which are in the "clear" state and
796 * writes the clear value directly into the primary or auxiliary surface.
797 * Once this operation completes, the surface is still compressed but no
798 * longer references the clear color. This operation is only available
799 * for CCS_E.
800 */
801 ISL_AUX_OP_PARTIAL_RESOLVE,
802
803 /** Ambiguate
804 *
805 * This operation throws away the current auxiliary data and replaces it
806 * with the magic pass-through value. If an ambiguate operation is
807 * performed when the primary surface does not contain 100% of the data,
808 * data will be lost. This operation is only implemented in hardware for
809 * depth where it is called a HiZ resolve.
810 */
811 ISL_AUX_OP_AMBIGUATE,
812 };
813
814 /* TODO(chadv): Explain */
815 enum isl_array_pitch_span {
816 ISL_ARRAY_PITCH_SPAN_FULL,
817 ISL_ARRAY_PITCH_SPAN_COMPACT,
818 };
819
820 /**
821 * @defgroup Surface Usage
822 * @{
823 */
824 typedef uint64_t isl_surf_usage_flags_t;
825 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
826 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
827 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
828 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
829 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
830 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
831 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
832 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
833 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
834 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
835 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
836 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
837 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
838 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
839 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
840 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
841 /** @} */
842
843 /**
844 * @defgroup Channel Mask
845 *
846 * These #define values are chosen to match the values of
847 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
848 *
849 * @{
850 */
851 typedef uint8_t isl_channel_mask_t;
852 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
853 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
854 #define ISL_CHANNEL_RED_BIT (1 << 2)
855 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
856 /** @} */
857
858 /**
859 * @brief A channel select (also known as texture swizzle) value
860 */
861 enum isl_channel_select {
862 ISL_CHANNEL_SELECT_ZERO = 0,
863 ISL_CHANNEL_SELECT_ONE = 1,
864 ISL_CHANNEL_SELECT_RED = 4,
865 ISL_CHANNEL_SELECT_GREEN = 5,
866 ISL_CHANNEL_SELECT_BLUE = 6,
867 ISL_CHANNEL_SELECT_ALPHA = 7,
868 };
869
870 /**
871 * Identical to VkSampleCountFlagBits.
872 */
873 enum isl_sample_count {
874 ISL_SAMPLE_COUNT_1_BIT = 1u,
875 ISL_SAMPLE_COUNT_2_BIT = 2u,
876 ISL_SAMPLE_COUNT_4_BIT = 4u,
877 ISL_SAMPLE_COUNT_8_BIT = 8u,
878 ISL_SAMPLE_COUNT_16_BIT = 16u,
879 };
880 typedef uint32_t isl_sample_count_mask_t;
881
882 /**
883 * @brief Multisample Format
884 */
885 enum isl_msaa_layout {
886 /**
887 * @brief Suface is single-sampled.
888 */
889 ISL_MSAA_LAYOUT_NONE,
890
891 /**
892 * @brief [SNB+] Interleaved Multisample Format
893 *
894 * In this format, multiple samples are interleaved into each cacheline.
895 * In other words, the sample index is swizzled into the low 6 bits of the
896 * surface's virtual address space.
897 *
898 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
899 * and its pixel format is 32bpp. Then the first cacheline is arranged
900 * thus:
901 *
902 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
903 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
904 *
905 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
906 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
907 *
908 * The hardware docs refer to this format with multiple terms. In
909 * Sandybridge, this is the only multisample format; so no term is used.
910 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
911 * Multisample Surface). Later hardware docs additionally refer to this
912 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
913 * color surfaces).
914 *
915 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
916 * Surface Behavior".
917 *
918 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
919 * Multisampled Surfaces".
920 */
921 ISL_MSAA_LAYOUT_INTERLEAVED,
922
923 /**
924 * @brief [IVB+] Array Multisample Format
925 *
926 * In this format, the surface's physical layout resembles that of a
927 * 2D array surface.
928 *
929 * Suppose the multisample surface's logical extent is (w, h) and its
930 * sample count is N. Then surface's physical extent is the same as
931 * a singlesample 2D surface whose logical extent is (w, h) and array
932 * length is N. Array slice `i` contains the pixel values for sample
933 * index `i`.
934 *
935 * The Ivybridge docs refer to surfaces in this format as UMS
936 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
937 * Surface). The Broadwell docs additionally refer to this format as
938 * MSFMT_MSS (MSS=Multisample Surface Storage).
939 *
940 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
941 * Multisample Surfaces".
942 *
943 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
944 * Multisample Surfaces".
945 */
946 ISL_MSAA_LAYOUT_ARRAY,
947 };
948
949
950 struct isl_device {
951 const struct gen_device_info *info;
952 bool use_separate_stencil;
953 bool has_bit6_swizzling;
954
955 /**
956 * Describes the layout of a RENDER_SURFACE_STATE structure for the
957 * current gen.
958 */
959 struct {
960 uint8_t size;
961 uint8_t align;
962 uint8_t addr_offset;
963 uint8_t aux_addr_offset;
964
965 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
966
967 /* size of the state buffer used to store the clear color + extra
968 * additional space used by the hardware */
969 uint8_t clear_color_state_size;
970 uint8_t clear_color_state_offset;
971 /* size of the clear color itself - used to copy it to/from a BO */
972 uint8_t clear_value_size;
973 uint8_t clear_value_offset;
974 } ss;
975
976 /**
977 * Describes the layout of the depth/stencil/hiz commands as emitted by
978 * isl_emit_depth_stencil_hiz.
979 */
980 struct {
981 uint8_t size;
982 uint8_t depth_offset;
983 uint8_t stencil_offset;
984 uint8_t hiz_offset;
985 } ds;
986 };
987
988 struct isl_extent2d {
989 union { uint32_t w, width; };
990 union { uint32_t h, height; };
991 };
992
993 struct isl_extent3d {
994 union { uint32_t w, width; };
995 union { uint32_t h, height; };
996 union { uint32_t d, depth; };
997 };
998
999 struct isl_extent4d {
1000 union { uint32_t w, width; };
1001 union { uint32_t h, height; };
1002 union { uint32_t d, depth; };
1003 union { uint32_t a, array_len; };
1004 };
1005
1006 struct isl_channel_layout {
1007 enum isl_base_type type;
1008 uint8_t start_bit; /**< Bit at which this channel starts */
1009 uint8_t bits; /**< Size in bits */
1010 };
1011
1012 /**
1013 * Each format has 3D block extent (width, height, depth). The block extent of
1014 * compressed formats is that of the format's compression block. For example,
1015 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1016 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1017 * is (w=1, h=1, d=1).
1018 */
1019 struct isl_format_layout {
1020 enum isl_format format;
1021 const char *name;
1022
1023 uint16_t bpb; /**< Bits per block */
1024 uint8_t bw; /**< Block width, in pixels */
1025 uint8_t bh; /**< Block height, in pixels */
1026 uint8_t bd; /**< Block depth, in pixels */
1027
1028 union {
1029 struct {
1030 struct isl_channel_layout r; /**< Red channel */
1031 struct isl_channel_layout g; /**< Green channel */
1032 struct isl_channel_layout b; /**< Blue channel */
1033 struct isl_channel_layout a; /**< Alpha channel */
1034 struct isl_channel_layout l; /**< Luminance channel */
1035 struct isl_channel_layout i; /**< Intensity channel */
1036 struct isl_channel_layout p; /**< Palette channel */
1037 } channels;
1038 struct isl_channel_layout channels_array[7];
1039 };
1040
1041 enum isl_colorspace colorspace;
1042 enum isl_txc txc;
1043 };
1044
1045 struct isl_tile_info {
1046 enum isl_tiling tiling;
1047
1048 /* The size (in bits per block) of a single surface element
1049 *
1050 * For surfaces with power-of-two formats, this is the same as
1051 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1052 * The logical_extent_el field is in terms of elements of this size.
1053 *
1054 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1055 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1056 * of the tiling formats can actually hold an integer number of 96-bit
1057 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1058 * 32-bit element size. It is the responsibility of the caller to
1059 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1060 * the width of a surface in tiles, you would do:
1061 *
1062 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1063 * tile_info.logical_extent_el.width);
1064 */
1065 uint32_t format_bpb;
1066
1067 /** The logical size of the tile in units of format_bpb size elements
1068 *
1069 * This field determines how a given surface is cut up into tiles. It is
1070 * used to compute the size of a surface in tiles and can be used to
1071 * determine the location of the tile containing any given surface element.
1072 * The exact value of this field depends heavily on the bits-per-block of
1073 * the format being used.
1074 */
1075 struct isl_extent2d logical_extent_el;
1076
1077 /** The physical size of the tile in bytes and rows of bytes
1078 *
1079 * This field determines how the tiles of a surface are physically layed
1080 * out in memory. The logical and physical tile extent are frequently the
1081 * same but this is not always the case. For instance, a W-tile (which is
1082 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1083 * its physical size is 128B x 32rows, the same as a Y-tile.
1084 *
1085 * @see isl_surf::row_pitch
1086 */
1087 struct isl_extent2d phys_extent_B;
1088 };
1089
1090 /**
1091 * Metadata about a DRM format modifier.
1092 */
1093 struct isl_drm_modifier_info {
1094 uint64_t modifier;
1095
1096 /** Text name of the modifier */
1097 const char *name;
1098
1099 /** ISL tiling implied by this modifier */
1100 enum isl_tiling tiling;
1101
1102 /** ISL aux usage implied by this modifier */
1103 enum isl_aux_usage aux_usage;
1104
1105 /** Whether or not this modifier supports clear color */
1106 bool supports_clear_color;
1107 };
1108
1109 /**
1110 * @brief Input to surface initialization
1111 *
1112 * @invariant width >= 1
1113 * @invariant height >= 1
1114 * @invariant depth >= 1
1115 * @invariant levels >= 1
1116 * @invariant samples >= 1
1117 * @invariant array_len >= 1
1118 *
1119 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1120 * @invariant if 2D then depth == 1
1121 * @invariant if 3D then array_len == 1 and samples == 1
1122 */
1123 struct isl_surf_init_info {
1124 enum isl_surf_dim dim;
1125 enum isl_format format;
1126
1127 uint32_t width;
1128 uint32_t height;
1129 uint32_t depth;
1130 uint32_t levels;
1131 uint32_t array_len;
1132 uint32_t samples;
1133
1134 /** Lower bound for isl_surf::alignment, in bytes. */
1135 uint32_t min_alignment;
1136
1137 /**
1138 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1139 * will fail if this is misaligned or out of bounds.
1140 */
1141 uint32_t row_pitch;
1142
1143 isl_surf_usage_flags_t usage;
1144
1145 /** Flags that alter how ISL selects isl_surf::tiling. */
1146 isl_tiling_flags_t tiling_flags;
1147 };
1148
1149 struct isl_surf {
1150 enum isl_surf_dim dim;
1151 enum isl_dim_layout dim_layout;
1152 enum isl_msaa_layout msaa_layout;
1153 enum isl_tiling tiling;
1154 enum isl_format format;
1155
1156 /**
1157 * Alignment of the upper-left sample of each subimage, in units of surface
1158 * elements.
1159 */
1160 struct isl_extent3d image_alignment_el;
1161
1162 /**
1163 * Logical extent of the surface's base level, in units of pixels. This is
1164 * identical to the extent defined in isl_surf_init_info.
1165 */
1166 struct isl_extent4d logical_level0_px;
1167
1168 /**
1169 * Physical extent of the surface's base level, in units of physical
1170 * surface samples and aligned to the format's compression block.
1171 *
1172 * Consider isl_dim_layout as an operator that transforms a logical surface
1173 * layout to a physical surface layout. Then
1174 *
1175 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1176 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1177 */
1178 struct isl_extent4d phys_level0_sa;
1179
1180 uint32_t levels;
1181 uint32_t samples;
1182
1183 /** Total size of the surface, in bytes. */
1184 uint64_t size;
1185
1186 /** Required alignment for the surface's base address. */
1187 uint32_t alignment;
1188
1189 /**
1190 * The interpretation of this field depends on the value of
1191 * isl_tile_info::physical_extent_B. In particular, the width of the
1192 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
1193 * and the distance in bytes between vertically adjacent tiles in the image
1194 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
1195 *
1196 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1197 * this cleanly reduces to being the distance, in bytes, between vertically
1198 * adjacent surface elements.
1199 *
1200 * @see isl_tile_info::phys_extent_B;
1201 */
1202 uint32_t row_pitch;
1203
1204 /**
1205 * Pitch between physical array slices, in rows of surface elements.
1206 */
1207 uint32_t array_pitch_el_rows;
1208
1209 enum isl_array_pitch_span array_pitch_span;
1210
1211 /** Copy of isl_surf_init_info::usage. */
1212 isl_surf_usage_flags_t usage;
1213 };
1214
1215 struct isl_swizzle {
1216 enum isl_channel_select r:4;
1217 enum isl_channel_select g:4;
1218 enum isl_channel_select b:4;
1219 enum isl_channel_select a:4;
1220 };
1221
1222 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1223 .r = ISL_CHANNEL_SELECT_##R, \
1224 .g = ISL_CHANNEL_SELECT_##G, \
1225 .b = ISL_CHANNEL_SELECT_##B, \
1226 .a = ISL_CHANNEL_SELECT_##A, \
1227 })
1228
1229 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1230
1231 struct isl_view {
1232 /**
1233 * Indicates the usage of the particular view
1234 *
1235 * Normally, this is one bit. However, for a cube map texture, it
1236 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1237 */
1238 isl_surf_usage_flags_t usage;
1239
1240 /**
1241 * The format to use in the view
1242 *
1243 * This may differ from the format of the actual isl_surf but must have
1244 * the same block size.
1245 */
1246 enum isl_format format;
1247
1248 uint32_t base_level;
1249 uint32_t levels;
1250
1251 /**
1252 * Base array layer
1253 *
1254 * For cube maps, both base_array_layer and array_len should be
1255 * specified in terms of 2-D layers and must be a multiple of 6.
1256 *
1257 * 3-D textures are effectively treated as 2-D arrays when used as a
1258 * storage image or render target. If `usage` contains
1259 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1260 * base_array_layer and array_len are applied. If the surface is only used
1261 * for texturing, they are ignored.
1262 */
1263 uint32_t base_array_layer;
1264
1265 /**
1266 * Array Length
1267 *
1268 * Indicates the number of array elements starting at Base Array Layer.
1269 */
1270 uint32_t array_len;
1271
1272 struct isl_swizzle swizzle;
1273 };
1274
1275 union isl_color_value {
1276 float f32[4];
1277 uint32_t u32[4];
1278 int32_t i32[4];
1279 };
1280
1281 struct isl_surf_fill_state_info {
1282 const struct isl_surf *surf;
1283 const struct isl_view *view;
1284
1285 /**
1286 * The address of the surface in GPU memory.
1287 */
1288 uint64_t address;
1289
1290 /**
1291 * The Memory Object Control state for the filled surface state.
1292 *
1293 * The exact format of this value depends on hardware generation.
1294 */
1295 uint32_t mocs;
1296
1297 /**
1298 * The auxilary surface or NULL if no auxilary surface is to be used.
1299 */
1300 const struct isl_surf *aux_surf;
1301 enum isl_aux_usage aux_usage;
1302 uint64_t aux_address;
1303
1304 /**
1305 * The clear color for this surface
1306 *
1307 * Valid values depend on hardware generation.
1308 */
1309 union isl_color_value clear_color;
1310
1311 /**
1312 * Send only the clear value address
1313 *
1314 * If set, we only pass the clear address to the GPU and it will fetch it
1315 * from wherever it is.
1316 */
1317 bool use_clear_address;
1318 uint64_t clear_address;
1319
1320 /**
1321 * Surface write disables for gen4-5
1322 */
1323 isl_channel_mask_t write_disables;
1324
1325 /* Intra-tile offset */
1326 uint16_t x_offset_sa, y_offset_sa;
1327 };
1328
1329 struct isl_buffer_fill_state_info {
1330 /**
1331 * The address of the surface in GPU memory.
1332 */
1333 uint64_t address;
1334
1335 /**
1336 * The size of the buffer
1337 */
1338 uint64_t size;
1339
1340 /**
1341 * The Memory Object Control state for the filled surface state.
1342 *
1343 * The exact format of this value depends on hardware generation.
1344 */
1345 uint32_t mocs;
1346
1347 /**
1348 * The format to use in the surface state
1349 *
1350 * This may differ from the format of the actual isl_surf but have the
1351 * same block size.
1352 */
1353 enum isl_format format;
1354
1355 uint32_t stride;
1356 };
1357
1358 struct isl_depth_stencil_hiz_emit_info {
1359 /**
1360 * The depth surface
1361 */
1362 const struct isl_surf *depth_surf;
1363
1364 /**
1365 * The stencil surface
1366 *
1367 * If separate stencil is not available, this must point to the same
1368 * isl_surf as depth_surf.
1369 */
1370 const struct isl_surf *stencil_surf;
1371
1372 /**
1373 * The view into the depth and stencil surfaces.
1374 *
1375 * This view applies to both surfaces simultaneously.
1376 */
1377 const struct isl_view *view;
1378
1379 /**
1380 * The address of the depth surface in GPU memory
1381 */
1382 uint64_t depth_address;
1383
1384 /**
1385 * The address of the stencil surface in GPU memory
1386 *
1387 * If separate stencil is not available, this must have the same value as
1388 * depth_address.
1389 */
1390 uint64_t stencil_address;
1391
1392 /**
1393 * The Memory Object Control state for depth and stencil buffers
1394 *
1395 * Both depth and stencil will get the same MOCS value. The exact format
1396 * of this value depends on hardware generation.
1397 */
1398 uint32_t mocs;
1399
1400 /**
1401 * The HiZ surface or NULL if HiZ is disabled.
1402 */
1403 const struct isl_surf *hiz_surf;
1404 enum isl_aux_usage hiz_usage;
1405 uint64_t hiz_address;
1406
1407 /**
1408 * The depth clear value
1409 */
1410 float depth_clear_value;
1411 };
1412
1413 extern const struct isl_format_layout isl_format_layouts[];
1414
1415 void
1416 isl_device_init(struct isl_device *dev,
1417 const struct gen_device_info *info,
1418 bool has_bit6_swizzling);
1419
1420 isl_sample_count_mask_t ATTRIBUTE_CONST
1421 isl_device_get_sample_counts(struct isl_device *dev);
1422
1423 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1424 isl_format_get_layout(enum isl_format fmt)
1425 {
1426 return &isl_format_layouts[fmt];
1427 }
1428
1429 bool isl_format_is_valid(enum isl_format);
1430
1431 static inline const char * ATTRIBUTE_CONST
1432 isl_format_get_name(enum isl_format fmt)
1433 {
1434 return isl_format_layouts[fmt].name;
1435 }
1436
1437 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1438 enum isl_format format);
1439 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1440 enum isl_format format);
1441 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1442 enum isl_format format);
1443 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1444 enum isl_format format);
1445 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1446 enum isl_format format);
1447 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1448 enum isl_format format);
1449 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1450 enum isl_format format);
1451 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1452 enum isl_format format);
1453 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1454 enum isl_format format);
1455 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1456 enum isl_format format);
1457
1458 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1459 enum isl_format format1,
1460 enum isl_format format2);
1461
1462 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1463 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1464 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1465 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1466 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1467 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1468
1469 static inline bool
1470 isl_format_has_normalized_channel(enum isl_format fmt)
1471 {
1472 return isl_format_has_unorm_channel(fmt) ||
1473 isl_format_has_snorm_channel(fmt);
1474 }
1475
1476 static inline bool
1477 isl_format_has_float_channel(enum isl_format fmt)
1478 {
1479 return isl_format_has_ufloat_channel(fmt) ||
1480 isl_format_has_sfloat_channel(fmt);
1481 }
1482
1483 static inline bool
1484 isl_format_has_int_channel(enum isl_format fmt)
1485 {
1486 return isl_format_has_uint_channel(fmt) ||
1487 isl_format_has_sint_channel(fmt);
1488 }
1489
1490 unsigned isl_format_get_num_channels(enum isl_format fmt);
1491
1492 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1493
1494 static inline bool
1495 isl_format_is_compressed(enum isl_format fmt)
1496 {
1497 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1498
1499 return fmtl->txc != ISL_TXC_NONE;
1500 }
1501
1502 static inline bool
1503 isl_format_has_bc_compression(enum isl_format fmt)
1504 {
1505 switch (isl_format_get_layout(fmt)->txc) {
1506 case ISL_TXC_DXT1:
1507 case ISL_TXC_DXT3:
1508 case ISL_TXC_DXT5:
1509 return true;
1510 case ISL_TXC_NONE:
1511 case ISL_TXC_FXT1:
1512 case ISL_TXC_RGTC1:
1513 case ISL_TXC_RGTC2:
1514 case ISL_TXC_BPTC:
1515 case ISL_TXC_ETC1:
1516 case ISL_TXC_ETC2:
1517 case ISL_TXC_ASTC:
1518 return false;
1519
1520 case ISL_TXC_HIZ:
1521 case ISL_TXC_MCS:
1522 case ISL_TXC_CCS:
1523 unreachable("Should not be called on an aux surface");
1524 }
1525
1526 unreachable("bad texture compression mode");
1527 return false;
1528 }
1529
1530 static inline bool
1531 isl_format_is_yuv(enum isl_format fmt)
1532 {
1533 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1534
1535 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1536 }
1537
1538 static inline bool
1539 isl_format_block_is_1x1x1(enum isl_format fmt)
1540 {
1541 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1542
1543 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1544 }
1545
1546 static inline bool
1547 isl_format_is_srgb(enum isl_format fmt)
1548 {
1549 return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB;
1550 }
1551
1552 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1553
1554 static inline bool
1555 isl_format_is_rgb(enum isl_format fmt)
1556 {
1557 if (isl_format_is_yuv(fmt))
1558 return false;
1559 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1560 isl_format_layouts[fmt].channels.g.bits > 0 &&
1561 isl_format_layouts[fmt].channels.b.bits > 0 &&
1562 isl_format_layouts[fmt].channels.a.bits == 0;
1563 }
1564
1565 static inline bool
1566 isl_format_is_rgbx(enum isl_format fmt)
1567 {
1568 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1569 isl_format_layouts[fmt].channels.g.bits > 0 &&
1570 isl_format_layouts[fmt].channels.b.bits > 0 &&
1571 isl_format_layouts[fmt].channels.a.bits > 0 &&
1572 isl_format_layouts[fmt].channels.a.type == ISL_VOID;
1573 }
1574
1575 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1576 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1577 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1578
1579 bool isl_is_storage_image_format(enum isl_format fmt);
1580
1581 enum isl_format
1582 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1583 enum isl_format fmt);
1584
1585 /* Returns true if this hardware supports typed load/store on a format with
1586 * the same size as the given format.
1587 */
1588 bool
1589 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1590 enum isl_format fmt);
1591
1592 static inline bool
1593 isl_tiling_is_any_y(enum isl_tiling tiling)
1594 {
1595 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1596 }
1597
1598 static inline bool
1599 isl_tiling_is_std_y(enum isl_tiling tiling)
1600 {
1601 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1602 }
1603
1604 uint32_t
1605 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1606
1607 enum isl_tiling
1608 isl_tiling_from_i915_tiling(uint32_t tiling);
1609
1610 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1611 isl_drm_modifier_get_info(uint64_t modifier);
1612
1613 static inline bool
1614 isl_drm_modifier_has_aux(uint64_t modifier)
1615 {
1616 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1617 }
1618
1619 /** Returns the default isl_aux_state for the given modifier.
1620 *
1621 * If we have a modifier which supports compression, then the auxiliary data
1622 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1623 * can be in any of the following:
1624 *
1625 * - ISL_AUX_STATE_CLEAR
1626 * - ISL_AUX_STATE_PARTIAL_CLEAR
1627 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1628 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1629 * - ISL_AUX_STATE_RESOLVED
1630 * - ISL_AUX_STATE_PASS_THROUGH
1631 *
1632 * If the modifier does not support fast-clears, then we are guaranteed
1633 * that the surface is at least partially resolved and the first three not
1634 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1635 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1636 * because they are the least common denominator of the set of possible aux
1637 * states and will yield a valid interpretation of the aux data.
1638 *
1639 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1640 */
1641 static inline enum isl_aux_state
1642 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1643 {
1644 const struct isl_drm_modifier_info *mod_info =
1645 isl_drm_modifier_get_info(modifier);
1646
1647 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1648 return ISL_AUX_STATE_AUX_INVALID;
1649
1650 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1651 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1652 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1653 }
1654
1655 struct isl_extent2d ATTRIBUTE_CONST
1656 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1657
1658 static inline bool
1659 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1660 {
1661 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1662 }
1663
1664 static inline bool
1665 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1666 {
1667 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1668 }
1669
1670 static inline bool
1671 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1672 {
1673 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1674 }
1675
1676 static inline bool
1677 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1678 {
1679 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1680 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1681 }
1682
1683 static inline bool
1684 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1685 {
1686 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1687 }
1688
1689 static inline bool
1690 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1691 {
1692 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1693 (info->format == ISL_FORMAT_R16_UNORM);
1694 }
1695
1696 static inline bool
1697 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1698 {
1699 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1700 (info->format == ISL_FORMAT_R32_FLOAT);
1701 }
1702
1703 static inline struct isl_extent2d
1704 isl_extent2d(uint32_t width, uint32_t height)
1705 {
1706 struct isl_extent2d e = { { 0 } };
1707
1708 e.width = width;
1709 e.height = height;
1710
1711 return e;
1712 }
1713
1714 static inline struct isl_extent3d
1715 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1716 {
1717 struct isl_extent3d e = { { 0 } };
1718
1719 e.width = width;
1720 e.height = height;
1721 e.depth = depth;
1722
1723 return e;
1724 }
1725
1726 static inline struct isl_extent4d
1727 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1728 uint32_t array_len)
1729 {
1730 struct isl_extent4d e = { { 0 } };
1731
1732 e.width = width;
1733 e.height = height;
1734 e.depth = depth;
1735 e.array_len = array_len;
1736
1737 return e;
1738 }
1739
1740 bool isl_color_value_is_zero(union isl_color_value value,
1741 enum isl_format format);
1742
1743 bool isl_color_value_is_zero_one(union isl_color_value value,
1744 enum isl_format format);
1745
1746 static inline bool
1747 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1748 {
1749 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1750 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1751 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1752 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1753 }
1754
1755 bool
1756 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1757 struct isl_swizzle swizzle);
1758
1759 struct isl_swizzle
1760 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
1761 struct isl_swizzle
1762 isl_swizzle_invert(struct isl_swizzle swizzle);
1763
1764 #define isl_surf_init(dev, surf, ...) \
1765 isl_surf_init_s((dev), (surf), \
1766 &(struct isl_surf_init_info) { __VA_ARGS__ });
1767
1768 bool
1769 isl_surf_init_s(const struct isl_device *dev,
1770 struct isl_surf *surf,
1771 const struct isl_surf_init_info *restrict info);
1772
1773 void
1774 isl_surf_get_tile_info(const struct isl_surf *surf,
1775 struct isl_tile_info *tile_info);
1776
1777 bool
1778 isl_surf_get_hiz_surf(const struct isl_device *dev,
1779 const struct isl_surf *surf,
1780 struct isl_surf *hiz_surf);
1781
1782 bool
1783 isl_surf_get_mcs_surf(const struct isl_device *dev,
1784 const struct isl_surf *surf,
1785 struct isl_surf *mcs_surf);
1786
1787 bool
1788 isl_surf_get_ccs_surf(const struct isl_device *dev,
1789 const struct isl_surf *surf,
1790 struct isl_surf *ccs_surf,
1791 uint32_t row_pitch /**< Ignored if 0 */);
1792
1793 #define isl_surf_fill_state(dev, state, ...) \
1794 isl_surf_fill_state_s((dev), (state), \
1795 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1796
1797 void
1798 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1799 const struct isl_surf_fill_state_info *restrict info);
1800
1801 #define isl_buffer_fill_state(dev, state, ...) \
1802 isl_buffer_fill_state_s((dev), (state), \
1803 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1804
1805 void
1806 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1807 const struct isl_buffer_fill_state_info *restrict info);
1808
1809 void
1810 isl_null_fill_state(const struct isl_device *dev, void *state,
1811 struct isl_extent3d size);
1812
1813 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1814 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1815 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1816
1817 void
1818 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
1819 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1820
1821 void
1822 isl_surf_fill_image_param(const struct isl_device *dev,
1823 struct brw_image_param *param,
1824 const struct isl_surf *surf,
1825 const struct isl_view *view);
1826
1827 void
1828 isl_buffer_fill_image_param(const struct isl_device *dev,
1829 struct brw_image_param *param,
1830 enum isl_format format,
1831 uint64_t size);
1832
1833 /**
1834 * Alignment of the upper-left sample of each subimage, in units of surface
1835 * elements.
1836 */
1837 static inline struct isl_extent3d
1838 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1839 {
1840 return surf->image_alignment_el;
1841 }
1842
1843 /**
1844 * Alignment of the upper-left sample of each subimage, in units of surface
1845 * samples.
1846 */
1847 static inline struct isl_extent3d
1848 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1849 {
1850 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1851
1852 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1853 fmtl->bh * surf->image_alignment_el.h,
1854 fmtl->bd * surf->image_alignment_el.d);
1855 }
1856
1857 /**
1858 * Pitch between vertically adjacent surface elements, in bytes.
1859 */
1860 static inline uint32_t
1861 isl_surf_get_row_pitch(const struct isl_surf *surf)
1862 {
1863 return surf->row_pitch;
1864 }
1865
1866 /**
1867 * Pitch between vertically adjacent surface elements, in units of surface elements.
1868 */
1869 static inline uint32_t
1870 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1871 {
1872 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1873
1874 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1875 return surf->row_pitch / (fmtl->bpb / 8);
1876 }
1877
1878 /**
1879 * Pitch between physical array slices, in rows of surface elements.
1880 */
1881 static inline uint32_t
1882 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1883 {
1884 return surf->array_pitch_el_rows;
1885 }
1886
1887 /**
1888 * Pitch between physical array slices, in units of surface elements.
1889 */
1890 static inline uint32_t
1891 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1892 {
1893 return isl_surf_get_array_pitch_el_rows(surf) *
1894 isl_surf_get_row_pitch_el(surf);
1895 }
1896
1897 /**
1898 * Pitch between physical array slices, in rows of surface samples.
1899 */
1900 static inline uint32_t
1901 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1902 {
1903 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1904 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1905 }
1906
1907 /**
1908 * Pitch between physical array slices, in bytes.
1909 */
1910 static inline uint32_t
1911 isl_surf_get_array_pitch(const struct isl_surf *surf)
1912 {
1913 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1914 }
1915
1916 /**
1917 * Calculate the offset, in units of surface samples, to a subimage in the
1918 * surface.
1919 *
1920 * @invariant level < surface levels
1921 * @invariant logical_array_layer < logical array length of surface
1922 * @invariant logical_z_offset_px < logical depth of surface at level
1923 */
1924 void
1925 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1926 uint32_t level,
1927 uint32_t logical_array_layer,
1928 uint32_t logical_z_offset_px,
1929 uint32_t *x_offset_sa,
1930 uint32_t *y_offset_sa);
1931
1932 /**
1933 * Calculate the offset, in units of surface elements, to a subimage in the
1934 * surface.
1935 *
1936 * @invariant level < surface levels
1937 * @invariant logical_array_layer < logical array length of surface
1938 * @invariant logical_z_offset_px < logical depth of surface at level
1939 */
1940 void
1941 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1942 uint32_t level,
1943 uint32_t logical_array_layer,
1944 uint32_t logical_z_offset_px,
1945 uint32_t *x_offset_el,
1946 uint32_t *y_offset_el);
1947
1948 /**
1949 * Calculate the offset, in bytes and intratile surface samples, to a
1950 * subimage in the surface.
1951 *
1952 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
1953 * result to isl_tiling_get_intratile_offset_el, and converting the tile
1954 * offsets to samples.
1955 *
1956 * @invariant level < surface levels
1957 * @invariant logical_array_layer < logical array length of surface
1958 * @invariant logical_z_offset_px < logical depth of surface at level
1959 */
1960 void
1961 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
1962 uint32_t level,
1963 uint32_t logical_array_layer,
1964 uint32_t logical_z_offset_px,
1965 uint32_t *offset_B,
1966 uint32_t *x_offset_sa,
1967 uint32_t *y_offset_sa);
1968
1969 /**
1970 * Create an isl_surf that represents a particular subimage in the surface.
1971 *
1972 * The newly created surface will have a single miplevel and array slice. The
1973 * surface lives at the returned byte and intratile offsets, in samples.
1974 *
1975 * It is safe to call this function with surf == image_surf.
1976 *
1977 * @invariant level < surface levels
1978 * @invariant logical_array_layer < logical array length of surface
1979 * @invariant logical_z_offset_px < logical depth of surface at level
1980 */
1981 void
1982 isl_surf_get_image_surf(const struct isl_device *dev,
1983 const struct isl_surf *surf,
1984 uint32_t level,
1985 uint32_t logical_array_layer,
1986 uint32_t logical_z_offset_px,
1987 struct isl_surf *image_surf,
1988 uint32_t *offset_B,
1989 uint32_t *x_offset_sa,
1990 uint32_t *y_offset_sa);
1991
1992 /**
1993 * @brief Calculate the intratile offsets to a surface.
1994 *
1995 * In @a base_address_offset return the offset from the base of the surface to
1996 * the base address of the first tile of the subimage. In @a x_offset_B and
1997 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1998 * tile's base to the subimage's first surface element. The x and y offsets
1999 * are intratile offsets; that is, they do not exceed the boundary of the
2000 * surface's tiling format.
2001 */
2002 void
2003 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2004 uint32_t bpb,
2005 uint32_t row_pitch,
2006 uint32_t total_x_offset_el,
2007 uint32_t total_y_offset_el,
2008 uint32_t *base_address_offset,
2009 uint32_t *x_offset_el,
2010 uint32_t *y_offset_el);
2011
2012 static inline void
2013 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2014 enum isl_format format,
2015 uint32_t row_pitch,
2016 uint32_t total_x_offset_sa,
2017 uint32_t total_y_offset_sa,
2018 uint32_t *base_address_offset,
2019 uint32_t *x_offset_sa,
2020 uint32_t *y_offset_sa)
2021 {
2022 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2023
2024 /* For computing the intratile offsets, we actually want a strange unit
2025 * which is samples for multisampled surfaces but elements for compressed
2026 * surfaces.
2027 */
2028 assert(total_x_offset_sa % fmtl->bw == 0);
2029 assert(total_y_offset_sa % fmtl->bh == 0);
2030 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2031 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2032
2033 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch,
2034 total_x_offset, total_y_offset,
2035 base_address_offset,
2036 x_offset_sa, y_offset_sa);
2037 *x_offset_sa *= fmtl->bw;
2038 *y_offset_sa *= fmtl->bh;
2039 }
2040
2041 /**
2042 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2043 *
2044 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2045 * @pre surf->format must be a valid format for depth surfaces
2046 */
2047 uint32_t
2048 isl_surf_get_depth_format(const struct isl_device *dev,
2049 const struct isl_surf *surf);
2050
2051 #ifdef __cplusplus
2052 }
2053 #endif
2054
2055 #endif /* ISL_H */