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i965: Pretend that CCS modified images are two planes
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51
52 struct gen_device_info;
53 struct brw_image_param;
54
55 #ifndef ISL_DEV_GEN
56 /**
57 * @brief Get the hardware generation of isl_device.
58 *
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 */
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #else
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
67 #endif
68
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
71 #endif
72
73 #ifndef ISL_DEV_IS_HASWELL
74 /**
75 * @brief Get the hardware generation of isl_device.
76 *
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 */
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
81 #endif
82
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
85 #endif
86
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 /**
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 */
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #else
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
97 #endif
98
99 /**
100 * Hardware enumeration SURFACE_FORMAT.
101 *
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
104 */
105 enum isl_format {
106 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
107 ISL_FORMAT_R32G32B32A32_SINT = 1,
108 ISL_FORMAT_R32G32B32A32_UINT = 2,
109 ISL_FORMAT_R32G32B32A32_UNORM = 3,
110 ISL_FORMAT_R32G32B32A32_SNORM = 4,
111 ISL_FORMAT_R64G64_FLOAT = 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
114 ISL_FORMAT_R32G32B32A32_USCALED = 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
116 ISL_FORMAT_R64G64_PASSTHRU = 33,
117 ISL_FORMAT_R32G32B32_FLOAT = 64,
118 ISL_FORMAT_R32G32B32_SINT = 65,
119 ISL_FORMAT_R32G32B32_UINT = 66,
120 ISL_FORMAT_R32G32B32_UNORM = 67,
121 ISL_FORMAT_R32G32B32_SNORM = 68,
122 ISL_FORMAT_R32G32B32_SSCALED = 69,
123 ISL_FORMAT_R32G32B32_USCALED = 70,
124 ISL_FORMAT_R32G32B32_SFIXED = 80,
125 ISL_FORMAT_R16G16B16A16_UNORM = 128,
126 ISL_FORMAT_R16G16B16A16_SNORM = 129,
127 ISL_FORMAT_R16G16B16A16_SINT = 130,
128 ISL_FORMAT_R16G16B16A16_UINT = 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
130 ISL_FORMAT_R32G32_FLOAT = 133,
131 ISL_FORMAT_R32G32_SINT = 134,
132 ISL_FORMAT_R32G32_UINT = 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
135 ISL_FORMAT_L32A32_FLOAT = 138,
136 ISL_FORMAT_R32G32_UNORM = 139,
137 ISL_FORMAT_R32G32_SNORM = 140,
138 ISL_FORMAT_R64_FLOAT = 141,
139 ISL_FORMAT_R16G16B16X16_UNORM = 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
141 ISL_FORMAT_A32X32_FLOAT = 144,
142 ISL_FORMAT_L32X32_FLOAT = 145,
143 ISL_FORMAT_I32X32_FLOAT = 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
145 ISL_FORMAT_R16G16B16A16_USCALED = 148,
146 ISL_FORMAT_R32G32_SSCALED = 149,
147 ISL_FORMAT_R32G32_USCALED = 150,
148 ISL_FORMAT_R32G32_FLOAT_LD = 151,
149 ISL_FORMAT_R32G32_SFIXED = 160,
150 ISL_FORMAT_R64_PASSTHRU = 161,
151 ISL_FORMAT_B8G8R8A8_UNORM = 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
153 ISL_FORMAT_R10G10B10A2_UNORM = 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
155 ISL_FORMAT_R10G10B10A2_UINT = 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
157 ISL_FORMAT_R8G8B8A8_UNORM = 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
159 ISL_FORMAT_R8G8B8A8_SNORM = 201,
160 ISL_FORMAT_R8G8B8A8_SINT = 202,
161 ISL_FORMAT_R8G8B8A8_UINT = 203,
162 ISL_FORMAT_R16G16_UNORM = 204,
163 ISL_FORMAT_R16G16_SNORM = 205,
164 ISL_FORMAT_R16G16_SINT = 206,
165 ISL_FORMAT_R16G16_UINT = 207,
166 ISL_FORMAT_R16G16_FLOAT = 208,
167 ISL_FORMAT_B10G10R10A2_UNORM = 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
169 ISL_FORMAT_R11G11B10_FLOAT = 211,
170 ISL_FORMAT_R32_SINT = 214,
171 ISL_FORMAT_R32_UINT = 215,
172 ISL_FORMAT_R32_FLOAT = 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
175 ISL_FORMAT_L32_UNORM = 221,
176 ISL_FORMAT_A32_UNORM = 222,
177 ISL_FORMAT_L16A16_UNORM = 223,
178 ISL_FORMAT_I24X8_UNORM = 224,
179 ISL_FORMAT_L24X8_UNORM = 225,
180 ISL_FORMAT_A24X8_UNORM = 226,
181 ISL_FORMAT_I32_FLOAT = 227,
182 ISL_FORMAT_L32_FLOAT = 228,
183 ISL_FORMAT_A32_FLOAT = 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
187 ISL_FORMAT_B8G8R8X8_UNORM = 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
189 ISL_FORMAT_R8G8B8X8_UNORM = 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
192 ISL_FORMAT_B10G10R10X2_UNORM = 238,
193 ISL_FORMAT_L16A16_FLOAT = 240,
194 ISL_FORMAT_R32_UNORM = 241,
195 ISL_FORMAT_R32_SNORM = 242,
196 ISL_FORMAT_R10G10B10X2_USCALED = 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
198 ISL_FORMAT_R8G8B8A8_USCALED = 245,
199 ISL_FORMAT_R16G16_SSCALED = 246,
200 ISL_FORMAT_R16G16_USCALED = 247,
201 ISL_FORMAT_R32_SSCALED = 248,
202 ISL_FORMAT_R32_USCALED = 249,
203 ISL_FORMAT_B5G6R5_UNORM = 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
205 ISL_FORMAT_B5G5R5A1_UNORM = 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
207 ISL_FORMAT_B4G4R4A4_UNORM = 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
209 ISL_FORMAT_R8G8_UNORM = 262,
210 ISL_FORMAT_R8G8_SNORM = 263,
211 ISL_FORMAT_R8G8_SINT = 264,
212 ISL_FORMAT_R8G8_UINT = 265,
213 ISL_FORMAT_R16_UNORM = 266,
214 ISL_FORMAT_R16_SNORM = 267,
215 ISL_FORMAT_R16_SINT = 268,
216 ISL_FORMAT_R16_UINT = 269,
217 ISL_FORMAT_R16_FLOAT = 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
220 ISL_FORMAT_I16_UNORM = 273,
221 ISL_FORMAT_L16_UNORM = 274,
222 ISL_FORMAT_A16_UNORM = 275,
223 ISL_FORMAT_L8A8_UNORM = 276,
224 ISL_FORMAT_I16_FLOAT = 277,
225 ISL_FORMAT_L16_FLOAT = 278,
226 ISL_FORMAT_A16_FLOAT = 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
229 ISL_FORMAT_B5G5R5X1_UNORM = 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
231 ISL_FORMAT_R8G8_SSCALED = 284,
232 ISL_FORMAT_R8G8_USCALED = 285,
233 ISL_FORMAT_R16_SSCALED = 286,
234 ISL_FORMAT_R16_USCALED = 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
237 ISL_FORMAT_A1B5G5R5_UNORM = 292,
238 ISL_FORMAT_A4B4G4R4_UNORM = 293,
239 ISL_FORMAT_L8A8_UINT = 294,
240 ISL_FORMAT_L8A8_SINT = 295,
241 ISL_FORMAT_R8_UNORM = 320,
242 ISL_FORMAT_R8_SNORM = 321,
243 ISL_FORMAT_R8_SINT = 322,
244 ISL_FORMAT_R8_UINT = 323,
245 ISL_FORMAT_A8_UNORM = 324,
246 ISL_FORMAT_I8_UNORM = 325,
247 ISL_FORMAT_L8_UNORM = 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
250 ISL_FORMAT_R8_SSCALED = 329,
251 ISL_FORMAT_R8_USCALED = 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
253 ISL_FORMAT_L8_UNORM_SRGB = 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
257 ISL_FORMAT_Y8_UNORM = 336,
258 ISL_FORMAT_L8_UINT = 338,
259 ISL_FORMAT_L8_SINT = 339,
260 ISL_FORMAT_I8_UINT = 340,
261 ISL_FORMAT_I8_SINT = 341,
262 ISL_FORMAT_DXT1_RGB_SRGB = 384,
263 ISL_FORMAT_R1_UNORM = 385,
264 ISL_FORMAT_YCRCB_NORMAL = 386,
265 ISL_FORMAT_YCRCB_SWAPUVY = 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
268 ISL_FORMAT_BC1_UNORM = 390,
269 ISL_FORMAT_BC2_UNORM = 391,
270 ISL_FORMAT_BC3_UNORM = 392,
271 ISL_FORMAT_BC4_UNORM = 393,
272 ISL_FORMAT_BC5_UNORM = 394,
273 ISL_FORMAT_BC1_UNORM_SRGB = 395,
274 ISL_FORMAT_BC2_UNORM_SRGB = 396,
275 ISL_FORMAT_BC3_UNORM_SRGB = 397,
276 ISL_FORMAT_MONO8 = 398,
277 ISL_FORMAT_YCRCB_SWAPUV = 399,
278 ISL_FORMAT_YCRCB_SWAPY = 400,
279 ISL_FORMAT_DXT1_RGB = 401,
280 ISL_FORMAT_FXT1 = 402,
281 ISL_FORMAT_R8G8B8_UNORM = 403,
282 ISL_FORMAT_R8G8B8_SNORM = 404,
283 ISL_FORMAT_R8G8B8_SSCALED = 405,
284 ISL_FORMAT_R8G8B8_USCALED = 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
286 ISL_FORMAT_R64G64B64_FLOAT = 408,
287 ISL_FORMAT_BC4_SNORM = 409,
288 ISL_FORMAT_BC5_SNORM = 410,
289 ISL_FORMAT_R16G16B16_FLOAT = 411,
290 ISL_FORMAT_R16G16B16_UNORM = 412,
291 ISL_FORMAT_R16G16B16_SNORM = 413,
292 ISL_FORMAT_R16G16B16_SSCALED = 414,
293 ISL_FORMAT_R16G16B16_USCALED = 415,
294 ISL_FORMAT_BC6H_SF16 = 417,
295 ISL_FORMAT_BC7_UNORM = 418,
296 ISL_FORMAT_BC7_UNORM_SRGB = 419,
297 ISL_FORMAT_BC6H_UF16 = 420,
298 ISL_FORMAT_PLANAR_420_8 = 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
300 ISL_FORMAT_ETC1_RGB8 = 425,
301 ISL_FORMAT_ETC2_RGB8 = 426,
302 ISL_FORMAT_EAC_R11 = 427,
303 ISL_FORMAT_EAC_RG11 = 428,
304 ISL_FORMAT_EAC_SIGNED_R11 = 429,
305 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
306 ISL_FORMAT_ETC2_SRGB8 = 431,
307 ISL_FORMAT_R16G16B16_UINT = 432,
308 ISL_FORMAT_R16G16B16_SINT = 433,
309 ISL_FORMAT_R32_SFIXED = 434,
310 ISL_FORMAT_R10G10B10A2_SNORM = 435,
311 ISL_FORMAT_R10G10B10A2_USCALED = 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
313 ISL_FORMAT_R10G10B10A2_SINT = 438,
314 ISL_FORMAT_B10G10R10A2_SNORM = 439,
315 ISL_FORMAT_B10G10R10A2_USCALED = 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
317 ISL_FORMAT_B10G10R10A2_UINT = 442,
318 ISL_FORMAT_B10G10R10A2_SINT = 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
321 ISL_FORMAT_ETC2_RGB8_PTA = 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
325 ISL_FORMAT_R8G8B8_UINT = 456,
326 ISL_FORMAT_R8G8B8_SINT = 457,
327 ISL_FORMAT_RAW = 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
370
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
374 */
375
376 /* Formats for auxiliary surfaces */
377 ISL_FORMAT_HIZ,
378 ISL_FORMAT_MCS_2X,
379 ISL_FORMAT_MCS_4X,
380 ISL_FORMAT_MCS_8X,
381 ISL_FORMAT_MCS_16X,
382 ISL_FORMAT_GEN7_CCS_32BPP_X,
383 ISL_FORMAT_GEN7_CCS_64BPP_X,
384 ISL_FORMAT_GEN7_CCS_128BPP_X,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y,
388 ISL_FORMAT_GEN9_CCS_32BPP,
389 ISL_FORMAT_GEN9_CCS_64BPP,
390 ISL_FORMAT_GEN9_CCS_128BPP,
391
392 /* Hardware doesn't understand this out-of-band value */
393 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
394 };
395
396 /**
397 * Numerical base type for channels of isl_format.
398 */
399 enum isl_base_type {
400 ISL_VOID,
401 ISL_RAW,
402 ISL_UNORM,
403 ISL_SNORM,
404 ISL_UFLOAT,
405 ISL_SFLOAT,
406 ISL_UFIXED,
407 ISL_SFIXED,
408 ISL_UINT,
409 ISL_SINT,
410 ISL_USCALED,
411 ISL_SSCALED,
412 };
413
414 /**
415 * Colorspace of isl_format.
416 */
417 enum isl_colorspace {
418 ISL_COLORSPACE_NONE = 0,
419 ISL_COLORSPACE_LINEAR,
420 ISL_COLORSPACE_SRGB,
421 ISL_COLORSPACE_YUV,
422 };
423
424 /**
425 * Texture compression mode of isl_format.
426 */
427 enum isl_txc {
428 ISL_TXC_NONE = 0,
429 ISL_TXC_DXT1,
430 ISL_TXC_DXT3,
431 ISL_TXC_DXT5,
432 ISL_TXC_FXT1,
433 ISL_TXC_RGTC1,
434 ISL_TXC_RGTC2,
435 ISL_TXC_BPTC,
436 ISL_TXC_ETC1,
437 ISL_TXC_ETC2,
438 ISL_TXC_ASTC,
439
440 /* Used for auxiliary surface formats */
441 ISL_TXC_HIZ,
442 ISL_TXC_MCS,
443 ISL_TXC_CCS,
444 };
445
446 /**
447 * @brief Hardware tile mode
448 *
449 * WARNING: These values differ from the hardware enum values, which are
450 * unstable across hardware generations.
451 *
452 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
453 * clearly distinguish it from Yf and Ys.
454 */
455 enum isl_tiling {
456 ISL_TILING_LINEAR = 0,
457 ISL_TILING_W,
458 ISL_TILING_X,
459 ISL_TILING_Y0, /**< Legacy Y tiling */
460 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
461 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
462 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
463 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
464 };
465
466 /**
467 * @defgroup Tiling Flags
468 * @{
469 */
470 typedef uint32_t isl_tiling_flags_t;
471 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
472 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
473 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
474 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
475 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
476 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
477 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
478 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
479 #define ISL_TILING_ANY_MASK (~0u)
480 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
481
482 /** Any Y tiling, including legacy Y tiling. */
483 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
484 ISL_TILING_Yf_BIT | \
485 ISL_TILING_Ys_BIT)
486
487 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
488 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
489 ISL_TILING_Ys_BIT)
490 /** @} */
491
492 /**
493 * @brief Logical dimension of surface.
494 *
495 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
496 * as 2D array surfaces.
497 */
498 enum isl_surf_dim {
499 ISL_SURF_DIM_1D,
500 ISL_SURF_DIM_2D,
501 ISL_SURF_DIM_3D,
502 };
503
504 /**
505 * @brief Physical layout of the surface's dimensions.
506 */
507 enum isl_dim_layout {
508 /**
509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
510 * 6.17.3: 2D Surfaces.
511 *
512 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
513 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
514 *
515 * One-dimensional surfaces are identical to 2D surfaces with height of
516 * one.
517 *
518 * @invariant isl_surf::phys_level0_sa::depth == 1
519 */
520 ISL_DIM_LAYOUT_GEN4_2D,
521
522 /**
523 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
524 * 6.17.5: 3D Surfaces.
525 *
526 * @invariant isl_surf::phys_level0_sa::array_len == 1
527 */
528 ISL_DIM_LAYOUT_GEN4_3D,
529
530 /**
531 * Special layout used for HiZ and stencil on Sandy Bridge to work around
532 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
533 * work the same as on gen7+ except that they don't technically support
534 * mipmapping. That does not, however, stop us from doing it. As far as
535 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
536 * single miplevel 2D (possibly array) image. The dimensions of that image
537 * are NOT minified.
538 *
539 * In order to implement HiZ and stencil on Sandy Bridge, we create one
540 * full-sized 2D (possibly array) image for every LOD with every image
541 * aligned to a page boundary. When the surface is used with the stencil
542 * or HiZ hardware, we manually offset to the image for the given LOD.
543 *
544 * As a memory saving measure, we pretend that the width of each miplevel
545 * is minified and we place LOD1 and above below LOD0 but horizontally
546 * adjacent to each other. When considered as full-sized images, LOD1 and
547 * above technically overlap. However, since we only write to part of that
548 * image, the hardware will never notice the overlap.
549 *
550 * This layout looks something like this:
551 *
552 * +---------+
553 * | |
554 * | |
555 * +---------+
556 * | |
557 * | |
558 * +---------+
559 *
560 * +----+ +-+ .
561 * | | +-+
562 * +----+
563 *
564 * +----+ +-+ .
565 * | | +-+
566 * +----+
567 */
568 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
569
570 /**
571 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
572 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
573 */
574 ISL_DIM_LAYOUT_GEN9_1D,
575 };
576
577 enum isl_aux_usage {
578 /** No Auxiliary surface is used */
579 ISL_AUX_USAGE_NONE,
580
581 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
582 ISL_AUX_USAGE_HIZ,
583
584 /** The auxiliary surface is an MCS
585 *
586 * @invariant isl_surf::samples > 1
587 */
588 ISL_AUX_USAGE_MCS,
589
590 /** The auxiliary surface is a fast-clear-only compression surface
591 *
592 * @invariant isl_surf::samples == 1
593 */
594 ISL_AUX_USAGE_CCS_D,
595
596 /** The auxiliary surface provides full lossless color compression
597 *
598 * @invariant isl_surf::samples == 1
599 */
600 ISL_AUX_USAGE_CCS_E,
601 };
602
603 /**
604 * Enum for keeping track of the state an auxiliary compressed surface.
605 *
606 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
607 * given slice (lod + array layer) can be in one of the six states described
608 * by this enum. Draw and resolve operations may cause the slice to change
609 * from one state to another. The six valid states are:
610 *
611 * 1) Clear: In this state, each block in the auxiliary surface contains a
612 * magic value that indicates that the block is in the clear state. If
613 * a block is in the clear state, it's values in the primary surface are
614 * ignored and the color of the samples in the block is taken either the
615 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
616 * depth. Since neither the primary surface nor the auxiliary surface
617 * contains the clear value, the surface can be cleared to a different
618 * color by simply changing the clear color without modifying either
619 * surface.
620 *
621 * 2) Partial Clear: In this state, each block in the auxiliary surface
622 * contains either the magic clear or pass-through value. See Clear and
623 * Pass-through for more details.
624 *
625 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
626 * nor the primary surface has a complete representation of the data.
627 * Instead, both surfaces must be used together or else rendering
628 * corruption may occur. Depending on the auxiliary compression format
629 * and the data, any given block in the primary surface may contain all,
630 * some, or none of the data required to reconstruct the actual sample
631 * values. Blocks may also be in the clear state (see Clear) and have
632 * their value taken from outside the surface.
633 *
634 * 4) Compressed w/o Clear: This state is identical to the state above
635 * except that no blocks are in the clear state. In this state, all of
636 * the data required to reconstruct the final sample values is contained
637 * in the auxiliary and primary surface and the clear value is not
638 * considered.
639 *
640 * 5) Resolved: In this state, the primary surface contains 100% of the
641 * data. The auxiliary surface is also valid so the surface can be
642 * validly used with or without aux enabled. The auxiliary surface may,
643 * however, contain non-trivial data and any update to the primary
644 * surface with aux disabled will cause the two to get out of sync.
645 *
646 * 6) Pass-through: In this state, the primary surface contains 100% of the
647 * data and every block in the auxiliary surface contains a magic value
648 * which indicates that the auxiliary surface should be ignored and the
649 * only the primary surface should be considered. Updating the primary
650 * surface without aux works fine and can be done repeatedly in this
651 * mode. Writing to a surface in pass-through mode with aux enabled may
652 * cause the auxiliary buffer to contain non-trivial data and no longer
653 * be in the pass-through state.
654 *
655 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
656 * data and the auxiliary surface is completely bogus. Any attempt to
657 * use the auxiliary surface is liable to result in rendering
658 * corruption. The only thing that one can do to re-enable aux once
659 * this state is reached is to use an ambiguate pass to transition into
660 * the pass-through state.
661 *
662 * Drawing with or without aux enabled may implicitly cause the surface to
663 * transition between these states. There are also four types of auxiliary
664 * compression operations which cause an explicit transition:
665 *
666 * 1) Fast Clear: This operation writes the magic "clear" value to the
667 * auxiliary surface. This operation will safely transition any slice
668 * of a surface from any state to the clear state so long as the entire
669 * slice is fast cleared at once. A fast clear that only covers part of
670 * a slice of a surface is called a partial fast clear.
671 *
672 * 2) Full Resolve: This operation combines the auxiliary surface data
673 * with the primary surface data and writes the result to the primary.
674 * For HiZ, the docs call this a depth resolve. For CCS, the hardware
675 * full resolve operation does both a full resolve and an ambiguate so
676 * it actually takes you all the way to the pass-through state.
677 *
678 * 3) Partial Resolve: This operation considers blocks which are in the
679 * "clear" state and writes the clear value directly into the primary or
680 * auxiliary surface. Once this operation completes, the surface is
681 * still compressed but no longer references the clear color. This
682 * operation is only available for CCS.
683 *
684 * 4) Ambiguate: This operation throws away the current auxiliary data and
685 * replaces it with the magic pass-through value. If an ambiguate
686 * operation is performed when the primary surface does not contain 100%
687 * of the data, data will be lost. This operation is only implemented
688 * in hardware for depth where it is called a HiZ resolve.
689 *
690 * Not all operations are valid or useful in all states. The diagram below
691 * contains a complete description of the states and all valid and useful
692 * transitions except clear.
693 *
694 * Draw w/ Aux
695 * +----------+
696 * | |
697 * | +-------------+ Draw w/ Aux +-------------+
698 * +------>| Compressed |<-------------------| Clear |
699 * | w/ Clear |----->----+ | |
700 * +-------------+ | +-------------+
701 * | /|\ | | |
702 * | | | | |
703 * | | +------<-----+ | Draw w/
704 * | | | | Clear Only
705 * | | Full | | +----------+
706 * Partial | | Resolve | \|/ | |
707 * Resolve | | | +-------------+ |
708 * | | | | Partial |<------+
709 * | | | | Clear |<----------+
710 * | | | +-------------+ |
711 * | | | | |
712 * | | +------>---------+ Full |
713 * | | | Resolve |
714 * Draw w/ aux | | Partial Fast Clear | |
715 * +----------+ | +--------------------------+ | |
716 * | | \|/ | \|/ |
717 * | +-------------+ Full Resolve +-------------+ |
718 * +------>| Compressed |------------------->| Resolved | |
719 * | w/o Clear |<-------------------| | |
720 * +-------------+ Draw w/ Aux +-------------+ |
721 * /|\ | | |
722 * | Draw | | Draw |
723 * | w/ Aux | | w/o Aux |
724 * | Ambiguate | | |
725 * | +--------------------------+ | |
726 * Draw w/o Aux | | | Draw w/o Aux |
727 * +----------+ | | | +----------+ |
728 * | | | \|/ \|/ | | |
729 * | +-------------+ Ambiguate +-------------+ | |
730 * +------>| Pass- |<-------------------| Aux |<------+ |
731 * +------>| through | | Invalid | |
732 * | +-------------+ +-------------+ |
733 * | | | |
734 * +----------+ +-----------------------------------------------------+
735 * Draw w/ Partial Fast Clear
736 * Clear Only
737 *
738 *
739 * While the above general theory applies to all forms of auxiliary
740 * compression on Intel hardware, not all states and operations are available
741 * on all compression types. However, each of the auxiliary states and
742 * operations can be fairly easily mapped onto the above diagram:
743 *
744 * HiZ: Hierarchical depth compression is capable of being in any of the
745 * states above. Hardware provides three HiZ operations: "Depth
746 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
747 * Clear", "Full Resolve", and "Ambiguate" respectively. The
748 * hardware provides no HiZ partial resolve operation so the only way
749 * to get into the "Compressed w/o Clear" state is to render with HiZ
750 * when the surface is in the resolved or pass-through states.
751 *
752 * MCS: Multisample compression is technically capable of being in any of
753 * the states above except that most of them aren't useful. Both the
754 * render engine and the sampler support MCS compression and, apart
755 * from clear color, MCS is format-unaware so we leave the surface
756 * compressed 100% of the time. The hardware provides no MCS
757 * operations.
758 *
759 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
760 * the simplest forms of compression since they don't do anything
761 * beyond clear color tracking. They really only support three of
762 * the six states: Clear, Partial Clear, and Pass-through. The
763 * only CCS_D operation is "Resolve" which maps to a full resolve
764 * followed by an ambiguate.
765 *
766 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
767 * is capable of being in almost all of the above states. THe only
768 * exception is that it does not have separate resolved and pass-
769 * through states. Instead, the CCS_E full resolve operation does
770 * both a resolve and an ambiguate so it goes directly into the
771 * pass-through state. CCS_E also provides fast clear and partial
772 * resolve operations which work as described above.
773 *
774 * While it is technically possible to perform a CCS_E ambiguate, it
775 * is not provided by Sky Lake hardware so we choose to avoid the aux
776 * invalid state. If the aux invalid state were determined to be
777 * useful, a CCS ambiguate could be done by carefully rendering to
778 * the CCS and filling it with zeros.
779 */
780 enum isl_aux_state {
781 ISL_AUX_STATE_CLEAR = 0,
782 ISL_AUX_STATE_PARTIAL_CLEAR,
783 ISL_AUX_STATE_COMPRESSED_CLEAR,
784 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
785 ISL_AUX_STATE_RESOLVED,
786 ISL_AUX_STATE_PASS_THROUGH,
787 ISL_AUX_STATE_AUX_INVALID,
788 };
789
790 /* TODO(chadv): Explain */
791 enum isl_array_pitch_span {
792 ISL_ARRAY_PITCH_SPAN_FULL,
793 ISL_ARRAY_PITCH_SPAN_COMPACT,
794 };
795
796 /**
797 * @defgroup Surface Usage
798 * @{
799 */
800 typedef uint64_t isl_surf_usage_flags_t;
801 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
802 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
803 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
804 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
805 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
806 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
807 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
808 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
809 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
810 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
811 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
812 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
813 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
814 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
815 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
816 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
817 /** @} */
818
819 /**
820 * @defgroup Channel Mask
821 *
822 * These #define values are chosen to match the values of
823 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
824 *
825 * @{
826 */
827 typedef uint8_t isl_channel_mask_t;
828 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
829 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
830 #define ISL_CHANNEL_RED_BIT (1 << 2)
831 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
832 /** @} */
833
834 /**
835 * @brief A channel select (also known as texture swizzle) value
836 */
837 enum isl_channel_select {
838 ISL_CHANNEL_SELECT_ZERO = 0,
839 ISL_CHANNEL_SELECT_ONE = 1,
840 ISL_CHANNEL_SELECT_RED = 4,
841 ISL_CHANNEL_SELECT_GREEN = 5,
842 ISL_CHANNEL_SELECT_BLUE = 6,
843 ISL_CHANNEL_SELECT_ALPHA = 7,
844 };
845
846 /**
847 * Identical to VkSampleCountFlagBits.
848 */
849 enum isl_sample_count {
850 ISL_SAMPLE_COUNT_1_BIT = 1u,
851 ISL_SAMPLE_COUNT_2_BIT = 2u,
852 ISL_SAMPLE_COUNT_4_BIT = 4u,
853 ISL_SAMPLE_COUNT_8_BIT = 8u,
854 ISL_SAMPLE_COUNT_16_BIT = 16u,
855 };
856 typedef uint32_t isl_sample_count_mask_t;
857
858 /**
859 * @brief Multisample Format
860 */
861 enum isl_msaa_layout {
862 /**
863 * @brief Suface is single-sampled.
864 */
865 ISL_MSAA_LAYOUT_NONE,
866
867 /**
868 * @brief [SNB+] Interleaved Multisample Format
869 *
870 * In this format, multiple samples are interleaved into each cacheline.
871 * In other words, the sample index is swizzled into the low 6 bits of the
872 * surface's virtual address space.
873 *
874 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
875 * and its pixel format is 32bpp. Then the first cacheline is arranged
876 * thus:
877 *
878 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
879 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
880 *
881 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
882 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
883 *
884 * The hardware docs refer to this format with multiple terms. In
885 * Sandybridge, this is the only multisample format; so no term is used.
886 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
887 * Multisample Surface). Later hardware docs additionally refer to this
888 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
889 * color surfaces).
890 *
891 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
892 * Surface Behavior".
893 *
894 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
895 * Multisampled Surfaces".
896 */
897 ISL_MSAA_LAYOUT_INTERLEAVED,
898
899 /**
900 * @brief [IVB+] Array Multisample Format
901 *
902 * In this format, the surface's physical layout resembles that of a
903 * 2D array surface.
904 *
905 * Suppose the multisample surface's logical extent is (w, h) and its
906 * sample count is N. Then surface's physical extent is the same as
907 * a singlesample 2D surface whose logical extent is (w, h) and array
908 * length is N. Array slice `i` contains the pixel values for sample
909 * index `i`.
910 *
911 * The Ivybridge docs refer to surfaces in this format as UMS
912 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
913 * Surface). The Broadwell docs additionally refer to this format as
914 * MSFMT_MSS (MSS=Multisample Surface Storage).
915 *
916 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
917 * Multisample Surfaces".
918 *
919 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
920 * Multisample Surfaces".
921 */
922 ISL_MSAA_LAYOUT_ARRAY,
923 };
924
925
926 struct isl_device {
927 const struct gen_device_info *info;
928 bool use_separate_stencil;
929 bool has_bit6_swizzling;
930
931 /**
932 * Describes the layout of a RENDER_SURFACE_STATE structure for the
933 * current gen.
934 */
935 struct {
936 uint8_t size;
937 uint8_t align;
938 uint8_t addr_offset;
939 uint8_t aux_addr_offset;
940
941 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
942 uint8_t clear_value_size;
943 uint8_t clear_value_offset;
944 } ss;
945
946 /**
947 * Describes the layout of the depth/stencil/hiz commands as emitted by
948 * isl_emit_depth_stencil_hiz.
949 */
950 struct {
951 uint8_t size;
952 uint8_t depth_offset;
953 uint8_t stencil_offset;
954 uint8_t hiz_offset;
955 } ds;
956 };
957
958 struct isl_extent2d {
959 union { uint32_t w, width; };
960 union { uint32_t h, height; };
961 };
962
963 struct isl_extent3d {
964 union { uint32_t w, width; };
965 union { uint32_t h, height; };
966 union { uint32_t d, depth; };
967 };
968
969 struct isl_extent4d {
970 union { uint32_t w, width; };
971 union { uint32_t h, height; };
972 union { uint32_t d, depth; };
973 union { uint32_t a, array_len; };
974 };
975
976 struct isl_channel_layout {
977 enum isl_base_type type;
978 uint8_t bits; /**< Size in bits */
979 };
980
981 /**
982 * Each format has 3D block extent (width, height, depth). The block extent of
983 * compressed formats is that of the format's compression block. For example,
984 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
985 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
986 * is (w=1, h=1, d=1).
987 */
988 struct isl_format_layout {
989 enum isl_format format;
990 const char *name;
991
992 uint16_t bpb; /**< Bits per block */
993 uint8_t bw; /**< Block width, in pixels */
994 uint8_t bh; /**< Block height, in pixels */
995 uint8_t bd; /**< Block depth, in pixels */
996
997 struct {
998 struct isl_channel_layout r; /**< Red channel */
999 struct isl_channel_layout g; /**< Green channel */
1000 struct isl_channel_layout b; /**< Blue channel */
1001 struct isl_channel_layout a; /**< Alpha channel */
1002 struct isl_channel_layout l; /**< Luminance channel */
1003 struct isl_channel_layout i; /**< Intensity channel */
1004 struct isl_channel_layout p; /**< Palette channel */
1005 } channels;
1006
1007 enum isl_colorspace colorspace;
1008 enum isl_txc txc;
1009 };
1010
1011 struct isl_tile_info {
1012 enum isl_tiling tiling;
1013
1014 /* The size (in bits per block) of a single surface element
1015 *
1016 * For surfaces with power-of-two formats, this is the same as
1017 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1018 * The logical_extent_el field is in terms of elements of this size.
1019 *
1020 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1021 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1022 * of the tiling formats can actually hold an integer number of 96-bit
1023 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1024 * 32-bit element size. It is the responsibility of the caller to
1025 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1026 * the width of a surface in tiles, you would do:
1027 *
1028 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1029 * tile_info.logical_extent_el.width);
1030 */
1031 uint32_t format_bpb;
1032
1033 /** The logical size of the tile in units of format_bpb size elements
1034 *
1035 * This field determines how a given surface is cut up into tiles. It is
1036 * used to compute the size of a surface in tiles and can be used to
1037 * determine the location of the tile containing any given surface element.
1038 * The exact value of this field depends heavily on the bits-per-block of
1039 * the format being used.
1040 */
1041 struct isl_extent2d logical_extent_el;
1042
1043 /** The physical size of the tile in bytes and rows of bytes
1044 *
1045 * This field determines how the tiles of a surface are physically layed
1046 * out in memory. The logical and physical tile extent are frequently the
1047 * same but this is not always the case. For instance, a W-tile (which is
1048 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1049 * its physical size is 128B x 32rows, the same as a Y-tile.
1050 *
1051 * @see isl_surf::row_pitch
1052 */
1053 struct isl_extent2d phys_extent_B;
1054 };
1055
1056 /**
1057 * Metadata about a DRM format modifier.
1058 */
1059 struct isl_drm_modifier_info {
1060 uint64_t modifier;
1061
1062 /** Text name of the modifier */
1063 const char *name;
1064
1065 /** ISL tiling implied by this modifier */
1066 enum isl_tiling tiling;
1067
1068 /** ISL aux usage implied by this modifier */
1069 enum isl_aux_usage aux_usage;
1070
1071 /** Whether or not this modifier supports clear color */
1072 bool supports_clear_color;
1073 };
1074
1075 /**
1076 * @brief Input to surface initialization
1077 *
1078 * @invariant width >= 1
1079 * @invariant height >= 1
1080 * @invariant depth >= 1
1081 * @invariant levels >= 1
1082 * @invariant samples >= 1
1083 * @invariant array_len >= 1
1084 *
1085 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1086 * @invariant if 2D then depth == 1
1087 * @invariant if 3D then array_len == 1 and samples == 1
1088 */
1089 struct isl_surf_init_info {
1090 enum isl_surf_dim dim;
1091 enum isl_format format;
1092
1093 uint32_t width;
1094 uint32_t height;
1095 uint32_t depth;
1096 uint32_t levels;
1097 uint32_t array_len;
1098 uint32_t samples;
1099
1100 /** Lower bound for isl_surf::alignment, in bytes. */
1101 uint32_t min_alignment;
1102
1103 /**
1104 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1105 * will fail if this is misaligned or out of bounds.
1106 */
1107 uint32_t row_pitch;
1108
1109 isl_surf_usage_flags_t usage;
1110
1111 /** Flags that alter how ISL selects isl_surf::tiling. */
1112 isl_tiling_flags_t tiling_flags;
1113 };
1114
1115 struct isl_surf {
1116 enum isl_surf_dim dim;
1117 enum isl_dim_layout dim_layout;
1118 enum isl_msaa_layout msaa_layout;
1119 enum isl_tiling tiling;
1120 enum isl_format format;
1121
1122 /**
1123 * Alignment of the upper-left sample of each subimage, in units of surface
1124 * elements.
1125 */
1126 struct isl_extent3d image_alignment_el;
1127
1128 /**
1129 * Logical extent of the surface's base level, in units of pixels. This is
1130 * identical to the extent defined in isl_surf_init_info.
1131 */
1132 struct isl_extent4d logical_level0_px;
1133
1134 /**
1135 * Physical extent of the surface's base level, in units of physical
1136 * surface samples and aligned to the format's compression block.
1137 *
1138 * Consider isl_dim_layout as an operator that transforms a logical surface
1139 * layout to a physical surface layout. Then
1140 *
1141 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1142 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1143 */
1144 struct isl_extent4d phys_level0_sa;
1145
1146 uint32_t levels;
1147 uint32_t samples;
1148
1149 /** Total size of the surface, in bytes. */
1150 uint64_t size;
1151
1152 /** Required alignment for the surface's base address. */
1153 uint32_t alignment;
1154
1155 /**
1156 * The interpretation of this field depends on the value of
1157 * isl_tile_info::physical_extent_B. In particular, the width of the
1158 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
1159 * and the distance in bytes between vertically adjacent tiles in the image
1160 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
1161 *
1162 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1163 * this cleanly reduces to being the distance, in bytes, between vertically
1164 * adjacent surface elements.
1165 *
1166 * @see isl_tile_info::phys_extent_B;
1167 */
1168 uint32_t row_pitch;
1169
1170 /**
1171 * Pitch between physical array slices, in rows of surface elements.
1172 */
1173 uint32_t array_pitch_el_rows;
1174
1175 enum isl_array_pitch_span array_pitch_span;
1176
1177 /** Copy of isl_surf_init_info::usage. */
1178 isl_surf_usage_flags_t usage;
1179 };
1180
1181 struct isl_swizzle {
1182 enum isl_channel_select r:4;
1183 enum isl_channel_select g:4;
1184 enum isl_channel_select b:4;
1185 enum isl_channel_select a:4;
1186 };
1187
1188 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1189 .r = ISL_CHANNEL_SELECT_##R, \
1190 .g = ISL_CHANNEL_SELECT_##G, \
1191 .b = ISL_CHANNEL_SELECT_##B, \
1192 .a = ISL_CHANNEL_SELECT_##A, \
1193 })
1194
1195 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1196
1197 struct isl_view {
1198 /**
1199 * Indicates the usage of the particular view
1200 *
1201 * Normally, this is one bit. However, for a cube map texture, it
1202 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1203 */
1204 isl_surf_usage_flags_t usage;
1205
1206 /**
1207 * The format to use in the view
1208 *
1209 * This may differ from the format of the actual isl_surf but must have
1210 * the same block size.
1211 */
1212 enum isl_format format;
1213
1214 uint32_t base_level;
1215 uint32_t levels;
1216
1217 /**
1218 * Base array layer
1219 *
1220 * For cube maps, both base_array_layer and array_len should be
1221 * specified in terms of 2-D layers and must be a multiple of 6.
1222 *
1223 * 3-D textures are effectively treated as 2-D arrays when used as a
1224 * storage image or render target. If `usage` contains
1225 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1226 * base_array_layer and array_len are applied. If the surface is only used
1227 * for texturing, they are ignored.
1228 */
1229 uint32_t base_array_layer;
1230
1231 /**
1232 * Array Length
1233 *
1234 * Indicates the number of array elements starting at Base Array Layer.
1235 */
1236 uint32_t array_len;
1237
1238 struct isl_swizzle swizzle;
1239 };
1240
1241 union isl_color_value {
1242 float f32[4];
1243 uint32_t u32[4];
1244 int32_t i32[4];
1245 };
1246
1247 struct isl_surf_fill_state_info {
1248 const struct isl_surf *surf;
1249 const struct isl_view *view;
1250
1251 /**
1252 * The address of the surface in GPU memory.
1253 */
1254 uint64_t address;
1255
1256 /**
1257 * The Memory Object Control state for the filled surface state.
1258 *
1259 * The exact format of this value depends on hardware generation.
1260 */
1261 uint32_t mocs;
1262
1263 /**
1264 * The auxilary surface or NULL if no auxilary surface is to be used.
1265 */
1266 const struct isl_surf *aux_surf;
1267 enum isl_aux_usage aux_usage;
1268 uint64_t aux_address;
1269
1270 /**
1271 * The clear color for this surface
1272 *
1273 * Valid values depend on hardware generation.
1274 */
1275 union isl_color_value clear_color;
1276
1277 /**
1278 * Surface write disables for gen4-5
1279 */
1280 isl_channel_mask_t write_disables;
1281
1282 /* Intra-tile offset */
1283 uint16_t x_offset_sa, y_offset_sa;
1284 };
1285
1286 struct isl_buffer_fill_state_info {
1287 /**
1288 * The address of the surface in GPU memory.
1289 */
1290 uint64_t address;
1291
1292 /**
1293 * The size of the buffer
1294 */
1295 uint64_t size;
1296
1297 /**
1298 * The Memory Object Control state for the filled surface state.
1299 *
1300 * The exact format of this value depends on hardware generation.
1301 */
1302 uint32_t mocs;
1303
1304 /**
1305 * The format to use in the surface state
1306 *
1307 * This may differ from the format of the actual isl_surf but have the
1308 * same block size.
1309 */
1310 enum isl_format format;
1311
1312 uint32_t stride;
1313 };
1314
1315 struct isl_depth_stencil_hiz_emit_info {
1316 /**
1317 * The depth surface
1318 */
1319 const struct isl_surf *depth_surf;
1320
1321 /**
1322 * The stencil surface
1323 *
1324 * If separate stencil is not available, this must point to the same
1325 * isl_surf as depth_surf.
1326 */
1327 const struct isl_surf *stencil_surf;
1328
1329 /**
1330 * The view into the depth and stencil surfaces.
1331 *
1332 * This view applies to both surfaces simultaneously.
1333 */
1334 const struct isl_view *view;
1335
1336 /**
1337 * The address of the depth surface in GPU memory
1338 */
1339 uint64_t depth_address;
1340
1341 /**
1342 * The address of the stencil surface in GPU memory
1343 *
1344 * If separate stencil is not available, this must have the same value as
1345 * depth_address.
1346 */
1347 uint64_t stencil_address;
1348
1349 /**
1350 * The Memory Object Control state for depth and stencil buffers
1351 *
1352 * Both depth and stencil will get the same MOCS value. The exact format
1353 * of this value depends on hardware generation.
1354 */
1355 uint32_t mocs;
1356
1357 /**
1358 * The HiZ surface or NULL if HiZ is disabled.
1359 */
1360 const struct isl_surf *hiz_surf;
1361 enum isl_aux_usage hiz_usage;
1362 uint64_t hiz_address;
1363
1364 /**
1365 * The depth clear value
1366 */
1367 float depth_clear_value;
1368 };
1369
1370 extern const struct isl_format_layout isl_format_layouts[];
1371
1372 void
1373 isl_device_init(struct isl_device *dev,
1374 const struct gen_device_info *info,
1375 bool has_bit6_swizzling);
1376
1377 isl_sample_count_mask_t ATTRIBUTE_CONST
1378 isl_device_get_sample_counts(struct isl_device *dev);
1379
1380 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1381 isl_format_get_layout(enum isl_format fmt)
1382 {
1383 return &isl_format_layouts[fmt];
1384 }
1385
1386 static inline const char * ATTRIBUTE_CONST
1387 isl_format_get_name(enum isl_format fmt)
1388 {
1389 return isl_format_layouts[fmt].name;
1390 }
1391
1392 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1393 enum isl_format format);
1394 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1395 enum isl_format format);
1396 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1397 enum isl_format format);
1398 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1399 enum isl_format format);
1400 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1401 enum isl_format format);
1402 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1403 enum isl_format format);
1404 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1405 enum isl_format format);
1406 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1407 enum isl_format format);
1408 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1409 enum isl_format format);
1410 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1411 enum isl_format format);
1412
1413 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1414 enum isl_format format1,
1415 enum isl_format format2);
1416
1417 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1418 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1419 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1420 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1421 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1422 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1423
1424 static inline bool
1425 isl_format_has_normalized_channel(enum isl_format fmt)
1426 {
1427 return isl_format_has_unorm_channel(fmt) ||
1428 isl_format_has_snorm_channel(fmt);
1429 }
1430
1431 static inline bool
1432 isl_format_has_float_channel(enum isl_format fmt)
1433 {
1434 return isl_format_has_ufloat_channel(fmt) ||
1435 isl_format_has_sfloat_channel(fmt);
1436 }
1437
1438 static inline bool
1439 isl_format_has_int_channel(enum isl_format fmt)
1440 {
1441 return isl_format_has_uint_channel(fmt) ||
1442 isl_format_has_sint_channel(fmt);
1443 }
1444
1445 unsigned isl_format_get_num_channels(enum isl_format fmt);
1446
1447 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1448
1449 static inline bool
1450 isl_format_is_compressed(enum isl_format fmt)
1451 {
1452 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1453
1454 return fmtl->txc != ISL_TXC_NONE;
1455 }
1456
1457 static inline bool
1458 isl_format_has_bc_compression(enum isl_format fmt)
1459 {
1460 switch (isl_format_get_layout(fmt)->txc) {
1461 case ISL_TXC_DXT1:
1462 case ISL_TXC_DXT3:
1463 case ISL_TXC_DXT5:
1464 return true;
1465 case ISL_TXC_NONE:
1466 case ISL_TXC_FXT1:
1467 case ISL_TXC_RGTC1:
1468 case ISL_TXC_RGTC2:
1469 case ISL_TXC_BPTC:
1470 case ISL_TXC_ETC1:
1471 case ISL_TXC_ETC2:
1472 case ISL_TXC_ASTC:
1473 return false;
1474
1475 case ISL_TXC_HIZ:
1476 case ISL_TXC_MCS:
1477 case ISL_TXC_CCS:
1478 unreachable("Should not be called on an aux surface");
1479 }
1480
1481 unreachable("bad texture compression mode");
1482 return false;
1483 }
1484
1485 static inline bool
1486 isl_format_is_yuv(enum isl_format fmt)
1487 {
1488 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1489
1490 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1491 }
1492
1493 static inline bool
1494 isl_format_block_is_1x1x1(enum isl_format fmt)
1495 {
1496 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1497
1498 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1499 }
1500
1501 static inline bool
1502 isl_format_is_srgb(enum isl_format fmt)
1503 {
1504 return isl_format_layouts[fmt].colorspace == ISL_COLORSPACE_SRGB;
1505 }
1506
1507 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1508
1509 static inline bool
1510 isl_format_is_rgb(enum isl_format fmt)
1511 {
1512 return isl_format_layouts[fmt].channels.r.bits > 0 &&
1513 isl_format_layouts[fmt].channels.g.bits > 0 &&
1514 isl_format_layouts[fmt].channels.b.bits > 0 &&
1515 isl_format_layouts[fmt].channels.a.bits == 0;
1516 }
1517
1518 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1519 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1520
1521 bool isl_is_storage_image_format(enum isl_format fmt);
1522
1523 enum isl_format
1524 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1525 enum isl_format fmt);
1526
1527 /* Returns true if this hardware supports typed load/store on a format with
1528 * the same size as the given format.
1529 */
1530 bool
1531 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1532 enum isl_format fmt);
1533
1534 static inline bool
1535 isl_tiling_is_any_y(enum isl_tiling tiling)
1536 {
1537 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1538 }
1539
1540 static inline bool
1541 isl_tiling_is_std_y(enum isl_tiling tiling)
1542 {
1543 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1544 }
1545
1546 uint32_t
1547 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1548
1549 enum isl_tiling
1550 isl_tiling_from_i915_tiling(uint32_t tiling);
1551
1552 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1553 isl_drm_modifier_get_info(uint64_t modifier);
1554
1555 static inline bool
1556 isl_drm_modifier_has_aux(uint64_t modifier)
1557 {
1558 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1559 }
1560
1561 struct isl_extent2d ATTRIBUTE_CONST
1562 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1563
1564 static inline bool
1565 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1566 {
1567 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1568 }
1569
1570 static inline bool
1571 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1572 {
1573 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1574 }
1575
1576 static inline bool
1577 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1578 {
1579 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1580 }
1581
1582 static inline bool
1583 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1584 {
1585 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1586 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1587 }
1588
1589 static inline bool
1590 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1591 {
1592 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1593 }
1594
1595 static inline bool
1596 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1597 {
1598 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1599 (info->format == ISL_FORMAT_R16_UNORM);
1600 }
1601
1602 static inline bool
1603 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1604 {
1605 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1606 (info->format == ISL_FORMAT_R32_FLOAT);
1607 }
1608
1609 static inline struct isl_extent2d
1610 isl_extent2d(uint32_t width, uint32_t height)
1611 {
1612 struct isl_extent2d e = { { 0 } };
1613
1614 e.width = width;
1615 e.height = height;
1616
1617 return e;
1618 }
1619
1620 static inline struct isl_extent3d
1621 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1622 {
1623 struct isl_extent3d e = { { 0 } };
1624
1625 e.width = width;
1626 e.height = height;
1627 e.depth = depth;
1628
1629 return e;
1630 }
1631
1632 static inline struct isl_extent4d
1633 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1634 uint32_t array_len)
1635 {
1636 struct isl_extent4d e = { { 0 } };
1637
1638 e.width = width;
1639 e.height = height;
1640 e.depth = depth;
1641 e.array_len = array_len;
1642
1643 return e;
1644 }
1645
1646 bool isl_color_value_is_zero_one(union isl_color_value value,
1647 enum isl_format format);
1648
1649 #define isl_surf_init(dev, surf, ...) \
1650 isl_surf_init_s((dev), (surf), \
1651 &(struct isl_surf_init_info) { __VA_ARGS__ });
1652
1653 bool
1654 isl_surf_init_s(const struct isl_device *dev,
1655 struct isl_surf *surf,
1656 const struct isl_surf_init_info *restrict info);
1657
1658 void
1659 isl_surf_get_tile_info(const struct isl_surf *surf,
1660 struct isl_tile_info *tile_info);
1661
1662 bool
1663 isl_surf_get_hiz_surf(const struct isl_device *dev,
1664 const struct isl_surf *surf,
1665 struct isl_surf *hiz_surf);
1666
1667 bool
1668 isl_surf_get_mcs_surf(const struct isl_device *dev,
1669 const struct isl_surf *surf,
1670 struct isl_surf *mcs_surf);
1671
1672 bool
1673 isl_surf_get_ccs_surf(const struct isl_device *dev,
1674 const struct isl_surf *surf,
1675 struct isl_surf *ccs_surf,
1676 uint32_t row_pitch /**< Ignored if 0 */);
1677
1678 #define isl_surf_fill_state(dev, state, ...) \
1679 isl_surf_fill_state_s((dev), (state), \
1680 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1681
1682 void
1683 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1684 const struct isl_surf_fill_state_info *restrict info);
1685
1686 #define isl_buffer_fill_state(dev, state, ...) \
1687 isl_buffer_fill_state_s((dev), (state), \
1688 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1689
1690 void
1691 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1692 const struct isl_buffer_fill_state_info *restrict info);
1693
1694 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1695 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1696 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1697
1698 void
1699 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
1700 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1701
1702 void
1703 isl_surf_fill_image_param(const struct isl_device *dev,
1704 struct brw_image_param *param,
1705 const struct isl_surf *surf,
1706 const struct isl_view *view);
1707
1708 void
1709 isl_buffer_fill_image_param(const struct isl_device *dev,
1710 struct brw_image_param *param,
1711 enum isl_format format,
1712 uint64_t size);
1713
1714 /**
1715 * Alignment of the upper-left sample of each subimage, in units of surface
1716 * elements.
1717 */
1718 static inline struct isl_extent3d
1719 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1720 {
1721 return surf->image_alignment_el;
1722 }
1723
1724 /**
1725 * Alignment of the upper-left sample of each subimage, in units of surface
1726 * samples.
1727 */
1728 static inline struct isl_extent3d
1729 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1730 {
1731 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1732
1733 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1734 fmtl->bh * surf->image_alignment_el.h,
1735 fmtl->bd * surf->image_alignment_el.d);
1736 }
1737
1738 /**
1739 * Pitch between vertically adjacent surface elements, in bytes.
1740 */
1741 static inline uint32_t
1742 isl_surf_get_row_pitch(const struct isl_surf *surf)
1743 {
1744 return surf->row_pitch;
1745 }
1746
1747 /**
1748 * Pitch between vertically adjacent surface elements, in units of surface elements.
1749 */
1750 static inline uint32_t
1751 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1752 {
1753 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1754
1755 assert(surf->row_pitch % (fmtl->bpb / 8) == 0);
1756 return surf->row_pitch / (fmtl->bpb / 8);
1757 }
1758
1759 /**
1760 * Pitch between physical array slices, in rows of surface elements.
1761 */
1762 static inline uint32_t
1763 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1764 {
1765 return surf->array_pitch_el_rows;
1766 }
1767
1768 /**
1769 * Pitch between physical array slices, in units of surface elements.
1770 */
1771 static inline uint32_t
1772 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1773 {
1774 return isl_surf_get_array_pitch_el_rows(surf) *
1775 isl_surf_get_row_pitch_el(surf);
1776 }
1777
1778 /**
1779 * Pitch between physical array slices, in rows of surface samples.
1780 */
1781 static inline uint32_t
1782 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1783 {
1784 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1785 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1786 }
1787
1788 /**
1789 * Pitch between physical array slices, in bytes.
1790 */
1791 static inline uint32_t
1792 isl_surf_get_array_pitch(const struct isl_surf *surf)
1793 {
1794 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch;
1795 }
1796
1797 /**
1798 * Calculate the offset, in units of surface samples, to a subimage in the
1799 * surface.
1800 *
1801 * @invariant level < surface levels
1802 * @invariant logical_array_layer < logical array length of surface
1803 * @invariant logical_z_offset_px < logical depth of surface at level
1804 */
1805 void
1806 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1807 uint32_t level,
1808 uint32_t logical_array_layer,
1809 uint32_t logical_z_offset_px,
1810 uint32_t *x_offset_sa,
1811 uint32_t *y_offset_sa);
1812
1813 /**
1814 * Calculate the offset, in units of surface elements, to a subimage in the
1815 * surface.
1816 *
1817 * @invariant level < surface levels
1818 * @invariant logical_array_layer < logical array length of surface
1819 * @invariant logical_z_offset_px < logical depth of surface at level
1820 */
1821 void
1822 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1823 uint32_t level,
1824 uint32_t logical_array_layer,
1825 uint32_t logical_z_offset_px,
1826 uint32_t *x_offset_el,
1827 uint32_t *y_offset_el);
1828
1829 /**
1830 * Calculate the offset, in bytes and intratile surface samples, to a
1831 * subimage in the surface.
1832 *
1833 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
1834 * result to isl_tiling_get_intratile_offset_el, and converting the tile
1835 * offsets to samples.
1836 *
1837 * @invariant level < surface levels
1838 * @invariant logical_array_layer < logical array length of surface
1839 * @invariant logical_z_offset_px < logical depth of surface at level
1840 */
1841 void
1842 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
1843 uint32_t level,
1844 uint32_t logical_array_layer,
1845 uint32_t logical_z_offset_px,
1846 uint32_t *offset_B,
1847 uint32_t *x_offset_sa,
1848 uint32_t *y_offset_sa);
1849
1850 /**
1851 * Create an isl_surf that represents a particular subimage in the surface.
1852 *
1853 * The newly created surface will have a single miplevel and array slice. The
1854 * surface lives at the returned byte and intratile offsets, in samples.
1855 *
1856 * It is safe to call this function with surf == image_surf.
1857 *
1858 * @invariant level < surface levels
1859 * @invariant logical_array_layer < logical array length of surface
1860 * @invariant logical_z_offset_px < logical depth of surface at level
1861 */
1862 void
1863 isl_surf_get_image_surf(const struct isl_device *dev,
1864 const struct isl_surf *surf,
1865 uint32_t level,
1866 uint32_t logical_array_layer,
1867 uint32_t logical_z_offset_px,
1868 struct isl_surf *image_surf,
1869 uint32_t *offset_B,
1870 uint32_t *x_offset_sa,
1871 uint32_t *y_offset_sa);
1872
1873 /**
1874 * @brief Calculate the intratile offsets to a surface.
1875 *
1876 * In @a base_address_offset return the offset from the base of the surface to
1877 * the base address of the first tile of the subimage. In @a x_offset_B and
1878 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1879 * tile's base to the subimage's first surface element. The x and y offsets
1880 * are intratile offsets; that is, they do not exceed the boundary of the
1881 * surface's tiling format.
1882 */
1883 void
1884 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
1885 uint32_t bpb,
1886 uint32_t row_pitch,
1887 uint32_t total_x_offset_el,
1888 uint32_t total_y_offset_el,
1889 uint32_t *base_address_offset,
1890 uint32_t *x_offset_el,
1891 uint32_t *y_offset_el);
1892
1893 static inline void
1894 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
1895 enum isl_format format,
1896 uint32_t row_pitch,
1897 uint32_t total_x_offset_sa,
1898 uint32_t total_y_offset_sa,
1899 uint32_t *base_address_offset,
1900 uint32_t *x_offset_sa,
1901 uint32_t *y_offset_sa)
1902 {
1903 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
1904
1905 /* For computing the intratile offsets, we actually want a strange unit
1906 * which is samples for multisampled surfaces but elements for compressed
1907 * surfaces.
1908 */
1909 assert(total_x_offset_sa % fmtl->bw == 0);
1910 assert(total_y_offset_sa % fmtl->bh == 0);
1911 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
1912 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
1913
1914 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch,
1915 total_x_offset, total_y_offset,
1916 base_address_offset,
1917 x_offset_sa, y_offset_sa);
1918 *x_offset_sa *= fmtl->bw;
1919 *y_offset_sa *= fmtl->bh;
1920 }
1921
1922 /**
1923 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1924 *
1925 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1926 * @pre surf->format must be a valid format for depth surfaces
1927 */
1928 uint32_t
1929 isl_surf_get_depth_format(const struct isl_device *dev,
1930 const struct isl_surf *surf);
1931
1932 #ifdef __cplusplus
1933 }
1934 #endif
1935
1936 #endif /* ISL_H */