2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
45 #include "c99_compat.h"
46 #include "util/macros.h"
52 struct gen_device_info
;
53 struct brw_image_param
;
57 * @brief Get the hardware generation of isl_device.
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
73 #ifndef ISL_DEV_IS_HASWELL
75 * @brief Get the hardware generation of isl_device.
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 * Hardware enumeration SURFACE_FORMAT.
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
106 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
107 ISL_FORMAT_R32G32B32A32_SINT
= 1,
108 ISL_FORMAT_R32G32B32A32_UINT
= 2,
109 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
110 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
111 ISL_FORMAT_R64G64_FLOAT
= 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
114 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
116 ISL_FORMAT_R64G64_PASSTHRU
= 33,
117 ISL_FORMAT_R32G32B32_FLOAT
= 64,
118 ISL_FORMAT_R32G32B32_SINT
= 65,
119 ISL_FORMAT_R32G32B32_UINT
= 66,
120 ISL_FORMAT_R32G32B32_UNORM
= 67,
121 ISL_FORMAT_R32G32B32_SNORM
= 68,
122 ISL_FORMAT_R32G32B32_SSCALED
= 69,
123 ISL_FORMAT_R32G32B32_USCALED
= 70,
124 ISL_FORMAT_R32G32B32_SFIXED
= 80,
125 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
126 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
127 ISL_FORMAT_R16G16B16A16_SINT
= 130,
128 ISL_FORMAT_R16G16B16A16_UINT
= 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
130 ISL_FORMAT_R32G32_FLOAT
= 133,
131 ISL_FORMAT_R32G32_SINT
= 134,
132 ISL_FORMAT_R32G32_UINT
= 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
135 ISL_FORMAT_L32A32_FLOAT
= 138,
136 ISL_FORMAT_R32G32_UNORM
= 139,
137 ISL_FORMAT_R32G32_SNORM
= 140,
138 ISL_FORMAT_R64_FLOAT
= 141,
139 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
141 ISL_FORMAT_A32X32_FLOAT
= 144,
142 ISL_FORMAT_L32X32_FLOAT
= 145,
143 ISL_FORMAT_I32X32_FLOAT
= 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
145 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
146 ISL_FORMAT_R32G32_SSCALED
= 149,
147 ISL_FORMAT_R32G32_USCALED
= 150,
148 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
149 ISL_FORMAT_R32G32_SFIXED
= 160,
150 ISL_FORMAT_R64_PASSTHRU
= 161,
151 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
153 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
155 ISL_FORMAT_R10G10B10A2_UINT
= 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
157 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
159 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
160 ISL_FORMAT_R8G8B8A8_SINT
= 202,
161 ISL_FORMAT_R8G8B8A8_UINT
= 203,
162 ISL_FORMAT_R16G16_UNORM
= 204,
163 ISL_FORMAT_R16G16_SNORM
= 205,
164 ISL_FORMAT_R16G16_SINT
= 206,
165 ISL_FORMAT_R16G16_UINT
= 207,
166 ISL_FORMAT_R16G16_FLOAT
= 208,
167 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
169 ISL_FORMAT_R11G11B10_FLOAT
= 211,
170 ISL_FORMAT_R32_SINT
= 214,
171 ISL_FORMAT_R32_UINT
= 215,
172 ISL_FORMAT_R32_FLOAT
= 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
175 ISL_FORMAT_L32_UNORM
= 221,
176 ISL_FORMAT_A32_UNORM
= 222,
177 ISL_FORMAT_L16A16_UNORM
= 223,
178 ISL_FORMAT_I24X8_UNORM
= 224,
179 ISL_FORMAT_L24X8_UNORM
= 225,
180 ISL_FORMAT_A24X8_UNORM
= 226,
181 ISL_FORMAT_I32_FLOAT
= 227,
182 ISL_FORMAT_L32_FLOAT
= 228,
183 ISL_FORMAT_A32_FLOAT
= 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
187 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
189 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
192 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
193 ISL_FORMAT_L16A16_FLOAT
= 240,
194 ISL_FORMAT_R32_UNORM
= 241,
195 ISL_FORMAT_R32_SNORM
= 242,
196 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
198 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
199 ISL_FORMAT_R16G16_SSCALED
= 246,
200 ISL_FORMAT_R16G16_USCALED
= 247,
201 ISL_FORMAT_R32_SSCALED
= 248,
202 ISL_FORMAT_R32_USCALED
= 249,
203 ISL_FORMAT_B5G6R5_UNORM
= 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
205 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
207 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
209 ISL_FORMAT_R8G8_UNORM
= 262,
210 ISL_FORMAT_R8G8_SNORM
= 263,
211 ISL_FORMAT_R8G8_SINT
= 264,
212 ISL_FORMAT_R8G8_UINT
= 265,
213 ISL_FORMAT_R16_UNORM
= 266,
214 ISL_FORMAT_R16_SNORM
= 267,
215 ISL_FORMAT_R16_SINT
= 268,
216 ISL_FORMAT_R16_UINT
= 269,
217 ISL_FORMAT_R16_FLOAT
= 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
220 ISL_FORMAT_I16_UNORM
= 273,
221 ISL_FORMAT_L16_UNORM
= 274,
222 ISL_FORMAT_A16_UNORM
= 275,
223 ISL_FORMAT_L8A8_UNORM
= 276,
224 ISL_FORMAT_I16_FLOAT
= 277,
225 ISL_FORMAT_L16_FLOAT
= 278,
226 ISL_FORMAT_A16_FLOAT
= 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
229 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
231 ISL_FORMAT_R8G8_SSCALED
= 284,
232 ISL_FORMAT_R8G8_USCALED
= 285,
233 ISL_FORMAT_R16_SSCALED
= 286,
234 ISL_FORMAT_R16_USCALED
= 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
237 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
238 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
239 ISL_FORMAT_L8A8_UINT
= 294,
240 ISL_FORMAT_L8A8_SINT
= 295,
241 ISL_FORMAT_R8_UNORM
= 320,
242 ISL_FORMAT_R8_SNORM
= 321,
243 ISL_FORMAT_R8_SINT
= 322,
244 ISL_FORMAT_R8_UINT
= 323,
245 ISL_FORMAT_A8_UNORM
= 324,
246 ISL_FORMAT_I8_UNORM
= 325,
247 ISL_FORMAT_L8_UNORM
= 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
250 ISL_FORMAT_R8_SSCALED
= 329,
251 ISL_FORMAT_R8_USCALED
= 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
253 ISL_FORMAT_L8_UNORM_SRGB
= 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
257 ISL_FORMAT_Y8_UNORM
= 336,
258 ISL_FORMAT_L8_UINT
= 338,
259 ISL_FORMAT_L8_SINT
= 339,
260 ISL_FORMAT_I8_UINT
= 340,
261 ISL_FORMAT_I8_SINT
= 341,
262 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
263 ISL_FORMAT_R1_UNORM
= 385,
264 ISL_FORMAT_YCRCB_NORMAL
= 386,
265 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
268 ISL_FORMAT_BC1_UNORM
= 390,
269 ISL_FORMAT_BC2_UNORM
= 391,
270 ISL_FORMAT_BC3_UNORM
= 392,
271 ISL_FORMAT_BC4_UNORM
= 393,
272 ISL_FORMAT_BC5_UNORM
= 394,
273 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
274 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
275 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
276 ISL_FORMAT_MONO8
= 398,
277 ISL_FORMAT_YCRCB_SWAPUV
= 399,
278 ISL_FORMAT_YCRCB_SWAPY
= 400,
279 ISL_FORMAT_DXT1_RGB
= 401,
280 ISL_FORMAT_FXT1
= 402,
281 ISL_FORMAT_R8G8B8_UNORM
= 403,
282 ISL_FORMAT_R8G8B8_SNORM
= 404,
283 ISL_FORMAT_R8G8B8_SSCALED
= 405,
284 ISL_FORMAT_R8G8B8_USCALED
= 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
286 ISL_FORMAT_R64G64B64_FLOAT
= 408,
287 ISL_FORMAT_BC4_SNORM
= 409,
288 ISL_FORMAT_BC5_SNORM
= 410,
289 ISL_FORMAT_R16G16B16_FLOAT
= 411,
290 ISL_FORMAT_R16G16B16_UNORM
= 412,
291 ISL_FORMAT_R16G16B16_SNORM
= 413,
292 ISL_FORMAT_R16G16B16_SSCALED
= 414,
293 ISL_FORMAT_R16G16B16_USCALED
= 415,
294 ISL_FORMAT_BC6H_SF16
= 417,
295 ISL_FORMAT_BC7_UNORM
= 418,
296 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
297 ISL_FORMAT_BC6H_UF16
= 420,
298 ISL_FORMAT_PLANAR_420_8
= 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
300 ISL_FORMAT_ETC1_RGB8
= 425,
301 ISL_FORMAT_ETC2_RGB8
= 426,
302 ISL_FORMAT_EAC_R11
= 427,
303 ISL_FORMAT_EAC_RG11
= 428,
304 ISL_FORMAT_EAC_SIGNED_R11
= 429,
305 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
306 ISL_FORMAT_ETC2_SRGB8
= 431,
307 ISL_FORMAT_R16G16B16_UINT
= 432,
308 ISL_FORMAT_R16G16B16_SINT
= 433,
309 ISL_FORMAT_R32_SFIXED
= 434,
310 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
311 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
313 ISL_FORMAT_R10G10B10A2_SINT
= 438,
314 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
315 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
317 ISL_FORMAT_B10G10R10A2_UINT
= 442,
318 ISL_FORMAT_B10G10R10A2_SINT
= 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
321 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
325 ISL_FORMAT_R8G8B8_UINT
= 456,
326 ISL_FORMAT_R8G8B8_SINT
= 457,
327 ISL_FORMAT_RAW
= 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16
= 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16
= 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16
= 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16
= 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16
= 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16
= 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16
= 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16
= 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16
= 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16
= 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16
= 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16
= 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16
= 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16
= 895,
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
376 /* Formats for auxiliary surfaces */
382 ISL_FORMAT_GEN7_CCS_32BPP_X
,
383 ISL_FORMAT_GEN7_CCS_64BPP_X
,
384 ISL_FORMAT_GEN7_CCS_128BPP_X
,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
388 ISL_FORMAT_GEN9_CCS_32BPP
,
389 ISL_FORMAT_GEN9_CCS_64BPP
,
390 ISL_FORMAT_GEN9_CCS_128BPP
,
392 /* Hardware doesn't understand this out-of-band value */
393 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
397 * Numerical base type for channels of isl_format.
415 * Colorspace of isl_format.
417 enum isl_colorspace
{
418 ISL_COLORSPACE_NONE
= 0,
419 ISL_COLORSPACE_LINEAR
,
425 * Texture compression mode of isl_format.
440 /* Used for auxiliary surface formats */
447 * @brief Hardware tile mode
449 * WARNING: These values differ from the hardware enum values, which are
450 * unstable across hardware generations.
452 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
453 * clearly distinguish it from Yf and Ys.
456 ISL_TILING_LINEAR
= 0,
459 ISL_TILING_Y0
, /**< Legacy Y tiling */
460 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
461 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
462 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
463 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
467 * @defgroup Tiling Flags
470 typedef uint32_t isl_tiling_flags_t
;
471 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
472 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
473 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
474 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
475 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
476 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
477 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
478 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
479 #define ISL_TILING_ANY_MASK (~0u)
480 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
482 /** Any Y tiling, including legacy Y tiling. */
483 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
484 ISL_TILING_Yf_BIT | \
487 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
488 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
493 * @brief Logical dimension of surface.
495 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
496 * as 2D array surfaces.
505 * @brief Physical layout of the surface's dimensions.
507 enum isl_dim_layout
{
509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
510 * 6.17.3: 2D Surfaces.
512 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
513 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
515 * One-dimensional surfaces are identical to 2D surfaces with height of
518 * @invariant isl_surf::phys_level0_sa::depth == 1
520 ISL_DIM_LAYOUT_GEN4_2D
,
523 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
524 * 6.17.5: 3D Surfaces.
526 * @invariant isl_surf::phys_level0_sa::array_len == 1
528 ISL_DIM_LAYOUT_GEN4_3D
,
531 * Special layout used for HiZ and stencil on Sandy Bridge to work around
532 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
533 * work the same as on gen7+ except that they don't technically support
534 * mipmapping. That does not, however, stop us from doing it. As far as
535 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
536 * single miplevel 2D (possibly array) image. The dimensions of that image
539 * In order to implement HiZ and stencil on Sandy Bridge, we create one
540 * full-sized 2D (possibly array) image for every LOD with every image
541 * aligned to a page boundary. When the surface is used with the stencil
542 * or HiZ hardware, we manually offset to the image for the given LOD.
544 * As a memory saving measure, we pretend that the width of each miplevel
545 * is minified and we place LOD1 and above below LOD0 but horizontally
546 * adjacent to each other. When considered as full-sized images, LOD1 and
547 * above technically overlap. However, since we only write to part of that
548 * image, the hardware will never notice the overlap.
550 * This layout looks something like this:
568 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
,
571 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
572 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
574 ISL_DIM_LAYOUT_GEN9_1D
,
578 /** No Auxiliary surface is used */
581 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
584 /** The auxiliary surface is an MCS
586 * @invariant isl_surf::samples > 1
590 /** The auxiliary surface is a fast-clear-only compression surface
592 * @invariant isl_surf::samples == 1
596 /** The auxiliary surface provides full lossless color compression
598 * @invariant isl_surf::samples == 1
604 * Enum for keeping track of the state an auxiliary compressed surface.
606 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
607 * given slice (lod + array layer) can be in one of the six states described
608 * by this enum. Draw and resolve operations may cause the slice to change
609 * from one state to another. The six valid states are:
611 * 1) Clear: In this state, each block in the auxiliary surface contains a
612 * magic value that indicates that the block is in the clear state. If
613 * a block is in the clear state, it's values in the primary surface are
614 * ignored and the color of the samples in the block is taken either the
615 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
616 * depth. Since neither the primary surface nor the auxiliary surface
617 * contains the clear value, the surface can be cleared to a different
618 * color by simply changing the clear color without modifying either
621 * 2) Compressed w/ Clear: In this state, neither the auxiliary surface
622 * nor the primary surface has a complete representation of the data.
623 * Instead, both surfaces must be used together or else rendering
624 * corruption may occur. Depending on the auxiliary compression format
625 * and the data, any given block in the primary surface may contain all,
626 * some, or none of the data required to reconstruct the actual sample
627 * values. Blocks may also be in the clear state (see Clear) and have
628 * their value taken from outside the surface.
630 * 3) Compressed w/o Clear: This state is identical to the state above
631 * except that no blocks are in the clear state. In this state, all of
632 * the data required to reconstruct the final sample values is contained
633 * in the auxiliary and primary surface and the clear value is not
636 * 4) Resolved: In this state, the primary surface contains 100% of the
637 * data. The auxiliary surface is also valid so the surface can be
638 * validly used with or without aux enabled. The auxiliary surface may,
639 * however, contain non-trivial data and any update to the primary
640 * surface with aux disabled will cause the two to get out of sync.
642 * 5) Pass-through: In this state, the primary surface contains 100% of the
643 * data and every block in the auxiliary surface contains a magic value
644 * which indicates that the auxiliary surface should be ignored and the
645 * only the primary surface should be considered. Updating the primary
646 * surface without aux works fine and can be done repeatedly in this
647 * mode. Writing to a surface in pass-through mode with aux enabled may
648 * cause the auxiliary buffer to contain non-trivial data and no longer
649 * be in the pass-through state.
651 * 5) Aux Invalid: In this state, the primary surface contains 100% of the
652 * data and the auxiliary surface is completely bogus. Any attempt to
653 * use the auxiliary surface is liable to result in rendering
654 * corruption. The only thing that one can do to re-enable aux once
655 * this state is reached is to use an ambiguate pass to transition into
656 * the pass-through state.
658 * Drawing with or without aux enabled may implicitly cause the surface to
659 * transition between these states. There are also four types of auxiliary
660 * compression operations which cause an explicit transition:
662 * 1) Fast Clear: This operation writes the magic "clear" value to the
663 * auxiliary surface. This operation will safely transition any slice
664 * of a surface from any state to the clear state so long as the entire
665 * slice is fast cleared at once.
667 * 2) Full Resolve: This operation combines the auxiliary surface data
668 * with the primary surface data and writes the result to the primary.
669 * For HiZ, the docs call this a depth resolve. For CCS, the hardware
670 * full resolve operation does both a full resolve and an ambiguate so
671 * it actually takes you all the way to the pass-through state.
673 * 3) Partial Resolve: This operation considers blocks which are in the
674 * "clear" state and writes the clear value directly into the primary or
675 * auxiliary surface. Once this operation completes, the surface is
676 * still compressed but no longer references the clear color. This
677 * operation is only available for CCS.
679 * 4) Ambiguate: This operation throws away the current auxiliary data and
680 * replaces it with the magic pass-through value. If an ambiguate
681 * operation is performed when the primary surface does not contain 100%
682 * of the data, data will be lost. This operation is only implemented
683 * in hardware for depth where it is called a HiZ resolve.
685 * Not all operations are valid or useful in all states. The diagram below
686 * contains a complete description of the states and all valid and useful
687 * transitions except clear.
692 * | +-------------+ Draw w/ Aux +-------------+
693 * +------>| Compressed |<---------------------| Clear |
695 * +-------------+ +-------------+
698 * Resolve | | Full Resolve |
699 * | +----------------------------+ | Full
704 * | +-------------+ Full Resolve +-------------+
705 * +------>| Compressed |--------------------->| Resolved |
706 * | w/o Clear |<---------------------| |
707 * +-------------+ Draw w/ Aux +-------------+
710 * | w/ Aux | | w/o Aux
712 * | +----------------------------+ |
713 * Draw w/o Aux | | | Draw w/o Aux
714 * +----------+ | | | +----------+
716 * | +-------------+ Ambiguate +-------------+ |
717 * +------>| Pass- |<---------------------| Aux |<------+
718 * | through | | Invalid |
719 * +-------------+ +-------------+
722 * While the above general theory applies to all forms of auxiliary
723 * compression on Intel hardware, not all states and operations are available
724 * on all compression types. However, each of the auxiliary states and
725 * operations can be fairly easily mapped onto the above diagram:
727 * HiZ: Hierarchical depth compression is capable of being in any of the
728 * states above. Hardware provides three HiZ operations: "Depth
729 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
730 * Clear", "Full Resolve", and "Ambiguate" respectively. The
731 * hardware provides no HiZ partial resolve operation so the only way
732 * to get into the "Compressed w/o Clear" state is to render with HiZ
733 * when the surface is in the resolved or pass-through states.
735 * MCS: Multisample compression is technically capable of being in any of
736 * the states above except that most of them aren't useful. Both the
737 * render engine and the sampler support MCS compression and, apart
738 * from clear color, MCS is format-unaware so we leave the surface
739 * compressed 100% of the time. The hardware provides no MCS
742 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
743 * the simplest forms of compression since they don't do anything
744 * beyond clear color tracking. They really only support three of
745 * the six states: Clear, Compressed w/ Clear, and Pass-through. The
746 * only CCS_D operation is "Resolve" which maps to a full resolve
747 * followed by an ambiguate.
749 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
750 * is capable of being in almost all of the above states. THe only
751 * exception is that it does not have separate resolved and pass-
752 * through states. Instead, the CCS_E full resolve operation does
753 * both a resolve and an ambiguate so it goes directly into the
754 * pass-through state. CCS_E also provides fast clear and partial
755 * resolve operations which work as described above.
757 * While it is technically possible to perform a CCS_E ambiguate, it
758 * is not provided by Sky Lake hardware so we choose to avoid the aux
759 * invalid state. If the aux invalid state were determined to be
760 * useful, a CCS ambiguate could be done by carefully rendering to
761 * the CCS and filling it with zeros.
764 ISL_AUX_STATE_CLEAR
= 0,
765 ISL_AUX_STATE_COMPRESSED_CLEAR
,
766 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
,
767 ISL_AUX_STATE_RESOLVED
,
768 ISL_AUX_STATE_PASS_THROUGH
,
769 ISL_AUX_STATE_AUX_INVALID
,
772 /* TODO(chadv): Explain */
773 enum isl_array_pitch_span
{
774 ISL_ARRAY_PITCH_SPAN_FULL
,
775 ISL_ARRAY_PITCH_SPAN_COMPACT
,
779 * @defgroup Surface Usage
782 typedef uint64_t isl_surf_usage_flags_t
;
783 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
784 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
785 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
786 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
787 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
788 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
789 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
790 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
791 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
792 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
793 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
794 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
795 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
796 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
797 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
798 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
802 * @defgroup Channel Mask
804 * These #define values are chosen to match the values of
805 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
809 typedef uint8_t isl_channel_mask_t
;
810 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
811 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
812 #define ISL_CHANNEL_RED_BIT (1 << 2)
813 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
817 * @brief A channel select (also known as texture swizzle) value
819 enum isl_channel_select
{
820 ISL_CHANNEL_SELECT_ZERO
= 0,
821 ISL_CHANNEL_SELECT_ONE
= 1,
822 ISL_CHANNEL_SELECT_RED
= 4,
823 ISL_CHANNEL_SELECT_GREEN
= 5,
824 ISL_CHANNEL_SELECT_BLUE
= 6,
825 ISL_CHANNEL_SELECT_ALPHA
= 7,
829 * Identical to VkSampleCountFlagBits.
831 enum isl_sample_count
{
832 ISL_SAMPLE_COUNT_1_BIT
= 1u,
833 ISL_SAMPLE_COUNT_2_BIT
= 2u,
834 ISL_SAMPLE_COUNT_4_BIT
= 4u,
835 ISL_SAMPLE_COUNT_8_BIT
= 8u,
836 ISL_SAMPLE_COUNT_16_BIT
= 16u,
838 typedef uint32_t isl_sample_count_mask_t
;
841 * @brief Multisample Format
843 enum isl_msaa_layout
{
845 * @brief Suface is single-sampled.
847 ISL_MSAA_LAYOUT_NONE
,
850 * @brief [SNB+] Interleaved Multisample Format
852 * In this format, multiple samples are interleaved into each cacheline.
853 * In other words, the sample index is swizzled into the low 6 bits of the
854 * surface's virtual address space.
856 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
857 * and its pixel format is 32bpp. Then the first cacheline is arranged
860 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
861 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
863 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
864 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
866 * The hardware docs refer to this format with multiple terms. In
867 * Sandybridge, this is the only multisample format; so no term is used.
868 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
869 * Multisample Surface). Later hardware docs additionally refer to this
870 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
873 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
876 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
877 * Multisampled Surfaces".
879 ISL_MSAA_LAYOUT_INTERLEAVED
,
882 * @brief [IVB+] Array Multisample Format
884 * In this format, the surface's physical layout resembles that of a
887 * Suppose the multisample surface's logical extent is (w, h) and its
888 * sample count is N. Then surface's physical extent is the same as
889 * a singlesample 2D surface whose logical extent is (w, h) and array
890 * length is N. Array slice `i` contains the pixel values for sample
893 * The Ivybridge docs refer to surfaces in this format as UMS
894 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
895 * Surface). The Broadwell docs additionally refer to this format as
896 * MSFMT_MSS (MSS=Multisample Surface Storage).
898 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
899 * Multisample Surfaces".
901 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
902 * Multisample Surfaces".
904 ISL_MSAA_LAYOUT_ARRAY
,
909 const struct gen_device_info
*info
;
910 bool use_separate_stencil
;
911 bool has_bit6_swizzling
;
914 * Describes the layout of a RENDER_SURFACE_STATE structure for the
921 uint8_t aux_addr_offset
;
925 * Describes the layout of the depth/stencil/hiz commands as emitted by
926 * isl_emit_depth_stencil_hiz.
930 uint8_t depth_offset
;
931 uint8_t stencil_offset
;
936 struct isl_extent2d
{
937 union { uint32_t w
, width
; };
938 union { uint32_t h
, height
; };
941 struct isl_extent3d
{
942 union { uint32_t w
, width
; };
943 union { uint32_t h
, height
; };
944 union { uint32_t d
, depth
; };
947 struct isl_extent4d
{
948 union { uint32_t w
, width
; };
949 union { uint32_t h
, height
; };
950 union { uint32_t d
, depth
; };
951 union { uint32_t a
, array_len
; };
954 struct isl_channel_layout
{
955 enum isl_base_type type
;
956 uint8_t bits
; /**< Size in bits */
960 * Each format has 3D block extent (width, height, depth). The block extent of
961 * compressed formats is that of the format's compression block. For example,
962 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
963 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
964 * is (w=1, h=1, d=1).
966 struct isl_format_layout
{
967 enum isl_format format
;
970 uint16_t bpb
; /**< Bits per block */
971 uint8_t bw
; /**< Block width, in pixels */
972 uint8_t bh
; /**< Block height, in pixels */
973 uint8_t bd
; /**< Block depth, in pixels */
976 struct isl_channel_layout r
; /**< Red channel */
977 struct isl_channel_layout g
; /**< Green channel */
978 struct isl_channel_layout b
; /**< Blue channel */
979 struct isl_channel_layout a
; /**< Alpha channel */
980 struct isl_channel_layout l
; /**< Luminance channel */
981 struct isl_channel_layout i
; /**< Intensity channel */
982 struct isl_channel_layout p
; /**< Palette channel */
985 enum isl_colorspace colorspace
;
989 struct isl_tile_info
{
990 enum isl_tiling tiling
;
992 /* The size (in bits per block) of a single surface element
994 * For surfaces with power-of-two formats, this is the same as
995 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
996 * The logical_extent_el field is in terms of elements of this size.
998 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
999 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1000 * of the tiling formats can actually hold an integer number of 96-bit
1001 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1002 * 32-bit element size. It is the responsibility of the caller to
1003 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1004 * the width of a surface in tiles, you would do:
1006 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1007 * tile_info.logical_extent_el.width);
1009 uint32_t format_bpb
;
1011 /** The logical size of the tile in units of format_bpb size elements
1013 * This field determines how a given surface is cut up into tiles. It is
1014 * used to compute the size of a surface in tiles and can be used to
1015 * determine the location of the tile containing any given surface element.
1016 * The exact value of this field depends heavily on the bits-per-block of
1017 * the format being used.
1019 struct isl_extent2d logical_extent_el
;
1021 /** The physical size of the tile in bytes and rows of bytes
1023 * This field determines how the tiles of a surface are physically layed
1024 * out in memory. The logical and physical tile extent are frequently the
1025 * same but this is not always the case. For instance, a W-tile (which is
1026 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1027 * its physical size is 128B x 32rows, the same as a Y-tile.
1029 * @see isl_surf::row_pitch
1031 struct isl_extent2d phys_extent_B
;
1035 * Metadata about a DRM format modifier.
1037 struct isl_drm_modifier_info
{
1040 /** Text name of the modifier */
1043 /** ISL tiling implied by this modifier */
1044 enum isl_tiling tiling
;
1046 /** ISL aux usage implied by this modifier */
1047 enum isl_aux_usage aux_usage
;
1049 /** Whether or not this modifier supports clear color */
1050 bool supports_clear_color
;
1054 * @brief Input to surface initialization
1056 * @invariant width >= 1
1057 * @invariant height >= 1
1058 * @invariant depth >= 1
1059 * @invariant levels >= 1
1060 * @invariant samples >= 1
1061 * @invariant array_len >= 1
1063 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1064 * @invariant if 2D then depth == 1
1065 * @invariant if 3D then array_len == 1 and samples == 1
1067 struct isl_surf_init_info
{
1068 enum isl_surf_dim dim
;
1069 enum isl_format format
;
1078 /** Lower bound for isl_surf::alignment, in bytes. */
1079 uint32_t min_alignment
;
1082 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1083 * will fail if this is misaligned or out of bounds.
1087 isl_surf_usage_flags_t usage
;
1089 /** Flags that alter how ISL selects isl_surf::tiling. */
1090 isl_tiling_flags_t tiling_flags
;
1094 enum isl_surf_dim dim
;
1095 enum isl_dim_layout dim_layout
;
1096 enum isl_msaa_layout msaa_layout
;
1097 enum isl_tiling tiling
;
1098 enum isl_format format
;
1101 * Alignment of the upper-left sample of each subimage, in units of surface
1104 struct isl_extent3d image_alignment_el
;
1107 * Logical extent of the surface's base level, in units of pixels. This is
1108 * identical to the extent defined in isl_surf_init_info.
1110 struct isl_extent4d logical_level0_px
;
1113 * Physical extent of the surface's base level, in units of physical
1114 * surface samples and aligned to the format's compression block.
1116 * Consider isl_dim_layout as an operator that transforms a logical surface
1117 * layout to a physical surface layout. Then
1119 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1120 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1122 struct isl_extent4d phys_level0_sa
;
1127 /** Total size of the surface, in bytes. */
1130 /** Required alignment for the surface's base address. */
1134 * The interpretation of this field depends on the value of
1135 * isl_tile_info::physical_extent_B. In particular, the width of the
1136 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
1137 * and the distance in bytes between vertically adjacent tiles in the image
1138 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
1140 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1141 * this cleanly reduces to being the distance, in bytes, between vertically
1142 * adjacent surface elements.
1144 * @see isl_tile_info::phys_extent_B;
1149 * Pitch between physical array slices, in rows of surface elements.
1151 uint32_t array_pitch_el_rows
;
1153 enum isl_array_pitch_span array_pitch_span
;
1155 /** Copy of isl_surf_init_info::usage. */
1156 isl_surf_usage_flags_t usage
;
1159 struct isl_swizzle
{
1160 enum isl_channel_select r
:4;
1161 enum isl_channel_select g
:4;
1162 enum isl_channel_select b
:4;
1163 enum isl_channel_select a
:4;
1166 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1167 .r = ISL_CHANNEL_SELECT_##R, \
1168 .g = ISL_CHANNEL_SELECT_##G, \
1169 .b = ISL_CHANNEL_SELECT_##B, \
1170 .a = ISL_CHANNEL_SELECT_##A, \
1173 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1177 * Indicates the usage of the particular view
1179 * Normally, this is one bit. However, for a cube map texture, it
1180 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1182 isl_surf_usage_flags_t usage
;
1185 * The format to use in the view
1187 * This may differ from the format of the actual isl_surf but must have
1188 * the same block size.
1190 enum isl_format format
;
1192 uint32_t base_level
;
1198 * For cube maps, both base_array_layer and array_len should be
1199 * specified in terms of 2-D layers and must be a multiple of 6.
1201 * 3-D textures are effectively treated as 2-D arrays when used as a
1202 * storage image or render target. If `usage` contains
1203 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1204 * base_array_layer and array_len are applied. If the surface is only used
1205 * for texturing, they are ignored.
1207 uint32_t base_array_layer
;
1212 * Indicates the number of array elements starting at Base Array Layer.
1216 struct isl_swizzle swizzle
;
1219 union isl_color_value
{
1225 struct isl_surf_fill_state_info
{
1226 const struct isl_surf
*surf
;
1227 const struct isl_view
*view
;
1230 * The address of the surface in GPU memory.
1235 * The Memory Object Control state for the filled surface state.
1237 * The exact format of this value depends on hardware generation.
1242 * The auxilary surface or NULL if no auxilary surface is to be used.
1244 const struct isl_surf
*aux_surf
;
1245 enum isl_aux_usage aux_usage
;
1246 uint64_t aux_address
;
1249 * The clear color for this surface
1251 * Valid values depend on hardware generation.
1253 union isl_color_value clear_color
;
1256 * Surface write disables for gen4-5
1258 isl_channel_mask_t write_disables
;
1260 /* Intra-tile offset */
1261 uint16_t x_offset_sa
, y_offset_sa
;
1264 struct isl_buffer_fill_state_info
{
1266 * The address of the surface in GPU memory.
1271 * The size of the buffer
1276 * The Memory Object Control state for the filled surface state.
1278 * The exact format of this value depends on hardware generation.
1283 * The format to use in the surface state
1285 * This may differ from the format of the actual isl_surf but have the
1288 enum isl_format format
;
1293 struct isl_depth_stencil_hiz_emit_info
{
1297 const struct isl_surf
*depth_surf
;
1300 * The stencil surface
1302 * If separate stencil is not available, this must point to the same
1303 * isl_surf as depth_surf.
1305 const struct isl_surf
*stencil_surf
;
1308 * The view into the depth and stencil surfaces.
1310 * This view applies to both surfaces simultaneously.
1312 const struct isl_view
*view
;
1315 * The address of the depth surface in GPU memory
1317 uint64_t depth_address
;
1320 * The address of the stencil surface in GPU memory
1322 * If separate stencil is not available, this must have the same value as
1325 uint64_t stencil_address
;
1328 * The Memory Object Control state for depth and stencil buffers
1330 * Both depth and stencil will get the same MOCS value. The exact format
1331 * of this value depends on hardware generation.
1336 * The HiZ surface or NULL if HiZ is disabled.
1338 const struct isl_surf
*hiz_surf
;
1339 enum isl_aux_usage hiz_usage
;
1340 uint64_t hiz_address
;
1343 * The depth clear value
1345 float depth_clear_value
;
1348 extern const struct isl_format_layout isl_format_layouts
[];
1351 isl_device_init(struct isl_device
*dev
,
1352 const struct gen_device_info
*info
,
1353 bool has_bit6_swizzling
);
1355 isl_sample_count_mask_t ATTRIBUTE_CONST
1356 isl_device_get_sample_counts(struct isl_device
*dev
);
1358 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
1359 isl_format_get_layout(enum isl_format fmt
)
1361 return &isl_format_layouts
[fmt
];
1364 static inline const char * ATTRIBUTE_CONST
1365 isl_format_get_name(enum isl_format fmt
)
1367 return isl_format_layouts
[fmt
].name
;
1370 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
1371 enum isl_format format
);
1372 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
1373 enum isl_format format
);
1374 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
1375 enum isl_format format
);
1376 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
1377 enum isl_format format
);
1378 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
1379 enum isl_format format
);
1380 bool isl_format_supports_typed_writes(const struct gen_device_info
*devinfo
,
1381 enum isl_format format
);
1382 bool isl_format_supports_typed_reads(const struct gen_device_info
*devinfo
,
1383 enum isl_format format
);
1384 bool isl_format_supports_ccs_d(const struct gen_device_info
*devinfo
,
1385 enum isl_format format
);
1386 bool isl_format_supports_ccs_e(const struct gen_device_info
*devinfo
,
1387 enum isl_format format
);
1388 bool isl_format_supports_multisampling(const struct gen_device_info
*devinfo
,
1389 enum isl_format format
);
1391 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info
*devinfo
,
1392 enum isl_format format1
,
1393 enum isl_format format2
);
1395 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1396 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1397 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1398 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1399 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1400 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1403 isl_format_has_normalized_channel(enum isl_format fmt
)
1405 return isl_format_has_unorm_channel(fmt
) ||
1406 isl_format_has_snorm_channel(fmt
);
1410 isl_format_has_float_channel(enum isl_format fmt
)
1412 return isl_format_has_ufloat_channel(fmt
) ||
1413 isl_format_has_sfloat_channel(fmt
);
1417 isl_format_has_int_channel(enum isl_format fmt
)
1419 return isl_format_has_uint_channel(fmt
) ||
1420 isl_format_has_sint_channel(fmt
);
1423 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1425 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1428 isl_format_is_compressed(enum isl_format fmt
)
1430 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1432 return fmtl
->txc
!= ISL_TXC_NONE
;
1436 isl_format_has_bc_compression(enum isl_format fmt
)
1438 switch (isl_format_get_layout(fmt
)->txc
) {
1456 unreachable("Should not be called on an aux surface");
1459 unreachable("bad texture compression mode");
1464 isl_format_is_yuv(enum isl_format fmt
)
1466 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1468 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1472 isl_format_block_is_1x1x1(enum isl_format fmt
)
1474 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1476 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1480 isl_format_is_rgb(enum isl_format fmt
)
1482 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
1483 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
1484 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
1485 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
1488 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1489 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1491 bool isl_is_storage_image_format(enum isl_format fmt
);
1494 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1495 enum isl_format fmt
);
1497 /* Returns true if this hardware supports typed load/store on a format with
1498 * the same size as the given format.
1501 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1502 enum isl_format fmt
);
1505 isl_tiling_is_any_y(enum isl_tiling tiling
)
1507 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1511 isl_tiling_is_std_y(enum isl_tiling tiling
)
1513 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1516 const struct isl_drm_modifier_info
* ATTRIBUTE_CONST
1517 isl_drm_modifier_get_info(uint64_t modifier
);
1519 struct isl_extent2d ATTRIBUTE_CONST
1520 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
);
1523 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1525 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1529 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1531 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1535 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1537 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1541 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1543 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1544 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1548 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1550 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1554 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1556 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1557 (info
->format
== ISL_FORMAT_R16_UNORM
);
1561 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1563 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1564 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1567 static inline struct isl_extent2d
1568 isl_extent2d(uint32_t width
, uint32_t height
)
1570 struct isl_extent2d e
= { { 0 } };
1578 static inline struct isl_extent3d
1579 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1581 struct isl_extent3d e
= { { 0 } };
1590 static inline struct isl_extent4d
1591 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1594 struct isl_extent4d e
= { { 0 } };
1599 e
.array_len
= array_len
;
1604 #define isl_surf_init(dev, surf, ...) \
1605 isl_surf_init_s((dev), (surf), \
1606 &(struct isl_surf_init_info) { __VA_ARGS__ });
1609 isl_surf_init_s(const struct isl_device
*dev
,
1610 struct isl_surf
*surf
,
1611 const struct isl_surf_init_info
*restrict info
);
1614 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1615 struct isl_tile_info
*tile_info
);
1618 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1619 const struct isl_surf
*surf
,
1620 struct isl_surf
*hiz_surf
);
1623 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1624 const struct isl_surf
*surf
,
1625 struct isl_surf
*mcs_surf
);
1628 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1629 const struct isl_surf
*surf
,
1630 struct isl_surf
*ccs_surf
);
1632 #define isl_surf_fill_state(dev, state, ...) \
1633 isl_surf_fill_state_s((dev), (state), \
1634 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1637 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1638 const struct isl_surf_fill_state_info
*restrict info
);
1640 #define isl_buffer_fill_state(dev, state, ...) \
1641 isl_buffer_fill_state_s((dev), (state), \
1642 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1645 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1646 const struct isl_buffer_fill_state_info
*restrict info
);
1648 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1649 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1650 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1653 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1654 const struct isl_depth_stencil_hiz_emit_info
*restrict info
);
1657 isl_surf_fill_image_param(const struct isl_device
*dev
,
1658 struct brw_image_param
*param
,
1659 const struct isl_surf
*surf
,
1660 const struct isl_view
*view
);
1663 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1664 struct brw_image_param
*param
,
1665 enum isl_format format
,
1669 * Alignment of the upper-left sample of each subimage, in units of surface
1672 static inline struct isl_extent3d
1673 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1675 return surf
->image_alignment_el
;
1679 * Alignment of the upper-left sample of each subimage, in units of surface
1682 static inline struct isl_extent3d
1683 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1685 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1687 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1688 fmtl
->bh
* surf
->image_alignment_el
.h
,
1689 fmtl
->bd
* surf
->image_alignment_el
.d
);
1693 * Pitch between vertically adjacent surface elements, in bytes.
1695 static inline uint32_t
1696 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
1698 return surf
->row_pitch
;
1702 * Pitch between vertically adjacent surface elements, in units of surface elements.
1704 static inline uint32_t
1705 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1707 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1709 assert(surf
->row_pitch
% (fmtl
->bpb
/ 8) == 0);
1710 return surf
->row_pitch
/ (fmtl
->bpb
/ 8);
1714 * Pitch between physical array slices, in rows of surface elements.
1716 static inline uint32_t
1717 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1719 return surf
->array_pitch_el_rows
;
1723 * Pitch between physical array slices, in units of surface elements.
1725 static inline uint32_t
1726 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1728 return isl_surf_get_array_pitch_el_rows(surf
) *
1729 isl_surf_get_row_pitch_el(surf
);
1733 * Pitch between physical array slices, in rows of surface samples.
1735 static inline uint32_t
1736 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1738 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1739 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1743 * Pitch between physical array slices, in bytes.
1745 static inline uint32_t
1746 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1748 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
1752 * Calculate the offset, in units of surface samples, to a subimage in the
1755 * @invariant level < surface levels
1756 * @invariant logical_array_layer < logical array length of surface
1757 * @invariant logical_z_offset_px < logical depth of surface at level
1760 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1762 uint32_t logical_array_layer
,
1763 uint32_t logical_z_offset_px
,
1764 uint32_t *x_offset_sa
,
1765 uint32_t *y_offset_sa
);
1768 * Calculate the offset, in units of surface elements, to a subimage in the
1771 * @invariant level < surface levels
1772 * @invariant logical_array_layer < logical array length of surface
1773 * @invariant logical_z_offset_px < logical depth of surface at level
1776 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1778 uint32_t logical_array_layer
,
1779 uint32_t logical_z_offset_px
,
1780 uint32_t *x_offset_el
,
1781 uint32_t *y_offset_el
);
1784 * Calculate the offset, in bytes and intratile surface samples, to a
1785 * subimage in the surface.
1787 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
1788 * result to isl_tiling_get_intratile_offset_el, and converting the tile
1789 * offsets to samples.
1791 * @invariant level < surface levels
1792 * @invariant logical_array_layer < logical array length of surface
1793 * @invariant logical_z_offset_px < logical depth of surface at level
1796 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
1798 uint32_t logical_array_layer
,
1799 uint32_t logical_z_offset_px
,
1801 uint32_t *x_offset_sa
,
1802 uint32_t *y_offset_sa
);
1805 * @brief Calculate the intratile offsets to a surface.
1807 * In @a base_address_offset return the offset from the base of the surface to
1808 * the base address of the first tile of the subimage. In @a x_offset_B and
1809 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1810 * tile's base to the subimage's first surface element. The x and y offsets
1811 * are intratile offsets; that is, they do not exceed the boundary of the
1812 * surface's tiling format.
1815 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
1818 uint32_t total_x_offset_el
,
1819 uint32_t total_y_offset_el
,
1820 uint32_t *base_address_offset
,
1821 uint32_t *x_offset_el
,
1822 uint32_t *y_offset_el
);
1825 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling
,
1826 enum isl_format format
,
1828 uint32_t total_x_offset_sa
,
1829 uint32_t total_y_offset_sa
,
1830 uint32_t *base_address_offset
,
1831 uint32_t *x_offset_sa
,
1832 uint32_t *y_offset_sa
)
1834 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1836 /* For computing the intratile offsets, we actually want a strange unit
1837 * which is samples for multisampled surfaces but elements for compressed
1840 assert(total_x_offset_sa
% fmtl
->bw
== 0);
1841 assert(total_y_offset_sa
% fmtl
->bh
== 0);
1842 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
1843 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
1845 isl_tiling_get_intratile_offset_el(tiling
, fmtl
->bpb
, row_pitch
,
1846 total_x_offset
, total_y_offset
,
1847 base_address_offset
,
1848 x_offset_sa
, y_offset_sa
);
1849 *x_offset_sa
*= fmtl
->bw
;
1850 *y_offset_sa
*= fmtl
->bh
;
1854 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1856 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1857 * @pre surf->format must be a valid format for depth surfaces
1860 isl_surf_get_depth_format(const struct isl_device
*dev
,
1861 const struct isl_surf
*surf
);