2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @brief Intel Surface Layout
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
45 #include "c99_compat.h"
46 #include "util/macros.h"
52 struct gen_device_info
;
53 struct brw_image_param
;
57 * @brief Get the hardware generation of isl_device.
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
73 #ifndef ISL_DEV_IS_HASWELL
75 * @brief Get the hardware generation of isl_device.
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 * Hardware enumeration SURFACE_FORMAT.
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
106 ISL_FORMAT_R32G32B32A32_FLOAT
= 0,
107 ISL_FORMAT_R32G32B32A32_SINT
= 1,
108 ISL_FORMAT_R32G32B32A32_UINT
= 2,
109 ISL_FORMAT_R32G32B32A32_UNORM
= 3,
110 ISL_FORMAT_R32G32B32A32_SNORM
= 4,
111 ISL_FORMAT_R64G64_FLOAT
= 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT
= 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED
= 7,
114 ISL_FORMAT_R32G32B32A32_USCALED
= 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED
= 32,
116 ISL_FORMAT_R64G64_PASSTHRU
= 33,
117 ISL_FORMAT_R32G32B32_FLOAT
= 64,
118 ISL_FORMAT_R32G32B32_SINT
= 65,
119 ISL_FORMAT_R32G32B32_UINT
= 66,
120 ISL_FORMAT_R32G32B32_UNORM
= 67,
121 ISL_FORMAT_R32G32B32_SNORM
= 68,
122 ISL_FORMAT_R32G32B32_SSCALED
= 69,
123 ISL_FORMAT_R32G32B32_USCALED
= 70,
124 ISL_FORMAT_R32G32B32_SFIXED
= 80,
125 ISL_FORMAT_R16G16B16A16_UNORM
= 128,
126 ISL_FORMAT_R16G16B16A16_SNORM
= 129,
127 ISL_FORMAT_R16G16B16A16_SINT
= 130,
128 ISL_FORMAT_R16G16B16A16_UINT
= 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT
= 132,
130 ISL_FORMAT_R32G32_FLOAT
= 133,
131 ISL_FORMAT_R32G32_SINT
= 134,
132 ISL_FORMAT_R32G32_UINT
= 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS
= 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT
= 137,
135 ISL_FORMAT_L32A32_FLOAT
= 138,
136 ISL_FORMAT_R32G32_UNORM
= 139,
137 ISL_FORMAT_R32G32_SNORM
= 140,
138 ISL_FORMAT_R64_FLOAT
= 141,
139 ISL_FORMAT_R16G16B16X16_UNORM
= 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT
= 143,
141 ISL_FORMAT_A32X32_FLOAT
= 144,
142 ISL_FORMAT_L32X32_FLOAT
= 145,
143 ISL_FORMAT_I32X32_FLOAT
= 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED
= 147,
145 ISL_FORMAT_R16G16B16A16_USCALED
= 148,
146 ISL_FORMAT_R32G32_SSCALED
= 149,
147 ISL_FORMAT_R32G32_USCALED
= 150,
148 ISL_FORMAT_R32G32_FLOAT_LD
= 151,
149 ISL_FORMAT_R32G32_SFIXED
= 160,
150 ISL_FORMAT_R64_PASSTHRU
= 161,
151 ISL_FORMAT_B8G8R8A8_UNORM
= 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB
= 193,
153 ISL_FORMAT_R10G10B10A2_UNORM
= 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB
= 195,
155 ISL_FORMAT_R10G10B10A2_UINT
= 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM
= 197,
157 ISL_FORMAT_R8G8B8A8_UNORM
= 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB
= 200,
159 ISL_FORMAT_R8G8B8A8_SNORM
= 201,
160 ISL_FORMAT_R8G8B8A8_SINT
= 202,
161 ISL_FORMAT_R8G8B8A8_UINT
= 203,
162 ISL_FORMAT_R16G16_UNORM
= 204,
163 ISL_FORMAT_R16G16_SNORM
= 205,
164 ISL_FORMAT_R16G16_SINT
= 206,
165 ISL_FORMAT_R16G16_UINT
= 207,
166 ISL_FORMAT_R16G16_FLOAT
= 208,
167 ISL_FORMAT_B10G10R10A2_UNORM
= 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB
= 210,
169 ISL_FORMAT_R11G11B10_FLOAT
= 211,
170 ISL_FORMAT_R32_SINT
= 214,
171 ISL_FORMAT_R32_UINT
= 215,
172 ISL_FORMAT_R32_FLOAT
= 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS
= 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT
= 218,
175 ISL_FORMAT_L32_UNORM
= 221,
176 ISL_FORMAT_A32_UNORM
= 222,
177 ISL_FORMAT_L16A16_UNORM
= 223,
178 ISL_FORMAT_I24X8_UNORM
= 224,
179 ISL_FORMAT_L24X8_UNORM
= 225,
180 ISL_FORMAT_A24X8_UNORM
= 226,
181 ISL_FORMAT_I32_FLOAT
= 227,
182 ISL_FORMAT_L32_FLOAT
= 228,
183 ISL_FORMAT_A32_FLOAT
= 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM
= 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM
= 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM
= 232,
187 ISL_FORMAT_B8G8R8X8_UNORM
= 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB
= 234,
189 ISL_FORMAT_R8G8B8X8_UNORM
= 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB
= 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP
= 237,
192 ISL_FORMAT_B10G10R10X2_UNORM
= 238,
193 ISL_FORMAT_L16A16_FLOAT
= 240,
194 ISL_FORMAT_R32_UNORM
= 241,
195 ISL_FORMAT_R32_SNORM
= 242,
196 ISL_FORMAT_R10G10B10X2_USCALED
= 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED
= 244,
198 ISL_FORMAT_R8G8B8A8_USCALED
= 245,
199 ISL_FORMAT_R16G16_SSCALED
= 246,
200 ISL_FORMAT_R16G16_USCALED
= 247,
201 ISL_FORMAT_R32_SSCALED
= 248,
202 ISL_FORMAT_R32_USCALED
= 249,
203 ISL_FORMAT_B5G6R5_UNORM
= 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB
= 257,
205 ISL_FORMAT_B5G5R5A1_UNORM
= 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB
= 259,
207 ISL_FORMAT_B4G4R4A4_UNORM
= 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB
= 261,
209 ISL_FORMAT_R8G8_UNORM
= 262,
210 ISL_FORMAT_R8G8_SNORM
= 263,
211 ISL_FORMAT_R8G8_SINT
= 264,
212 ISL_FORMAT_R8G8_UINT
= 265,
213 ISL_FORMAT_R16_UNORM
= 266,
214 ISL_FORMAT_R16_SNORM
= 267,
215 ISL_FORMAT_R16_SINT
= 268,
216 ISL_FORMAT_R16_UINT
= 269,
217 ISL_FORMAT_R16_FLOAT
= 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0
= 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1
= 272,
220 ISL_FORMAT_I16_UNORM
= 273,
221 ISL_FORMAT_L16_UNORM
= 274,
222 ISL_FORMAT_A16_UNORM
= 275,
223 ISL_FORMAT_L8A8_UNORM
= 276,
224 ISL_FORMAT_I16_FLOAT
= 277,
225 ISL_FORMAT_L16_FLOAT
= 278,
226 ISL_FORMAT_A16_FLOAT
= 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB
= 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM
= 281,
229 ISL_FORMAT_B5G5R5X1_UNORM
= 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB
= 283,
231 ISL_FORMAT_R8G8_SSCALED
= 284,
232 ISL_FORMAT_R8G8_USCALED
= 285,
233 ISL_FORMAT_R16_SSCALED
= 286,
234 ISL_FORMAT_R16_USCALED
= 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0
= 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1
= 291,
237 ISL_FORMAT_A1B5G5R5_UNORM
= 292,
238 ISL_FORMAT_A4B4G4R4_UNORM
= 293,
239 ISL_FORMAT_L8A8_UINT
= 294,
240 ISL_FORMAT_L8A8_SINT
= 295,
241 ISL_FORMAT_R8_UNORM
= 320,
242 ISL_FORMAT_R8_SNORM
= 321,
243 ISL_FORMAT_R8_SINT
= 322,
244 ISL_FORMAT_R8_UINT
= 323,
245 ISL_FORMAT_A8_UNORM
= 324,
246 ISL_FORMAT_I8_UNORM
= 325,
247 ISL_FORMAT_L8_UNORM
= 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0
= 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0
= 328,
250 ISL_FORMAT_R8_SSCALED
= 329,
251 ISL_FORMAT_R8_USCALED
= 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0
= 331,
253 ISL_FORMAT_L8_UNORM_SRGB
= 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1
= 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1
= 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1
= 335,
257 ISL_FORMAT_Y8_UNORM
= 336,
258 ISL_FORMAT_L8_UINT
= 338,
259 ISL_FORMAT_L8_SINT
= 339,
260 ISL_FORMAT_I8_UINT
= 340,
261 ISL_FORMAT_I8_SINT
= 341,
262 ISL_FORMAT_DXT1_RGB_SRGB
= 384,
263 ISL_FORMAT_R1_UNORM
= 385,
264 ISL_FORMAT_YCRCB_NORMAL
= 386,
265 ISL_FORMAT_YCRCB_SWAPUVY
= 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0
= 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1
= 389,
268 ISL_FORMAT_BC1_UNORM
= 390,
269 ISL_FORMAT_BC2_UNORM
= 391,
270 ISL_FORMAT_BC3_UNORM
= 392,
271 ISL_FORMAT_BC4_UNORM
= 393,
272 ISL_FORMAT_BC5_UNORM
= 394,
273 ISL_FORMAT_BC1_UNORM_SRGB
= 395,
274 ISL_FORMAT_BC2_UNORM_SRGB
= 396,
275 ISL_FORMAT_BC3_UNORM_SRGB
= 397,
276 ISL_FORMAT_MONO8
= 398,
277 ISL_FORMAT_YCRCB_SWAPUV
= 399,
278 ISL_FORMAT_YCRCB_SWAPY
= 400,
279 ISL_FORMAT_DXT1_RGB
= 401,
280 ISL_FORMAT_FXT1
= 402,
281 ISL_FORMAT_R8G8B8_UNORM
= 403,
282 ISL_FORMAT_R8G8B8_SNORM
= 404,
283 ISL_FORMAT_R8G8B8_SSCALED
= 405,
284 ISL_FORMAT_R8G8B8_USCALED
= 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT
= 407,
286 ISL_FORMAT_R64G64B64_FLOAT
= 408,
287 ISL_FORMAT_BC4_SNORM
= 409,
288 ISL_FORMAT_BC5_SNORM
= 410,
289 ISL_FORMAT_R16G16B16_FLOAT
= 411,
290 ISL_FORMAT_R16G16B16_UNORM
= 412,
291 ISL_FORMAT_R16G16B16_SNORM
= 413,
292 ISL_FORMAT_R16G16B16_SSCALED
= 414,
293 ISL_FORMAT_R16G16B16_USCALED
= 415,
294 ISL_FORMAT_BC6H_SF16
= 417,
295 ISL_FORMAT_BC7_UNORM
= 418,
296 ISL_FORMAT_BC7_UNORM_SRGB
= 419,
297 ISL_FORMAT_BC6H_UF16
= 420,
298 ISL_FORMAT_PLANAR_420_8
= 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB
= 424,
300 ISL_FORMAT_ETC1_RGB8
= 425,
301 ISL_FORMAT_ETC2_RGB8
= 426,
302 ISL_FORMAT_EAC_R11
= 427,
303 ISL_FORMAT_EAC_RG11
= 428,
304 ISL_FORMAT_EAC_SIGNED_R11
= 429,
305 ISL_FORMAT_EAC_SIGNED_RG11
= 430,
306 ISL_FORMAT_ETC2_SRGB8
= 431,
307 ISL_FORMAT_R16G16B16_UINT
= 432,
308 ISL_FORMAT_R16G16B16_SINT
= 433,
309 ISL_FORMAT_R32_SFIXED
= 434,
310 ISL_FORMAT_R10G10B10A2_SNORM
= 435,
311 ISL_FORMAT_R10G10B10A2_USCALED
= 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED
= 437,
313 ISL_FORMAT_R10G10B10A2_SINT
= 438,
314 ISL_FORMAT_B10G10R10A2_SNORM
= 439,
315 ISL_FORMAT_B10G10R10A2_USCALED
= 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED
= 441,
317 ISL_FORMAT_B10G10R10A2_UINT
= 442,
318 ISL_FORMAT_B10G10R10A2_SINT
= 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU
= 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU
= 445,
321 ISL_FORMAT_ETC2_RGB8_PTA
= 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA
= 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8
= 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8
= 451,
325 ISL_FORMAT_R8G8B8_UINT
= 456,
326 ISL_FORMAT_R8G8B8_SINT
= 457,
327 ISL_FORMAT_RAW
= 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB
= 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB
= 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB
= 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB
= 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB
= 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB
= 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB
= 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB
= 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB
= 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB
= 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB
= 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB
= 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB
= 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB
= 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16
= 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16
= 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16
= 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16
= 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16
= 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16
= 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16
= 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16
= 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16
= 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16
= 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16
= 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16
= 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16
= 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16
= 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16
= 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16
= 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16
= 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16
= 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16
= 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16
= 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16
= 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16
= 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16
= 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16
= 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16
= 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16
= 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16
= 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16
= 895,
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
376 /* Formats for auxiliary surfaces */
382 ISL_FORMAT_GEN7_CCS_32BPP_X
,
383 ISL_FORMAT_GEN7_CCS_64BPP_X
,
384 ISL_FORMAT_GEN7_CCS_128BPP_X
,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y
,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y
,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y
,
388 ISL_FORMAT_GEN9_CCS_32BPP
,
389 ISL_FORMAT_GEN9_CCS_64BPP
,
390 ISL_FORMAT_GEN9_CCS_128BPP
,
392 /* Hardware doesn't understand this out-of-band value */
393 ISL_FORMAT_UNSUPPORTED
= UINT16_MAX
,
397 * Numerical base type for channels of isl_format.
415 * Colorspace of isl_format.
417 enum isl_colorspace
{
418 ISL_COLORSPACE_NONE
= 0,
419 ISL_COLORSPACE_LINEAR
,
425 * Texture compression mode of isl_format.
440 /* Used for auxiliary surface formats */
447 * @brief Hardware tile mode
449 * WARNING: These values differ from the hardware enum values, which are
450 * unstable across hardware generations.
452 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
453 * clearly distinguish it from Yf and Ys.
456 ISL_TILING_LINEAR
= 0,
459 ISL_TILING_Y0
, /**< Legacy Y tiling */
460 ISL_TILING_Yf
, /**< Standard 4K tiling. The 'f' means "four". */
461 ISL_TILING_Ys
, /**< Standard 64K tiling. The 's' means "sixty-four". */
462 ISL_TILING_HIZ
, /**< Tiling format for HiZ surfaces */
463 ISL_TILING_CCS
, /**< Tiling format for CCS surfaces */
467 * @defgroup Tiling Flags
470 typedef uint32_t isl_tiling_flags_t
;
471 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
472 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
473 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
474 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
475 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
476 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
477 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
478 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
479 #define ISL_TILING_ANY_MASK (~0u)
480 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
482 /** Any Y tiling, including legacy Y tiling. */
483 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
484 ISL_TILING_Yf_BIT | \
487 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
488 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
493 * @brief Logical dimension of surface.
495 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
496 * as 2D array surfaces.
505 * @brief Physical layout of the surface's dimensions.
507 enum isl_dim_layout
{
509 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
510 * 6.17.3: 2D Surfaces.
512 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
513 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
515 * One-dimensional surfaces are identical to 2D surfaces with height of
518 * @invariant isl_surf::phys_level0_sa::depth == 1
520 ISL_DIM_LAYOUT_GEN4_2D
,
523 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
524 * 6.17.5: 3D Surfaces.
526 * @invariant isl_surf::phys_level0_sa::array_len == 1
528 ISL_DIM_LAYOUT_GEN4_3D
,
531 * Special layout used for HiZ and stencil on Sandy Bridge to work around
532 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
533 * work the same as on gen7+ except that they don't technically support
534 * mipmapping. That does not, however, stop us from doing it. As far as
535 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
536 * single miplevel 2D (possibly array) image. The dimensions of that image
539 * In order to implement HiZ and stencil on Sandy Bridge, we create one
540 * full-sized 2D (possibly array) image for every LOD with every image
541 * aligned to a page boundary. When the surface is used with the stencil
542 * or HiZ hardware, we manually offset to the image for the given LOD.
544 * As a memory saving measure, we pretend that the width of each miplevel
545 * is minified and we place LOD1 and above below LOD0 but horizontally
546 * adjacent to each other. When considered as full-sized images, LOD1 and
547 * above technically overlap. However, since we only write to part of that
548 * image, the hardware will never notice the overlap.
550 * This layout looks something like this:
568 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
,
571 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
572 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
574 ISL_DIM_LAYOUT_GEN9_1D
,
578 /** No Auxiliary surface is used */
581 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
584 /** The auxiliary surface is an MCS
586 * @invariant isl_surf::samples > 1
590 /** The auxiliary surface is a fast-clear-only compression surface
592 * @invariant isl_surf::samples == 1
596 /** The auxiliary surface provides full lossless color compression
598 * @invariant isl_surf::samples == 1
603 /* TODO(chadv): Explain */
604 enum isl_array_pitch_span
{
605 ISL_ARRAY_PITCH_SPAN_FULL
,
606 ISL_ARRAY_PITCH_SPAN_COMPACT
,
610 * @defgroup Surface Usage
613 typedef uint64_t isl_surf_usage_flags_t
;
614 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
615 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
616 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
617 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
618 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
619 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
620 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
621 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
622 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
623 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
624 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
625 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
626 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
627 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
628 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
629 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
633 * @defgroup Channel Mask
635 * These #define values are chosen to match the values of
636 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
640 typedef uint8_t isl_channel_mask_t
;
641 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
642 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
643 #define ISL_CHANNEL_RED_BIT (1 << 2)
644 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
648 * @brief A channel select (also known as texture swizzle) value
650 enum isl_channel_select
{
651 ISL_CHANNEL_SELECT_ZERO
= 0,
652 ISL_CHANNEL_SELECT_ONE
= 1,
653 ISL_CHANNEL_SELECT_RED
= 4,
654 ISL_CHANNEL_SELECT_GREEN
= 5,
655 ISL_CHANNEL_SELECT_BLUE
= 6,
656 ISL_CHANNEL_SELECT_ALPHA
= 7,
660 * Identical to VkSampleCountFlagBits.
662 enum isl_sample_count
{
663 ISL_SAMPLE_COUNT_1_BIT
= 1u,
664 ISL_SAMPLE_COUNT_2_BIT
= 2u,
665 ISL_SAMPLE_COUNT_4_BIT
= 4u,
666 ISL_SAMPLE_COUNT_8_BIT
= 8u,
667 ISL_SAMPLE_COUNT_16_BIT
= 16u,
669 typedef uint32_t isl_sample_count_mask_t
;
672 * @brief Multisample Format
674 enum isl_msaa_layout
{
676 * @brief Suface is single-sampled.
678 ISL_MSAA_LAYOUT_NONE
,
681 * @brief [SNB+] Interleaved Multisample Format
683 * In this format, multiple samples are interleaved into each cacheline.
684 * In other words, the sample index is swizzled into the low 6 bits of the
685 * surface's virtual address space.
687 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
688 * and its pixel format is 32bpp. Then the first cacheline is arranged
691 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
692 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
694 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
695 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
697 * The hardware docs refer to this format with multiple terms. In
698 * Sandybridge, this is the only multisample format; so no term is used.
699 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
700 * Multisample Surface). Later hardware docs additionally refer to this
701 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
704 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
707 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
708 * Multisampled Surfaces".
710 ISL_MSAA_LAYOUT_INTERLEAVED
,
713 * @brief [IVB+] Array Multisample Format
715 * In this format, the surface's physical layout resembles that of a
718 * Suppose the multisample surface's logical extent is (w, h) and its
719 * sample count is N. Then surface's physical extent is the same as
720 * a singlesample 2D surface whose logical extent is (w, h) and array
721 * length is N. Array slice `i` contains the pixel values for sample
724 * The Ivybridge docs refer to surfaces in this format as UMS
725 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
726 * Surface). The Broadwell docs additionally refer to this format as
727 * MSFMT_MSS (MSS=Multisample Surface Storage).
729 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
730 * Multisample Surfaces".
732 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
733 * Multisample Surfaces".
735 ISL_MSAA_LAYOUT_ARRAY
,
740 const struct gen_device_info
*info
;
741 bool use_separate_stencil
;
742 bool has_bit6_swizzling
;
745 * Describes the layout of a RENDER_SURFACE_STATE structure for the
752 uint8_t aux_addr_offset
;
756 * Describes the layout of the depth/stencil/hiz commands as emitted by
757 * isl_emit_depth_stencil_hiz.
761 uint8_t depth_offset
;
762 uint8_t stencil_offset
;
767 struct isl_extent2d
{
768 union { uint32_t w
, width
; };
769 union { uint32_t h
, height
; };
772 struct isl_extent3d
{
773 union { uint32_t w
, width
; };
774 union { uint32_t h
, height
; };
775 union { uint32_t d
, depth
; };
778 struct isl_extent4d
{
779 union { uint32_t w
, width
; };
780 union { uint32_t h
, height
; };
781 union { uint32_t d
, depth
; };
782 union { uint32_t a
, array_len
; };
785 struct isl_channel_layout
{
786 enum isl_base_type type
;
787 uint8_t bits
; /**< Size in bits */
791 * Each format has 3D block extent (width, height, depth). The block extent of
792 * compressed formats is that of the format's compression block. For example,
793 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
794 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
795 * is (w=1, h=1, d=1).
797 struct isl_format_layout
{
798 enum isl_format format
;
801 uint16_t bpb
; /**< Bits per block */
802 uint8_t bw
; /**< Block width, in pixels */
803 uint8_t bh
; /**< Block height, in pixels */
804 uint8_t bd
; /**< Block depth, in pixels */
807 struct isl_channel_layout r
; /**< Red channel */
808 struct isl_channel_layout g
; /**< Green channel */
809 struct isl_channel_layout b
; /**< Blue channel */
810 struct isl_channel_layout a
; /**< Alpha channel */
811 struct isl_channel_layout l
; /**< Luminance channel */
812 struct isl_channel_layout i
; /**< Intensity channel */
813 struct isl_channel_layout p
; /**< Palette channel */
816 enum isl_colorspace colorspace
;
820 struct isl_tile_info
{
821 enum isl_tiling tiling
;
823 /* The size (in bits per block) of a single surface element
825 * For surfaces with power-of-two formats, this is the same as
826 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
827 * The logical_extent_el field is in terms of elements of this size.
829 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
830 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
831 * of the tiling formats can actually hold an integer number of 96-bit
832 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
833 * 32-bit element size. It is the responsibility of the caller to
834 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
835 * the width of a surface in tiles, you would do:
837 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
838 * tile_info.logical_extent_el.width);
842 /** The logical size of the tile in units of format_bpb size elements
844 * This field determines how a given surface is cut up into tiles. It is
845 * used to compute the size of a surface in tiles and can be used to
846 * determine the location of the tile containing any given surface element.
847 * The exact value of this field depends heavily on the bits-per-block of
848 * the format being used.
850 struct isl_extent2d logical_extent_el
;
852 /** The physical size of the tile in bytes and rows of bytes
854 * This field determines how the tiles of a surface are physically layed
855 * out in memory. The logical and physical tile extent are frequently the
856 * same but this is not always the case. For instance, a W-tile (which is
857 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
858 * its physical size is 128B x 32rows, the same as a Y-tile.
860 * @see isl_surf::row_pitch
862 struct isl_extent2d phys_extent_B
;
866 * @brief Input to surface initialization
868 * @invariant width >= 1
869 * @invariant height >= 1
870 * @invariant depth >= 1
871 * @invariant levels >= 1
872 * @invariant samples >= 1
873 * @invariant array_len >= 1
875 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
876 * @invariant if 2D then depth == 1
877 * @invariant if 3D then array_len == 1 and samples == 1
879 struct isl_surf_init_info
{
880 enum isl_surf_dim dim
;
881 enum isl_format format
;
890 /** Lower bound for isl_surf::alignment, in bytes. */
891 uint32_t min_alignment
;
894 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
895 * will fail if this is misaligned or out of bounds.
899 isl_surf_usage_flags_t usage
;
901 /** Flags that alter how ISL selects isl_surf::tiling. */
902 isl_tiling_flags_t tiling_flags
;
906 enum isl_surf_dim dim
;
907 enum isl_dim_layout dim_layout
;
908 enum isl_msaa_layout msaa_layout
;
909 enum isl_tiling tiling
;
910 enum isl_format format
;
913 * Alignment of the upper-left sample of each subimage, in units of surface
916 struct isl_extent3d image_alignment_el
;
919 * Logical extent of the surface's base level, in units of pixels. This is
920 * identical to the extent defined in isl_surf_init_info.
922 struct isl_extent4d logical_level0_px
;
925 * Physical extent of the surface's base level, in units of physical
926 * surface samples and aligned to the format's compression block.
928 * Consider isl_dim_layout as an operator that transforms a logical surface
929 * layout to a physical surface layout. Then
931 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
932 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
934 struct isl_extent4d phys_level0_sa
;
939 /** Total size of the surface, in bytes. */
942 /** Required alignment for the surface's base address. */
946 * The interpretation of this field depends on the value of
947 * isl_tile_info::physical_extent_B. In particular, the width of the
948 * surface in tiles is row_pitch / isl_tile_info::physical_extent_B.width
949 * and the distance in bytes between vertically adjacent tiles in the image
950 * is given by row_pitch * isl_tile_info::physical_extent_B.height.
952 * For linear images where isl_tile_info::physical_extent_B.height == 1,
953 * this cleanly reduces to being the distance, in bytes, between vertically
954 * adjacent surface elements.
956 * @see isl_tile_info::phys_extent_B;
961 * Pitch between physical array slices, in rows of surface elements.
963 uint32_t array_pitch_el_rows
;
965 enum isl_array_pitch_span array_pitch_span
;
967 /** Copy of isl_surf_init_info::usage. */
968 isl_surf_usage_flags_t usage
;
972 enum isl_channel_select r
:4;
973 enum isl_channel_select g
:4;
974 enum isl_channel_select b
:4;
975 enum isl_channel_select a
:4;
978 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
979 .r = ISL_CHANNEL_SELECT_##R, \
980 .g = ISL_CHANNEL_SELECT_##G, \
981 .b = ISL_CHANNEL_SELECT_##B, \
982 .a = ISL_CHANNEL_SELECT_##A, \
985 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
989 * Indicates the usage of the particular view
991 * Normally, this is one bit. However, for a cube map texture, it
992 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
994 isl_surf_usage_flags_t usage
;
997 * The format to use in the view
999 * This may differ from the format of the actual isl_surf but must have
1000 * the same block size.
1002 enum isl_format format
;
1004 uint32_t base_level
;
1010 * For cube maps, both base_array_layer and array_len should be
1011 * specified in terms of 2-D layers and must be a multiple of 6.
1013 * 3-D textures are effectively treated as 2-D arrays when used as a
1014 * storage image or render target. If `usage` contains
1015 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1016 * base_array_layer and array_len are applied. If the surface is only used
1017 * for texturing, they are ignored.
1019 uint32_t base_array_layer
;
1024 * Indicates the number of array elements starting at Base Array Layer.
1028 struct isl_swizzle swizzle
;
1031 union isl_color_value
{
1037 struct isl_surf_fill_state_info
{
1038 const struct isl_surf
*surf
;
1039 const struct isl_view
*view
;
1042 * The address of the surface in GPU memory.
1047 * The Memory Object Control state for the filled surface state.
1049 * The exact format of this value depends on hardware generation.
1054 * The auxilary surface or NULL if no auxilary surface is to be used.
1056 const struct isl_surf
*aux_surf
;
1057 enum isl_aux_usage aux_usage
;
1058 uint64_t aux_address
;
1061 * The clear color for this surface
1063 * Valid values depend on hardware generation.
1065 union isl_color_value clear_color
;
1068 * Surface write disables for gen4-5
1070 isl_channel_mask_t write_disables
;
1072 /* Intra-tile offset */
1073 uint16_t x_offset_sa
, y_offset_sa
;
1076 struct isl_buffer_fill_state_info
{
1078 * The address of the surface in GPU memory.
1083 * The size of the buffer
1088 * The Memory Object Control state for the filled surface state.
1090 * The exact format of this value depends on hardware generation.
1095 * The format to use in the surface state
1097 * This may differ from the format of the actual isl_surf but have the
1100 enum isl_format format
;
1105 struct isl_depth_stencil_hiz_emit_info
{
1109 const struct isl_surf
*depth_surf
;
1112 * The stencil surface
1114 * If separate stencil is not available, this must point to the same
1115 * isl_surf as depth_surf.
1117 const struct isl_surf
*stencil_surf
;
1120 * The view into the depth and stencil surfaces.
1122 * This view applies to both surfaces simultaneously.
1124 const struct isl_view
*view
;
1127 * The address of the depth surface in GPU memory
1129 uint64_t depth_address
;
1132 * The address of the stencil surface in GPU memory
1134 * If separate stencil is not available, this must have the same value as
1137 uint64_t stencil_address
;
1140 * The Memory Object Control state for depth and stencil buffers
1142 * Both depth and stencil will get the same MOCS value. The exact format
1143 * of this value depends on hardware generation.
1148 * The HiZ surface or NULL if HiZ is disabled.
1150 const struct isl_surf
*hiz_surf
;
1151 enum isl_aux_usage hiz_usage
;
1152 uint64_t hiz_address
;
1155 * The depth clear value
1157 float depth_clear_value
;
1160 extern const struct isl_format_layout isl_format_layouts
[];
1163 isl_device_init(struct isl_device
*dev
,
1164 const struct gen_device_info
*info
,
1165 bool has_bit6_swizzling
);
1167 isl_sample_count_mask_t ATTRIBUTE_CONST
1168 isl_device_get_sample_counts(struct isl_device
*dev
);
1170 static inline const struct isl_format_layout
* ATTRIBUTE_CONST
1171 isl_format_get_layout(enum isl_format fmt
)
1173 return &isl_format_layouts
[fmt
];
1176 static inline const char * ATTRIBUTE_CONST
1177 isl_format_get_name(enum isl_format fmt
)
1179 return isl_format_layouts
[fmt
].name
;
1182 bool isl_format_supports_rendering(const struct gen_device_info
*devinfo
,
1183 enum isl_format format
);
1184 bool isl_format_supports_alpha_blending(const struct gen_device_info
*devinfo
,
1185 enum isl_format format
);
1186 bool isl_format_supports_sampling(const struct gen_device_info
*devinfo
,
1187 enum isl_format format
);
1188 bool isl_format_supports_filtering(const struct gen_device_info
*devinfo
,
1189 enum isl_format format
);
1190 bool isl_format_supports_vertex_fetch(const struct gen_device_info
*devinfo
,
1191 enum isl_format format
);
1192 bool isl_format_supports_typed_writes(const struct gen_device_info
*devinfo
,
1193 enum isl_format format
);
1194 bool isl_format_supports_typed_reads(const struct gen_device_info
*devinfo
,
1195 enum isl_format format
);
1196 bool isl_format_supports_ccs_d(const struct gen_device_info
*devinfo
,
1197 enum isl_format format
);
1198 bool isl_format_supports_ccs_e(const struct gen_device_info
*devinfo
,
1199 enum isl_format format
);
1200 bool isl_format_supports_multisampling(const struct gen_device_info
*devinfo
,
1201 enum isl_format format
);
1203 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info
*devinfo
,
1204 enum isl_format format1
,
1205 enum isl_format format2
);
1207 bool isl_format_has_unorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1208 bool isl_format_has_snorm_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1209 bool isl_format_has_ufloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1210 bool isl_format_has_sfloat_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1211 bool isl_format_has_uint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1212 bool isl_format_has_sint_channel(enum isl_format fmt
) ATTRIBUTE_CONST
;
1215 isl_format_has_normalized_channel(enum isl_format fmt
)
1217 return isl_format_has_unorm_channel(fmt
) ||
1218 isl_format_has_snorm_channel(fmt
);
1222 isl_format_has_float_channel(enum isl_format fmt
)
1224 return isl_format_has_ufloat_channel(fmt
) ||
1225 isl_format_has_sfloat_channel(fmt
);
1229 isl_format_has_int_channel(enum isl_format fmt
)
1231 return isl_format_has_uint_channel(fmt
) ||
1232 isl_format_has_sint_channel(fmt
);
1235 unsigned isl_format_get_num_channels(enum isl_format fmt
);
1237 uint32_t isl_format_get_depth_format(enum isl_format fmt
, bool has_stencil
);
1240 isl_format_is_compressed(enum isl_format fmt
)
1242 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1244 return fmtl
->txc
!= ISL_TXC_NONE
;
1248 isl_format_has_bc_compression(enum isl_format fmt
)
1250 switch (isl_format_get_layout(fmt
)->txc
) {
1268 unreachable("Should not be called on an aux surface");
1271 unreachable("bad texture compression mode");
1276 isl_format_is_yuv(enum isl_format fmt
)
1278 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1280 return fmtl
->colorspace
== ISL_COLORSPACE_YUV
;
1284 isl_format_block_is_1x1x1(enum isl_format fmt
)
1286 const struct isl_format_layout
*fmtl
= isl_format_get_layout(fmt
);
1288 return fmtl
->bw
== 1 && fmtl
->bh
== 1 && fmtl
->bd
== 1;
1292 isl_format_is_rgb(enum isl_format fmt
)
1294 return isl_format_layouts
[fmt
].channels
.r
.bits
> 0 &&
1295 isl_format_layouts
[fmt
].channels
.g
.bits
> 0 &&
1296 isl_format_layouts
[fmt
].channels
.b
.bits
> 0 &&
1297 isl_format_layouts
[fmt
].channels
.a
.bits
== 0;
1300 enum isl_format
isl_format_rgb_to_rgba(enum isl_format rgb
) ATTRIBUTE_CONST
;
1301 enum isl_format
isl_format_rgb_to_rgbx(enum isl_format rgb
) ATTRIBUTE_CONST
;
1303 bool isl_is_storage_image_format(enum isl_format fmt
);
1306 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
1307 enum isl_format fmt
);
1309 /* Returns true if this hardware supports typed load/store on a format with
1310 * the same size as the given format.
1313 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
1314 enum isl_format fmt
);
1317 isl_tiling_is_any_y(enum isl_tiling tiling
)
1319 return (1u << tiling
) & ISL_TILING_ANY_Y_MASK
;
1323 isl_tiling_is_std_y(enum isl_tiling tiling
)
1325 return (1u << tiling
) & ISL_TILING_STD_Y_MASK
;
1328 struct isl_extent2d ATTRIBUTE_CONST
1329 isl_get_interleaved_msaa_px_size_sa(uint32_t samples
);
1332 isl_surf_usage_is_display(isl_surf_usage_flags_t usage
)
1334 return usage
& ISL_SURF_USAGE_DISPLAY_BIT
;
1338 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage
)
1340 return usage
& ISL_SURF_USAGE_DEPTH_BIT
;
1344 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage
)
1346 return usage
& ISL_SURF_USAGE_STENCIL_BIT
;
1350 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage
)
1352 return (usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1353 (usage
& ISL_SURF_USAGE_STENCIL_BIT
);
1357 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage
)
1359 return usage
& (ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
);
1363 isl_surf_info_is_z16(const struct isl_surf_init_info
*info
)
1365 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1366 (info
->format
== ISL_FORMAT_R16_UNORM
);
1370 isl_surf_info_is_z32_float(const struct isl_surf_init_info
*info
)
1372 return (info
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) &&
1373 (info
->format
== ISL_FORMAT_R32_FLOAT
);
1376 static inline struct isl_extent2d
1377 isl_extent2d(uint32_t width
, uint32_t height
)
1379 struct isl_extent2d e
= { { 0 } };
1387 static inline struct isl_extent3d
1388 isl_extent3d(uint32_t width
, uint32_t height
, uint32_t depth
)
1390 struct isl_extent3d e
= { { 0 } };
1399 static inline struct isl_extent4d
1400 isl_extent4d(uint32_t width
, uint32_t height
, uint32_t depth
,
1403 struct isl_extent4d e
= { { 0 } };
1408 e
.array_len
= array_len
;
1413 #define isl_surf_init(dev, surf, ...) \
1414 isl_surf_init_s((dev), (surf), \
1415 &(struct isl_surf_init_info) { __VA_ARGS__ });
1418 isl_surf_init_s(const struct isl_device
*dev
,
1419 struct isl_surf
*surf
,
1420 const struct isl_surf_init_info
*restrict info
);
1423 isl_surf_get_tile_info(const struct isl_surf
*surf
,
1424 struct isl_tile_info
*tile_info
);
1427 isl_surf_get_hiz_surf(const struct isl_device
*dev
,
1428 const struct isl_surf
*surf
,
1429 struct isl_surf
*hiz_surf
);
1432 isl_surf_get_mcs_surf(const struct isl_device
*dev
,
1433 const struct isl_surf
*surf
,
1434 struct isl_surf
*mcs_surf
);
1437 isl_surf_get_ccs_surf(const struct isl_device
*dev
,
1438 const struct isl_surf
*surf
,
1439 struct isl_surf
*ccs_surf
);
1441 #define isl_surf_fill_state(dev, state, ...) \
1442 isl_surf_fill_state_s((dev), (state), \
1443 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1446 isl_surf_fill_state_s(const struct isl_device
*dev
, void *state
,
1447 const struct isl_surf_fill_state_info
*restrict info
);
1449 #define isl_buffer_fill_state(dev, state, ...) \
1450 isl_buffer_fill_state_s((dev), (state), \
1451 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1454 isl_buffer_fill_state_s(const struct isl_device
*dev
, void *state
,
1455 const struct isl_buffer_fill_state_info
*restrict info
);
1457 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1458 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1459 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1462 isl_emit_depth_stencil_hiz_s(const struct isl_device
*dev
, void *batch
,
1463 const struct isl_depth_stencil_hiz_emit_info
*restrict info
);
1466 isl_surf_fill_image_param(const struct isl_device
*dev
,
1467 struct brw_image_param
*param
,
1468 const struct isl_surf
*surf
,
1469 const struct isl_view
*view
);
1472 isl_buffer_fill_image_param(const struct isl_device
*dev
,
1473 struct brw_image_param
*param
,
1474 enum isl_format format
,
1478 * Alignment of the upper-left sample of each subimage, in units of surface
1481 static inline struct isl_extent3d
1482 isl_surf_get_image_alignment_el(const struct isl_surf
*surf
)
1484 return surf
->image_alignment_el
;
1488 * Alignment of the upper-left sample of each subimage, in units of surface
1491 static inline struct isl_extent3d
1492 isl_surf_get_image_alignment_sa(const struct isl_surf
*surf
)
1494 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1496 return isl_extent3d(fmtl
->bw
* surf
->image_alignment_el
.w
,
1497 fmtl
->bh
* surf
->image_alignment_el
.h
,
1498 fmtl
->bd
* surf
->image_alignment_el
.d
);
1502 * Pitch between vertically adjacent surface elements, in bytes.
1504 static inline uint32_t
1505 isl_surf_get_row_pitch(const struct isl_surf
*surf
)
1507 return surf
->row_pitch
;
1511 * Pitch between vertically adjacent surface elements, in units of surface elements.
1513 static inline uint32_t
1514 isl_surf_get_row_pitch_el(const struct isl_surf
*surf
)
1516 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1518 assert(surf
->row_pitch
% (fmtl
->bpb
/ 8) == 0);
1519 return surf
->row_pitch
/ (fmtl
->bpb
/ 8);
1523 * Pitch between physical array slices, in rows of surface elements.
1525 static inline uint32_t
1526 isl_surf_get_array_pitch_el_rows(const struct isl_surf
*surf
)
1528 return surf
->array_pitch_el_rows
;
1532 * Pitch between physical array slices, in units of surface elements.
1534 static inline uint32_t
1535 isl_surf_get_array_pitch_el(const struct isl_surf
*surf
)
1537 return isl_surf_get_array_pitch_el_rows(surf
) *
1538 isl_surf_get_row_pitch_el(surf
);
1542 * Pitch between physical array slices, in rows of surface samples.
1544 static inline uint32_t
1545 isl_surf_get_array_pitch_sa_rows(const struct isl_surf
*surf
)
1547 const struct isl_format_layout
*fmtl
= isl_format_get_layout(surf
->format
);
1548 return fmtl
->bh
* isl_surf_get_array_pitch_el_rows(surf
);
1552 * Pitch between physical array slices, in bytes.
1554 static inline uint32_t
1555 isl_surf_get_array_pitch(const struct isl_surf
*surf
)
1557 return isl_surf_get_array_pitch_sa_rows(surf
) * surf
->row_pitch
;
1561 * Calculate the offset, in units of surface samples, to a subimage in the
1564 * @invariant level < surface levels
1565 * @invariant logical_array_layer < logical array length of surface
1566 * @invariant logical_z_offset_px < logical depth of surface at level
1569 isl_surf_get_image_offset_sa(const struct isl_surf
*surf
,
1571 uint32_t logical_array_layer
,
1572 uint32_t logical_z_offset_px
,
1573 uint32_t *x_offset_sa
,
1574 uint32_t *y_offset_sa
);
1577 * Calculate the offset, in units of surface elements, to a subimage in the
1580 * @invariant level < surface levels
1581 * @invariant logical_array_layer < logical array length of surface
1582 * @invariant logical_z_offset_px < logical depth of surface at level
1585 isl_surf_get_image_offset_el(const struct isl_surf
*surf
,
1587 uint32_t logical_array_layer
,
1588 uint32_t logical_z_offset_px
,
1589 uint32_t *x_offset_el
,
1590 uint32_t *y_offset_el
);
1593 * Calculate the offset, in bytes and intratile surface samples, to a
1594 * subimage in the surface.
1596 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
1597 * result to isl_tiling_get_intratile_offset_el, and converting the tile
1598 * offsets to samples.
1600 * @invariant level < surface levels
1601 * @invariant logical_array_layer < logical array length of surface
1602 * @invariant logical_z_offset_px < logical depth of surface at level
1605 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf
*surf
,
1607 uint32_t logical_array_layer
,
1608 uint32_t logical_z_offset_px
,
1610 uint32_t *x_offset_sa
,
1611 uint32_t *y_offset_sa
);
1614 * @brief Calculate the intratile offsets to a surface.
1616 * In @a base_address_offset return the offset from the base of the surface to
1617 * the base address of the first tile of the subimage. In @a x_offset_B and
1618 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
1619 * tile's base to the subimage's first surface element. The x and y offsets
1620 * are intratile offsets; that is, they do not exceed the boundary of the
1621 * surface's tiling format.
1624 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling
,
1627 uint32_t total_x_offset_el
,
1628 uint32_t total_y_offset_el
,
1629 uint32_t *base_address_offset
,
1630 uint32_t *x_offset_el
,
1631 uint32_t *y_offset_el
);
1634 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling
,
1635 enum isl_format format
,
1637 uint32_t total_x_offset_sa
,
1638 uint32_t total_y_offset_sa
,
1639 uint32_t *base_address_offset
,
1640 uint32_t *x_offset_sa
,
1641 uint32_t *y_offset_sa
)
1643 const struct isl_format_layout
*fmtl
= isl_format_get_layout(format
);
1645 /* For computing the intratile offsets, we actually want a strange unit
1646 * which is samples for multisampled surfaces but elements for compressed
1649 assert(total_x_offset_sa
% fmtl
->bw
== 0);
1650 assert(total_y_offset_sa
% fmtl
->bh
== 0);
1651 const uint32_t total_x_offset
= total_x_offset_sa
/ fmtl
->bw
;
1652 const uint32_t total_y_offset
= total_y_offset_sa
/ fmtl
->bh
;
1654 isl_tiling_get_intratile_offset_el(tiling
, fmtl
->bpb
, row_pitch
,
1655 total_x_offset
, total_y_offset
,
1656 base_address_offset
,
1657 x_offset_sa
, y_offset_sa
);
1658 *x_offset_sa
*= fmtl
->bw
;
1659 *y_offset_sa
*= fmtl
->bh
;
1663 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
1665 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
1666 * @pre surf->format must be a valid format for depth surfaces
1669 isl_surf_get_depth_format(const struct isl_device
*dev
,
1670 const struct isl_surf
*surf
);