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intel/isl: Add isl_format_has_color_component() function.
[mesa.git] / src / intel / isl / isl.h
1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "c99_compat.h"
46 #include "util/macros.h"
47
48 #ifdef __cplusplus
49 extern "C" {
50 #endif
51
52 struct gen_device_info;
53 struct brw_image_param;
54
55 #ifndef ISL_DEV_GEN
56 /**
57 * @brief Get the hardware generation of isl_device.
58 *
59 * You can define this as a compile-time constant in the CFLAGS. For example,
60 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
61 */
62 #define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
63 #define ISL_DEV_GEN_SANITIZE(__dev)
64 #else
65 #define ISL_DEV_GEN_SANITIZE(__dev) \
66 (assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
67 #endif
68
69 #ifndef ISL_DEV_IS_G4X
70 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->is_g4x)
71 #endif
72
73 #ifndef ISL_DEV_IS_HASWELL
74 /**
75 * @brief Get the hardware generation of isl_device.
76 *
77 * You can define this as a compile-time constant in the CFLAGS. For example,
78 * `gcc -DISL_DEV_GEN(dev)=9 ...`.
79 */
80 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->is_haswell)
81 #endif
82
83 #ifndef ISL_DEV_IS_BAYTRAIL
84 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
85 #endif
86
87 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
88 /**
89 * You can define this as a compile-time constant in the CFLAGS. For example,
90 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
91 */
92 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
93 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
94 #else
95 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
96 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
97 #endif
98
99 /**
100 * Hardware enumeration SURFACE_FORMAT.
101 *
102 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
103 * Enumerations: SURFACE_FORMAT.
104 */
105 enum isl_format {
106 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
107 ISL_FORMAT_R32G32B32A32_SINT = 1,
108 ISL_FORMAT_R32G32B32A32_UINT = 2,
109 ISL_FORMAT_R32G32B32A32_UNORM = 3,
110 ISL_FORMAT_R32G32B32A32_SNORM = 4,
111 ISL_FORMAT_R64G64_FLOAT = 5,
112 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
113 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
114 ISL_FORMAT_R32G32B32A32_USCALED = 8,
115 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
116 ISL_FORMAT_R64G64_PASSTHRU = 33,
117 ISL_FORMAT_R32G32B32_FLOAT = 64,
118 ISL_FORMAT_R32G32B32_SINT = 65,
119 ISL_FORMAT_R32G32B32_UINT = 66,
120 ISL_FORMAT_R32G32B32_UNORM = 67,
121 ISL_FORMAT_R32G32B32_SNORM = 68,
122 ISL_FORMAT_R32G32B32_SSCALED = 69,
123 ISL_FORMAT_R32G32B32_USCALED = 70,
124 ISL_FORMAT_R32G32B32_SFIXED = 80,
125 ISL_FORMAT_R16G16B16A16_UNORM = 128,
126 ISL_FORMAT_R16G16B16A16_SNORM = 129,
127 ISL_FORMAT_R16G16B16A16_SINT = 130,
128 ISL_FORMAT_R16G16B16A16_UINT = 131,
129 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
130 ISL_FORMAT_R32G32_FLOAT = 133,
131 ISL_FORMAT_R32G32_SINT = 134,
132 ISL_FORMAT_R32G32_UINT = 135,
133 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
134 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
135 ISL_FORMAT_L32A32_FLOAT = 138,
136 ISL_FORMAT_R32G32_UNORM = 139,
137 ISL_FORMAT_R32G32_SNORM = 140,
138 ISL_FORMAT_R64_FLOAT = 141,
139 ISL_FORMAT_R16G16B16X16_UNORM = 142,
140 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
141 ISL_FORMAT_A32X32_FLOAT = 144,
142 ISL_FORMAT_L32X32_FLOAT = 145,
143 ISL_FORMAT_I32X32_FLOAT = 146,
144 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
145 ISL_FORMAT_R16G16B16A16_USCALED = 148,
146 ISL_FORMAT_R32G32_SSCALED = 149,
147 ISL_FORMAT_R32G32_USCALED = 150,
148 ISL_FORMAT_R32G32_FLOAT_LD = 151,
149 ISL_FORMAT_R32G32_SFIXED = 160,
150 ISL_FORMAT_R64_PASSTHRU = 161,
151 ISL_FORMAT_B8G8R8A8_UNORM = 192,
152 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
153 ISL_FORMAT_R10G10B10A2_UNORM = 194,
154 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
155 ISL_FORMAT_R10G10B10A2_UINT = 196,
156 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
157 ISL_FORMAT_R8G8B8A8_UNORM = 199,
158 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
159 ISL_FORMAT_R8G8B8A8_SNORM = 201,
160 ISL_FORMAT_R8G8B8A8_SINT = 202,
161 ISL_FORMAT_R8G8B8A8_UINT = 203,
162 ISL_FORMAT_R16G16_UNORM = 204,
163 ISL_FORMAT_R16G16_SNORM = 205,
164 ISL_FORMAT_R16G16_SINT = 206,
165 ISL_FORMAT_R16G16_UINT = 207,
166 ISL_FORMAT_R16G16_FLOAT = 208,
167 ISL_FORMAT_B10G10R10A2_UNORM = 209,
168 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
169 ISL_FORMAT_R11G11B10_FLOAT = 211,
170 ISL_FORMAT_R32_SINT = 214,
171 ISL_FORMAT_R32_UINT = 215,
172 ISL_FORMAT_R32_FLOAT = 216,
173 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
174 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
175 ISL_FORMAT_L32_UNORM = 221,
176 ISL_FORMAT_A32_UNORM = 222,
177 ISL_FORMAT_L16A16_UNORM = 223,
178 ISL_FORMAT_I24X8_UNORM = 224,
179 ISL_FORMAT_L24X8_UNORM = 225,
180 ISL_FORMAT_A24X8_UNORM = 226,
181 ISL_FORMAT_I32_FLOAT = 227,
182 ISL_FORMAT_L32_FLOAT = 228,
183 ISL_FORMAT_A32_FLOAT = 229,
184 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
185 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
186 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
187 ISL_FORMAT_B8G8R8X8_UNORM = 233,
188 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
189 ISL_FORMAT_R8G8B8X8_UNORM = 235,
190 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
191 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
192 ISL_FORMAT_B10G10R10X2_UNORM = 238,
193 ISL_FORMAT_L16A16_FLOAT = 240,
194 ISL_FORMAT_R32_UNORM = 241,
195 ISL_FORMAT_R32_SNORM = 242,
196 ISL_FORMAT_R10G10B10X2_USCALED = 243,
197 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
198 ISL_FORMAT_R8G8B8A8_USCALED = 245,
199 ISL_FORMAT_R16G16_SSCALED = 246,
200 ISL_FORMAT_R16G16_USCALED = 247,
201 ISL_FORMAT_R32_SSCALED = 248,
202 ISL_FORMAT_R32_USCALED = 249,
203 ISL_FORMAT_B5G6R5_UNORM = 256,
204 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
205 ISL_FORMAT_B5G5R5A1_UNORM = 258,
206 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
207 ISL_FORMAT_B4G4R4A4_UNORM = 260,
208 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
209 ISL_FORMAT_R8G8_UNORM = 262,
210 ISL_FORMAT_R8G8_SNORM = 263,
211 ISL_FORMAT_R8G8_SINT = 264,
212 ISL_FORMAT_R8G8_UINT = 265,
213 ISL_FORMAT_R16_UNORM = 266,
214 ISL_FORMAT_R16_SNORM = 267,
215 ISL_FORMAT_R16_SINT = 268,
216 ISL_FORMAT_R16_UINT = 269,
217 ISL_FORMAT_R16_FLOAT = 270,
218 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
219 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
220 ISL_FORMAT_I16_UNORM = 273,
221 ISL_FORMAT_L16_UNORM = 274,
222 ISL_FORMAT_A16_UNORM = 275,
223 ISL_FORMAT_L8A8_UNORM = 276,
224 ISL_FORMAT_I16_FLOAT = 277,
225 ISL_FORMAT_L16_FLOAT = 278,
226 ISL_FORMAT_A16_FLOAT = 279,
227 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
228 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
229 ISL_FORMAT_B5G5R5X1_UNORM = 282,
230 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
231 ISL_FORMAT_R8G8_SSCALED = 284,
232 ISL_FORMAT_R8G8_USCALED = 285,
233 ISL_FORMAT_R16_SSCALED = 286,
234 ISL_FORMAT_R16_USCALED = 287,
235 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
236 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
237 ISL_FORMAT_A1B5G5R5_UNORM = 292,
238 ISL_FORMAT_A4B4G4R4_UNORM = 293,
239 ISL_FORMAT_L8A8_UINT = 294,
240 ISL_FORMAT_L8A8_SINT = 295,
241 ISL_FORMAT_R8_UNORM = 320,
242 ISL_FORMAT_R8_SNORM = 321,
243 ISL_FORMAT_R8_SINT = 322,
244 ISL_FORMAT_R8_UINT = 323,
245 ISL_FORMAT_A8_UNORM = 324,
246 ISL_FORMAT_I8_UNORM = 325,
247 ISL_FORMAT_L8_UNORM = 326,
248 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
249 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
250 ISL_FORMAT_R8_SSCALED = 329,
251 ISL_FORMAT_R8_USCALED = 330,
252 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
253 ISL_FORMAT_L8_UNORM_SRGB = 332,
254 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
255 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
256 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
257 ISL_FORMAT_Y8_UNORM = 336,
258 ISL_FORMAT_L8_UINT = 338,
259 ISL_FORMAT_L8_SINT = 339,
260 ISL_FORMAT_I8_UINT = 340,
261 ISL_FORMAT_I8_SINT = 341,
262 ISL_FORMAT_DXT1_RGB_SRGB = 384,
263 ISL_FORMAT_R1_UNORM = 385,
264 ISL_FORMAT_YCRCB_NORMAL = 386,
265 ISL_FORMAT_YCRCB_SWAPUVY = 387,
266 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
267 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
268 ISL_FORMAT_BC1_UNORM = 390,
269 ISL_FORMAT_BC2_UNORM = 391,
270 ISL_FORMAT_BC3_UNORM = 392,
271 ISL_FORMAT_BC4_UNORM = 393,
272 ISL_FORMAT_BC5_UNORM = 394,
273 ISL_FORMAT_BC1_UNORM_SRGB = 395,
274 ISL_FORMAT_BC2_UNORM_SRGB = 396,
275 ISL_FORMAT_BC3_UNORM_SRGB = 397,
276 ISL_FORMAT_MONO8 = 398,
277 ISL_FORMAT_YCRCB_SWAPUV = 399,
278 ISL_FORMAT_YCRCB_SWAPY = 400,
279 ISL_FORMAT_DXT1_RGB = 401,
280 ISL_FORMAT_FXT1 = 402,
281 ISL_FORMAT_R8G8B8_UNORM = 403,
282 ISL_FORMAT_R8G8B8_SNORM = 404,
283 ISL_FORMAT_R8G8B8_SSCALED = 405,
284 ISL_FORMAT_R8G8B8_USCALED = 406,
285 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
286 ISL_FORMAT_R64G64B64_FLOAT = 408,
287 ISL_FORMAT_BC4_SNORM = 409,
288 ISL_FORMAT_BC5_SNORM = 410,
289 ISL_FORMAT_R16G16B16_FLOAT = 411,
290 ISL_FORMAT_R16G16B16_UNORM = 412,
291 ISL_FORMAT_R16G16B16_SNORM = 413,
292 ISL_FORMAT_R16G16B16_SSCALED = 414,
293 ISL_FORMAT_R16G16B16_USCALED = 415,
294 ISL_FORMAT_BC6H_SF16 = 417,
295 ISL_FORMAT_BC7_UNORM = 418,
296 ISL_FORMAT_BC7_UNORM_SRGB = 419,
297 ISL_FORMAT_BC6H_UF16 = 420,
298 ISL_FORMAT_PLANAR_420_8 = 421,
299 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
300 ISL_FORMAT_ETC1_RGB8 = 425,
301 ISL_FORMAT_ETC2_RGB8 = 426,
302 ISL_FORMAT_EAC_R11 = 427,
303 ISL_FORMAT_EAC_RG11 = 428,
304 ISL_FORMAT_EAC_SIGNED_R11 = 429,
305 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
306 ISL_FORMAT_ETC2_SRGB8 = 431,
307 ISL_FORMAT_R16G16B16_UINT = 432,
308 ISL_FORMAT_R16G16B16_SINT = 433,
309 ISL_FORMAT_R32_SFIXED = 434,
310 ISL_FORMAT_R10G10B10A2_SNORM = 435,
311 ISL_FORMAT_R10G10B10A2_USCALED = 436,
312 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
313 ISL_FORMAT_R10G10B10A2_SINT = 438,
314 ISL_FORMAT_B10G10R10A2_SNORM = 439,
315 ISL_FORMAT_B10G10R10A2_USCALED = 440,
316 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
317 ISL_FORMAT_B10G10R10A2_UINT = 442,
318 ISL_FORMAT_B10G10R10A2_SINT = 443,
319 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
320 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
321 ISL_FORMAT_ETC2_RGB8_PTA = 448,
322 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
323 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
324 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
325 ISL_FORMAT_R8G8B8_UINT = 456,
326 ISL_FORMAT_R8G8B8_SINT = 457,
327 ISL_FORMAT_RAW = 511,
328 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
329 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
330 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
331 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
332 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
333 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
334 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
335 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
336 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
337 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
338 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
339 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
340 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
341 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
342 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
343 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
344 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
345 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
346 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
347 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
348 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
349 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
350 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
351 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
352 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
353 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
354 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
355 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
356 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
357 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
358 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
359 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
360 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
361 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
362 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
363 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
364 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
365 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
366 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
367 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
368 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
369 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
370
371 /* The formats that follow are internal to ISL and as such don't have an
372 * explicit number. We'll just let the C compiler assign it for us. Any
373 * actual hardware formats *must* come before these in the list.
374 */
375
376 /* Formats for auxiliary surfaces */
377 ISL_FORMAT_HIZ,
378 ISL_FORMAT_MCS_2X,
379 ISL_FORMAT_MCS_4X,
380 ISL_FORMAT_MCS_8X,
381 ISL_FORMAT_MCS_16X,
382 ISL_FORMAT_GEN7_CCS_32BPP_X,
383 ISL_FORMAT_GEN7_CCS_64BPP_X,
384 ISL_FORMAT_GEN7_CCS_128BPP_X,
385 ISL_FORMAT_GEN7_CCS_32BPP_Y,
386 ISL_FORMAT_GEN7_CCS_64BPP_Y,
387 ISL_FORMAT_GEN7_CCS_128BPP_Y,
388 ISL_FORMAT_GEN9_CCS_32BPP,
389 ISL_FORMAT_GEN9_CCS_64BPP,
390 ISL_FORMAT_GEN9_CCS_128BPP,
391
392 /* An upper bound on the supported format enumerations */
393 ISL_NUM_FORMATS,
394
395 /* Hardware doesn't understand this out-of-band value */
396 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
397 };
398
399 /**
400 * Numerical base type for channels of isl_format.
401 */
402 enum isl_base_type {
403 ISL_VOID,
404 ISL_RAW,
405 ISL_UNORM,
406 ISL_SNORM,
407 ISL_UFLOAT,
408 ISL_SFLOAT,
409 ISL_UFIXED,
410 ISL_SFIXED,
411 ISL_UINT,
412 ISL_SINT,
413 ISL_USCALED,
414 ISL_SSCALED,
415 };
416
417 /**
418 * Colorspace of isl_format.
419 */
420 enum isl_colorspace {
421 ISL_COLORSPACE_NONE = 0,
422 ISL_COLORSPACE_LINEAR,
423 ISL_COLORSPACE_SRGB,
424 ISL_COLORSPACE_YUV,
425 };
426
427 /**
428 * Texture compression mode of isl_format.
429 */
430 enum isl_txc {
431 ISL_TXC_NONE = 0,
432 ISL_TXC_DXT1,
433 ISL_TXC_DXT3,
434 ISL_TXC_DXT5,
435 ISL_TXC_FXT1,
436 ISL_TXC_RGTC1,
437 ISL_TXC_RGTC2,
438 ISL_TXC_BPTC,
439 ISL_TXC_ETC1,
440 ISL_TXC_ETC2,
441 ISL_TXC_ASTC,
442
443 /* Used for auxiliary surface formats */
444 ISL_TXC_HIZ,
445 ISL_TXC_MCS,
446 ISL_TXC_CCS,
447 };
448
449 /**
450 * @brief Hardware tile mode
451 *
452 * WARNING: These values differ from the hardware enum values, which are
453 * unstable across hardware generations.
454 *
455 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
456 * clearly distinguish it from Yf and Ys.
457 */
458 enum isl_tiling {
459 ISL_TILING_LINEAR = 0,
460 ISL_TILING_W,
461 ISL_TILING_X,
462 ISL_TILING_Y0, /**< Legacy Y tiling */
463 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
464 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
465 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
466 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
467 };
468
469 /**
470 * @defgroup Tiling Flags
471 * @{
472 */
473 typedef uint32_t isl_tiling_flags_t;
474 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
475 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
476 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
477 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
478 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
479 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
480 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
481 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
482 #define ISL_TILING_ANY_MASK (~0u)
483 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
484
485 /** Any Y tiling, including legacy Y tiling. */
486 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
487 ISL_TILING_Yf_BIT | \
488 ISL_TILING_Ys_BIT)
489
490 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
491 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
492 ISL_TILING_Ys_BIT)
493 /** @} */
494
495 /**
496 * @brief Logical dimension of surface.
497 *
498 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
499 * as 2D array surfaces.
500 */
501 enum isl_surf_dim {
502 ISL_SURF_DIM_1D,
503 ISL_SURF_DIM_2D,
504 ISL_SURF_DIM_3D,
505 };
506
507 /**
508 * @brief Physical layout of the surface's dimensions.
509 */
510 enum isl_dim_layout {
511 /**
512 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
513 * 6.17.3: 2D Surfaces.
514 *
515 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
516 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
517 *
518 * One-dimensional surfaces are identical to 2D surfaces with height of
519 * one.
520 *
521 * @invariant isl_surf::phys_level0_sa::depth == 1
522 */
523 ISL_DIM_LAYOUT_GEN4_2D,
524
525 /**
526 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
527 * 6.17.5: 3D Surfaces.
528 *
529 * @invariant isl_surf::phys_level0_sa::array_len == 1
530 */
531 ISL_DIM_LAYOUT_GEN4_3D,
532
533 /**
534 * Special layout used for HiZ and stencil on Sandy Bridge to work around
535 * the hardware's lack of mipmap support. On gen6, HiZ and stencil buffers
536 * work the same as on gen7+ except that they don't technically support
537 * mipmapping. That does not, however, stop us from doing it. As far as
538 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
539 * single miplevel 2D (possibly array) image. The dimensions of that image
540 * are NOT minified.
541 *
542 * In order to implement HiZ and stencil on Sandy Bridge, we create one
543 * full-sized 2D (possibly array) image for every LOD with every image
544 * aligned to a page boundary. When the surface is used with the stencil
545 * or HiZ hardware, we manually offset to the image for the given LOD.
546 *
547 * As a memory saving measure, we pretend that the width of each miplevel
548 * is minified and we place LOD1 and above below LOD0 but horizontally
549 * adjacent to each other. When considered as full-sized images, LOD1 and
550 * above technically overlap. However, since we only write to part of that
551 * image, the hardware will never notice the overlap.
552 *
553 * This layout looks something like this:
554 *
555 * +---------+
556 * | |
557 * | |
558 * +---------+
559 * | |
560 * | |
561 * +---------+
562 *
563 * +----+ +-+ .
564 * | | +-+
565 * +----+
566 *
567 * +----+ +-+ .
568 * | | +-+
569 * +----+
570 */
571 ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ,
572
573 /**
574 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
575 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
576 */
577 ISL_DIM_LAYOUT_GEN9_1D,
578 };
579
580 enum isl_aux_usage {
581 /** No Auxiliary surface is used */
582 ISL_AUX_USAGE_NONE,
583
584 /** The primary surface is a depth surface and the auxiliary surface is HiZ */
585 ISL_AUX_USAGE_HIZ,
586
587 /** The auxiliary surface is an MCS
588 *
589 * @invariant isl_surf::samples > 1
590 */
591 ISL_AUX_USAGE_MCS,
592
593 /** The auxiliary surface is a fast-clear-only compression surface
594 *
595 * @invariant isl_surf::samples == 1
596 */
597 ISL_AUX_USAGE_CCS_D,
598
599 /** The auxiliary surface provides full lossless color compression
600 *
601 * @invariant isl_surf::samples == 1
602 */
603 ISL_AUX_USAGE_CCS_E,
604 };
605
606 /**
607 * Enum for keeping track of the state an auxiliary compressed surface.
608 *
609 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
610 * given slice (lod + array layer) can be in one of the six states described
611 * by this enum. Draw and resolve operations may cause the slice to change
612 * from one state to another. The six valid states are:
613 *
614 * 1) Clear: In this state, each block in the auxiliary surface contains a
615 * magic value that indicates that the block is in the clear state. If
616 * a block is in the clear state, it's values in the primary surface are
617 * ignored and the color of the samples in the block is taken either the
618 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for
619 * depth. Since neither the primary surface nor the auxiliary surface
620 * contains the clear value, the surface can be cleared to a different
621 * color by simply changing the clear color without modifying either
622 * surface.
623 *
624 * 2) Partial Clear: In this state, each block in the auxiliary surface
625 * contains either the magic clear or pass-through value. See Clear and
626 * Pass-through for more details.
627 *
628 * 3) Compressed w/ Clear: In this state, neither the auxiliary surface
629 * nor the primary surface has a complete representation of the data.
630 * Instead, both surfaces must be used together or else rendering
631 * corruption may occur. Depending on the auxiliary compression format
632 * and the data, any given block in the primary surface may contain all,
633 * some, or none of the data required to reconstruct the actual sample
634 * values. Blocks may also be in the clear state (see Clear) and have
635 * their value taken from outside the surface.
636 *
637 * 4) Compressed w/o Clear: This state is identical to the state above
638 * except that no blocks are in the clear state. In this state, all of
639 * the data required to reconstruct the final sample values is contained
640 * in the auxiliary and primary surface and the clear value is not
641 * considered.
642 *
643 * 5) Resolved: In this state, the primary surface contains 100% of the
644 * data. The auxiliary surface is also valid so the surface can be
645 * validly used with or without aux enabled. The auxiliary surface may,
646 * however, contain non-trivial data and any update to the primary
647 * surface with aux disabled will cause the two to get out of sync.
648 *
649 * 6) Pass-through: In this state, the primary surface contains 100% of the
650 * data and every block in the auxiliary surface contains a magic value
651 * which indicates that the auxiliary surface should be ignored and the
652 * only the primary surface should be considered. Updating the primary
653 * surface without aux works fine and can be done repeatedly in this
654 * mode. Writing to a surface in pass-through mode with aux enabled may
655 * cause the auxiliary buffer to contain non-trivial data and no longer
656 * be in the pass-through state.
657 *
658 * 7) Aux Invalid: In this state, the primary surface contains 100% of the
659 * data and the auxiliary surface is completely bogus. Any attempt to
660 * use the auxiliary surface is liable to result in rendering
661 * corruption. The only thing that one can do to re-enable aux once
662 * this state is reached is to use an ambiguate pass to transition into
663 * the pass-through state.
664 *
665 * Drawing with or without aux enabled may implicitly cause the surface to
666 * transition between these states. There are also four types of auxiliary
667 * compression operations which cause an explicit transition which are
668 * described by the isl_aux_op enum below.
669 *
670 * Not all operations are valid or useful in all states. The diagram below
671 * contains a complete description of the states and all valid and useful
672 * transitions except clear.
673 *
674 * Draw w/ Aux
675 * +----------+
676 * | |
677 * | +-------------+ Draw w/ Aux +-------------+
678 * +------>| Compressed |<-------------------| Clear |
679 * | w/ Clear |----->----+ | |
680 * +-------------+ | +-------------+
681 * | /|\ | | |
682 * | | | | |
683 * | | +------<-----+ | Draw w/
684 * | | | | Clear Only
685 * | | Full | | +----------+
686 * Partial | | Resolve | \|/ | |
687 * Resolve | | | +-------------+ |
688 * | | | | Partial |<------+
689 * | | | | Clear |<----------+
690 * | | | +-------------+ |
691 * | | | | |
692 * | | +------>---------+ Full |
693 * | | | Resolve |
694 * Draw w/ aux | | Partial Fast Clear | |
695 * +----------+ | +--------------------------+ | |
696 * | | \|/ | \|/ |
697 * | +-------------+ Full Resolve +-------------+ |
698 * +------>| Compressed |------------------->| Resolved | |
699 * | w/o Clear |<-------------------| | |
700 * +-------------+ Draw w/ Aux +-------------+ |
701 * /|\ | | |
702 * | Draw | | Draw |
703 * | w/ Aux | | w/o Aux |
704 * | Ambiguate | | |
705 * | +--------------------------+ | |
706 * Draw w/o Aux | | | Draw w/o Aux |
707 * +----------+ | | | +----------+ |
708 * | | | \|/ \|/ | | |
709 * | +-------------+ Ambiguate +-------------+ | |
710 * +------>| Pass- |<-------------------| Aux |<------+ |
711 * +------>| through | | Invalid | |
712 * | +-------------+ +-------------+ |
713 * | | | |
714 * +----------+ +-----------------------------------------------------+
715 * Draw w/ Partial Fast Clear
716 * Clear Only
717 *
718 *
719 * While the above general theory applies to all forms of auxiliary
720 * compression on Intel hardware, not all states and operations are available
721 * on all compression types. However, each of the auxiliary states and
722 * operations can be fairly easily mapped onto the above diagram:
723 *
724 * HiZ: Hierarchical depth compression is capable of being in any of the
725 * states above. Hardware provides three HiZ operations: "Depth
726 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast
727 * Clear", "Full Resolve", and "Ambiguate" respectively. The
728 * hardware provides no HiZ partial resolve operation so the only way
729 * to get into the "Compressed w/o Clear" state is to render with HiZ
730 * when the surface is in the resolved or pass-through states.
731 *
732 * MCS: Multisample compression is technically capable of being in any of
733 * the states above except that most of them aren't useful. Both the
734 * render engine and the sampler support MCS compression and, apart
735 * from clear color, MCS is format-unaware so we leave the surface
736 * compressed 100% of the time. The hardware provides no MCS
737 * operations.
738 *
739 * CCS_D: Single-sample fast-clears (also called CCS_D in ISL) are one of
740 * the simplest forms of compression since they don't do anything
741 * beyond clear color tracking. They really only support three of
742 * the six states: Clear, Partial Clear, and Pass-through. The
743 * only CCS_D operation is "Resolve" which maps to a full resolve
744 * followed by an ambiguate.
745 *
746 * CCS_E: Single-sample render target compression (also called CCS_E in ISL)
747 * is capable of being in almost all of the above states. THe only
748 * exception is that it does not have separate resolved and pass-
749 * through states. Instead, the CCS_E full resolve operation does
750 * both a resolve and an ambiguate so it goes directly into the
751 * pass-through state. CCS_E also provides fast clear and partial
752 * resolve operations which work as described above.
753 *
754 * While it is technically possible to perform a CCS_E ambiguate, it
755 * is not provided by Sky Lake hardware so we choose to avoid the aux
756 * invalid state. If the aux invalid state were determined to be
757 * useful, a CCS ambiguate could be done by carefully rendering to
758 * the CCS and filling it with zeros.
759 */
760 enum isl_aux_state {
761 ISL_AUX_STATE_CLEAR = 0,
762 ISL_AUX_STATE_PARTIAL_CLEAR,
763 ISL_AUX_STATE_COMPRESSED_CLEAR,
764 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
765 ISL_AUX_STATE_RESOLVED,
766 ISL_AUX_STATE_PASS_THROUGH,
767 ISL_AUX_STATE_AUX_INVALID,
768 };
769
770 /**
771 * Enum which describes explicit aux transition operations.
772 */
773 enum isl_aux_op {
774 ISL_AUX_OP_NONE,
775
776 /** Fast Clear
777 *
778 * This operation writes the magic "clear" value to the auxiliary surface.
779 * This operation will safely transition any slice of a surface from any
780 * state to the clear state so long as the entire slice is fast cleared at
781 * once. A fast clear that only covers part of a slice of a surface is
782 * called a partial fast clear.
783 */
784 ISL_AUX_OP_FAST_CLEAR,
785
786 /** Full Resolve
787 *
788 * This operation combines the auxiliary surface data with the primary
789 * surface data and writes the result to the primary. For HiZ, the docs
790 * call this a depth resolve. For CCS, the hardware full resolve operation
791 * does both a full resolve and an ambiguate so it actually takes you all
792 * the way to the pass-through state.
793 */
794 ISL_AUX_OP_FULL_RESOLVE,
795
796 /** Partial Resolve
797 *
798 * This operation considers blocks which are in the "clear" state and
799 * writes the clear value directly into the primary or auxiliary surface.
800 * Once this operation completes, the surface is still compressed but no
801 * longer references the clear color. This operation is only available
802 * for CCS_E.
803 */
804 ISL_AUX_OP_PARTIAL_RESOLVE,
805
806 /** Ambiguate
807 *
808 * This operation throws away the current auxiliary data and replaces it
809 * with the magic pass-through value. If an ambiguate operation is
810 * performed when the primary surface does not contain 100% of the data,
811 * data will be lost. This operation is only implemented in hardware for
812 * depth where it is called a HiZ resolve.
813 */
814 ISL_AUX_OP_AMBIGUATE,
815 };
816
817 /* TODO(chadv): Explain */
818 enum isl_array_pitch_span {
819 ISL_ARRAY_PITCH_SPAN_FULL,
820 ISL_ARRAY_PITCH_SPAN_COMPACT,
821 };
822
823 /**
824 * @defgroup Surface Usage
825 * @{
826 */
827 typedef uint64_t isl_surf_usage_flags_t;
828 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
829 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
830 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
831 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
832 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
833 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
834 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
835 #define ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT (1u << 7)
836 #define ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT (1u << 8)
837 #define ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT (1u << 9)
838 #define ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT (1u << 10)
839 #define ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT (1u << 11)
840 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 12)
841 #define ISL_SURF_USAGE_HIZ_BIT (1u << 13)
842 #define ISL_SURF_USAGE_MCS_BIT (1u << 14)
843 #define ISL_SURF_USAGE_CCS_BIT (1u << 15)
844 /** @} */
845
846 /**
847 * @defgroup Channel Mask
848 *
849 * These #define values are chosen to match the values of
850 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
851 *
852 * @{
853 */
854 typedef uint8_t isl_channel_mask_t;
855 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
856 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
857 #define ISL_CHANNEL_RED_BIT (1 << 2)
858 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
859 /** @} */
860
861 /**
862 * @brief A channel select (also known as texture swizzle) value
863 */
864 enum isl_channel_select {
865 ISL_CHANNEL_SELECT_ZERO = 0,
866 ISL_CHANNEL_SELECT_ONE = 1,
867 ISL_CHANNEL_SELECT_RED = 4,
868 ISL_CHANNEL_SELECT_GREEN = 5,
869 ISL_CHANNEL_SELECT_BLUE = 6,
870 ISL_CHANNEL_SELECT_ALPHA = 7,
871 };
872
873 /**
874 * Identical to VkSampleCountFlagBits.
875 */
876 enum isl_sample_count {
877 ISL_SAMPLE_COUNT_1_BIT = 1u,
878 ISL_SAMPLE_COUNT_2_BIT = 2u,
879 ISL_SAMPLE_COUNT_4_BIT = 4u,
880 ISL_SAMPLE_COUNT_8_BIT = 8u,
881 ISL_SAMPLE_COUNT_16_BIT = 16u,
882 };
883 typedef uint32_t isl_sample_count_mask_t;
884
885 /**
886 * @brief Multisample Format
887 */
888 enum isl_msaa_layout {
889 /**
890 * @brief Suface is single-sampled.
891 */
892 ISL_MSAA_LAYOUT_NONE,
893
894 /**
895 * @brief [SNB+] Interleaved Multisample Format
896 *
897 * In this format, multiple samples are interleaved into each cacheline.
898 * In other words, the sample index is swizzled into the low 6 bits of the
899 * surface's virtual address space.
900 *
901 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
902 * and its pixel format is 32bpp. Then the first cacheline is arranged
903 * thus:
904 *
905 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
906 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
907 *
908 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
909 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
910 *
911 * The hardware docs refer to this format with multiple terms. In
912 * Sandybridge, this is the only multisample format; so no term is used.
913 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
914 * Multisample Surface). Later hardware docs additionally refer to this
915 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
916 * color surfaces).
917 *
918 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
919 * Surface Behavior".
920 *
921 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
922 * Multisampled Surfaces".
923 */
924 ISL_MSAA_LAYOUT_INTERLEAVED,
925
926 /**
927 * @brief [IVB+] Array Multisample Format
928 *
929 * In this format, the surface's physical layout resembles that of a
930 * 2D array surface.
931 *
932 * Suppose the multisample surface's logical extent is (w, h) and its
933 * sample count is N. Then surface's physical extent is the same as
934 * a singlesample 2D surface whose logical extent is (w, h) and array
935 * length is N. Array slice `i` contains the pixel values for sample
936 * index `i`.
937 *
938 * The Ivybridge docs refer to surfaces in this format as UMS
939 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
940 * Surface). The Broadwell docs additionally refer to this format as
941 * MSFMT_MSS (MSS=Multisample Surface Storage).
942 *
943 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
944 * Multisample Surfaces".
945 *
946 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
947 * Multisample Surfaces".
948 */
949 ISL_MSAA_LAYOUT_ARRAY,
950 };
951
952 typedef enum {
953 ISL_MEMCPY = 0,
954 ISL_MEMCPY_BGRA8,
955 ISL_MEMCPY_STREAMING_LOAD,
956 ISL_MEMCPY_INVALID,
957 } isl_memcpy_type;
958
959 struct isl_device {
960 const struct gen_device_info *info;
961 bool use_separate_stencil;
962 bool has_bit6_swizzling;
963
964 /**
965 * Describes the layout of a RENDER_SURFACE_STATE structure for the
966 * current gen.
967 */
968 struct {
969 uint8_t size;
970 uint8_t align;
971 uint8_t addr_offset;
972 uint8_t aux_addr_offset;
973
974 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
975
976 /* size of the state buffer used to store the clear color + extra
977 * additional space used by the hardware */
978 uint8_t clear_color_state_size;
979 uint8_t clear_color_state_offset;
980 /* size of the clear color itself - used to copy it to/from a BO */
981 uint8_t clear_value_size;
982 uint8_t clear_value_offset;
983 } ss;
984
985 /**
986 * Describes the layout of the depth/stencil/hiz commands as emitted by
987 * isl_emit_depth_stencil_hiz.
988 */
989 struct {
990 uint8_t size;
991 uint8_t depth_offset;
992 uint8_t stencil_offset;
993 uint8_t hiz_offset;
994 } ds;
995 };
996
997 struct isl_extent2d {
998 union { uint32_t w, width; };
999 union { uint32_t h, height; };
1000 };
1001
1002 struct isl_extent3d {
1003 union { uint32_t w, width; };
1004 union { uint32_t h, height; };
1005 union { uint32_t d, depth; };
1006 };
1007
1008 struct isl_extent4d {
1009 union { uint32_t w, width; };
1010 union { uint32_t h, height; };
1011 union { uint32_t d, depth; };
1012 union { uint32_t a, array_len; };
1013 };
1014
1015 struct isl_channel_layout {
1016 enum isl_base_type type;
1017 uint8_t start_bit; /**< Bit at which this channel starts */
1018 uint8_t bits; /**< Size in bits */
1019 };
1020
1021 /**
1022 * Each format has 3D block extent (width, height, depth). The block extent of
1023 * compressed formats is that of the format's compression block. For example,
1024 * the block extent of ISL_FORMAT_ETC2_RGB8 is (w=4, h=4, d=1). The block
1025 * extent of uncompressed pixel formats, such as ISL_FORMAT_R8G8B8A8_UNORM, is
1026 * is (w=1, h=1, d=1).
1027 */
1028 struct isl_format_layout {
1029 enum isl_format format;
1030 const char *name;
1031
1032 uint16_t bpb; /**< Bits per block */
1033 uint8_t bw; /**< Block width, in pixels */
1034 uint8_t bh; /**< Block height, in pixels */
1035 uint8_t bd; /**< Block depth, in pixels */
1036
1037 union {
1038 struct {
1039 struct isl_channel_layout r; /**< Red channel */
1040 struct isl_channel_layout g; /**< Green channel */
1041 struct isl_channel_layout b; /**< Blue channel */
1042 struct isl_channel_layout a; /**< Alpha channel */
1043 struct isl_channel_layout l; /**< Luminance channel */
1044 struct isl_channel_layout i; /**< Intensity channel */
1045 struct isl_channel_layout p; /**< Palette channel */
1046 } channels;
1047 struct isl_channel_layout channels_array[7];
1048 };
1049
1050 enum isl_colorspace colorspace;
1051 enum isl_txc txc;
1052 };
1053
1054 struct isl_tile_info {
1055 enum isl_tiling tiling;
1056
1057 /* The size (in bits per block) of a single surface element
1058 *
1059 * For surfaces with power-of-two formats, this is the same as
1060 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1061 * The logical_extent_el field is in terms of elements of this size.
1062 *
1063 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1064 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1065 * of the tiling formats can actually hold an integer number of 96-bit
1066 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1067 * 32-bit element size. It is the responsibility of the caller to
1068 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1069 * the width of a surface in tiles, you would do:
1070 *
1071 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1072 * tile_info.logical_extent_el.width);
1073 */
1074 uint32_t format_bpb;
1075
1076 /** The logical size of the tile in units of format_bpb size elements
1077 *
1078 * This field determines how a given surface is cut up into tiles. It is
1079 * used to compute the size of a surface in tiles and can be used to
1080 * determine the location of the tile containing any given surface element.
1081 * The exact value of this field depends heavily on the bits-per-block of
1082 * the format being used.
1083 */
1084 struct isl_extent2d logical_extent_el;
1085
1086 /** The physical size of the tile in bytes and rows of bytes
1087 *
1088 * This field determines how the tiles of a surface are physically layed
1089 * out in memory. The logical and physical tile extent are frequently the
1090 * same but this is not always the case. For instance, a W-tile (which is
1091 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1092 * its physical size is 128B x 32rows, the same as a Y-tile.
1093 *
1094 * @see isl_surf::row_pitch_B
1095 */
1096 struct isl_extent2d phys_extent_B;
1097 };
1098
1099 /**
1100 * Metadata about a DRM format modifier.
1101 */
1102 struct isl_drm_modifier_info {
1103 uint64_t modifier;
1104
1105 /** Text name of the modifier */
1106 const char *name;
1107
1108 /** ISL tiling implied by this modifier */
1109 enum isl_tiling tiling;
1110
1111 /** ISL aux usage implied by this modifier */
1112 enum isl_aux_usage aux_usage;
1113
1114 /** Whether or not this modifier supports clear color */
1115 bool supports_clear_color;
1116 };
1117
1118 /**
1119 * @brief Input to surface initialization
1120 *
1121 * @invariant width >= 1
1122 * @invariant height >= 1
1123 * @invariant depth >= 1
1124 * @invariant levels >= 1
1125 * @invariant samples >= 1
1126 * @invariant array_len >= 1
1127 *
1128 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1129 * @invariant if 2D then depth == 1
1130 * @invariant if 3D then array_len == 1 and samples == 1
1131 */
1132 struct isl_surf_init_info {
1133 enum isl_surf_dim dim;
1134 enum isl_format format;
1135
1136 uint32_t width;
1137 uint32_t height;
1138 uint32_t depth;
1139 uint32_t levels;
1140 uint32_t array_len;
1141 uint32_t samples;
1142
1143 /** Lower bound for isl_surf::alignment, in bytes. */
1144 uint32_t min_alignment_B;
1145
1146 /**
1147 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1148 * will fail if this is misaligned or out of bounds.
1149 */
1150 uint32_t row_pitch_B;
1151
1152 isl_surf_usage_flags_t usage;
1153
1154 /** Flags that alter how ISL selects isl_surf::tiling. */
1155 isl_tiling_flags_t tiling_flags;
1156 };
1157
1158 struct isl_surf {
1159 enum isl_surf_dim dim;
1160 enum isl_dim_layout dim_layout;
1161 enum isl_msaa_layout msaa_layout;
1162 enum isl_tiling tiling;
1163 enum isl_format format;
1164
1165 /**
1166 * Alignment of the upper-left sample of each subimage, in units of surface
1167 * elements.
1168 */
1169 struct isl_extent3d image_alignment_el;
1170
1171 /**
1172 * Logical extent of the surface's base level, in units of pixels. This is
1173 * identical to the extent defined in isl_surf_init_info.
1174 */
1175 struct isl_extent4d logical_level0_px;
1176
1177 /**
1178 * Physical extent of the surface's base level, in units of physical
1179 * surface samples and aligned to the format's compression block.
1180 *
1181 * Consider isl_dim_layout as an operator that transforms a logical surface
1182 * layout to a physical surface layout. Then
1183 *
1184 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1185 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1186 */
1187 struct isl_extent4d phys_level0_sa;
1188
1189 uint32_t levels;
1190 uint32_t samples;
1191
1192 /** Total size of the surface, in bytes. */
1193 uint64_t size_B;
1194
1195 /** Required alignment for the surface's base address. */
1196 uint32_t alignment_B;
1197
1198 /**
1199 * The interpretation of this field depends on the value of
1200 * isl_tile_info::physical_extent_B. In particular, the width of the
1201 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1202 * and the distance in bytes between vertically adjacent tiles in the image
1203 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1204 *
1205 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1206 * this cleanly reduces to being the distance, in bytes, between vertically
1207 * adjacent surface elements.
1208 *
1209 * @see isl_tile_info::phys_extent_B;
1210 */
1211 uint32_t row_pitch_B;
1212
1213 /**
1214 * Pitch between physical array slices, in rows of surface elements.
1215 */
1216 uint32_t array_pitch_el_rows;
1217
1218 enum isl_array_pitch_span array_pitch_span;
1219
1220 /** Copy of isl_surf_init_info::usage. */
1221 isl_surf_usage_flags_t usage;
1222 };
1223
1224 struct isl_swizzle {
1225 enum isl_channel_select r:4;
1226 enum isl_channel_select g:4;
1227 enum isl_channel_select b:4;
1228 enum isl_channel_select a:4;
1229 };
1230
1231 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1232 .r = ISL_CHANNEL_SELECT_##R, \
1233 .g = ISL_CHANNEL_SELECT_##G, \
1234 .b = ISL_CHANNEL_SELECT_##B, \
1235 .a = ISL_CHANNEL_SELECT_##A, \
1236 })
1237
1238 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1239
1240 struct isl_view {
1241 /**
1242 * Indicates the usage of the particular view
1243 *
1244 * Normally, this is one bit. However, for a cube map texture, it
1245 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1246 */
1247 isl_surf_usage_flags_t usage;
1248
1249 /**
1250 * The format to use in the view
1251 *
1252 * This may differ from the format of the actual isl_surf but must have
1253 * the same block size.
1254 */
1255 enum isl_format format;
1256
1257 uint32_t base_level;
1258 uint32_t levels;
1259
1260 /**
1261 * Base array layer
1262 *
1263 * For cube maps, both base_array_layer and array_len should be
1264 * specified in terms of 2-D layers and must be a multiple of 6.
1265 *
1266 * 3-D textures are effectively treated as 2-D arrays when used as a
1267 * storage image or render target. If `usage` contains
1268 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1269 * base_array_layer and array_len are applied. If the surface is only used
1270 * for texturing, they are ignored.
1271 */
1272 uint32_t base_array_layer;
1273
1274 /**
1275 * Array Length
1276 *
1277 * Indicates the number of array elements starting at Base Array Layer.
1278 */
1279 uint32_t array_len;
1280
1281 struct isl_swizzle swizzle;
1282 };
1283
1284 union isl_color_value {
1285 float f32[4];
1286 uint32_t u32[4];
1287 int32_t i32[4];
1288 };
1289
1290 struct isl_surf_fill_state_info {
1291 const struct isl_surf *surf;
1292 const struct isl_view *view;
1293
1294 /**
1295 * The address of the surface in GPU memory.
1296 */
1297 uint64_t address;
1298
1299 /**
1300 * The Memory Object Control state for the filled surface state.
1301 *
1302 * The exact format of this value depends on hardware generation.
1303 */
1304 uint32_t mocs;
1305
1306 /**
1307 * The auxilary surface or NULL if no auxilary surface is to be used.
1308 */
1309 const struct isl_surf *aux_surf;
1310 enum isl_aux_usage aux_usage;
1311 uint64_t aux_address;
1312
1313 /**
1314 * The clear color for this surface
1315 *
1316 * Valid values depend on hardware generation.
1317 */
1318 union isl_color_value clear_color;
1319
1320 /**
1321 * Send only the clear value address
1322 *
1323 * If set, we only pass the clear address to the GPU and it will fetch it
1324 * from wherever it is.
1325 */
1326 bool use_clear_address;
1327 uint64_t clear_address;
1328
1329 /**
1330 * Surface write disables for gen4-5
1331 */
1332 isl_channel_mask_t write_disables;
1333
1334 /* Intra-tile offset */
1335 uint16_t x_offset_sa, y_offset_sa;
1336 };
1337
1338 struct isl_buffer_fill_state_info {
1339 /**
1340 * The address of the surface in GPU memory.
1341 */
1342 uint64_t address;
1343
1344 /**
1345 * The size of the buffer
1346 */
1347 uint64_t size_B;
1348
1349 /**
1350 * The Memory Object Control state for the filled surface state.
1351 *
1352 * The exact format of this value depends on hardware generation.
1353 */
1354 uint32_t mocs;
1355
1356 /**
1357 * The format to use in the surface state
1358 *
1359 * This may differ from the format of the actual isl_surf but have the
1360 * same block size.
1361 */
1362 enum isl_format format;
1363
1364 /**
1365 * The swizzle to use in the surface state
1366 */
1367 struct isl_swizzle swizzle;
1368
1369 uint32_t stride_B;
1370 };
1371
1372 struct isl_depth_stencil_hiz_emit_info {
1373 /**
1374 * The depth surface
1375 */
1376 const struct isl_surf *depth_surf;
1377
1378 /**
1379 * The stencil surface
1380 *
1381 * If separate stencil is not available, this must point to the same
1382 * isl_surf as depth_surf.
1383 */
1384 const struct isl_surf *stencil_surf;
1385
1386 /**
1387 * The view into the depth and stencil surfaces.
1388 *
1389 * This view applies to both surfaces simultaneously.
1390 */
1391 const struct isl_view *view;
1392
1393 /**
1394 * The address of the depth surface in GPU memory
1395 */
1396 uint64_t depth_address;
1397
1398 /**
1399 * The address of the stencil surface in GPU memory
1400 *
1401 * If separate stencil is not available, this must have the same value as
1402 * depth_address.
1403 */
1404 uint64_t stencil_address;
1405
1406 /**
1407 * The Memory Object Control state for depth and stencil buffers
1408 *
1409 * Both depth and stencil will get the same MOCS value. The exact format
1410 * of this value depends on hardware generation.
1411 */
1412 uint32_t mocs;
1413
1414 /**
1415 * The HiZ surface or NULL if HiZ is disabled.
1416 */
1417 const struct isl_surf *hiz_surf;
1418 enum isl_aux_usage hiz_usage;
1419 uint64_t hiz_address;
1420
1421 /**
1422 * The depth clear value
1423 */
1424 float depth_clear_value;
1425 };
1426
1427 extern const struct isl_format_layout isl_format_layouts[];
1428
1429 void
1430 isl_device_init(struct isl_device *dev,
1431 const struct gen_device_info *info,
1432 bool has_bit6_swizzling);
1433
1434 isl_sample_count_mask_t ATTRIBUTE_CONST
1435 isl_device_get_sample_counts(struct isl_device *dev);
1436
1437 static inline const struct isl_format_layout * ATTRIBUTE_CONST
1438 isl_format_get_layout(enum isl_format fmt)
1439 {
1440 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1441 assert(fmt < ISL_NUM_FORMATS);
1442 return &isl_format_layouts[fmt];
1443 }
1444
1445 bool isl_format_is_valid(enum isl_format);
1446
1447 static inline const char * ATTRIBUTE_CONST
1448 isl_format_get_name(enum isl_format fmt)
1449 {
1450 return isl_format_get_layout(fmt)->name;
1451 }
1452
1453 bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
1454 enum isl_format format);
1455 bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
1456 enum isl_format format);
1457 bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
1458 enum isl_format format);
1459 bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
1460 enum isl_format format);
1461 bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
1462 enum isl_format format);
1463 bool isl_format_supports_typed_writes(const struct gen_device_info *devinfo,
1464 enum isl_format format);
1465 bool isl_format_supports_typed_reads(const struct gen_device_info *devinfo,
1466 enum isl_format format);
1467 bool isl_format_supports_ccs_d(const struct gen_device_info *devinfo,
1468 enum isl_format format);
1469 bool isl_format_supports_ccs_e(const struct gen_device_info *devinfo,
1470 enum isl_format format);
1471 bool isl_format_supports_multisampling(const struct gen_device_info *devinfo,
1472 enum isl_format format);
1473
1474 bool isl_formats_are_ccs_e_compatible(const struct gen_device_info *devinfo,
1475 enum isl_format format1,
1476 enum isl_format format2);
1477
1478 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1479 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1480 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1481 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1482 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1483 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1484
1485 static inline bool
1486 isl_format_has_normalized_channel(enum isl_format fmt)
1487 {
1488 return isl_format_has_unorm_channel(fmt) ||
1489 isl_format_has_snorm_channel(fmt);
1490 }
1491
1492 static inline bool
1493 isl_format_has_float_channel(enum isl_format fmt)
1494 {
1495 return isl_format_has_ufloat_channel(fmt) ||
1496 isl_format_has_sfloat_channel(fmt);
1497 }
1498
1499 static inline bool
1500 isl_format_has_int_channel(enum isl_format fmt)
1501 {
1502 return isl_format_has_uint_channel(fmt) ||
1503 isl_format_has_sint_channel(fmt);
1504 }
1505
1506 bool isl_format_has_color_component(enum isl_format fmt,
1507 int component) ATTRIBUTE_CONST;
1508
1509 unsigned isl_format_get_num_channels(enum isl_format fmt);
1510
1511 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1512
1513 static inline bool
1514 isl_format_is_compressed(enum isl_format fmt)
1515 {
1516 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1517
1518 return fmtl->txc != ISL_TXC_NONE;
1519 }
1520
1521 static inline bool
1522 isl_format_has_bc_compression(enum isl_format fmt)
1523 {
1524 switch (isl_format_get_layout(fmt)->txc) {
1525 case ISL_TXC_DXT1:
1526 case ISL_TXC_DXT3:
1527 case ISL_TXC_DXT5:
1528 return true;
1529 case ISL_TXC_NONE:
1530 case ISL_TXC_FXT1:
1531 case ISL_TXC_RGTC1:
1532 case ISL_TXC_RGTC2:
1533 case ISL_TXC_BPTC:
1534 case ISL_TXC_ETC1:
1535 case ISL_TXC_ETC2:
1536 case ISL_TXC_ASTC:
1537 return false;
1538
1539 case ISL_TXC_HIZ:
1540 case ISL_TXC_MCS:
1541 case ISL_TXC_CCS:
1542 unreachable("Should not be called on an aux surface");
1543 }
1544
1545 unreachable("bad texture compression mode");
1546 return false;
1547 }
1548
1549 static inline bool
1550 isl_format_is_yuv(enum isl_format fmt)
1551 {
1552 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1553
1554 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1555 }
1556
1557 static inline bool
1558 isl_format_block_is_1x1x1(enum isl_format fmt)
1559 {
1560 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1561
1562 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1563 }
1564
1565 static inline bool
1566 isl_format_is_srgb(enum isl_format fmt)
1567 {
1568 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1569 }
1570
1571 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1572
1573 static inline bool
1574 isl_format_is_rgb(enum isl_format fmt)
1575 {
1576 if (isl_format_is_yuv(fmt))
1577 return false;
1578
1579 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1580
1581 return fmtl->channels.r.bits > 0 &&
1582 fmtl->channels.g.bits > 0 &&
1583 fmtl->channels.b.bits > 0 &&
1584 fmtl->channels.a.bits == 0;
1585 }
1586
1587 static inline bool
1588 isl_format_is_rgbx(enum isl_format fmt)
1589 {
1590 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1591
1592 return fmtl->channels.r.bits > 0 &&
1593 fmtl->channels.g.bits > 0 &&
1594 fmtl->channels.b.bits > 0 &&
1595 fmtl->channels.a.bits > 0 &&
1596 fmtl->channels.a.type == ISL_VOID;
1597 }
1598
1599 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1600 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
1601 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
1602
1603 void isl_color_value_pack(const union isl_color_value *value,
1604 enum isl_format format,
1605 uint32_t *data_out);
1606 void isl_color_value_unpack(union isl_color_value *value,
1607 enum isl_format format,
1608 const uint32_t *data_in);
1609
1610 bool isl_is_storage_image_format(enum isl_format fmt);
1611
1612 enum isl_format
1613 isl_lower_storage_image_format(const struct gen_device_info *devinfo,
1614 enum isl_format fmt);
1615
1616 /* Returns true if this hardware supports typed load/store on a format with
1617 * the same size as the given format.
1618 */
1619 bool
1620 isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
1621 enum isl_format fmt);
1622
1623 static inline bool
1624 isl_tiling_is_any_y(enum isl_tiling tiling)
1625 {
1626 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
1627 }
1628
1629 static inline bool
1630 isl_tiling_is_std_y(enum isl_tiling tiling)
1631 {
1632 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
1633 }
1634
1635 uint32_t
1636 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
1637
1638 enum isl_tiling
1639 isl_tiling_from_i915_tiling(uint32_t tiling);
1640
1641 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
1642 isl_drm_modifier_get_info(uint64_t modifier);
1643
1644 static inline bool
1645 isl_drm_modifier_has_aux(uint64_t modifier)
1646 {
1647 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
1648 }
1649
1650 /** Returns the default isl_aux_state for the given modifier.
1651 *
1652 * If we have a modifier which supports compression, then the auxiliary data
1653 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
1654 * can be in any of the following:
1655 *
1656 * - ISL_AUX_STATE_CLEAR
1657 * - ISL_AUX_STATE_PARTIAL_CLEAR
1658 * - ISL_AUX_STATE_COMPRESSED_CLEAR
1659 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
1660 * - ISL_AUX_STATE_RESOLVED
1661 * - ISL_AUX_STATE_PASS_THROUGH
1662 *
1663 * If the modifier does not support fast-clears, then we are guaranteed
1664 * that the surface is at least partially resolved and the first three not
1665 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
1666 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
1667 * because they are the least common denominator of the set of possible aux
1668 * states and will yield a valid interpretation of the aux data.
1669 *
1670 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
1671 */
1672 static inline enum isl_aux_state
1673 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
1674 {
1675 const struct isl_drm_modifier_info *mod_info =
1676 isl_drm_modifier_get_info(modifier);
1677
1678 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
1679 return ISL_AUX_STATE_AUX_INVALID;
1680
1681 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1682 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
1683 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1684 }
1685
1686 struct isl_extent2d ATTRIBUTE_CONST
1687 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
1688
1689 static inline bool
1690 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
1691 {
1692 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
1693 }
1694
1695 static inline bool
1696 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
1697 {
1698 return usage & ISL_SURF_USAGE_DEPTH_BIT;
1699 }
1700
1701 static inline bool
1702 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
1703 {
1704 return usage & ISL_SURF_USAGE_STENCIL_BIT;
1705 }
1706
1707 static inline bool
1708 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
1709 {
1710 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1711 (usage & ISL_SURF_USAGE_STENCIL_BIT);
1712 }
1713
1714 static inline bool
1715 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
1716 {
1717 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
1718 }
1719
1720 static inline bool
1721 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
1722 {
1723 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1724 (info->format == ISL_FORMAT_R16_UNORM);
1725 }
1726
1727 static inline bool
1728 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
1729 {
1730 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
1731 (info->format == ISL_FORMAT_R32_FLOAT);
1732 }
1733
1734 static inline struct isl_extent2d
1735 isl_extent2d(uint32_t width, uint32_t height)
1736 {
1737 struct isl_extent2d e = { { 0 } };
1738
1739 e.width = width;
1740 e.height = height;
1741
1742 return e;
1743 }
1744
1745 static inline struct isl_extent3d
1746 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
1747 {
1748 struct isl_extent3d e = { { 0 } };
1749
1750 e.width = width;
1751 e.height = height;
1752 e.depth = depth;
1753
1754 return e;
1755 }
1756
1757 static inline struct isl_extent4d
1758 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
1759 uint32_t array_len)
1760 {
1761 struct isl_extent4d e = { { 0 } };
1762
1763 e.width = width;
1764 e.height = height;
1765 e.depth = depth;
1766 e.array_len = array_len;
1767
1768 return e;
1769 }
1770
1771 bool isl_color_value_is_zero(union isl_color_value value,
1772 enum isl_format format);
1773
1774 bool isl_color_value_is_zero_one(union isl_color_value value,
1775 enum isl_format format);
1776
1777 static inline bool
1778 isl_swizzle_is_identity(struct isl_swizzle swizzle)
1779 {
1780 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
1781 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
1782 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
1783 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
1784 }
1785
1786 bool
1787 isl_swizzle_supports_rendering(const struct gen_device_info *devinfo,
1788 struct isl_swizzle swizzle);
1789
1790 struct isl_swizzle
1791 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
1792 struct isl_swizzle
1793 isl_swizzle_invert(struct isl_swizzle swizzle);
1794
1795 #define isl_surf_init(dev, surf, ...) \
1796 isl_surf_init_s((dev), (surf), \
1797 &(struct isl_surf_init_info) { __VA_ARGS__ });
1798
1799 bool
1800 isl_surf_init_s(const struct isl_device *dev,
1801 struct isl_surf *surf,
1802 const struct isl_surf_init_info *restrict info);
1803
1804 void
1805 isl_surf_get_tile_info(const struct isl_surf *surf,
1806 struct isl_tile_info *tile_info);
1807
1808 bool
1809 isl_surf_get_hiz_surf(const struct isl_device *dev,
1810 const struct isl_surf *surf,
1811 struct isl_surf *hiz_surf);
1812
1813 bool
1814 isl_surf_get_mcs_surf(const struct isl_device *dev,
1815 const struct isl_surf *surf,
1816 struct isl_surf *mcs_surf);
1817
1818 bool
1819 isl_surf_get_ccs_surf(const struct isl_device *dev,
1820 const struct isl_surf *surf,
1821 struct isl_surf *ccs_surf,
1822 uint32_t row_pitch_B /**< Ignored if 0 */);
1823
1824 #define isl_surf_fill_state(dev, state, ...) \
1825 isl_surf_fill_state_s((dev), (state), \
1826 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
1827
1828 void
1829 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
1830 const struct isl_surf_fill_state_info *restrict info);
1831
1832 #define isl_buffer_fill_state(dev, state, ...) \
1833 isl_buffer_fill_state_s((dev), (state), \
1834 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
1835
1836 void
1837 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
1838 const struct isl_buffer_fill_state_info *restrict info);
1839
1840 void
1841 isl_null_fill_state(const struct isl_device *dev, void *state,
1842 struct isl_extent3d size);
1843
1844 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
1845 isl_emit_depth_stencil_hiz_s((dev), (batch), \
1846 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
1847
1848 void
1849 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
1850 const struct isl_depth_stencil_hiz_emit_info *restrict info);
1851
1852 void
1853 isl_surf_fill_image_param(const struct isl_device *dev,
1854 struct brw_image_param *param,
1855 const struct isl_surf *surf,
1856 const struct isl_view *view);
1857
1858 void
1859 isl_buffer_fill_image_param(const struct isl_device *dev,
1860 struct brw_image_param *param,
1861 enum isl_format format,
1862 uint64_t size);
1863
1864 /**
1865 * Alignment of the upper-left sample of each subimage, in units of surface
1866 * elements.
1867 */
1868 static inline struct isl_extent3d
1869 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
1870 {
1871 return surf->image_alignment_el;
1872 }
1873
1874 /**
1875 * Alignment of the upper-left sample of each subimage, in units of surface
1876 * samples.
1877 */
1878 static inline struct isl_extent3d
1879 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
1880 {
1881 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1882
1883 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
1884 fmtl->bh * surf->image_alignment_el.h,
1885 fmtl->bd * surf->image_alignment_el.d);
1886 }
1887
1888 /**
1889 * Pitch between vertically adjacent surface elements, in bytes.
1890 */
1891 static inline uint32_t
1892 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
1893 {
1894 return surf->row_pitch_B;
1895 }
1896
1897 /**
1898 * Pitch between vertically adjacent surface elements, in units of surface elements.
1899 */
1900 static inline uint32_t
1901 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
1902 {
1903 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1904
1905 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
1906 return surf->row_pitch_B / (fmtl->bpb / 8);
1907 }
1908
1909 /**
1910 * Pitch between physical array slices, in rows of surface elements.
1911 */
1912 static inline uint32_t
1913 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
1914 {
1915 return surf->array_pitch_el_rows;
1916 }
1917
1918 /**
1919 * Pitch between physical array slices, in units of surface elements.
1920 */
1921 static inline uint32_t
1922 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
1923 {
1924 return isl_surf_get_array_pitch_el_rows(surf) *
1925 isl_surf_get_row_pitch_el(surf);
1926 }
1927
1928 /**
1929 * Pitch between physical array slices, in rows of surface samples.
1930 */
1931 static inline uint32_t
1932 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
1933 {
1934 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
1935 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
1936 }
1937
1938 /**
1939 * Pitch between physical array slices, in bytes.
1940 */
1941 static inline uint32_t
1942 isl_surf_get_array_pitch(const struct isl_surf *surf)
1943 {
1944 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
1945 }
1946
1947 /**
1948 * Calculate the offset, in units of surface samples, to a subimage in the
1949 * surface.
1950 *
1951 * @invariant level < surface levels
1952 * @invariant logical_array_layer < logical array length of surface
1953 * @invariant logical_z_offset_px < logical depth of surface at level
1954 */
1955 void
1956 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
1957 uint32_t level,
1958 uint32_t logical_array_layer,
1959 uint32_t logical_z_offset_px,
1960 uint32_t *x_offset_sa,
1961 uint32_t *y_offset_sa);
1962
1963 /**
1964 * Calculate the offset, in units of surface elements, to a subimage in the
1965 * surface.
1966 *
1967 * @invariant level < surface levels
1968 * @invariant logical_array_layer < logical array length of surface
1969 * @invariant logical_z_offset_px < logical depth of surface at level
1970 */
1971 void
1972 isl_surf_get_image_offset_el(const struct isl_surf *surf,
1973 uint32_t level,
1974 uint32_t logical_array_layer,
1975 uint32_t logical_z_offset_px,
1976 uint32_t *x_offset_el,
1977 uint32_t *y_offset_el);
1978
1979 /**
1980 * Calculate the offset, in bytes and intratile surface samples, to a
1981 * subimage in the surface.
1982 *
1983 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
1984 * result to isl_tiling_get_intratile_offset_el, and converting the tile
1985 * offsets to samples.
1986 *
1987 * @invariant level < surface levels
1988 * @invariant logical_array_layer < logical array length of surface
1989 * @invariant logical_z_offset_px < logical depth of surface at level
1990 */
1991 void
1992 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
1993 uint32_t level,
1994 uint32_t logical_array_layer,
1995 uint32_t logical_z_offset_px,
1996 uint32_t *offset_B,
1997 uint32_t *x_offset_sa,
1998 uint32_t *y_offset_sa);
1999
2000 /**
2001 * Create an isl_surf that represents a particular subimage in the surface.
2002 *
2003 * The newly created surface will have a single miplevel and array slice. The
2004 * surface lives at the returned byte and intratile offsets, in samples.
2005 *
2006 * It is safe to call this function with surf == image_surf.
2007 *
2008 * @invariant level < surface levels
2009 * @invariant logical_array_layer < logical array length of surface
2010 * @invariant logical_z_offset_px < logical depth of surface at level
2011 */
2012 void
2013 isl_surf_get_image_surf(const struct isl_device *dev,
2014 const struct isl_surf *surf,
2015 uint32_t level,
2016 uint32_t logical_array_layer,
2017 uint32_t logical_z_offset_px,
2018 struct isl_surf *image_surf,
2019 uint32_t *offset_B,
2020 uint32_t *x_offset_sa,
2021 uint32_t *y_offset_sa);
2022
2023 /**
2024 * @brief Calculate the intratile offsets to a surface.
2025 *
2026 * In @a base_address_offset return the offset from the base of the surface to
2027 * the base address of the first tile of the subimage. In @a x_offset_B and
2028 * @a y_offset_rows, return the offset, in units of bytes and rows, from the
2029 * tile's base to the subimage's first surface element. The x and y offsets
2030 * are intratile offsets; that is, they do not exceed the boundary of the
2031 * surface's tiling format.
2032 */
2033 void
2034 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2035 uint32_t bpb,
2036 uint32_t row_pitch_B,
2037 uint32_t total_x_offset_el,
2038 uint32_t total_y_offset_el,
2039 uint32_t *base_address_offset,
2040 uint32_t *x_offset_el,
2041 uint32_t *y_offset_el);
2042
2043 static inline void
2044 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2045 enum isl_format format,
2046 uint32_t row_pitch_B,
2047 uint32_t total_x_offset_sa,
2048 uint32_t total_y_offset_sa,
2049 uint32_t *base_address_offset,
2050 uint32_t *x_offset_sa,
2051 uint32_t *y_offset_sa)
2052 {
2053 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2054
2055 /* For computing the intratile offsets, we actually want a strange unit
2056 * which is samples for multisampled surfaces but elements for compressed
2057 * surfaces.
2058 */
2059 assert(total_x_offset_sa % fmtl->bw == 0);
2060 assert(total_y_offset_sa % fmtl->bh == 0);
2061 const uint32_t total_x_offset = total_x_offset_sa / fmtl->bw;
2062 const uint32_t total_y_offset = total_y_offset_sa / fmtl->bh;
2063
2064 isl_tiling_get_intratile_offset_el(tiling, fmtl->bpb, row_pitch_B,
2065 total_x_offset, total_y_offset,
2066 base_address_offset,
2067 x_offset_sa, y_offset_sa);
2068 *x_offset_sa *= fmtl->bw;
2069 *y_offset_sa *= fmtl->bh;
2070 }
2071
2072 /**
2073 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2074 *
2075 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2076 * @pre surf->format must be a valid format for depth surfaces
2077 */
2078 uint32_t
2079 isl_surf_get_depth_format(const struct isl_device *dev,
2080 const struct isl_surf *surf);
2081
2082 /**
2083 * @brief performs a copy from linear to tiled surface
2084 *
2085 */
2086 void
2087 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2088 uint32_t yt1, uint32_t yt2,
2089 char *dst, const char *src,
2090 uint32_t dst_pitch, int32_t src_pitch,
2091 bool has_swizzling,
2092 enum isl_tiling tiling,
2093 isl_memcpy_type copy_type);
2094
2095 /**
2096 * @brief performs a copy from tiled to linear surface
2097 *
2098 */
2099 void
2100 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2101 uint32_t yt1, uint32_t yt2,
2102 char *dst, const char *src,
2103 int32_t dst_pitch, uint32_t src_pitch,
2104 bool has_swizzling,
2105 enum isl_tiling tiling,
2106 isl_memcpy_type copy_type);
2107
2108 #ifdef __cplusplus
2109 }
2110 #endif
2111
2112 #endif /* ISL_H */