2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
30 __gen_combine_address(__attribute__((unused
)) void *data
,
31 __attribute__((unused
)) void *loc
, uint64_t addr
,
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
42 static const uint32_t isl_to_gen_ds_surftype
[] = {
44 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType":
46 * "If depth/stencil is enabled with 1D render target, depth/stencil
47 * surface type needs to be set to 2D surface type and height set to 1.
48 * Depth will use (legacy) TileY and stencil will use TileW. For this
49 * case only, the Surface Type of the depth buffer can be 2D while the
50 * Surface Type of the render target(s) are 1D, representing an
51 * exception to a programming note above.
53 [ISL_SURF_DIM_1D
] = SURFTYPE_2D
,
55 [ISL_SURF_DIM_1D
] = SURFTYPE_1D
,
57 [ISL_SURF_DIM_2D
] = SURFTYPE_2D
,
58 [ISL_SURF_DIM_3D
] = SURFTYPE_3D
,
62 isl_genX(emit_depth_stencil_hiz_s
)(const struct isl_device
*dev
, void *batch
,
63 const struct isl_depth_stencil_hiz_emit_info
*restrict info
)
65 struct GENX(3DSTATE_DEPTH_BUFFER
) db
= {
66 GENX(3DSTATE_DEPTH_BUFFER_header
),
69 if (info
->depth_surf
) {
70 db
.SurfaceType
= isl_to_gen_ds_surftype
[info
->depth_surf
->dim
];
71 db
.SurfaceFormat
= isl_surf_get_depth_format(dev
, info
->depth_surf
);
72 db
.Width
= info
->depth_surf
->logical_level0_px
.width
- 1;
73 db
.Height
= info
->depth_surf
->logical_level0_px
.height
- 1;
74 } else if (info
->stencil_surf
) {
75 db
.SurfaceType
= isl_to_gen_ds_surftype
[info
->stencil_surf
->dim
];
76 db
.SurfaceFormat
= D32_FLOAT
;
77 db
.Width
= info
->stencil_surf
->logical_level0_px
.width
- 1;
78 db
.Height
= info
->stencil_surf
->logical_level0_px
.height
- 1;
80 db
.SurfaceType
= SURFTYPE_NULL
;
81 db
.SurfaceFormat
= D32_FLOAT
;
84 if (info
->depth_surf
|| info
->stencil_surf
) {
85 /* These are based entirely on the view */
86 db
.Depth
= db
.RenderTargetViewExtent
= info
->view
->array_len
- 1;
87 db
.LOD
= info
->view
->base_level
;
88 db
.MinimumArrayElement
= info
->view
->base_array_layer
;
91 if (info
->depth_surf
) {
93 db
.DepthWriteEnable
= true;
95 db
.SurfaceBaseAddress
= info
->depth_address
;
101 db
.TiledSurface
= info
->depth_surf
->tiling
!= ISL_TILING_LINEAR
;
102 db
.TileWalk
= info
->depth_surf
->tiling
== ISL_TILING_Y0
? TILEWALK_YMAJOR
:
104 db
.MIPMapLayoutMode
= MIPLAYOUT_BELOW
;
107 db
.SurfacePitch
= info
->depth_surf
->row_pitch_B
- 1;
110 isl_surf_get_array_pitch_el_rows(info
->depth_surf
) >> 2;
114 db
.ControlSurfaceEnable
= db
.DepthBufferCompressionEnable
=
115 info
->hiz_usage
== ISL_AUX_USAGE_HIZ_CCS
;
119 #if GEN_GEN == 5 || GEN_GEN == 6
120 const bool separate_stencil
=
121 info
->stencil_surf
&& info
->stencil_surf
->format
== ISL_FORMAT_R8_UINT
;
122 if (separate_stencil
|| info
->hiz_usage
== ISL_AUX_USAGE_HIZ
) {
123 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
124 db
.SeparateStencilBufferEnable
= true;
125 db
.HierarchicalDepthBufferEnable
= true;
130 struct GENX(3DSTATE_STENCIL_BUFFER
) sb
= {
131 GENX(3DSTATE_STENCIL_BUFFER_header
),
137 if (info
->stencil_surf
) {
138 #if GEN_GEN >= 7 && GEN_GEN < 12
139 db
.StencilWriteEnable
= true;
142 sb
.StencilWriteEnable
= true;
143 sb
.SurfaceType
= SURFTYPE_2D
;
144 sb
.Width
= info
->stencil_surf
->logical_level0_px
.width
- 1;
145 sb
.Height
= info
->stencil_surf
->logical_level0_px
.height
- 1;
146 sb
.Depth
= sb
.RenderTargetViewExtent
= info
->view
->array_len
- 1;
147 sb
.SurfLOD
= info
->view
->base_level
;
148 sb
.MinimumArrayElement
= info
->view
->base_array_layer
;
149 sb
.StencilCompressionEnable
=
150 info
->stencil_aux_usage
== ISL_AUX_USAGE_CCS_E
;
151 sb
.ControlSurfaceEnable
= sb
.StencilCompressionEnable
;
152 #elif GEN_GEN >= 8 || GEN_IS_HASWELL
153 sb
.StencilBufferEnable
= true;
155 sb
.SurfaceBaseAddress
= info
->stencil_address
;
157 sb
.MOCS
= info
->mocs
;
159 sb
.SurfacePitch
= info
->stencil_surf
->row_pitch_B
- 1;
162 isl_surf_get_array_pitch_el_rows(info
->stencil_surf
) >> 2;
166 sb
.SurfaceType
= SURFTYPE_NULL
;
168 /* The docs seem to indicate that if surf-type is null, then we may need
169 * to match the depth-buffer value for `Depth`. It may be a
170 * documentation bug, since the other fields don't require this.
172 * TODO: Confirm documentation and remove seeting of `Depth` if not
180 struct GENX(3DSTATE_HIER_DEPTH_BUFFER
) hiz
= {
181 GENX(3DSTATE_HIER_DEPTH_BUFFER_header
),
183 struct GENX(3DSTATE_CLEAR_PARAMS
) clear
= {
184 GENX(3DSTATE_CLEAR_PARAMS_header
),
187 assert(info
->hiz_usage
== ISL_AUX_USAGE_NONE
||
188 info
->hiz_usage
== ISL_AUX_USAGE_HIZ
||
189 info
->hiz_usage
== ISL_AUX_USAGE_HIZ_CCS
);
190 if (info
->hiz_usage
== ISL_AUX_USAGE_HIZ
||
191 info
->hiz_usage
== ISL_AUX_USAGE_HIZ_CCS
) {
192 assert(GEN_GEN
>= 12 || info
->hiz_usage
== ISL_AUX_USAGE_HIZ
);
193 db
.HierarchicalDepthBufferEnable
= true;
195 hiz
.SurfaceBaseAddress
= info
->hiz_address
;
196 hiz
.MOCS
= info
->mocs
;
197 hiz
.SurfacePitch
= info
->hiz_surf
->row_pitch_B
- 1;
199 hiz
.HierarchicalDepthBufferWriteThruEnable
=
200 isl_surf_supports_hiz_ccs_wt(dev
->info
, info
->depth_surf
,
205 /* From the SKL PRM Vol2a:
207 * The interpretation of this field is dependent on Surface Type
209 * - SURFTYPE_1D: distance in pixels between array slices
210 * - SURFTYPE_2D/CUBE: distance in rows between array slices
211 * - SURFTYPE_3D: distance in rows between R - slices
213 * Unfortunately, the docs aren't 100% accurate here. They fail to
214 * mention that the 1-D rule only applies to linear 1-D images.
215 * Since depth and HiZ buffers are always tiled, they are treated as
216 * 2-D images. Prior to Sky Lake, this field is always in rows.
219 isl_surf_get_array_pitch_sa_rows(info
->hiz_surf
) >> 2;
222 clear
.DepthClearValueValid
= true;
224 clear
.DepthClearValue
= info
->depth_clear_value
;
226 switch (info
->depth_surf
->format
) {
227 case ISL_FORMAT_R32_FLOAT
: {
228 union { float f
; uint32_t u
; } fu
;
229 fu
.f
= info
->depth_clear_value
;
230 clear
.DepthClearValue
= fu
.u
;
233 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
234 clear
.DepthClearValue
= info
->depth_clear_value
* ((1u << 24) - 1);
236 case ISL_FORMAT_R16_UNORM
:
237 clear
.DepthClearValue
= info
->depth_clear_value
* ((1u << 16) - 1);
240 unreachable("Invalid depth type");
244 #endif /* GEN_GEN >= 6 */
246 /* Pack everything into the batch */
247 uint32_t *dw
= batch
;
248 GENX(3DSTATE_DEPTH_BUFFER_pack
)(NULL
, dw
, &db
);
249 dw
+= GENX(3DSTATE_DEPTH_BUFFER_length
);
252 GENX(3DSTATE_STENCIL_BUFFER_pack
)(NULL
, dw
, &sb
);
253 dw
+= GENX(3DSTATE_STENCIL_BUFFER_length
);
255 GENX(3DSTATE_HIER_DEPTH_BUFFER_pack
)(NULL
, dw
, &hiz
);
256 dw
+= GENX(3DSTATE_HIER_DEPTH_BUFFER_length
);
258 GENX(3DSTATE_CLEAR_PARAMS_pack
)(NULL
, dw
, &clear
);
259 dw
+= GENX(3DSTATE_CLEAR_PARAMS_length
);