2 * Copyright 2015 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 isl_gen4_choose_msaa_layout(const struct isl_device
*dev
,
29 const struct isl_surf_init_info
*info
,
30 enum isl_tiling tiling
,
31 enum isl_msaa_layout
*msaa_layout
)
33 /* Gen4 and Gen5 do not support MSAA */
34 assert(info
->samples
>= 1);
36 *msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
41 isl_gen4_filter_tiling(const struct isl_device
*dev
,
42 const struct isl_surf_init_info
*restrict info
,
43 isl_tiling_flags_t
*flags
)
45 /* Gen4-5 only support linear, X, and Y-tiling. */
46 *flags
&= (ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
| ISL_TILING_Y0_BIT
);
48 if (isl_surf_usage_is_depth_or_stencil(info
->usage
)) {
49 assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev
));
51 /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
53 * "The Depth Buffer, if tiled, must use Y-Major tiling"
55 * Errata Description Project
56 * BWT014 The Depth Buffer Must be Tiled, it cannot be linear. This
57 * field must be set to 1 on DevBW-A. [DevBW -A,B]
59 * In testing, the linear configuration doesn't seem to work on gen4.
61 *flags
&= (ISL_DEV_GEN(dev
) == 4 && !ISL_DEV_IS_G4X(dev
)) ?
62 ISL_TILING_Y0_BIT
: (ISL_TILING_Y0_BIT
| ISL_TILING_LINEAR_BIT
);
65 if (info
->usage
& (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT
|
66 ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT
|
67 ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT
)) {
68 assert(*flags
& ISL_SURF_USAGE_DISPLAY_BIT
);
69 isl_finishme("%s:%s: handle rotated display surfaces",
73 if (info
->usage
& (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT
|
74 ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT
)) {
75 assert(*flags
& ISL_SURF_USAGE_DISPLAY_BIT
);
76 isl_finishme("%s:%s: handle flipped display surfaces",
80 if (info
->usage
& ISL_SURF_USAGE_DISPLAY_BIT
) {
81 /* Before Skylake, the display engine does not accept Y */
82 *flags
&= (ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
);
85 assert(info
->samples
== 1);
87 /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
89 * "NOTE: 128BPE Format Color buffer ( render target ) MUST be either
92 * This is required all the way up to Sandy Bridge.
94 if (isl_format_get_layout(info
->format
)->bpb
>= 128)
95 *flags
&= ~ISL_TILING_Y0_BIT
;
99 isl_gen4_choose_image_alignment_el(const struct isl_device
*dev
,
100 const struct isl_surf_init_info
*restrict info
,
101 enum isl_tiling tiling
,
102 enum isl_dim_layout dim_layout
,
103 enum isl_msaa_layout msaa_layout
,
104 struct isl_extent3d
*image_align_el
)
106 assert(info
->samples
== 1);
107 assert(msaa_layout
== ISL_MSAA_LAYOUT_NONE
);
108 assert(!isl_tiling_is_std_y(tiling
));
110 /* Note that neither the surface's horizontal nor vertical image alignment
111 * is programmable on gen4 nor gen5.
113 * From the G35 PRM (2008-01), Volume 1 Graphics Core, Section 6.17.3.4
114 * Alignment Unit Size:
116 * Note that the compressed formats are padded to a full compression
119 * +------------------------+--------+--------+
120 * | format | halign | valign |
121 * +------------------------+--------+--------+
122 * | YUV 4:2:2 formats | 4 | 2 |
123 * | uncompressed formats | 4 | 2 |
124 * +------------------------+--------+--------+
127 if (isl_format_is_compressed(info
->format
)) {
128 *image_align_el
= isl_extent3d(1, 1, 1);
132 *image_align_el
= isl_extent3d(4, 2, 1);