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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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28 gen7_choose_msaa_layout(const struct isl_device
*dev
,
29 const struct isl_surf_init_info
*info
,
30 enum isl_tiling tiling
,
31 enum isl_msaa_layout
*msaa_layout
)
33 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
35 bool require_array
= false;
36 bool require_interleaved
= false;
38 assert(ISL_DEV_GEN(dev
) == 7);
39 assert(info
->samples
>= 1);
41 if (info
->samples
== 1) {
42 *msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
46 /* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface
49 * If Number of Multisamples is set to a value other than
50 * MULTISAMPLECOUNT_1, this field cannot be set to the following
51 * formats: any format with greater than 64 bits per element, any
52 * compressed texture format (BC*), and any YCRCB* format.
56 if (isl_format_is_compressed(info
->format
))
58 if (isl_format_is_yuv(info
->format
))
61 /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
64 * - If this field is any value other than MULTISAMPLECOUNT_1, the
65 * Surface Type must be SURFTYPE_2D.
67 * - If this field is any value other than MULTISAMPLECOUNT_1, Surface
68 * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero
70 if (info
->dim
!= ISL_SURF_DIM_2D
)
75 /* The Ivyrbridge PRM insists twice that signed integer formats cannot be
78 * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
81 * - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
82 * all RT channels are not written.
84 * And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
85 * RENDER_SURFACE_STATE, MCS Enable:
87 * This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
88 * when all RT channels are not written.
90 * Note that the above SINT restrictions apply only to *MSRTs* (that is,
91 * *multisampled* render targets). The restrictions seem to permit an MCS
92 * if the render target is singlesampled.
94 if (isl_format_has_sint_channel(info
->format
))
97 /* More obvious restrictions */
98 if (isl_surf_usage_is_display(info
->usage
))
100 if (tiling
== ISL_TILING_LINEAR
)
103 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
104 * Suface Storage Format:
106 * +---------------------+----------------------------------------------------------------+
107 * | MSFMT_MSS | Multsampled surface was/is rendered as a render target |
108 * | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer |
109 * +---------------------+----------------------------------------------------------------+
111 * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and
112 * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED.
114 if (isl_surf_usage_is_depth_or_stencil(info
->usage
))
115 require_interleaved
= true;
117 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
118 * Suface Storage Format:
120 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
121 * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
122 * field must be set to MSFMT_MSS.
124 if (info
->samples
== 8 && info
->width
== 8192)
125 require_array
= true;
127 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
128 * Suface Storage Format:
130 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
131 * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number
132 * of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is
133 * > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.
135 if ((info
->samples
== 8 && info
->height
> 4194304u) ||
136 (info
->samples
== 4 && info
->height
> 8388608u))
137 require_interleaved
= true;
139 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
140 * Suface Storage Format:
142 * This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is
143 * one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
144 * R24_UNORM_X8_TYPELESS.
146 if (info
->format
== ISL_FORMAT_I24X8_UNORM
||
147 info
->format
== ISL_FORMAT_L24X8_UNORM
||
148 info
->format
== ISL_FORMAT_A24X8_UNORM
||
149 info
->format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
)
150 require_interleaved
= true;
152 if (require_array
&& require_interleaved
)
155 if (require_interleaved
) {
156 *msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
160 /* Default to the array layout because it permits multisample
163 *msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
168 gen7_format_needs_valign2(const struct isl_device
*dev
,
169 enum isl_format format
)
171 /* This workaround applies only to gen7 */
172 if (ISL_DEV_GEN(dev
) > 7)
175 /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
176 * RENDER_SURFACE_STATE Surface Vertical Alignment:
178 * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
179 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
182 * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
184 return isl_format_is_yuv(format
) ||
185 format
== ISL_FORMAT_R32G32B32_FLOAT
;
189 * @brief Filter out tiling flags that are incompatible with the surface.
191 * The resultant outgoing @a flags is a subset of the incoming @a flags. The
192 * outgoing flags may be empty (0x0) if the incoming flags were too
195 * For example, if the surface will be used for a display
196 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
197 * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT.
200 gen7_filter_tiling(const struct isl_device
*dev
,
201 const struct isl_surf_init_info
*restrict info
,
202 isl_tiling_flags_t
*flags
)
204 /* IVB+ requires separate stencil */
205 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
207 /* Clear flags unsupported on this hardware */
208 if (ISL_DEV_GEN(dev
) < 9) {
209 *flags
&= ~ISL_TILING_Yf_BIT
;
210 *flags
&= ~ISL_TILING_Ys_BIT
;
213 /* And... clear the Yf and Ys bits anyway because Anvil doesn't support
216 *flags
&= ~ISL_TILING_Yf_BIT
; /* FINISHME[SKL]: Support Yf */
217 *flags
&= ~ISL_TILING_Ys_BIT
; /* FINISHME[SKL]: Support Ys */
219 if (isl_surf_usage_is_depth(info
->usage
)) {
220 /* Depth requires Y. */
221 *flags
&= ISL_TILING_ANY_Y_MASK
;
224 /* Separate stencil requires W tiling, and W tiling requires separate
227 if (isl_surf_usage_is_stencil(info
->usage
)) {
228 *flags
&= ISL_TILING_W_BIT
;
230 *flags
&= ~ISL_TILING_W_BIT
;
233 if (info
->usage
& (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT
|
234 ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT
|
235 ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT
)) {
236 assert(*flags
& ISL_SURF_USAGE_DISPLAY_BIT
);
237 isl_finishme("%s:%s: handle rotated display surfaces",
241 if (info
->usage
& (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT
|
242 ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT
)) {
243 assert(*flags
& ISL_SURF_USAGE_DISPLAY_BIT
);
244 isl_finishme("%s:%s: handle flipped display surfaces",
248 if (info
->usage
& ISL_SURF_USAGE_DISPLAY_BIT
) {
249 /* Before Skylake, the display engine does not accept Y */
250 /* FINISHME[SKL]: Y tiling for display surfaces */
251 *flags
&= (ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
);
254 if (info
->samples
> 1) {
255 /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled
258 * For multisample render targets, this field must be 1 (true). MSRTs
261 * Multisample surfaces never require X tiling, and Y tiling generally
262 * performs better than X. So choose Y. (Unless it's stencil, then it
265 *flags
&= (ISL_TILING_ANY_Y_MASK
| ISL_TILING_W_BIT
);
269 if (ISL_DEV_GEN(dev
) == 7 &&
270 gen7_format_needs_valign2(dev
, info
->format
) &&
271 (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
272 info
->samples
== 1) {
273 /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
274 * SURFACE_STATE Surface Vertical Alignment:
276 * This field must be set to VALIGN_4 for all tiled Y Render Target
279 *flags
&= ~ISL_TILING_Y0_BIT
;
284 * Choose horizontal subimage alignment, in units of surface elements.
287 gen7_choose_halign_el(const struct isl_device
*dev
,
288 const struct isl_surf_init_info
*restrict info
)
290 if (isl_format_is_compressed(info
->format
))
293 /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
294 * RENDER_SURFACE_STATE Surface Hoizontal Alignment:
296 * - This field is intended to be set to HALIGN_8 only if the surface
297 * was rendered as a depth buffer with Z16 format or a stencil buffer,
298 * since these surfaces support only alignment of 8. Use of HALIGN_8
299 * for other surfaces is supported, but uses more memory.
301 if (isl_surf_info_is_z16(info
) ||
302 isl_surf_usage_is_stencil(info
->usage
))
309 * Choose vertical subimage alignment, in units of surface elements.
312 gen7_choose_valign_el(const struct isl_device
*dev
,
313 const struct isl_surf_init_info
*restrict info
,
314 enum isl_tiling tiling
)
316 bool require_valign2
= false;
317 bool require_valign4
= false;
319 if (isl_format_is_compressed(info
->format
))
322 if (gen7_format_needs_valign2(dev
, info
->format
))
323 require_valign2
= true;
325 /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1:
326 * RENDER_SURFACE_STATE Surface Vertical Alignment:
328 * - This field is intended to be set to VALIGN_4 if the surface was
329 * rendered as a depth buffer, for a multisampled (4x) render target,
330 * or for a multisampled (8x) render target, since these surfaces
331 * support only alignment of 4. Use of VALIGN_4 for other surfaces is
332 * supported, but uses more memory. This field must be set to
333 * VALIGN_4 for all tiled Y Render Target surfaces.
336 if (isl_surf_usage_is_depth(info
->usage
) ||
338 tiling
== ISL_TILING_Y0
) {
339 require_valign4
= true;
342 if (isl_surf_usage_is_stencil(info
->usage
)) {
343 /* The Ivybridge PRM states that the stencil buffer's vertical alignment
344 * is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment
345 * Unit Size]. However, valign=8 is outside the set of valid values of
346 * RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2
347 * (0x0) and VALIGN_4 (0x1).
349 * The PRM is generally confused about the width, height, and alignment
350 * of the stencil buffer; and this confusion appears elsewhere. For
351 * example, the following PRM text effectively converts the stencil
352 * buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM,
353 * Volume 1, Part 1, Section
354 * 6.18.4.2 Base Address and LOD Calculation]:
356 * For separate stencil buffer, the width must be mutiplied by 2 and
357 * height divided by 2 as follows:
359 * w_L = 2*i*ceil(W_L/i)
360 * h_L = 1/2*j*ceil(H_L/j)
362 * The root of the confusion is that, in W tiling, each pair of rows is
363 * interleaved into one.
365 * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API
368 require_valign4
= true;
371 assert(!require_valign2
|| !require_valign4
);
376 /* Prefer VALIGN_2 because it conserves memory. */
381 gen7_choose_image_alignment_el(const struct isl_device
*dev
,
382 const struct isl_surf_init_info
*restrict info
,
383 enum isl_tiling tiling
,
384 enum isl_msaa_layout msaa_layout
,
385 struct isl_extent3d
*image_align_el
)
387 /* IVB+ does not support combined depthstencil. */
388 assert(!isl_surf_usage_is_depth_and_stencil(info
->usage
));
390 *image_align_el
= (struct isl_extent3d
) {
391 .w
= gen7_choose_halign_el(dev
, info
),
392 .h
= gen7_choose_valign_el(dev
, info
, tiling
),