2 * Copyright 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 gen7_format_needs_valign2(const struct isl_device
*dev
,
29 enum isl_format format
)
31 assert(ISL_DEV_GEN(dev
) == 7);
33 /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
34 * RENDER_SURFACE_STATE Surface Vertical Alignment:
36 * - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
37 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
40 * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
42 * The R32G32B32_FLOAT restriction is dropped on Haswell.
44 return isl_format_is_yuv(format
) ||
45 (format
== ISL_FORMAT_R32G32B32_FLOAT
&& !ISL_DEV_IS_HASWELL(dev
));
49 isl_gen7_choose_msaa_layout(const struct isl_device
*dev
,
50 const struct isl_surf_init_info
*info
,
51 enum isl_tiling tiling
,
52 enum isl_msaa_layout
*msaa_layout
)
54 bool require_array
= false;
55 bool require_interleaved
= false;
57 assert(ISL_DEV_GEN(dev
) == 7);
58 assert(info
->samples
>= 1);
60 if (info
->samples
== 1) {
61 *msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
65 if (!isl_format_supports_multisampling(dev
->info
, info
->format
))
68 /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
71 * - If this field is any value other than MULTISAMPLECOUNT_1, the
72 * Surface Type must be SURFTYPE_2D.
74 * - If this field is any value other than MULTISAMPLECOUNT_1, Surface
75 * Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero
77 if (info
->dim
!= ISL_SURF_DIM_2D
)
82 /* The Ivyrbridge PRM insists twice that signed integer formats cannot be
85 * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
88 * - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
89 * all RT channels are not written.
91 * And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
92 * RENDER_SURFACE_STATE, MCS Enable:
94 * This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
95 * when all RT channels are not written.
97 * Note that the above SINT restrictions apply only to *MSRTs* (that is,
98 * *multisampled* render targets). The restrictions seem to permit an MCS
99 * if the render target is singlesampled.
101 * Moreover, empirically it looks that hardware can render multisampled
102 * surfaces with RGBA8I, RGBA16I and RGBA32I.
105 /* Multisampling requires vertical alignment of four. */
106 if (info
->samples
> 1 && gen7_format_needs_valign2(dev
, info
->format
))
109 /* More obvious restrictions */
110 if (isl_surf_usage_is_display(info
->usage
))
112 if (tiling
== ISL_TILING_LINEAR
)
115 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
116 * Suface Storage Format:
118 * +---------------------+----------------------------------------------------------------+
119 * | MSFMT_MSS | Multsampled surface was/is rendered as a render target |
120 * | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer |
121 * +---------------------+----------------------------------------------------------------+
123 * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and
124 * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED.
126 if (isl_surf_usage_is_depth_or_stencil(info
->usage
) ||
127 (info
->usage
& ISL_SURF_USAGE_HIZ_BIT
))
128 require_interleaved
= true;
130 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
131 * Suface Storage Format:
133 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
134 * is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
135 * field must be set to MSFMT_MSS.
137 if (info
->samples
== 8 && info
->width
> 8192)
138 require_array
= true;
140 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
141 * Suface Storage Format:
143 * If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
144 * ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number
145 * of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is
146 * > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.
148 if ((info
->samples
== 8 && info
->height
> 4194304u) ||
149 (info
->samples
== 4 && info
->height
> 8388608u))
150 require_interleaved
= true;
152 /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
153 * Suface Storage Format:
155 * This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is
156 * one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
157 * R24_UNORM_X8_TYPELESS.
159 if (info
->format
== ISL_FORMAT_I24X8_UNORM
||
160 info
->format
== ISL_FORMAT_L24X8_UNORM
||
161 info
->format
== ISL_FORMAT_A24X8_UNORM
||
162 info
->format
== ISL_FORMAT_R24_UNORM_X8_TYPELESS
)
163 require_interleaved
= true;
165 if (require_array
&& require_interleaved
)
168 if (require_interleaved
) {
169 *msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
173 /* Default to the array layout because it permits multisample
176 *msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
181 * @brief Filter out tiling flags that are incompatible with the surface.
183 * The resultant outgoing @a flags is a subset of the incoming @a flags. The
184 * outgoing flags may be empty (0x0) if the incoming flags were too
187 * For example, if the surface will be used for a display
188 * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
189 * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT.
192 isl_gen6_filter_tiling(const struct isl_device
*dev
,
193 const struct isl_surf_init_info
*restrict info
,
194 isl_tiling_flags_t
*flags
)
196 /* IVB+ requires separate stencil */
197 assert(ISL_DEV_USE_SEPARATE_STENCIL(dev
));
199 /* Clear flags unsupported on this hardware */
200 if (ISL_DEV_GEN(dev
) < 9) {
201 *flags
&= ~ISL_TILING_Yf_BIT
;
202 *flags
&= ~ISL_TILING_Ys_BIT
;
205 /* And... clear the Yf and Ys bits anyway because Anvil doesn't support
208 *flags
&= ~ISL_TILING_Yf_BIT
; /* FINISHME[SKL]: Support Yf */
209 *flags
&= ~ISL_TILING_Ys_BIT
; /* FINISHME[SKL]: Support Ys */
211 if (isl_surf_usage_is_depth(info
->usage
)) {
212 /* Depth requires Y. */
213 *flags
&= ISL_TILING_ANY_Y_MASK
;
216 if (isl_surf_usage_is_stencil(info
->usage
)) {
217 if (ISL_DEV_GEN(dev
) >= 12) {
218 /* Stencil requires Y. */
219 *flags
&= ISL_TILING_ANY_Y_MASK
;
221 /* Stencil requires W. */
222 *flags
&= ISL_TILING_W_BIT
;
225 *flags
&= ~ISL_TILING_W_BIT
;
228 /* From the SKL+ PRMs, RENDER_SURFACE_STATE:TileMode,
229 * If Surface Format is ASTC*, this field must be TILEMODE_YMAJOR.
231 if (isl_format_get_layout(info
->format
)->txc
== ISL_TXC_ASTC
)
232 *flags
&= ISL_TILING_Y0_BIT
;
234 /* MCS buffers are always Y-tiled */
235 if (isl_format_get_layout(info
->format
)->txc
== ISL_TXC_MCS
)
236 *flags
&= ISL_TILING_Y0_BIT
;
238 if (info
->usage
& (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT
|
239 ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT
|
240 ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT
)) {
241 assert(*flags
& ISL_SURF_USAGE_DISPLAY_BIT
);
242 isl_finishme("%s:%s: handle rotated display surfaces",
246 if (info
->usage
& (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT
|
247 ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT
)) {
248 assert(*flags
& ISL_SURF_USAGE_DISPLAY_BIT
);
249 isl_finishme("%s:%s: handle flipped display surfaces",
253 if (info
->usage
& ISL_SURF_USAGE_DISPLAY_BIT
) {
254 if (ISL_DEV_GEN(dev
) >= 12) {
255 *flags
&= (ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
|
257 } else if (ISL_DEV_GEN(dev
) >= 9) {
258 /* Note we let Yf even though it was cleared above. This is just for
261 *flags
&= (ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
|
262 ISL_TILING_Y0_BIT
| ISL_TILING_Yf_BIT
);
264 /* Before Skylake, the display engine does not accept Y */
265 *flags
&= (ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
);
269 if (info
->samples
> 1) {
270 /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled
273 * For multisample render targets, this field must be 1 (true). MSRTs
276 * From the Broadwell PRM >> Volume2d: Command Structures >>
277 * RENDER_SURFACE_STATE Tile Mode:
279 * If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
282 * As usual, though, stencil is special and requires W-tiling.
284 *flags
&= (ISL_TILING_ANY_Y_MASK
| ISL_TILING_W_BIT
);
288 if (ISL_DEV_GEN(dev
) == 7 &&
289 gen7_format_needs_valign2(dev
, info
->format
) &&
290 (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
291 info
->samples
== 1) {
292 /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
293 * SURFACE_STATE Surface Vertical Alignment:
295 * This field must be set to VALIGN_4 for all tiled Y Render Target
298 *flags
&= ~ISL_TILING_Y0_BIT
;
301 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
303 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
306 * This is necessary all the way back to 965, but is permitted on Gen7+.
308 if (ISL_DEV_GEN(dev
) < 7 && isl_format_get_layout(info
->format
)->bpb
>= 128)
309 *flags
&= ~ISL_TILING_Y0_BIT
;
311 /* From the BDW and SKL PRMs, Volume 2d,
312 * RENDER_SURFACE_STATE::Width - Programming Notes:
314 * A known issue exists if a primitive is rendered to the first 2 rows and
315 * last 2 columns of a 16K width surface. If any geometry is drawn inside
316 * this square it will be copied to column X=2 and X=3 (arrangement on Y
317 * position will stay the same). If any geometry exceeds the boundaries of
318 * this 2x2 region it will be drawn normally. The issue also only occurs
319 * if the surface has TileMode != Linear.
321 * [Internal documentation notes that this issue isn't present on SKL GT4.]
322 * To prevent this rendering corruption, only allow linear tiling for
323 * surfaces with widths greater than 16K-2 pixels.
325 * TODO: Is this an issue for multisampled surfaces as well?
327 if (info
->width
> 16382 && info
->samples
== 1 &&
328 info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
&&
329 (ISL_DEV_GEN(dev
) == 8 ||
330 (dev
->info
->is_skylake
&& dev
->info
->gt
!= 4))) {
331 *flags
&= ISL_TILING_LINEAR_BIT
;
336 isl_gen7_choose_image_alignment_el(const struct isl_device
*dev
,
337 const struct isl_surf_init_info
*restrict info
,
338 enum isl_tiling tiling
,
339 enum isl_dim_layout dim_layout
,
340 enum isl_msaa_layout msaa_layout
,
341 struct isl_extent3d
*image_align_el
)
343 assert(ISL_DEV_GEN(dev
) == 7);
345 /* Handled by isl_choose_image_alignment_el */
346 assert(info
->format
!= ISL_FORMAT_HIZ
);
348 /* IVB+ does not support combined depthstencil. */
349 assert(!isl_surf_usage_is_depth_and_stencil(info
->usage
));
351 /* From the Ivy Bridge PRM, Vol. 2, Part 2, Section 6.18.4.4,
352 * "Alignment unit size", the alignment parameters are summarized in the
355 * Surface Defined By | Surface Format | Align Width | Align Height
356 * --------------------+-----------------+-------------+--------------
357 * DEPTH_BUFFER | D16_UNORM | 8 | 4
359 * --------------------+-----------------+-------------+--------------
360 * STENCIL_BUFFER | N/A | 8 | 8
361 * --------------------+-----------------+-------------+--------------
362 * SURFACE_STATE | BC*, ETC*, EAC* | 4 | 4
364 * | all others | HALIGN | VALIGN
365 * -------------------------------------------------------------------
367 if (isl_surf_usage_is_depth(info
->usage
)) {
368 *image_align_el
= info
->format
== ISL_FORMAT_R16_UNORM
?
369 isl_extent3d(8, 4, 1) : isl_extent3d(4, 4, 1);
371 } else if (isl_surf_usage_is_stencil(info
->usage
)) {
372 *image_align_el
= isl_extent3d(8, 8, 1);
374 } else if (isl_format_is_compressed(info
->format
)) {
375 /* Compressed formats all have alignment equal to block size. */
376 *image_align_el
= isl_extent3d(1, 1, 1);
380 /* Everything after this point is in the "set by Surface Horizontal or
381 * Vertical Alignment" case. Now it's just a matter of applying
385 /* There are no restrictions on halign beyond what's given in the table
386 * above. We set it to the minimum value of 4 because that uses the least
389 const uint32_t halign
= 4;
391 bool require_valign4
= false;
393 /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1:
394 * RENDER_SURFACE_STATE Surface Vertical Alignment:
396 * * This field is intended to be set to VALIGN_4 if the surface was
397 * rendered as a depth buffer,
399 * * for a multisampled (4x) render target, or for a multisampled (8x)
400 * render target, since these surfaces support only alignment of 4.
402 * * This field must be set to VALIGN_4 for all tiled Y Render Target
405 * * Value of 1 is not supported for format YCRCB_NORMAL (0x182),
406 * YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190)
408 * * If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
409 * must be set to VALIGN_4."
411 * The first restriction is already handled by the table above and the
412 * second restriction is redundant with the fifth.
414 if (info
->samples
> 1)
415 require_valign4
= true;
417 if (tiling
== ISL_TILING_Y0
&&
418 (info
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
))
419 require_valign4
= true;
421 assert(!(require_valign4
&& gen7_format_needs_valign2(dev
, info
->format
)));
423 /* We default to VALIGN_2 because it uses the least memory. */
424 const uint32_t valign
= require_valign4
? 4 : 2;
426 *image_align_el
= isl_extent3d(halign
, valign
, 1);