src/intel/isl/isl_gen7.c

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include "isl_gen7.h"
  25 #include "isl_priv.h"
  26
  27 bool
  28 gen7_choose_msaa_layout(const struct isl_device *dev,
  29                         const struct isl_surf_init_info *info,
  30                         enum isl_tiling tiling,
  31                         enum isl_msaa_layout *msaa_layout)
  32 {
  33    const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
  34
  35    bool require_array = false;
  36    bool require_interleaved = false;
  37
  38    assert(ISL_DEV_GEN(dev) == 7);
  39    assert(info->samples >= 1);
  40
  41    if (info->samples == 1) {
  42       *msaa_layout = ISL_MSAA_LAYOUT_NONE;
  43       return true;
  44    }
  45
  46    /* From the Ivybridge PRM, Volume 4 Part 1 p63, SURFACE_STATE, Surface
  47     * Format:
  48     *
  49     *    If Number of Multisamples is set to a value other than
  50     *    MULTISAMPLECOUNT_1, this field cannot be set to the following
  51     *    formats: any format with greater than 64 bits per element, any
  52     *    compressed texture format (BC*), and any YCRCB* format.
  53     */
  54    if (fmtl->bpb > 64)
  55       return false;
  56    if (isl_format_is_compressed(info->format))
  57       return false;
  58    if (isl_format_is_yuv(info->format))
  59       return false;
  60
  61    /* From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
  62     * Multisamples:
  63     *
  64     *    - If this field is any value other than MULTISAMPLECOUNT_1, the
  65     *      Surface Type must be SURFTYPE_2D.
  66     *
  67     *    - If this field is any value other than MULTISAMPLECOUNT_1, Surface
  68     *      Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero
  69     */
  70    if (info->dim != ISL_SURF_DIM_2D)
  71       return false;
  72    if (info->levels > 1)
  73       return false;
  74
  75    /* The Ivyrbridge PRM insists twice that signed integer formats cannot be
  76     * multisampled.
  77     *
  78     * From the Ivybridge PRM, Volume 4 Part 1 p73, SURFACE_STATE, Number of
  79     * Multisamples:
  80     *
  81     *    - This field must be set to MULTISAMPLECOUNT_1 for SINT MSRTs when
  82     *      all RT channels are not written.
  83     *
  84     * And errata from the Ivybridge PRM, Volume 4 Part 1 p77,
  85     * RENDER_SURFACE_STATE, MCS Enable:
  86     *
  87     *   This field must be set to 0 [MULTISAMPLECOUNT_1] for all SINT MSRTs
  88     *   when all RT channels are not written.
  89     *
  90     * Note that the above SINT restrictions apply only to *MSRTs* (that is,
  91     * *multisampled* render targets). The restrictions seem to permit an MCS
  92     * if the render target is singlesampled.
  93     */
  94    if (isl_format_has_sint_channel(info->format))
  95       return false;
  96
  97    /* More obvious restrictions */
  98    if (isl_surf_usage_is_display(info->usage))
  99       return false;
 100    if (tiling == ISL_TILING_LINEAR)
 101       return false;
 102
 103    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 104     * Suface Storage Format:
 105     *
 106     *    +---------------------+----------------------------------------------------------------+
 107     *    | MSFMT_MSS           | Multsampled surface was/is rendered as a render target         |
 108     *    | MSFMT_DEPTH_STENCIL | Multisampled surface was rendered as a depth or stencil buffer |
 109     *    +---------------------+----------------------------------------------------------------+
 110     *
 111     * In the table above, MSFMT_MSS refers to ISL_MSAA_LAYOUT_ARRAY, and
 112     * MSFMT_DEPTH_STENCIL refers to ISL_MSAA_LAYOUT_INTERLEAVED.
 113     */
 114    if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
 115        (info->usage & ISL_SURF_USAGE_HIZ_BIT))
 116       require_interleaved = true;
 117
 118    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 119     * Suface Storage Format:
 120     *
 121     *    If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8, Width
 122     *    is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
 123     *    field must be set to MSFMT_MSS.
 124     */
 125    if (info->samples == 8 && info->width == 8192)
 126       require_array = true;
 127
 128    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 129     * Suface Storage Format:
 130     *
 131     *    If the surface’s Number of Multisamples is MULTISAMPLECOUNT_8,
 132     *    ((Depth+1) * (Height+1)) is > 4,194,304, OR if the surface’s Number
 133     *    of Multisamples is MULTISAMPLECOUNT_4, ((Depth+1) * (Height+1)) is
 134     *    > 8,388,608, this field must be set to MSFMT_DEPTH_STENCIL.
 135     */
 136    if ((info->samples == 8 && info->height > 4194304u) ||
 137        (info->samples == 4 && info->height > 8388608u))
 138       require_interleaved = true;
 139
 140    /* From the Ivybridge PRM, Volume 4 Part 1 p72, SURFACE_STATE, Multisampled
 141     * Suface Storage Format:
 142     *
 143     *    This field must be set to MSFMT_DEPTH_STENCIL if Surface Format is
 144     *    one of the following: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, or
 145     *    R24_UNORM_X8_TYPELESS.
 146     */
 147    if (info->format == ISL_FORMAT_I24X8_UNORM ||
 148        info->format == ISL_FORMAT_L24X8_UNORM ||
 149        info->format == ISL_FORMAT_A24X8_UNORM ||
 150        info->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS)
 151       require_interleaved = true;
 152
 153    if (require_array && require_interleaved)
 154       return false;
 155
 156    if (require_interleaved) {
 157       *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
 158       return true;
 159    }
 160
 161    /* Default to the array layout because it permits multisample
 162     * compression.
 163     */
 164    *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
 165    return true;
 166 }
 167
 168 static bool
 169 gen7_format_needs_valign2(const struct isl_device *dev,
 170                           enum isl_format format)
 171 {
 172    /* This workaround applies only to gen7 */
 173    if (ISL_DEV_GEN(dev) > 7)
 174       return false;
 175
 176    /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
 177     * RENDER_SURFACE_STATE Surface Vertical Alignment:
 178     *
 179     *    - Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
 180     *      (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
 181     *      (0x190)
 182     *
 183     *    - VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
 184     */
 185    return isl_format_is_yuv(format) ||
 186           format == ISL_FORMAT_R32G32B32_FLOAT;
 187 }
 188
 189 /**
 190  * @brief Filter out tiling flags that are incompatible with the surface.
 191  *
 192  * The resultant outgoing @a flags is a subset of the incoming @a flags. The
 193  * outgoing flags may be empty (0x0) if the incoming flags were too
 194  * restrictive.
 195  *
 196  * For example, if the surface will be used for a display
 197  * (ISL_SURF_USAGE_DISPLAY_BIT), then this function filters out all tiling
 198  * flags except ISL_TILING_X_BIT and ISL_TILING_LINEAR_BIT.
 199  */
 200 void
 201 gen6_filter_tiling(const struct isl_device *dev,
 202                    const struct isl_surf_init_info *restrict info,
 203                    isl_tiling_flags_t *flags)
 204 {
 205    /* IVB+ requires separate stencil */
 206    assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
 207
 208    /* Clear flags unsupported on this hardware */
 209    if (ISL_DEV_GEN(dev) < 9) {
 210       *flags &= ~ISL_TILING_Yf_BIT;
 211       *flags &= ~ISL_TILING_Ys_BIT;
 212    }
 213
 214    /* And... clear the Yf and Ys bits anyway because Anvil doesn't support
 215     * them yet.
 216     */
 217    *flags &= ~ISL_TILING_Yf_BIT; /* FINISHME[SKL]: Support Yf */
 218    *flags &= ~ISL_TILING_Ys_BIT; /* FINISHME[SKL]: Support Ys */
 219
 220    if (isl_surf_usage_is_depth(info->usage)) {
 221       /* Depth requires Y. */
 222       *flags &= ISL_TILING_ANY_Y_MASK;
 223    }
 224
 225    /* Separate stencil requires W tiling, and W tiling requires separate
 226     * stencil.
 227     */
 228    if (isl_surf_usage_is_stencil(info->usage)) {
 229       *flags &= ISL_TILING_W_BIT;
 230    } else {
 231       *flags &= ~ISL_TILING_W_BIT;
 232    }
 233
 234    /* The HiZ format and tiling always go together */
 235    if (info->format == ISL_FORMAT_HIZ) {
 236       *flags &= ISL_TILING_HIZ_BIT;
 237    } else {
 238       *flags &= ~ISL_TILING_HIZ_BIT;
 239    }
 240
 241    /* MCS buffers are always Y-tiled */
 242    if (isl_format_get_layout(info->format)->txc == ISL_TXC_MCS)
 243       *flags &= ISL_TILING_Y0_BIT;
 244
 245    /* The CCS formats and tiling always go together */
 246    if (isl_format_get_layout(info->format)->txc == ISL_TXC_CCS) {
 247       *flags &= ISL_TILING_CCS_BIT;
 248    } else {
 249       *flags &= ~ISL_TILING_CCS_BIT;
 250    }
 251
 252    if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
 253                       ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
 254                       ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
 255       assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
 256       isl_finishme("%s:%s: handle rotated display surfaces",
 257                    __FILE__, __func__);
 258    }
 259
 260    if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
 261                       ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
 262       assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
 263       isl_finishme("%s:%s: handle flipped display surfaces",
 264                    __FILE__, __func__);
 265    }
 266
 267    if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
 268       /* Before Skylake, the display engine does not accept Y */
 269       /* FINISHME[SKL]: Y tiling for display surfaces */
 270       *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
 271    }
 272
 273    if (info->samples > 1) {
 274       /* From the Sandybridge PRM, Volume 4 Part 1, SURFACE_STATE Tiled
 275        * Surface:
 276        *
 277        *   For multisample render targets, this field must be 1 (true). MSRTs
 278        *   can only be tiled.
 279        *
 280        * Multisample surfaces never require X tiling, and Y tiling generally
 281        * performs better than X. So choose Y. (Unless it's stencil, then it
 282        * must be W).
 283        */
 284       *flags &= (ISL_TILING_ANY_Y_MASK | ISL_TILING_W_BIT);
 285    }
 286
 287    /* workaround */
 288    if (ISL_DEV_GEN(dev) == 7 &&
 289        gen7_format_needs_valign2(dev, info->format) &&
 290        (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 291        info->samples == 1) {
 292       /* Y tiling is illegal. From the Ivybridge PRM, Vol4 Part1 2.12.2.1,
 293        * SURFACE_STATE Surface Vertical Alignment:
 294        *
 295        *     This field must be set to VALIGN_4 for all tiled Y Render Target
 296        *     surfaces.
 297        */
 298       *flags &= ~ISL_TILING_Y0_BIT;
 299    }
 300
 301    /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
 302     *
 303     *    "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either
 304     *     TileX or Linear."
 305     *
 306     * This is necessary all the way back to 965, but is permitted on Gen7+.
 307     */
 308    if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
 309       *flags &= ~ISL_TILING_Y0_BIT;
 310 }
 311
 312 /**
 313  * Choose horizontal subimage alignment, in units of surface elements.
 314  */
 315 static uint32_t
 316 gen7_choose_halign_el(const struct isl_device *dev,
 317                       const struct isl_surf_init_info *restrict info)
 318 {
 319    if (isl_format_is_compressed(info->format))
 320       return 1;
 321
 322    /* From the Ivybridge PRM (2012-05-31), Volume 4, Part 1, Section 2.12.1,
 323     * RENDER_SURFACE_STATE Surface Hoizontal Alignment:
 324     *
 325     *    - This field is intended to be set to HALIGN_8 only if the surface
 326     *      was rendered as a depth buffer with Z16 format or a stencil buffer,
 327     *      since these surfaces support only alignment of 8. Use of HALIGN_8
 328     *      for other surfaces is supported, but uses more memory.
 329     */
 330    if (isl_surf_info_is_z16(info) ||
 331        isl_surf_usage_is_stencil(info->usage))
 332       return 8;
 333
 334    return 4;
 335 }
 336
 337 /**
 338  * Choose vertical subimage alignment, in units of surface elements.
 339  */
 340 static uint32_t
 341 gen7_choose_valign_el(const struct isl_device *dev,
 342                       const struct isl_surf_init_info *restrict info,
 343                       enum isl_tiling tiling)
 344 {
 345    MAYBE_UNUSED bool require_valign2 = false;
 346    bool require_valign4 = false;
 347
 348    if (isl_format_is_compressed(info->format))
 349       return 1;
 350
 351    if (gen7_format_needs_valign2(dev, info->format))
 352       require_valign2 = true;
 353
 354    /* From the Ivybridge PRM, Volume 4, Part 1, Section 2.12.1:
 355     * RENDER_SURFACE_STATE Surface Vertical Alignment:
 356     *
 357     *    - This field is intended to be set to VALIGN_4 if the surface was
 358     *      rendered as a depth buffer, for a multisampled (4x) render target,
 359     *      or for a multisampled (8x) render target, since these surfaces
 360     *      support only alignment of 4.  Use of VALIGN_4 for other surfaces is
 361     *      supported, but uses more memory.  This field must be set to
 362     *      VALIGN_4 for all tiled Y Render Target surfaces.
 363     *
 364     */
 365    if (isl_surf_usage_is_depth(info->usage) ||
 366        info->samples > 1 ||
 367        ((info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 368         tiling == ISL_TILING_Y0)) {
 369       require_valign4 = true;
 370    }
 371
 372    if (isl_surf_usage_is_stencil(info->usage)) {
 373       /* The Ivybridge PRM states that the stencil buffer's vertical alignment
 374        * is 8 [Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.4 Alignment
 375        * Unit Size]. However, valign=8 is outside the set of valid values of
 376        * RENDER_SURFACE_STATE.SurfaceVerticalAlignment, which is VALIGN_2
 377        * (0x0) and VALIGN_4 (0x1).
 378        *
 379        * The PRM is generally confused about the width, height, and alignment
 380        * of the stencil buffer; and this confusion appears elsewhere. For
 381        * example, the following PRM text effectively converts the stencil
 382        * buffer's 8-pixel alignment to a 4-pixel alignment [Ivybridge PRM,
 383        * Volume 1, Part 1, Section
 384        * 6.18.4.2 Base Address and LOD Calculation]:
 385        *
 386        *    For separate stencil buffer, the width must be mutiplied by 2 and
 387        *    height divided by 2 as follows:
 388        *
 389        *       w_L = 2*i*ceil(W_L/i)
 390        *       h_L = 1/2*j*ceil(H_L/j)
 391        *
 392        * The root of the confusion is that, in W tiling, each pair of rows is
 393        * interleaved into one.
 394        *
 395        * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's API
 396        * is more polished.
 397        */
 398       require_valign4 = true;
 399    }
 400
 401    assert(!require_valign2 || !require_valign4);
 402
 403    if (require_valign4)
 404       return 4;
 405
 406    /* Prefer VALIGN_2 because it conserves memory. */
 407    return 2;
 408 }
 409
 410 void
 411 gen7_choose_image_alignment_el(const struct isl_device *dev,
 412                                const struct isl_surf_init_info *restrict info,
 413                                enum isl_tiling tiling,
 414                                enum isl_dim_layout dim_layout,
 415                                enum isl_msaa_layout msaa_layout,
 416                                struct isl_extent3d *image_align_el)
 417 {
 418    /* Handled by isl_choose_image_alignment_el */
 419    assert(info->format != ISL_FORMAT_HIZ);
 420
 421    /* IVB+ does not support combined depthstencil. */
 422    assert(!isl_surf_usage_is_depth_and_stencil(info->usage));
 423
 424    *image_align_el = (struct isl_extent3d) {
 425       .w = gen7_choose_halign_el(dev, info),
 426       .h = gen7_choose_valign_el(dev, info, tiling),
 427       .d = 1,
 428    };
 429 }