src/intel/isl/isl_gen8.c

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include "isl_gen8.h"
  25 #include "isl_priv.h"
  26
  27 bool
  28 isl_gen8_choose_msaa_layout(const struct isl_device *dev,
  29                             const struct isl_surf_init_info *info,
  30                             enum isl_tiling tiling,
  31                             enum isl_msaa_layout *msaa_layout)
  32 {
  33    bool require_array = false;
  34    bool require_interleaved = false;
  35
  36    assert(info->samples >= 1);
  37
  38    if (info->samples == 1) {
  39       *msaa_layout = ISL_MSAA_LAYOUT_NONE;
  40       return true;
  41    }
  42
  43    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  44     * RENDER_SURFACE_STATE Multisampled Surface Storage Format:
  45     *
  46     *    All multisampled render target surfaces must have this field set to
  47     *    MSFMT_MSS
  48     */
  49    if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
  50       require_array = true;
  51
  52    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  53     * RENDER_SURFACE_STATE Number of Multisamples:
  54     *
  55     *    - If this field is any value other than MULTISAMPLECOUNT_1, the
  56     *      Surface Type must be SURFTYPE_2D This field must be set to
  57     *      MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
  58     *      or Render Target surface.
  59     *
  60     *    - If this field is any value other than MULTISAMPLECOUNT_1, Surface
  61     *      Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
  62     */
  63    if (info->dim != ISL_SURF_DIM_2D)
  64       return false;
  65    if (info->levels > 1)
  66       return false;
  67
  68    /* More obvious restrictions */
  69    if (isl_surf_usage_is_display(info->usage))
  70       return false;
  71    if (!isl_format_supports_multisampling(dev->info, info->format))
  72       return false;
  73
  74    if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
  75        (info->usage & ISL_SURF_USAGE_HIZ_BIT))
  76       require_interleaved = true;
  77
  78    if (require_array && require_interleaved)
  79       return false;
  80
  81    if (require_interleaved) {
  82       *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
  83       return true;
  84    }
  85
  86    *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
  87    return true;
  88 }
  89
  90 /**
  91  * Choose horizontal subimage alignment, in units of surface elements.
  92  */
  93 static uint32_t
  94 gen8_choose_halign_el(const struct isl_device *dev,
  95                       const struct isl_surf_init_info *restrict info)
  96 {
  97    /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
  98     * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
  99     *
 100     *    - This field is intended to be set to HALIGN_8 only if the surface
 101     *      was rendered as a depth buffer with Z16 format or a stencil buffer.
 102     *      In this case it must be set to HALIGN_8 since these surfaces
 103     *      support only alignment of 8.  For Z32 formats it must be set to
 104     *      HALIGN_4.
 105     *
 106     * From the Broadwell PRM, Volume 4, "Memory Views" p. 186, the alignment
 107     * parameters are summarized in the following table:
 108     *
 109     *     Surface Defined By | Surface Format  | Align Width | Align Height
 110     *    --------------------+-----------------+-------------+--------------
 111     *       DEPTH_BUFFER     |   D16_UNORM     |      8      |      4
 112     *                        |     other       |      4      |      4
 113     *    --------------------+-----------------+-------------+--------------
 114     *       STENCIL_BUFFER   |      N/A        |      8      |      8
 115     *    --------------------+-----------------+-------------+--------------
 116     *       SURFACE_STATE    | BC*, ETC*, EAC* |      4      |      4
 117     *                        |      FXT1       |      8      |      4
 118     *                        |   all others    |   HALIGN    |   VALIGN
 119     *    -------------------------------------------------------------------
 120     */
 121    if (isl_surf_usage_is_depth(info->usage))
 122       return info->format == ISL_FORMAT_R16_UNORM ? 8 : 4;
 123
 124    if (isl_surf_usage_is_stencil(info->usage))
 125       return 8;
 126
 127    /* All compressed formats in the above table have an alignment equal to
 128     * their compression block size.  This translates to an alignment in
 129     * elements of 1.
 130     */
 131    if (isl_format_is_compressed(info->format))
 132       return 1;
 133
 134    if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
 135       /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 136        * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 137        *
 138        *    - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
 139        *      HALIGN 16 must be used.
 140        *
 141        * This case handles color surfaces that may own an auxiliary MCS, CCS_D,
 142        * or CCS_E. Depth buffers, including those that own an auxiliary HiZ
 143        * surface, are handled above and do not require HALIGN_16.
 144        */
 145       assert(!isl_surf_usage_is_depth(info->usage));
 146       return 16;
 147    }
 148
 149    /* XXX(chadv): I believe the hardware requires each image to be
 150     * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
 151     * many formats. Depending on the format's block size, we may need to
 152     * increase halign to 8.
 153     */
 154    return 4;
 155 }
 156
 157 /**
 158  * Choose vertical subimage alignment, in units of surface elements.
 159  */
 160 static uint32_t
 161 gen8_choose_valign_el(const struct isl_device *dev,
 162                       const struct isl_surf_init_info *restrict info)
 163 {
 164    /* From the Broadwell PRM > Volume 2d: Command Reference: Structures
 165     * > RENDER_SURFACE_STATE Surface Vertical Alignment (p325):
 166     *
 167     *    - For Sampling Engine and Render Target Surfaces: This field
 168     *      specifies the vertical alignment requirement in elements for the
 169     *      surface. [...] An element is defined as a pixel in uncompresed
 170     *      surface formats, and as a compression block in compressed surface
 171     *      formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
 172     *      element is a sample.
 173     *
 174     *    - This field is intended to be set to VALIGN_4 if the surface was
 175     *      rendered as a depth buffer, for a multisampled (4x) render target,
 176     *      or for a multisampled (8x) render target, since these surfaces
 177     *      support only alignment of 4. Use of VALIGN_4 for other surfaces is
 178     *      supported, but increases memory usage.
 179     *
 180     *    - This field is intended to be set to VALIGN_8 only if the surface
 181     *       was rendered as a stencil buffer, since stencil buffer surfaces
 182     *       support only alignment of 8. If set to VALIGN_8, Surface Format
 183     *       must be R8_UINT.
 184     *
 185     * From the Broadwell PRM, Volume 4, "Memory Views" p. 186, the alignment
 186     * parameters are summarized in the following table:
 187     *
 188     *     Surface Defined By | Surface Format  | Align Width | Align Height
 189     *    --------------------+-----------------+-------------+--------------
 190     *       DEPTH_BUFFER     |   D16_UNORM     |      8      |      4
 191     *                        |     other       |      4      |      4
 192     *    --------------------+-----------------+-------------+--------------
 193     *       STENCIL_BUFFER   |      N/A        |      8      |      8
 194     *    --------------------+-----------------+-------------+--------------
 195     *       SURFACE_STATE    | BC*, ETC*, EAC* |      4      |      4
 196     *                        |      FXT1       |      8      |      4
 197     *                        |   all others    |   HALIGN    |   VALIGN
 198     *    -------------------------------------------------------------------
 199     */
 200    if (isl_surf_usage_is_depth(info->usage))
 201       return 4;
 202
 203    if (isl_surf_usage_is_stencil(info->usage))
 204       return 8;
 205
 206    /* All compressed formats in the above table have an alignment equal to
 207     * their compression block size.  This translates to an alignment in
 208     * elements of 1.
 209     */
 210    if (isl_format_is_compressed(info->format))
 211       return 1;
 212
 213    return 4;
 214 }
 215
 216 void
 217 isl_gen8_choose_image_alignment_el(const struct isl_device *dev,
 218                                    const struct isl_surf_init_info *restrict info,
 219                                    enum isl_tiling tiling,
 220                                    enum isl_dim_layout dim_layout,
 221                                    enum isl_msaa_layout msaa_layout,
 222                                    struct isl_extent3d *image_align_el)
 223 {
 224    /* Handled by isl_choose_image_alignment_el */
 225    assert(info->format != ISL_FORMAT_HIZ);
 226
 227    assert(!isl_tiling_is_std_y(tiling));
 228
 229    const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
 230    if (fmtl->txc == ISL_TXC_CCS) {
 231       /*
 232        * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676):
 233        *
 234        *    "Mip-mapped and arrayed surfaces are supported with MCS buffer
 235        *    layout with these alignments in the RT space: Horizontal
 236        *    Alignment = 256 and Vertical Alignment = 128.
 237        */
 238       *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1);
 239       return;
 240    }
 241
 242    /* The below text from the Broadwell PRM provides some insight into the
 243     * hardware's requirements for LOD alignment.  From the Broadwell PRM >>
 244     * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces:
 245     *
 246     *    These [2D surfaces] must adhere to the following memory organization
 247     *    rules:
 248     *
 249     *       - For non-compressed texture formats, each mipmap must start on an
 250     *         even row within the monolithic rectangular area. For
 251     *         1-texel-high mipmaps, this may require a row of padding below
 252     *         the previous mipmap. This restriction does not apply to any
 253     *         compressed texture formats; each subsequent (lower-res)
 254     *         compressed mipmap is positioned directly below the previous
 255     *         mipmap.
 256     *
 257     *       - Vertical alignment restrictions vary with memory tiling type:
 258     *         1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled
 259     *         mipmaps are not required to start at the left edge of a tile
 260     *         row.)
 261     */
 262
 263    *image_align_el = (struct isl_extent3d) {
 264       .w = gen8_choose_halign_el(dev, info),
 265       .h = gen8_choose_valign_el(dev, info),
 266       .d = 1,
 267    };
 268 }