src/intel/isl/isl_gen8.c

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include "isl_gen8.h"
  25 #include "isl_priv.h"
  26
  27 bool
  28 gen8_choose_msaa_layout(const struct isl_device *dev,
  29                         const struct isl_surf_init_info *info,
  30                         enum isl_tiling tiling,
  31                         enum isl_msaa_layout *msaa_layout)
  32 {
  33    bool require_array = false;
  34    bool require_interleaved = false;
  35
  36    assert(info->samples >= 1);
  37
  38    if (info->samples == 1) {
  39       *msaa_layout = ISL_MSAA_LAYOUT_NONE;
  40       return true;
  41    }
  42
  43    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  44     * RENDER_SURFACE_STATE Tile Mode:
  45     *
  46     *    - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
  47     *      must be YMAJOR.
  48     *
  49     * As usual, though, stencil is special.
  50     */
  51    if (!isl_tiling_is_any_y(tiling) && !isl_surf_usage_is_stencil(info->usage))
  52       return false;
  53
  54    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  55     * RENDER_SURFACE_STATE Multisampled Surface Storage Format:
  56     *
  57     *    All multisampled render target surfaces must have this field set to
  58     *    MSFMT_MSS
  59     */
  60    if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
  61       require_array = true;
  62
  63    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  64     * RENDER_SURFACE_STATE Number of Multisamples:
  65     *
  66     *    - If this field is any value other than MULTISAMPLECOUNT_1, the
  67     *      Surface Type must be SURFTYPE_2D This field must be set to
  68     *      MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
  69     *      or Render Target surface.
  70     *
  71     *    - If this field is any value other than MULTISAMPLECOUNT_1, Surface
  72     *      Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
  73     */
  74    if (info->dim != ISL_SURF_DIM_2D)
  75       return false;
  76    if (info->levels > 1)
  77       return false;
  78
  79    /* More obvious restrictions */
  80    if (isl_surf_usage_is_display(info->usage))
  81       return false;
  82    if (isl_format_is_compressed(info->format))
  83       return false;
  84    if (isl_format_is_yuv(info->format))
  85       return false;
  86
  87    if (isl_surf_usage_is_depth_or_stencil(info->usage) ||
  88        (info->usage & ISL_SURF_USAGE_HIZ_BIT))
  89       require_interleaved = true;
  90
  91    if (require_array && require_interleaved)
  92       return false;
  93
  94    if (require_interleaved) {
  95       *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
  96       return true;
  97    }
  98
  99    *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
 100    return true;
 101 }
 102
 103 /**
 104  * Choose horizontal subimage alignment, in units of surface elements.
 105  */
 106 static uint32_t
 107 gen8_choose_halign_el(const struct isl_device *dev,
 108                       const struct isl_surf_init_info *restrict info)
 109 {
 110    if (isl_format_is_compressed(info->format))
 111       return 1;
 112
 113    /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 114     * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 115     *
 116     *    - This field is intended to be set to HALIGN_8 only if the surface
 117     *      was rendered as a depth buffer with Z16 format or a stencil buffer.
 118     *      In this case it must be set to HALIGN_8 since these surfaces
 119     *      support only alignment of 8. [...]
 120     */
 121    if (isl_surf_info_is_z16(info))
 122       return 8;
 123    if (isl_surf_usage_is_stencil(info->usage))
 124       return 8;
 125
 126    /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 127     * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 128     *
 129     *      [...] For Z32 formats it must be set to HALIGN_4.
 130     */
 131    if (isl_surf_usage_is_depth(info->usage))
 132       return 4;
 133
 134    if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
 135       /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 136        * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 137        *
 138        *    - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
 139        *      HALIGN 16 must be used.
 140        *
 141        * This case handles color surfaces that may own an auxiliary MCS, CCS_D,
 142        * or CCS_E. Depth buffers, including those that own an auxiliary HiZ
 143        * surface, are handled above and do not require HALIGN_16.
 144        */
 145       assert(!isl_surf_usage_is_depth(info->usage));
 146       return 16;
 147    }
 148
 149    /* XXX(chadv): I believe the hardware requires each image to be
 150     * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
 151     * many formats. Depending on the format's block size, we may need to
 152     * increase halign to 8.
 153     */
 154    return 4;
 155 }
 156
 157 /**
 158  * Choose vertical subimage alignment, in units of surface elements.
 159  */
 160 static uint32_t
 161 gen8_choose_valign_el(const struct isl_device *dev,
 162                       const struct isl_surf_init_info *restrict info)
 163 {
 164    /* From the Broadwell PRM > Volume 2d: Command Reference: Structures
 165     * > RENDER_SURFACE_STATE Surface Vertical Alignment (p325):
 166     *
 167     *    - For Sampling Engine and Render Target Surfaces: This field
 168     *      specifies the vertical alignment requirement in elements for the
 169     *      surface. [...] An element is defined as a pixel in uncompresed
 170     *      surface formats, and as a compression block in compressed surface
 171     *      formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
 172     *      element is a sample.
 173     *
 174     *    - This field is intended to be set to VALIGN_4 if the surface was
 175     *      rendered as a depth buffer, for a multisampled (4x) render target,
 176     *      or for a multisampled (8x) render target, since these surfaces
 177     *      support only alignment of 4. Use of VALIGN_4 for other surfaces is
 178     *      supported, but increases memory usage.
 179     *
 180     *    - This field is intended to be set to VALIGN_8 only if the surface
 181     *       was rendered as a stencil buffer, since stencil buffer surfaces
 182     *       support only alignment of 8. If set to VALIGN_8, Surface Format
 183     *       must be R8_UINT.
 184     */
 185
 186    if (isl_format_is_compressed(info->format))
 187       return 1;
 188
 189    if (isl_surf_usage_is_stencil(info->usage))
 190       return 8;
 191
 192    return 4;
 193 }
 194
 195 void
 196 gen8_choose_image_alignment_el(const struct isl_device *dev,
 197                                const struct isl_surf_init_info *restrict info,
 198                                enum isl_tiling tiling,
 199                                enum isl_msaa_layout msaa_layout,
 200                                struct isl_extent3d *image_align_el)
 201 {
 202    /* Handled by isl_choose_image_alignment_el */
 203    assert(info->format != ISL_FORMAT_HIZ);
 204
 205    assert(!isl_tiling_is_std_y(tiling));
 206
 207    const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
 208    if (fmtl->txc == ISL_TXC_CCS) {
 209       /*
 210        * Broadwell PRM Vol 7, "MCS Buffer for Render Target(s)" (p. 676):
 211        *
 212        *    "Mip-mapped and arrayed surfaces are supported with MCS buffer
 213        *    layout with these alignments in the RT space: Horizontal
 214        *    Alignment = 256 and Vertical Alignment = 128.
 215        */
 216       *image_align_el = isl_extent3d(256 / fmtl->bw, 128 / fmtl->bh, 1);
 217       return;
 218    }
 219
 220    /* The below text from the Broadwell PRM provides some insight into the
 221     * hardware's requirements for LOD alignment.  From the Broadwell PRM >>
 222     * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces:
 223     *
 224     *    These [2D surfaces] must adhere to the following memory organization
 225     *    rules:
 226     *
 227     *       - For non-compressed texture formats, each mipmap must start on an
 228     *         even row within the monolithic rectangular area. For
 229     *         1-texel-high mipmaps, this may require a row of padding below
 230     *         the previous mipmap. This restriction does not apply to any
 231     *         compressed texture formats; each subsequent (lower-res)
 232     *         compressed mipmap is positioned directly below the previous
 233     *         mipmap.
 234     *
 235     *       - Vertical alignment restrictions vary with memory tiling type:
 236     *         1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled
 237     *         mipmaps are not required to start at the left edge of a tile
 238     *         row.)
 239     */
 240
 241    *image_align_el = (struct isl_extent3d) {
 242       .w = gen8_choose_halign_el(dev, info),
 243       .h = gen8_choose_valign_el(dev, info),
 244       .d = 1,
 245    };
 246 }