src/intel/isl/isl_gen8.c

   1 /*
   2  * Copyright 2015 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include "isl_gen8.h"
  25 #include "isl_priv.h"
  26
  27 bool
  28 gen8_choose_msaa_layout(const struct isl_device *dev,
  29                         const struct isl_surf_init_info *info,
  30                         enum isl_tiling tiling,
  31                         enum isl_msaa_layout *msaa_layout)
  32 {
  33    bool require_array = false;
  34    bool require_interleaved = false;
  35
  36    assert(info->samples >= 1);
  37
  38    if (info->samples == 1) {
  39       *msaa_layout = ISL_MSAA_LAYOUT_NONE;
  40       return true;
  41    }
  42
  43    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  44     * RENDER_SURFACE_STATE Tile Mode:
  45     *
  46     *    - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
  47     *      must be YMAJOR.
  48     *
  49     * As usual, though, stencil is special.
  50     */
  51    if (!isl_tiling_is_any_y(tiling) && !isl_surf_usage_is_stencil(info->usage))
  52       return false;
  53
  54    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  55     * RENDER_SURFACE_STATE Multisampled Surface Storage Format:
  56     *
  57     *    All multisampled render target surfaces must have this field set to
  58     *    MSFMT_MSS
  59     */
  60    if (info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
  61       require_array = true;
  62
  63    /* From the Broadwell PRM >> Volume2d: Command Structures >>
  64     * RENDER_SURFACE_STATE Number of Multisamples:
  65     *
  66     *    - If this field is any value other than MULTISAMPLECOUNT_1, the
  67     *      Surface Type must be SURFTYPE_2D This field must be set to
  68     *      MULTISAMPLECOUNT_1 unless the surface is a Sampling Engine surface
  69     *      or Render Target surface.
  70     *
  71     *    - If this field is any value other than MULTISAMPLECOUNT_1, Surface
  72     *      Min LOD, Mip Count / LOD, and Resource Min LOD must be set to zero.
  73     */
  74    if (info->dim != ISL_SURF_DIM_2D)
  75       return false;
  76    if (info->levels > 1)
  77       return false;
  78
  79    /* More obvious restrictions */
  80    if (isl_surf_usage_is_display(info->usage))
  81       return false;
  82    if (isl_format_is_compressed(info->format))
  83       return false;
  84    if (isl_format_is_yuv(info->format))
  85       return false;
  86
  87    if (isl_surf_usage_is_depth_or_stencil(info->usage))
  88       require_interleaved = true;
  89
  90    if (require_array && require_interleaved)
  91       return false;
  92
  93    if (require_interleaved) {
  94       *msaa_layout = ISL_MSAA_LAYOUT_INTERLEAVED;
  95       return true;
  96    }
  97
  98    *msaa_layout = ISL_MSAA_LAYOUT_ARRAY;
  99    return true;
 100 }
 101
 102 /**
 103  * Choose horizontal subimage alignment, in units of surface elements.
 104  */
 105 static uint32_t
 106 gen8_choose_halign_el(const struct isl_device *dev,
 107                       const struct isl_surf_init_info *restrict info)
 108 {
 109    if (isl_format_is_compressed(info->format))
 110       return 1;
 111
 112    /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 113     * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 114     *
 115     *    - This field is intended to be set to HALIGN_8 only if the surface
 116     *      was rendered as a depth buffer with Z16 format or a stencil buffer.
 117     *      In this case it must be set to HALIGN_8 since these surfaces
 118     *      support only alignment of 8. [...]
 119     */
 120    if (isl_surf_info_is_z16(info))
 121       return 8;
 122    if (isl_surf_usage_is_stencil(info->usage))
 123       return 8;
 124
 125    /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 126     * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 127     *
 128     *      [...] For Z32 formats it must be set to HALIGN_4.
 129     */
 130    if (isl_surf_usage_is_depth(info->usage))
 131       return 4;
 132
 133    if (!(info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
 134       /* From the Broadwell PRM, Volume 2d "Command Reference: Structures",
 135        * RENDER_SURFACE_STATE Surface Horizontal Alignment, p326:
 136        *
 137        *    - When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
 138        *      HALIGN 16 must be used.
 139        *
 140        * This case handles color surfaces that may own an auxiliary MCS, CCS_D,
 141        * or CCS_E. Depth buffers, including those that own an auxiliary HiZ
 142        * surface, are handled above and do not require HALIGN_16.
 143        */
 144       assert(!isl_surf_usage_is_depth(info->usage));
 145       return 16;
 146    }
 147
 148    /* XXX(chadv): I believe the hardware requires each image to be
 149     * cache-aligned. If that's true, then defaulting to halign=4 is wrong for
 150     * many formats. Depending on the format's block size, we may need to
 151     * increase halign to 8.
 152     */
 153    return 4;
 154 }
 155
 156 /**
 157  * Choose vertical subimage alignment, in units of surface elements.
 158  */
 159 static uint32_t
 160 gen8_choose_valign_el(const struct isl_device *dev,
 161                       const struct isl_surf_init_info *restrict info)
 162 {
 163    /* From the Broadwell PRM > Volume 2d: Command Reference: Structures
 164     * > RENDER_SURFACE_STATE Surface Vertical Alignment (p325):
 165     *
 166     *    - For Sampling Engine and Render Target Surfaces: This field
 167     *      specifies the vertical alignment requirement in elements for the
 168     *      surface. [...] An element is defined as a pixel in uncompresed
 169     *      surface formats, and as a compression block in compressed surface
 170     *      formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
 171     *      element is a sample.
 172     *
 173     *    - This field is intended to be set to VALIGN_4 if the surface was
 174     *      rendered as a depth buffer, for a multisampled (4x) render target,
 175     *      or for a multisampled (8x) render target, since these surfaces
 176     *      support only alignment of 4. Use of VALIGN_4 for other surfaces is
 177     *      supported, but increases memory usage.
 178     *
 179     *    - This field is intended to be set to VALIGN_8 only if the surface
 180     *       was rendered as a stencil buffer, since stencil buffer surfaces
 181     *       support only alignment of 8. If set to VALIGN_8, Surface Format
 182     *       must be R8_UINT.
 183     */
 184
 185    if (isl_format_is_compressed(info->format))
 186       return 1;
 187
 188    if (isl_surf_usage_is_stencil(info->usage))
 189       return 8;
 190
 191    return 4;
 192 }
 193
 194 void
 195 gen8_choose_image_alignment_el(const struct isl_device *dev,
 196                                const struct isl_surf_init_info *restrict info,
 197                                enum isl_tiling tiling,
 198                                enum isl_msaa_layout msaa_layout,
 199                                struct isl_extent3d *image_align_el)
 200 {
 201    assert(!isl_tiling_is_std_y(tiling));
 202
 203    /* The below text from the Broadwell PRM provides some insight into the
 204     * hardware's requirements for LOD alignment.  From the Broadwell PRM >>
 205     * Volume 5: Memory Views >> Surface Layout >> 2D Surfaces:
 206     *
 207     *    These [2D surfaces] must adhere to the following memory organization
 208     *    rules:
 209     *
 210     *       - For non-compressed texture formats, each mipmap must start on an
 211     *         even row within the monolithic rectangular area. For
 212     *         1-texel-high mipmaps, this may require a row of padding below
 213     *         the previous mipmap. This restriction does not apply to any
 214     *         compressed texture formats; each subsequent (lower-res)
 215     *         compressed mipmap is positioned directly below the previous
 216     *         mipmap.
 217     *
 218     *       - Vertical alignment restrictions vary with memory tiling type:
 219     *         1 DWord for linear, 16-byte (DQWord) for tiled. (Note that tiled
 220     *         mipmaps are not required to start at the left edge of a tile
 221     *         row.)
 222     */
 223
 224    *image_align_el = (struct isl_extent3d) {
 225       .w = gen8_choose_halign_el(dev, info),
 226       .h = gen8_choose_valign_el(dev, info),
 227       .d = 1,
 228    };
 229 }