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29 * Calculate the surface's subimage alignment, in units of surface samples,
30 * for the standard tiling formats Yf and Ys.
33 gen9_calc_std_image_alignment_sa(const struct isl_device
*dev
,
34 const struct isl_surf_init_info
*restrict info
,
35 enum isl_tiling tiling
,
36 enum isl_msaa_layout msaa_layout
,
37 struct isl_extent3d
*align_sa
)
39 const struct isl_format_layout
*fmtl
= isl_format_get_layout(info
->format
);
41 assert(isl_tiling_is_std_y(tiling
));
43 const uint32_t bpb
= fmtl
->bpb
;
44 const uint32_t is_Ys
= tiling
== ISL_TILING_Ys
;
48 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
49 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
51 *align_sa
= (struct isl_extent3d
) {
52 .w
= 1 << (12 - (ffs(bpb
) - 4) + (4 * is_Ys
)),
58 /* See the Skylake BSpec > Memory Views > Common Surface Formats >
59 * Surface Layout and Tiling > 2D Surfaces > 2D/CUBE Alignment
62 *align_sa
= (struct isl_extent3d
) {
63 .w
= 1 << (6 - ((ffs(bpb
) - 4) / 2) + (4 * is_Ys
)),
64 .h
= 1 << (6 - ((ffs(bpb
) - 3) / 2) + (4 * is_Ys
)),
69 /* FINISHME(chadv): I don't trust this code. Untested. */
70 isl_finishme("%s:%s: [SKL+] multisample TileYs", __FILE__
, __func__
);
72 switch (msaa_layout
) {
73 case ISL_MSAA_LAYOUT_NONE
:
74 case ISL_MSAA_LAYOUT_INTERLEAVED
:
76 case ISL_MSAA_LAYOUT_ARRAY
:
77 align_sa
->w
>>= (ffs(info
->samples
) - 0) / 2;
78 align_sa
->h
>>= (ffs(info
->samples
) - 1) / 2;
85 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
86 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
88 *align_sa
= (struct isl_extent3d
) {
89 .w
= 1 << (4 - ((ffs(bpb
) - 2) / 3) + (4 * is_Ys
)),
90 .h
= 1 << (4 - ((ffs(bpb
) - 4) / 3) + (2 * is_Ys
)),
91 .d
= 1 << (4 - ((ffs(bpb
) - 3) / 3) + (2 * is_Ys
)),
96 unreachable("bad isl_surface_type");
100 gen9_choose_image_alignment_el(const struct isl_device
*dev
,
101 const struct isl_surf_init_info
*restrict info
,
102 enum isl_tiling tiling
,
103 enum isl_msaa_layout msaa_layout
,
104 struct isl_extent3d
*image_align_el
)
106 /* Handled by isl_choose_image_alignment_el */
107 assert(info
->format
!= ISL_FORMAT_HIZ
);
109 /* This BSpec text provides some insight into the hardware's alignment
110 * requirements [Skylake BSpec > Memory Views > Common Surface Formats >
111 * Surface Layout and Tiling > 2D Surfaces]:
113 * An LOD must be aligned to a cache-line except for some special cases
114 * related to Planar YUV surfaces. In general, the cache-alignment
115 * restriction implies there is a minimum height for an LOD of 4 texels.
116 * So, LODs which are smaller than 4 high are padded.
118 * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Vertical Alignment:
120 * - For Sampling Engine and Render Target Surfaces: This field
121 * specifies the vertical alignment requirement in elements for the
122 * surface. [...] An element is defined as a pixel in uncompresed
123 * surface formats, and as a compression block in compressed surface
124 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
125 * element is a sample.
127 * - This field is used for 2D, CUBE, and 3D surface alignment when Tiled
128 * Resource Mode is TRMODE_NONE (Tiled Resource Mode is disabled).
129 * This field is ignored for 1D surfaces and also when Tiled Resource
130 * Mode is not TRMODE_NONE (e.g. Tiled Resource Mode is enabled).
132 * See the appropriate Alignment table in the "Surface Layout and
133 * Tiling" section under Common Surface Formats for the table of
134 * alignment values for Tiled Resrouces.
136 * - For uncompressed surfaces, the units of "j" are rows of pixels on
137 * the physical surface. For compressed texture formats, the units of
138 * "j" are in compression blocks, thus each increment in "j" is equal
139 * to h pixels, where h is the height of the compression block in
142 * - Valid Values: VALIGN_4, VALIGN_8, VALIGN_16
144 * From the Skylake BSpec, RENDER_SURFACE_STATE Surface Horizontal
147 * - For uncompressed surfaces, the units of "i" are pixels on the
148 * physical surface. For compressed texture formats, the units of "i"
149 * are in compression blocks, thus each increment in "i" is equal to
150 * w pixels, where w is the width of the compression block in pixels.
152 * - Valid Values: HALIGN_4, HALIGN_8, HALIGN_16
155 if (isl_tiling_is_std_y(tiling
)) {
156 struct isl_extent3d image_align_sa
;
157 gen9_calc_std_image_alignment_sa(dev
, info
, tiling
, msaa_layout
,
160 *image_align_el
= isl_extent3d_sa_to_el(info
->format
, image_align_sa
);
164 if (info
->dim
== ISL_SURF_DIM_1D
) {
165 /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
166 * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
168 *image_align_el
= isl_extent3d(64, 1, 1);
172 if (isl_format_is_compressed(info
->format
)) {
173 /* On Gen9, the meaning of RENDER_SURFACE_STATE's
174 * SurfaceHorizontalAlignment and SurfaceVerticalAlignment changed for
175 * compressed formats. They now indicate a multiple of the compression
176 * block. For example, if the compression mode is ETC2 then HALIGN_4
177 * indicates a horizontal alignment of 16 pixels.
179 * To avoid wasting memory, choose the smallest alignment possible:
180 * HALIGN_4 and VALIGN_4.
182 *image_align_el
= isl_extent3d(4, 4, 1);
186 gen8_choose_image_alignment_el(dev
, info
, tiling
, msaa_layout
,