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25 #include "compiler/brw_compiler.h"
28 isl_is_storage_image_format(enum isl_format format
)
30 /* XXX: Maybe we should put this in the CSV? */
33 case ISL_FORMAT_R32G32B32A32_UINT
:
34 case ISL_FORMAT_R32G32B32A32_SINT
:
35 case ISL_FORMAT_R32G32B32A32_FLOAT
:
36 case ISL_FORMAT_R32_UINT
:
37 case ISL_FORMAT_R32_SINT
:
38 case ISL_FORMAT_R32_FLOAT
:
39 case ISL_FORMAT_R16G16B16A16_UINT
:
40 case ISL_FORMAT_R16G16B16A16_SINT
:
41 case ISL_FORMAT_R16G16B16A16_FLOAT
:
42 case ISL_FORMAT_R32G32_UINT
:
43 case ISL_FORMAT_R32G32_SINT
:
44 case ISL_FORMAT_R32G32_FLOAT
:
45 case ISL_FORMAT_R8G8B8A8_UINT
:
46 case ISL_FORMAT_R8G8B8A8_SINT
:
47 case ISL_FORMAT_R16G16_UINT
:
48 case ISL_FORMAT_R16G16_SINT
:
49 case ISL_FORMAT_R16G16_FLOAT
:
50 case ISL_FORMAT_R8G8_UINT
:
51 case ISL_FORMAT_R8G8_SINT
:
52 case ISL_FORMAT_R16_UINT
:
53 case ISL_FORMAT_R16_FLOAT
:
54 case ISL_FORMAT_R16_SINT
:
55 case ISL_FORMAT_R8_UINT
:
56 case ISL_FORMAT_R8_SINT
:
57 case ISL_FORMAT_R10G10B10A2_UINT
:
58 case ISL_FORMAT_R10G10B10A2_UNORM
:
59 case ISL_FORMAT_R11G11B10_FLOAT
:
60 case ISL_FORMAT_R16G16B16A16_UNORM
:
61 case ISL_FORMAT_R16G16B16A16_SNORM
:
62 case ISL_FORMAT_R8G8B8A8_UNORM
:
63 case ISL_FORMAT_R8G8B8A8_SNORM
:
64 case ISL_FORMAT_R16G16_UNORM
:
65 case ISL_FORMAT_R16G16_SNORM
:
66 case ISL_FORMAT_R8G8_UNORM
:
67 case ISL_FORMAT_R8G8_SNORM
:
68 case ISL_FORMAT_R16_UNORM
:
69 case ISL_FORMAT_R16_SNORM
:
70 case ISL_FORMAT_R8_UNORM
:
71 case ISL_FORMAT_R8_SNORM
:
79 isl_lower_storage_image_format(const struct gen_device_info
*devinfo
,
80 enum isl_format format
)
83 /* These are never lowered. Up to BDW we'll have to fall back to untyped
84 * surface access for 128bpp formats.
86 case ISL_FORMAT_R32G32B32A32_UINT
:
87 case ISL_FORMAT_R32G32B32A32_SINT
:
88 case ISL_FORMAT_R32G32B32A32_FLOAT
:
89 case ISL_FORMAT_R32_UINT
:
90 case ISL_FORMAT_R32_SINT
:
93 /* The Skylake PRM's "Surface Formats" section says:
95 * "The surface format for the typed atomic integer operations must
96 * be R32_UINT or R32_SINT."
98 case ISL_FORMAT_R32_FLOAT
:
99 return ISL_FORMAT_R32_UINT
;
101 /* From HSW to BDW the only 64bpp format supported for typed access is
102 * RGBA_UINT16. IVB falls back to untyped.
104 case ISL_FORMAT_R16G16B16A16_UINT
:
105 case ISL_FORMAT_R16G16B16A16_SINT
:
106 case ISL_FORMAT_R16G16B16A16_FLOAT
:
107 case ISL_FORMAT_R32G32_UINT
:
108 case ISL_FORMAT_R32G32_SINT
:
109 case ISL_FORMAT_R32G32_FLOAT
:
110 return (devinfo
->gen
>= 9 ? format
:
111 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
112 ISL_FORMAT_R16G16B16A16_UINT
:
113 ISL_FORMAT_R32G32_UINT
);
115 /* Up to BDW no SINT or FLOAT formats of less than 32 bits per component
116 * are supported. IVB doesn't support formats with more than one component
117 * for typed access. For 8 and 16 bpp formats IVB relies on the
118 * undocumented behavior that typed reads from R_UINT8 and R_UINT16
119 * surfaces actually do a 32-bit misaligned read. The alternative would be
120 * to use two surface state entries with different formats for each image,
121 * one for reading (using R_UINT32) and another one for writing (using
122 * R_UINT8 or R_UINT16), but that would complicate the shaders we generate
125 case ISL_FORMAT_R8G8B8A8_UINT
:
126 case ISL_FORMAT_R8G8B8A8_SINT
:
127 return (devinfo
->gen
>= 9 ? format
:
128 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
129 ISL_FORMAT_R8G8B8A8_UINT
: ISL_FORMAT_R32_UINT
);
131 case ISL_FORMAT_R16G16_UINT
:
132 case ISL_FORMAT_R16G16_SINT
:
133 case ISL_FORMAT_R16G16_FLOAT
:
134 return (devinfo
->gen
>= 9 ? format
:
135 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
136 ISL_FORMAT_R16G16_UINT
: ISL_FORMAT_R32_UINT
);
138 case ISL_FORMAT_R8G8_UINT
:
139 case ISL_FORMAT_R8G8_SINT
:
140 return (devinfo
->gen
>= 9 ? format
:
141 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
142 ISL_FORMAT_R8G8_UINT
: ISL_FORMAT_R16_UINT
);
144 case ISL_FORMAT_R16_UINT
:
145 case ISL_FORMAT_R16_FLOAT
:
146 case ISL_FORMAT_R16_SINT
:
147 return (devinfo
->gen
>= 9 ? format
: ISL_FORMAT_R16_UINT
);
149 case ISL_FORMAT_R8_UINT
:
150 case ISL_FORMAT_R8_SINT
:
151 return (devinfo
->gen
>= 9 ? format
: ISL_FORMAT_R8_UINT
);
153 /* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported
156 case ISL_FORMAT_R10G10B10A2_UINT
:
157 case ISL_FORMAT_R10G10B10A2_UNORM
:
158 case ISL_FORMAT_R11G11B10_FLOAT
:
159 return ISL_FORMAT_R32_UINT
;
161 /* No normalized fixed-point formats are supported by the hardware. */
162 case ISL_FORMAT_R16G16B16A16_UNORM
:
163 case ISL_FORMAT_R16G16B16A16_SNORM
:
164 return (devinfo
->gen
>= 11 ? format
:
165 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
166 ISL_FORMAT_R16G16B16A16_UINT
:
167 ISL_FORMAT_R32G32_UINT
);
169 case ISL_FORMAT_R8G8B8A8_UNORM
:
170 case ISL_FORMAT_R8G8B8A8_SNORM
:
171 return (devinfo
->gen
>= 11 ? format
:
172 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
173 ISL_FORMAT_R8G8B8A8_UINT
: ISL_FORMAT_R32_UINT
);
175 case ISL_FORMAT_R16G16_UNORM
:
176 case ISL_FORMAT_R16G16_SNORM
:
177 return (devinfo
->gen
>= 11 ? format
:
178 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
179 ISL_FORMAT_R16G16_UINT
: ISL_FORMAT_R32_UINT
);
181 case ISL_FORMAT_R8G8_UNORM
:
182 case ISL_FORMAT_R8G8_SNORM
:
183 return (devinfo
->gen
>= 11 ? format
:
184 devinfo
->gen
>= 8 || devinfo
->is_haswell
?
185 ISL_FORMAT_R8G8_UINT
: ISL_FORMAT_R16_UINT
);
187 case ISL_FORMAT_R16_UNORM
:
188 case ISL_FORMAT_R16_SNORM
:
189 return (devinfo
->gen
>= 11 ? format
: ISL_FORMAT_R16_UINT
);
191 case ISL_FORMAT_R8_UNORM
:
192 case ISL_FORMAT_R8_SNORM
:
193 return (devinfo
->gen
>= 11 ? format
: ISL_FORMAT_R8_UINT
);
196 assert(!"Unknown image format");
197 return ISL_FORMAT_UNSUPPORTED
;
202 isl_has_matching_typed_storage_image_format(const struct gen_device_info
*devinfo
,
205 if (devinfo
->gen
>= 9) {
207 } else if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
208 return isl_format_get_layout(fmt
)->bpb
<= 64;
210 return isl_format_get_layout(fmt
)->bpb
<= 32;
214 static const struct brw_image_param image_param_defaults
= {
215 /* Set the swizzling shifts to all-ones to effectively disable
216 * swizzling -- See emit_address_calculation() in
217 * brw_fs_surface_builder.cpp for a more detailed explanation of
220 .swizzling
= { 0xff, 0xff },
224 isl_surf_fill_image_param(const struct isl_device
*dev
,
225 struct brw_image_param
*param
,
226 const struct isl_surf
*surf
,
227 const struct isl_view
*view
)
229 *param
= image_param_defaults
;
231 if (surf
->dim
!= ISL_SURF_DIM_3D
) {
232 assert(view
->base_array_layer
+ view
->array_len
<=
233 surf
->logical_level0_px
.array_len
);
235 param
->size
[0] = isl_minify(surf
->logical_level0_px
.w
, view
->base_level
);
236 param
->size
[1] = surf
->dim
== ISL_SURF_DIM_1D
?
238 isl_minify(surf
->logical_level0_px
.h
, view
->base_level
);
239 param
->size
[2] = surf
->dim
== ISL_SURF_DIM_2D
?
241 isl_minify(surf
->logical_level0_px
.d
, view
->base_level
);
243 isl_surf_get_image_offset_el(surf
, view
->base_level
,
244 surf
->dim
== ISL_SURF_DIM_3D
?
245 0 : view
->base_array_layer
,
246 surf
->dim
== ISL_SURF_DIM_3D
?
247 view
->base_array_layer
: 0,
248 ¶m
->offset
[0], ¶m
->offset
[1]);
250 const int cpp
= isl_format_get_layout(surf
->format
)->bpb
/ 8;
251 param
->stride
[0] = cpp
;
252 param
->stride
[1] = surf
->row_pitch_B
/ cpp
;
254 const struct isl_extent3d image_align_sa
=
255 isl_surf_get_image_alignment_sa(surf
);
256 if (ISL_DEV_GEN(dev
) < 9 && surf
->dim
== ISL_SURF_DIM_3D
) {
257 param
->stride
[2] = isl_align_npot(param
->size
[0], image_align_sa
.w
);
258 param
->stride
[3] = isl_align_npot(param
->size
[1], image_align_sa
.h
);
260 param
->stride
[2] = 0;
261 param
->stride
[3] = isl_surf_get_array_pitch_el_rows(surf
);
264 switch (surf
->tiling
) {
265 case ISL_TILING_LINEAR
:
266 /* image_param_defaults is good enough */
270 /* An X tile is a rectangular block of 512x8 bytes. */
271 param
->tiling
[0] = isl_log2u(512 / cpp
);
272 param
->tiling
[1] = isl_log2u(8);
274 if (dev
->has_bit6_swizzling
) {
275 /* Right shifts required to swizzle bits 9 and 10 of the memory
276 * address with bit 6.
278 param
->swizzling
[0] = 3;
279 param
->swizzling
[1] = 4;
284 /* The layout of a Y-tiled surface in memory isn't really fundamentally
285 * different to the layout of an X-tiled surface, we simply pretend that
286 * the surface is broken up in a number of smaller 16Bx32 tiles, each
287 * one arranged in X-major order just like is the case for X-tiling.
289 param
->tiling
[0] = isl_log2u(16 / cpp
);
290 param
->tiling
[1] = isl_log2u(32);
292 if (dev
->has_bit6_swizzling
) {
293 /* Right shift required to swizzle bit 9 of the memory address with
296 param
->swizzling
[0] = 3;
297 param
->swizzling
[1] = 0xff;
302 assert(!"Unhandled storage image tiling");
305 /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
306 * address calculation algorithm (emit_address_calculation() in
307 * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
308 * modulus equal to the LOD.
310 param
->tiling
[2] = (ISL_DEV_GEN(dev
) < 9 && surf
->dim
== ISL_SURF_DIM_3D
?
311 view
->base_level
: 0);
315 isl_buffer_fill_image_param(const struct isl_device
*dev
,
316 struct brw_image_param
*param
,
317 enum isl_format format
,
320 *param
= image_param_defaults
;
322 param
->stride
[0] = isl_format_get_layout(format
)->bpb
/ 8;
323 param
->size
[0] = size
/ param
->stride
[0];