src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static uint64_t
  30 __gen_combine_address(__attribute__((unused)) void *data,
  31                       __attribute__((unused)) void *loc, uint64_t addr,
  32                       uint32_t delta)
  33 {
  34    return addr + delta;
  35 }
  36
  37 #include "genxml/gen_macros.h"
  38 #include "genxml/genX_pack.h"
  39
  40 #include "isl_priv.h"
  41
  42 #if GEN_GEN >= 8
  43 static const uint8_t isl_to_gen_halign[] = {
  44     [4] = HALIGN4,
  45     [8] = HALIGN8,
  46     [16] = HALIGN16,
  47 };
  48 #elif GEN_GEN >= 7
  49 static const uint8_t isl_to_gen_halign[] = {
  50     [4] = HALIGN_4,
  51     [8] = HALIGN_8,
  52 };
  53 #endif
  54
  55 #if GEN_GEN >= 8
  56 static const uint8_t isl_to_gen_valign[] = {
  57     [4] = VALIGN4,
  58     [8] = VALIGN8,
  59     [16] = VALIGN16,
  60 };
  61 #elif GEN_GEN >= 6
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75 #if GEN_GEN <= 11
  76    [ISL_TILING_W]       = WMAJOR,
  77 #endif
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 12
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94    [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
  95    [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
  96 };
  97 #elif GEN_GEN >= 9
  98 static const uint32_t isl_to_gen_aux_mode[] = {
  99    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 100    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 101    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
 102    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
 103    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
 104 };
 105 #elif GEN_GEN >= 8
 106 static const uint32_t isl_to_gen_aux_mode[] = {
 107    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 108    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 109    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 110    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 111 };
 112 #endif
 113
 114 static uint8_t
 115 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 116 {
 117    switch (dim) {
 118    default:
 119       unreachable("bad isl_surf_dim");
 120    case ISL_SURF_DIM_1D:
 121       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 122       return SURFTYPE_1D;
 123    case ISL_SURF_DIM_2D:
 124       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 125           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 126          /* We need SURFTYPE_CUBE to make cube sampling work */
 127          return SURFTYPE_CUBE;
 128       } else {
 129          /* Everything else (render and storage) treat cubes as plain
 130           * 2D array textures
 131           */
 132          return SURFTYPE_2D;
 133       }
 134    case ISL_SURF_DIM_3D:
 135       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 136       return SURFTYPE_3D;
 137    }
 138 }
 139
 140 /**
 141  * Get the horizontal and vertical alignment in the units expected by the
 142  * hardware.  Note that this does NOT give you the actual hardware enum values
 143  * but an index into the isl_to_gen_[hv]align arrays above.
 144  */
 145 UNUSED static struct isl_extent3d
 146 get_image_alignment(const struct isl_surf *surf)
 147 {
 148    if (GEN_GEN >= 9) {
 149       if (isl_tiling_is_std_y(surf->tiling) ||
 150           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 151          /* The hardware ignores the alignment values. Anyway, the surface's
 152           * true alignment is likely outside the enum range of HALIGN* and
 153           * VALIGN*.
 154           */
 155          return isl_extent3d(4, 4, 1);
 156       } else {
 157          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 158           * of surface elements (not pixels nor samples). For compressed formats,
 159           * a "surface element" is defined as a compression block.  For example,
 160           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 161           * format (ETC2 has a block height of 4), then the vertical alignment is
 162           * 4 compression blocks or, equivalently, 16 pixels.
 163           */
 164          return isl_surf_get_image_alignment_el(surf);
 165       }
 166    } else {
 167       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 168        * units of surface samples.  For example, if SurfaceVerticalAlignment
 169        * is VALIGN_4 and the surface is singlesampled, then for any surface
 170        * format (compressed or not) the vertical alignment is
 171        * 4 pixels.
 172        */
 173       return isl_surf_get_image_alignment_sa(surf);
 174    }
 175 }
 176
 177 #if GEN_GEN >= 8
 178 static uint32_t
 179 get_qpitch(const struct isl_surf *surf)
 180 {
 181    switch (surf->dim_layout) {
 182    default:
 183       unreachable("Bad isl_surf_dim");
 184    case ISL_DIM_LAYOUT_GEN4_2D:
 185       if (GEN_GEN >= 9) {
 186          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 187             /* This is rather annoying and completely undocumented.  It
 188              * appears that the hardware has a bug (or undocumented feature)
 189              * regarding stencil buffers most likely related to the way
 190              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 191              * stencil buffer normally, and use texelFetch on it, the z or
 192              * array index will get implicitly multiplied by 2 for no obvious
 193              * reason.  The fix appears to be to divide qpitch by 2 for
 194              * W-tiled surfaces.
 195              */
 196             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 197          } else {
 198             return isl_surf_get_array_pitch_el_rows(surf);
 199          }
 200       } else {
 201          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 202           *
 203           *    "This field must be set to an integer multiple of the Surface
 204           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 205           *    ETC*, and EAC* Surface Formats), this field is in units of
 206           *    rows in the uncompressed surface, and must be set to an
 207           *    integer multiple of the vertical alignment parameter "j"
 208           *    defined in the Common Surface Formats section."
 209           */
 210          return isl_surf_get_array_pitch_sa_rows(surf);
 211       }
 212    case ISL_DIM_LAYOUT_GEN9_1D:
 213       /* QPitch is usually expressed as rows of surface elements (where
 214        * a surface element is an compression block or a single surface
 215        * sample). Skylake 1D is an outlier.
 216        *
 217        * From the Skylake BSpec >> Memory Views >> Common Surface
 218        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 219        *
 220        *    Surface QPitch specifies the distance in pixels between array
 221        *    slices.
 222        */
 223       return isl_surf_get_array_pitch_el(surf);
 224    case ISL_DIM_LAYOUT_GEN4_3D:
 225       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 226        * different pitch at each LOD.  Also, the QPitch field is ignored for
 227        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 228        *
 229        *    This field specifies the distance in rows between array slices. It
 230        *    is used only in the following cases:
 231        *     - Surface Array is enabled OR
 232        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 233        *       Surface Storage Format set to MSFMT_MSS OR
 234        *     - Surface Type is SURFTYPE_CUBE
 235        *
 236        * None of the three conditions above can possibly apply to a 3D surface
 237        * so it is safe to just set QPitch to 0.
 238        */
 239       return 0;
 240    }
 241 }
 242 #endif /* GEN_GEN >= 8 */
 243
 244 void
 245 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 246                             const struct isl_surf_fill_state_info *restrict info)
 247 {
 248    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 249
 250    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 251
 252    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 253       assert(isl_format_supports_rendering(dev->info, info->view->format));
 254    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 255       assert(isl_format_supports_sampling(dev->info, info->view->format));
 256
 257    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 258     *
 259     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 260     *    format if the Surface Type is SURFTYPE_1D
 261     */
 262    if (info->surf->dim == ISL_SURF_DIM_1D)
 263       assert(!isl_format_is_compressed(info->view->format));
 264
 265    if (isl_format_is_compressed(info->surf->format)) {
 266       /* You're not allowed to make a view of a compressed format with any
 267        * format other than the surface format.  None of the userspace APIs
 268        * allow for this directly and doing so would mess up a number of
 269        * surface parameters such as Width, Height, and alignments.  Ideally,
 270        * we'd like to assert that the two formats match.  However, we have an
 271        * S3TC workaround that requires us to do reinterpretation.  So assert
 272        * that they're at least the same bpb and block size.
 273        */
 274       ASSERTED const struct isl_format_layout *surf_fmtl =
 275          isl_format_get_layout(info->surf->format);
 276       ASSERTED const struct isl_format_layout *view_fmtl =
 277          isl_format_get_layout(info->surf->format);
 278       assert(surf_fmtl->bpb == view_fmtl->bpb);
 279       assert(surf_fmtl->bw == view_fmtl->bw);
 280       assert(surf_fmtl->bh == view_fmtl->bh);
 281    }
 282
 283    s.SurfaceFormat = info->view->format;
 284
 285 #if GEN_GEN >= 12
 286    s.DepthStencilResource =
 287       isl_surf_usage_is_depth_or_stencil(info->surf->usage);
 288 #endif
 289
 290 #if GEN_GEN <= 5
 291    s.ColorBufferComponentWriteDisables = info->write_disables;
 292 #else
 293    assert(info->write_disables == 0);
 294 #endif
 295
 296 #if GEN_IS_HASWELL
 297    s.IntegerSurfaceFormat =
 298       isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 299 #endif
 300
 301    assert(info->surf->logical_level0_px.width > 0 &&
 302           info->surf->logical_level0_px.height > 0);
 303
 304    s.Width = info->surf->logical_level0_px.width - 1;
 305    s.Height = info->surf->logical_level0_px.height - 1;
 306
 307    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 308     * (Surface Arrays For all surfaces other than separate stencil buffer):
 309     *
 310     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 311     *  calculated in the equation above , for every other odd Surface Height
 312     *  starting from 1 i.e. 1,5,9,13"
 313     *
 314     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 315     * input for the rendering surface to achieve the same qpitch. For the
 316     * affected heights, we increment the height by 1 for the rendering
 317     * surface.
 318     */
 319    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 320        info->surf->samples > 1 &&
 321        (info->surf->logical_level0_px.height % 4) == 1)
 322       s.Height++;
 323
 324    switch (s.SurfaceType) {
 325    case SURFTYPE_1D:
 326    case SURFTYPE_2D:
 327       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 328        *
 329        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 330        *    must be set to zero if this surface is used with sampling engine
 331        *    messages."
 332        *
 333        * This restriction appears to exist only on Ivy Bridge.
 334        */
 335       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 336           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 337           info->surf->samples > 1)
 338          assert(info->view->base_array_layer == 0);
 339
 340       s.MinimumArrayElement = info->view->base_array_layer;
 341
 342       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 343        *
 344        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 345        *    by one for each increase from zero of Minimum Array Element. For
 346        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 347        *    the range of this field is reduced to [0,1023].
 348        *
 349        * In other words, 'Depth' is the number of array layers.
 350        */
 351       s.Depth = info->view->array_len - 1;
 352
 353       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 354        *
 355        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 356        *    This field must be set to the same value as the Depth field.
 357        */
 358       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 359                                ISL_SURF_USAGE_STORAGE_BIT))
 360          s.RenderTargetViewExtent = s.Depth;
 361       break;
 362    case SURFTYPE_CUBE:
 363       s.MinimumArrayElement = info->view->base_array_layer;
 364       /* Same as SURFTYPE_2D, but divided by 6 */
 365       s.Depth = info->view->array_len / 6 - 1;
 366       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 367                                ISL_SURF_USAGE_STORAGE_BIT))
 368          s.RenderTargetViewExtent = s.Depth;
 369       break;
 370    case SURFTYPE_3D:
 371       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 372        *
 373        *    If the volume texture is MIP-mapped, this field specifies the
 374        *    depth of the base MIP level.
 375        */
 376       s.Depth = info->surf->logical_level0_px.depth - 1;
 377
 378       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 379        *
 380        *    For Render Target and Typed Dataport 3D Surfaces: This field
 381        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 382        *    the LOD currently being rendered to.
 383        *
 384        * The docs specify that this only matters for render targets and
 385        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 386        * Depth field has more bits than RenderTargetViewExtent so we can have
 387        * textures with more levels than we can render to.  In order to prevent
 388        * assert-failures in the packing function below, we only set the field
 389        * when it's actually going to be used by the hardware.
 390        *
 391        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 392        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 393        * Since it's already initialized to 0, we can just leave it alone for
 394        * texture surfaces.
 395        */
 396       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 397                                ISL_SURF_USAGE_STORAGE_BIT)) {
 398          s.MinimumArrayElement = info->view->base_array_layer;
 399          s.RenderTargetViewExtent = info->view->array_len - 1;
 400       }
 401       break;
 402    default:
 403       unreachable("bad SurfaceType");
 404    }
 405
 406 #if GEN_GEN >= 12
 407    /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
 408    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
 409       info->view->array_len > 1;
 410 #elif GEN_GEN >= 7
 411    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 412 #endif
 413
 414    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 415       /* For render target surfaces, the hardware interprets field
 416        * MIPCount/LOD as LOD. The Broadwell PRM says:
 417        *
 418        *    MIPCountLOD defines the LOD that will be rendered into.
 419        *    SurfaceMinLOD is ignored.
 420        */
 421       s.MIPCountLOD = info->view->base_level;
 422       s.SurfaceMinLOD = 0;
 423    } else {
 424       /* For non render target surfaces, the hardware interprets field
 425        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 426        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 427        */
 428       s.SurfaceMinLOD = info->view->base_level;
 429       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 430    }
 431
 432 #if GEN_GEN >= 9
 433    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 434     * Start LOD" to 15 to prevent the hardware from trying to use them.
 435     */
 436    s.TiledResourceMode = NONE;
 437    s.MipTailStartLOD = 15;
 438 #endif
 439
 440 #if GEN_GEN >= 6
 441    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 442    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 443 #if GEN_GEN >= 7
 444    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 445 #endif
 446 #endif
 447
 448    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 449       /* For gen9 1-D textures, surface pitch is ignored */
 450       s.SurfacePitch = 0;
 451    } else {
 452       s.SurfacePitch = info->surf->row_pitch_B - 1;
 453    }
 454
 455 #if GEN_GEN >= 8
 456    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 457 #elif GEN_GEN == 7
 458    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 459                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 460 #endif
 461
 462 #if GEN_GEN >= 8
 463    assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
 464    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 465 #else
 466    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 467    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 468                                                       TILEWALK_XMAJOR,
 469 #endif
 470
 471 #if GEN_GEN >= 8
 472    s.RenderCacheReadWriteMode = WriteOnlyCache;
 473 #else
 474    s.RenderCacheReadWriteMode = 0;
 475 #endif
 476
 477 #if GEN_GEN >= 11
 478    /* We've seen dEQP failures when enabling this bit with UINT formats,
 479     * which particularly affects blorp_copy() operations.  It shouldn't
 480     * have any effect on UINT textures anyway, so disable it for them.
 481     */
 482    s.EnableUnormPathInColorPipe =
 483       !isl_format_has_int_channel(info->view->format);
 484 #endif
 485
 486    s.CubeFaceEnablePositiveZ = 1;
 487    s.CubeFaceEnableNegativeZ = 1;
 488    s.CubeFaceEnablePositiveY = 1;
 489    s.CubeFaceEnableNegativeY = 1;
 490    s.CubeFaceEnablePositiveX = 1;
 491    s.CubeFaceEnableNegativeX = 1;
 492
 493 #if GEN_GEN >= 6
 494    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 495 #if GEN_GEN >= 7
 496    s.MultisampledSurfaceStorageFormat =
 497       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 498 #endif
 499 #endif
 500
 501 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 502    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 503       assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
 504
 505    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
 506    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
 507    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
 508    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
 509 #else
 510    assert(isl_swizzle_is_identity(info->view->swizzle));
 511 #endif
 512
 513    s.SurfaceBaseAddress = info->address;
 514
 515 #if GEN_GEN >= 6
 516    s.MOCS = info->mocs;
 517 #endif
 518
 519 #if GEN_GEN > 4 || GEN_IS_G4X
 520    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 521       /* There are fairly strict rules about when the offsets can be used.
 522        * These are mostly taken from the Sky Lake PRM documentation for
 523        * RENDER_SURFACE_STATE.
 524        */
 525       assert(info->surf->tiling != ISL_TILING_LINEAR);
 526       assert(info->surf->dim == ISL_SURF_DIM_2D);
 527       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 528       assert(info->surf->levels == 1);
 529       assert(info->surf->logical_level0_px.array_len == 1);
 530       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 531
 532       if (GEN_GEN >= 8) {
 533          /* Broadwell added more rules. */
 534          assert(info->surf->samples == 1);
 535          if (isl_format_get_layout(info->view->format)->bpb == 8)
 536             assert(info->x_offset_sa % 16 == 0);
 537          if (isl_format_get_layout(info->view->format)->bpb == 16)
 538             assert(info->x_offset_sa % 8 == 0);
 539       }
 540
 541 #if GEN_GEN >= 7
 542       s.SurfaceArray = false;
 543 #endif
 544    }
 545
 546    const unsigned x_div = 4;
 547    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 548    assert(info->x_offset_sa % x_div == 0);
 549    assert(info->y_offset_sa % y_div == 0);
 550    s.XOffset = info->x_offset_sa / x_div;
 551    s.YOffset = info->y_offset_sa / y_div;
 552 #else
 553    assert(info->x_offset_sa == 0);
 554    assert(info->y_offset_sa == 0);
 555 #endif
 556
 557 #if GEN_GEN >= 7
 558    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 559       /* Check valid aux usages per-gen */
 560       if (GEN_GEN >= 12) {
 561          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 562                 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
 563                 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
 564                 info->aux_usage == ISL_AUX_USAGE_MCS_CCS);
 565       } else if (GEN_GEN >= 9) {
 566          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 567                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 568                 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
 569                 info->aux_usage == ISL_AUX_USAGE_CCS_E);
 570       } else if (GEN_GEN >= 8) {
 571          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 572                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 573                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 574       } else if (GEN_GEN >= 7) {
 575          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 576                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 577       }
 578
 579       /* The docs don't appear to say anything whatsoever about compression
 580        * and the data port.  Testing seems to indicate that the data port
 581        * completely ignores the AuxiliarySurfaceMode field.
 582        */
 583       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 584
 585       if (isl_aux_usage_has_hiz(info->aux_usage)) {
 586          /* For Gen8-10, there are some restrictions around sampling from HiZ.
 587           * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
 588           * say:
 589           *
 590           *    "If this field is set to AUX_HIZ, Number of Multisamples must
 591           *    be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
 592           *
 593           * On Gen12, the docs are a bit less obvious but the restriction is
 594           * the same.  The limitation isn't called out explicitly but the docs
 595           * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
 596           * say:
 597           *
 598           *    "If Number of multisamples > 1, programming this value means
 599           *    MSAA compression is enabled for that surface. Auxillary surface
 600           *    is MSC with tile y."
 601           *
 602           * Since this interpretation ignores whether the surface is
 603           * depth/stencil or not and since multisampled depth buffers use
 604           * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
 605           * compression, this means that we can't even specify MSAA depth CCS
 606           * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
 607           */
 608          assert(info->surf->samples == 1);
 609
 610          /* The dimension must not be 3D */
 611          assert(info->surf->dim != ISL_SURF_DIM_3D);
 612
 613          /* The format must be one of the following: */
 614          switch (info->view->format) {
 615          case ISL_FORMAT_R32_FLOAT:
 616          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 617          case ISL_FORMAT_R16_UNORM:
 618             break;
 619          default:
 620             assert(!"Incompatible HiZ Sampling format");
 621             break;
 622          }
 623       }
 624
 625 #if GEN_GEN >= 8
 626       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 627 #else
 628       s.MCSEnable = true;
 629 #endif
 630    }
 631
 632    /* The auxiliary buffer info is filled when it's useable by the HW.
 633     *
 634     * Starting with Gen12, the only form of compression that can be used
 635     * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
 636     * HiZ still requires a surface but the HiZ surface can only be
 637     * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
 638     *
 639     * On all earlier hardware, an aux surface is required for all forms
 640     * of compression.
 641     */
 642    if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
 643        (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
 644
 645       assert(info->aux_surf != NULL);
 646
 647       struct isl_tile_info tile_info;
 648       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 649       uint32_t pitch_in_tiles =
 650          info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
 651
 652       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 653       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 654
 655 #if GEN_GEN >= 8
 656       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 657        * doesn't expect our definition of the compression, it expects qpitch
 658        * in units of samples on the main surface.
 659        */
 660       s.AuxiliarySurfaceQPitch =
 661          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 662 #endif
 663    }
 664 #endif
 665
 666 #if GEN_GEN >= 8 && GEN_GEN < 11
 667    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 668     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 669     *
 670     *    This bit must be set for the following surface types: BC2_UNORM
 671     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 672     */
 673    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 674       switch (info->view->format) {
 675       case ISL_FORMAT_BC2_UNORM:
 676       case ISL_FORMAT_BC3_UNORM:
 677       case ISL_FORMAT_BC5_UNORM:
 678       case ISL_FORMAT_BC5_SNORM:
 679       case ISL_FORMAT_BC7_UNORM:
 680          s.SamplerL2BypassModeDisable = true;
 681          break;
 682       default:
 683          /* From the SKL PRM, Programming Note under Sampler Output Channel
 684           * Mapping:
 685           *
 686           *    If a surface has an associated HiZ Auxilliary surface, the
 687           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 688           *    must be set.
 689           */
 690          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 691             s.SamplerL2BypassModeDisable = true;
 692          break;
 693       }
 694    }
 695 #endif
 696
 697    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 698       if (info->use_clear_address) {
 699 #if GEN_GEN >= 10
 700          s.ClearValueAddressEnable = true;
 701          s.ClearValueAddress = info->clear_address;
 702 #else
 703          unreachable("Gen9 and earlier do not support indirect clear colors");
 704 #endif
 705       }
 706
 707 #if GEN_GEN == 11
 708       /*
 709        * From BXML > GT > Shared Functions > vol5c Shared Functions >
 710        * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
 711        *
 712        *   Project: Gen11
 713        *
 714        *   "Enables Pixel backend hw to convert clear values into native format
 715        *    and write back to clear address, so that display and sampler can use
 716        *    the converted value for resolving fast cleared RTs."
 717        *
 718        * Summary:
 719        *   Clear color conversion must be enabled if the clear color is stored
 720        *   indirectly and fast color clears are enabled.
 721        */
 722       if (info->use_clear_address) {
 723          s.ClearColorConversionEnable = true;
 724       }
 725 #endif
 726
 727 #if GEN_GEN >= 12
 728       assert(info->use_clear_address);
 729 #elif GEN_GEN >= 9
 730       if (!info->use_clear_address) {
 731          s.RedClearColor = info->clear_color.u32[0];
 732          s.GreenClearColor = info->clear_color.u32[1];
 733          s.BlueClearColor = info->clear_color.u32[2];
 734          s.AlphaClearColor = info->clear_color.u32[3];
 735       }
 736 #elif GEN_GEN >= 7
 737       /* Prior to Sky Lake, we only have one bit for the clear color which
 738        * gives us 0 or 1 in whatever the surface's format happens to be.
 739        */
 740       if (isl_format_has_int_channel(info->view->format)) {
 741          for (unsigned i = 0; i < 4; i++) {
 742             assert(info->clear_color.u32[i] == 0 ||
 743                    info->clear_color.u32[i] == 1);
 744          }
 745          s.RedClearColor = info->clear_color.u32[0] != 0;
 746          s.GreenClearColor = info->clear_color.u32[1] != 0;
 747          s.BlueClearColor = info->clear_color.u32[2] != 0;
 748          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 749       } else {
 750          for (unsigned i = 0; i < 4; i++) {
 751             assert(info->clear_color.f32[i] == 0.0f ||
 752                    info->clear_color.f32[i] == 1.0f);
 753          }
 754          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 755          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 756          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 757          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 758       }
 759 #endif
 760    }
 761
 762    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 763 }
 764
 765 void
 766 isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
 767                               const struct isl_buffer_fill_state_info *restrict info)
 768 {
 769    uint64_t buffer_size = info->size_B;
 770
 771    /* Uniform and Storage buffers need to have surface size not less that the
 772     * aligned 32-bit size of the buffer. To calculate the array lenght on
 773     * unsized arrays in StorageBuffer the last 2 bits store the padding size
 774     * added to the surface, so we can calculate latter the original buffer
 775     * size to know the number of elements.
 776     *
 777     *  surface_size = isl_align(buffer_size, 4) +
 778     *                 (isl_align(buffer_size) - buffer_size)
 779     *
 780     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
 781     */
 782    if (info->format == ISL_FORMAT_RAW  ||
 783        info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
 784       assert(info->stride_B == 1);
 785       uint64_t aligned_size = isl_align(buffer_size, 4);
 786       buffer_size = aligned_size + (aligned_size - buffer_size);
 787    }
 788
 789    uint32_t num_elements = buffer_size / info->stride_B;
 790
 791    if (GEN_GEN >= 7) {
 792       /* From the IVB PRM, SURFACE_STATE::Height,
 793        *
 794        *    For typed buffer and structured buffer surfaces, the number
 795        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 796        *    surfaces, the number of entries in the buffer is the number of bytes
 797        *    which can range from 1 to 2^30.
 798        */
 799       if (info->format == ISL_FORMAT_RAW) {
 800          assert(num_elements <= (1ull << 30));
 801          assert(num_elements > 0);
 802       } else {
 803          assert(num_elements <= (1ull << 27));
 804       }
 805    } else {
 806       assert(num_elements <= (1ull << 27));
 807    }
 808
 809    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 810
 811    s.SurfaceType = SURFTYPE_BUFFER;
 812    s.SurfaceFormat = info->format;
 813
 814 #if GEN_GEN >= 6
 815    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 816 #if GEN_GEN >= 7
 817    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 818    s.SurfaceArray = false;
 819 #endif
 820 #endif
 821
 822 #if GEN_GEN >= 7
 823    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 824    s.Width = (num_elements - 1) & 0x7f;
 825    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 826 #else
 827    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 828    s.Width = (num_elements - 1) & 0x7f;
 829    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 830 #endif
 831
 832    if (GEN_GEN == 12 && dev->info->revision == 0) {
 833       /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
 834        * textures with very close base addresses (delta < 64B) to corrupt each
 835        * other.  We can sort-of work around this by making small buffer
 836        * textures 1D textures instead.  This doesn't fix the problem for large
 837        * buffer textures but the liklihood of large, overlapping, and very
 838        * close buffer textures is fairly low and the point is to hack around
 839        * the bug so we can run apps and tests.
 840        */
 841        if (info->format != ISL_FORMAT_RAW &&
 842            info->stride_B == isl_format_get_layout(info->format)->bpb / 8 &&
 843            num_elements <= (1 << 14)) {
 844          s.SurfaceType = SURFTYPE_1D;
 845          s.Width = num_elements - 1;
 846          s.Height = 0;
 847          s.Depth = 0;
 848       }
 849    }
 850
 851    s.SurfacePitch = info->stride_B - 1;
 852
 853 #if GEN_GEN >= 6
 854    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 855 #endif
 856
 857 #if (GEN_GEN >= 8)
 858    s.TileMode = LINEAR;
 859 #else
 860    s.TiledSurface = false;
 861 #endif
 862
 863 #if (GEN_GEN >= 8)
 864    s.RenderCacheReadWriteMode = WriteOnlyCache;
 865 #else
 866    s.RenderCacheReadWriteMode = 0;
 867 #endif
 868
 869    s.SurfaceBaseAddress = info->address;
 870 #if GEN_GEN >= 6
 871    s.MOCS = info->mocs;
 872 #endif
 873
 874 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 875    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
 876    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
 877    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
 878    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
 879 #endif
 880
 881    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 882 }
 883
 884 void
 885 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
 886 {
 887    struct GENX(RENDER_SURFACE_STATE) s = {
 888       .SurfaceType = SURFTYPE_NULL,
 889       /* We previously had this format set to B8G8R8A8_UNORM but ran into
 890        * hangs on IVB. R32_UINT seems to work for everybody.
 891        *
 892        * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
 893        */
 894       .SurfaceFormat = ISL_FORMAT_R32_UINT,
 895 #if GEN_GEN >= 7
 896       .SurfaceArray = size.depth > 1,
 897 #endif
 898 #if GEN_GEN >= 8
 899       .TileMode = YMAJOR,
 900 #else
 901       .TiledSurface = true,
 902       .TileWalk = TILEWALK_YMAJOR,
 903 #endif
 904 #if GEN_GEN == 7
 905       /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
 906        * Functions"
 907        *
 908        * RENDER_SURFACE_STATE::Surface Vertical Alignment
 909        *
 910        *    "This field must be set to VALIGN_4 for all tiled Y Render Target
 911        *     surfaces."
 912        *
 913        * Affect IVB, HSW.
 914        */
 915       .SurfaceVerticalAlignment = VALIGN_4,
 916 #endif
 917       .Width = size.width - 1,
 918       .Height = size.height - 1,
 919       .Depth = size.depth - 1,
 920       .RenderTargetViewExtent = size.depth - 1,
 921 #if GEN_GEN <= 5
 922       .ColorBufferComponentWriteDisables = 0xf,
 923 #endif
 924    };
 925    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 926 }