2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
30 __gen_combine_address(__attribute__((unused
)) void *data
,
31 __attribute__((unused
)) void *loc
, uint64_t addr
,
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
43 static const uint8_t isl_to_gen_halign
[] = {
49 static const uint8_t isl_to_gen_halign
[] = {
56 static const uint8_t isl_to_gen_valign
[] = {
62 static const uint8_t isl_to_gen_valign
[] = {
69 static const uint8_t isl_to_gen_tiling
[] = {
70 [ISL_TILING_LINEAR
] = LINEAR
,
71 [ISL_TILING_X
] = XMAJOR
,
72 [ISL_TILING_Y0
] = YMAJOR
,
73 [ISL_TILING_Yf
] = YMAJOR
,
74 [ISL_TILING_Ys
] = YMAJOR
,
76 [ISL_TILING_W
] = WMAJOR
,
82 static const uint32_t isl_to_gen_multisample_layout
[] = {
83 [ISL_MSAA_LAYOUT_NONE
] = MSFMT_MSS
,
84 [ISL_MSAA_LAYOUT_INTERLEAVED
] = MSFMT_DEPTH_STENCIL
,
85 [ISL_MSAA_LAYOUT_ARRAY
] = MSFMT_MSS
,
90 static const uint32_t isl_to_gen_aux_mode
[] = {
91 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
92 [ISL_AUX_USAGE_MCS
] = AUX_CCS_E
,
93 [ISL_AUX_USAGE_CCS_E
] = AUX_CCS_E
,
94 [ISL_AUX_USAGE_HIZ_CCS_WT
] = AUX_CCS_E
,
95 [ISL_AUX_USAGE_MCS_CCS
] = AUX_MCS_LCE
,
96 [ISL_AUX_USAGE_STC_CCS
] = AUX_CCS_E
,
99 static const uint32_t isl_to_gen_aux_mode
[] = {
100 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
101 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
102 [ISL_AUX_USAGE_MCS
] = AUX_CCS_D
,
103 [ISL_AUX_USAGE_CCS_D
] = AUX_CCS_D
,
104 [ISL_AUX_USAGE_CCS_E
] = AUX_CCS_E
,
107 static const uint32_t isl_to_gen_aux_mode
[] = {
108 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
109 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
110 [ISL_AUX_USAGE_MCS
] = AUX_MCS
,
111 [ISL_AUX_USAGE_CCS_D
] = AUX_MCS
,
116 get_surftype(enum isl_surf_dim dim
, isl_surf_usage_flags_t usage
)
120 unreachable("bad isl_surf_dim");
121 case ISL_SURF_DIM_1D
:
122 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
124 case ISL_SURF_DIM_2D
:
125 if ((usage
& ISL_SURF_USAGE_CUBE_BIT
) &&
126 (usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
127 /* We need SURFTYPE_CUBE to make cube sampling work */
128 return SURFTYPE_CUBE
;
130 /* Everything else (render and storage) treat cubes as plain
135 case ISL_SURF_DIM_3D
:
136 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
142 * Get the horizontal and vertical alignment in the units expected by the
143 * hardware. Note that this does NOT give you the actual hardware enum values
144 * but an index into the isl_to_gen_[hv]align arrays above.
146 UNUSED
static struct isl_extent3d
147 get_image_alignment(const struct isl_surf
*surf
)
150 if (isl_tiling_is_std_y(surf
->tiling
) ||
151 surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
152 /* The hardware ignores the alignment values. Anyway, the surface's
153 * true alignment is likely outside the enum range of HALIGN* and
156 return isl_extent3d(4, 4, 1);
158 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
159 * of surface elements (not pixels nor samples). For compressed formats,
160 * a "surface element" is defined as a compression block. For example,
161 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
162 * format (ETC2 has a block height of 4), then the vertical alignment is
163 * 4 compression blocks or, equivalently, 16 pixels.
165 return isl_surf_get_image_alignment_el(surf
);
168 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
169 * units of surface samples. For example, if SurfaceVerticalAlignment
170 * is VALIGN_4 and the surface is singlesampled, then for any surface
171 * format (compressed or not) the vertical alignment is
174 return isl_surf_get_image_alignment_sa(surf
);
180 get_qpitch(const struct isl_surf
*surf
)
182 switch (surf
->dim_layout
) {
184 unreachable("Bad isl_surf_dim");
185 case ISL_DIM_LAYOUT_GEN4_2D
:
187 if (surf
->dim
== ISL_SURF_DIM_3D
&& surf
->tiling
== ISL_TILING_W
) {
188 /* This is rather annoying and completely undocumented. It
189 * appears that the hardware has a bug (or undocumented feature)
190 * regarding stencil buffers most likely related to the way
191 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
192 * stencil buffer normally, and use texelFetch on it, the z or
193 * array index will get implicitly multiplied by 2 for no obvious
194 * reason. The fix appears to be to divide qpitch by 2 for
197 return isl_surf_get_array_pitch_el_rows(surf
) / 2;
199 return isl_surf_get_array_pitch_el_rows(surf
);
202 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
204 * "This field must be set to an integer multiple of the Surface
205 * Vertical Alignment. For compressed textures (BC*, FXT1,
206 * ETC*, and EAC* Surface Formats), this field is in units of
207 * rows in the uncompressed surface, and must be set to an
208 * integer multiple of the vertical alignment parameter "j"
209 * defined in the Common Surface Formats section."
211 return isl_surf_get_array_pitch_sa_rows(surf
);
213 case ISL_DIM_LAYOUT_GEN9_1D
:
214 /* QPitch is usually expressed as rows of surface elements (where
215 * a surface element is an compression block or a single surface
216 * sample). Skylake 1D is an outlier.
218 * From the Skylake BSpec >> Memory Views >> Common Surface
219 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
221 * Surface QPitch specifies the distance in pixels between array
224 return isl_surf_get_array_pitch_el(surf
);
225 case ISL_DIM_LAYOUT_GEN4_3D
:
226 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
227 * different pitch at each LOD. Also, the QPitch field is ignored for
228 * these surfaces. From the Broadwell PRM documentation for QPitch:
230 * This field specifies the distance in rows between array slices. It
231 * is used only in the following cases:
232 * - Surface Array is enabled OR
233 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
234 * Surface Storage Format set to MSFMT_MSS OR
235 * - Surface Type is SURFTYPE_CUBE
237 * None of the three conditions above can possibly apply to a 3D surface
238 * so it is safe to just set QPitch to 0.
243 #endif /* GEN_GEN >= 8 */
246 isl_genX(surf_fill_state_s
)(const struct isl_device
*dev
, void *state
,
247 const struct isl_surf_fill_state_info
*restrict info
)
249 struct GENX(RENDER_SURFACE_STATE
) s
= { 0 };
251 s
.SurfaceType
= get_surftype(info
->surf
->dim
, info
->view
->usage
);
253 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
)
254 assert(isl_format_supports_rendering(dev
->info
, info
->view
->format
));
255 else if (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
)
256 assert(isl_format_supports_sampling(dev
->info
, info
->view
->format
));
258 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
260 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
261 * format if the Surface Type is SURFTYPE_1D
263 if (info
->surf
->dim
== ISL_SURF_DIM_1D
)
264 assert(!isl_format_is_compressed(info
->view
->format
));
266 if (isl_format_is_compressed(info
->surf
->format
)) {
267 /* You're not allowed to make a view of a compressed format with any
268 * format other than the surface format. None of the userspace APIs
269 * allow for this directly and doing so would mess up a number of
270 * surface parameters such as Width, Height, and alignments. Ideally,
271 * we'd like to assert that the two formats match. However, we have an
272 * S3TC workaround that requires us to do reinterpretation. So assert
273 * that they're at least the same bpb and block size.
275 ASSERTED
const struct isl_format_layout
*surf_fmtl
=
276 isl_format_get_layout(info
->surf
->format
);
277 ASSERTED
const struct isl_format_layout
*view_fmtl
=
278 isl_format_get_layout(info
->surf
->format
);
279 assert(surf_fmtl
->bpb
== view_fmtl
->bpb
);
280 assert(surf_fmtl
->bw
== view_fmtl
->bw
);
281 assert(surf_fmtl
->bh
== view_fmtl
->bh
);
284 s
.SurfaceFormat
= info
->view
->format
;
287 /* The BSpec description of this field says:
289 * "This bit field, when set, indicates if the resource is created as
290 * Depth/Stencil resource."
292 * "SW must set this bit for any resource that was created with
293 * Depth/Stencil resource flag. Setting this bit allows HW to properly
294 * interpret the data-layout for various cases. For any resource that's
295 * created without Depth/Stencil resource flag, it must be reset."
297 * Even though the docs for this bit seem to imply that it's required for
298 * anything which might have been used for depth/stencil, empirical
299 * evidence suggests that it only affects CCS compression usage. There are
300 * a few things which back this up:
302 * 1. The docs are also pretty clear that this bit was added as part
303 * of enabling Gen12 depth/stencil lossless compression.
305 * 2. The only new difference between depth/stencil and color images on
306 * Gen12 (where the bit was added) is how they treat CCS compression.
307 * All other differences such as alignment requirements and MSAA layout
308 * are already covered by other bits.
310 * Under these assumptions, it makes sense for ISL to model this bit as
311 * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT
312 * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource
315 s
.DepthStencilResource
= info
->aux_usage
== ISL_AUX_USAGE_HIZ_CCS_WT
||
316 info
->aux_usage
== ISL_AUX_USAGE_STC_CCS
;
320 s
.ColorBufferComponentWriteDisables
= info
->write_disables
;
322 assert(info
->write_disables
== 0);
326 s
.IntegerSurfaceFormat
=
327 isl_format_has_int_channel((enum isl_format
) s
.SurfaceFormat
);
330 assert(info
->surf
->logical_level0_px
.width
> 0 &&
331 info
->surf
->logical_level0_px
.height
> 0);
333 s
.Width
= info
->surf
->logical_level0_px
.width
- 1;
334 s
.Height
= info
->surf
->logical_level0_px
.height
- 1;
336 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
337 * (Surface Arrays For all surfaces other than separate stencil buffer):
339 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
340 * calculated in the equation above , for every other odd Surface Height
341 * starting from 1 i.e. 1,5,9,13"
343 * Since this Qpitch errata only impacts the sampler, we have to adjust the
344 * input for the rendering surface to achieve the same qpitch. For the
345 * affected heights, we increment the height by 1 for the rendering
348 if (GEN_GEN
== 6 && (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
349 info
->surf
->samples
> 1 &&
350 (info
->surf
->logical_level0_px
.height
% 4) == 1)
353 switch (s
.SurfaceType
) {
356 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
358 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
359 * must be set to zero if this surface is used with sampling engine
362 * This restriction appears to exist only on Ivy Bridge.
364 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !ISL_DEV_IS_BAYTRAIL(dev
) &&
365 (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
) &&
366 info
->surf
->samples
> 1)
367 assert(info
->view
->base_array_layer
== 0);
369 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
371 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
373 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
374 * by one for each increase from zero of Minimum Array Element. For
375 * example, if Minimum Array Element is set to 1024 on a 2D surface,
376 * the range of this field is reduced to [0,1023].
378 * In other words, 'Depth' is the number of array layers.
380 s
.Depth
= info
->view
->array_len
- 1;
382 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
384 * For Render Target and Typed Dataport 1D and 2D Surfaces:
385 * This field must be set to the same value as the Depth field.
387 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
388 ISL_SURF_USAGE_STORAGE_BIT
))
389 s
.RenderTargetViewExtent
= s
.Depth
;
392 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
393 /* Same as SURFTYPE_2D, but divided by 6 */
394 s
.Depth
= info
->view
->array_len
/ 6 - 1;
395 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
396 ISL_SURF_USAGE_STORAGE_BIT
))
397 s
.RenderTargetViewExtent
= s
.Depth
;
400 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
402 * If the volume texture is MIP-mapped, this field specifies the
403 * depth of the base MIP level.
405 s
.Depth
= info
->surf
->logical_level0_px
.depth
- 1;
407 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
409 * For Render Target and Typed Dataport 3D Surfaces: This field
410 * indicates the extent of the accessible 'R' coordinates minus 1 on
411 * the LOD currently being rendered to.
413 * The docs specify that this only matters for render targets and
414 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
415 * Depth field has more bits than RenderTargetViewExtent so we can have
416 * textures with more levels than we can render to. In order to prevent
417 * assert-failures in the packing function below, we only set the field
418 * when it's actually going to be used by the hardware.
420 * Similaraly, the MinimumArrayElement field is ignored by all hardware
421 * prior to Sky Lake when texturing and we want it set to 0 anyway.
422 * Since it's already initialized to 0, we can just leave it alone for
425 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
426 ISL_SURF_USAGE_STORAGE_BIT
)) {
427 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
428 s
.RenderTargetViewExtent
= info
->view
->array_len
- 1;
432 unreachable("bad SurfaceType");
436 /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
437 s
.SurfaceArray
= info
->surf
->dim
!= ISL_SURF_DIM_3D
&&
438 info
->view
->array_len
> 1;
440 s
.SurfaceArray
= info
->surf
->dim
!= ISL_SURF_DIM_3D
;
443 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
444 /* For render target surfaces, the hardware interprets field
445 * MIPCount/LOD as LOD. The Broadwell PRM says:
447 * MIPCountLOD defines the LOD that will be rendered into.
448 * SurfaceMinLOD is ignored.
450 s
.MIPCountLOD
= info
->view
->base_level
;
453 /* For non render target surfaces, the hardware interprets field
454 * MIPCount/LOD as MIPCount. The range of levels accessible by the
455 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
457 s
.SurfaceMinLOD
= info
->view
->base_level
;
458 s
.MIPCountLOD
= MAX(info
->view
->levels
, 1) - 1;
462 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
463 * Start LOD" to 15 to prevent the hardware from trying to use them.
465 s
.TiledResourceMode
= NONE
;
466 s
.MipTailStartLOD
= 15;
470 const struct isl_extent3d image_align
= get_image_alignment(info
->surf
);
471 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[image_align
.height
];
473 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[image_align
.width
];
477 if (info
->surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
478 /* For gen9 1-D textures, surface pitch is ignored */
481 s
.SurfacePitch
= info
->surf
->row_pitch_B
- 1;
485 s
.SurfaceQPitch
= get_qpitch(info
->surf
) >> 2;
487 s
.SurfaceArraySpacing
= info
->surf
->array_pitch_span
==
488 ISL_ARRAY_PITCH_SPAN_COMPACT
;
492 assert(GEN_GEN
< 12 || info
->surf
->tiling
!= ISL_TILING_W
);
493 s
.TileMode
= isl_to_gen_tiling
[info
->surf
->tiling
];
495 s
.TiledSurface
= info
->surf
->tiling
!= ISL_TILING_LINEAR
,
496 s
.TileWalk
= info
->surf
->tiling
== ISL_TILING_Y0
? TILEWALK_YMAJOR
:
501 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
503 s
.RenderCacheReadWriteMode
= 0;
507 /* We've seen dEQP failures when enabling this bit with UINT formats,
508 * which particularly affects blorp_copy() operations. It shouldn't
509 * have any effect on UINT textures anyway, so disable it for them.
511 s
.EnableUnormPathInColorPipe
=
512 !isl_format_has_int_channel(info
->view
->format
);
515 s
.CubeFaceEnablePositiveZ
= 1;
516 s
.CubeFaceEnableNegativeZ
= 1;
517 s
.CubeFaceEnablePositiveY
= 1;
518 s
.CubeFaceEnableNegativeY
= 1;
519 s
.CubeFaceEnablePositiveX
= 1;
520 s
.CubeFaceEnableNegativeX
= 1;
523 s
.NumberofMultisamples
= ffs(info
->surf
->samples
) - 1;
525 s
.MultisampledSurfaceStorageFormat
=
526 isl_to_gen_multisample_layout
[info
->surf
->msaa_layout
];
530 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
531 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
)
532 assert(isl_swizzle_supports_rendering(dev
->info
, info
->view
->swizzle
));
534 s
.ShaderChannelSelectRed
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.r
;
535 s
.ShaderChannelSelectGreen
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.g
;
536 s
.ShaderChannelSelectBlue
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.b
;
537 s
.ShaderChannelSelectAlpha
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.a
;
539 assert(isl_swizzle_is_identity(info
->view
->swizzle
));
542 s
.SurfaceBaseAddress
= info
->address
;
548 #if GEN_GEN > 4 || GEN_IS_G4X
549 if (info
->x_offset_sa
!= 0 || info
->y_offset_sa
!= 0) {
550 /* There are fairly strict rules about when the offsets can be used.
551 * These are mostly taken from the Sky Lake PRM documentation for
552 * RENDER_SURFACE_STATE.
554 assert(info
->surf
->tiling
!= ISL_TILING_LINEAR
);
555 assert(info
->surf
->dim
== ISL_SURF_DIM_2D
);
556 assert(isl_is_pow2(isl_format_get_layout(info
->view
->format
)->bpb
));
557 assert(info
->surf
->levels
== 1);
558 assert(info
->surf
->logical_level0_px
.array_len
== 1);
559 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
562 /* Broadwell added more rules. */
563 assert(info
->surf
->samples
== 1);
564 if (isl_format_get_layout(info
->view
->format
)->bpb
== 8)
565 assert(info
->x_offset_sa
% 16 == 0);
566 if (isl_format_get_layout(info
->view
->format
)->bpb
== 16)
567 assert(info
->x_offset_sa
% 8 == 0);
571 s
.SurfaceArray
= false;
575 const unsigned x_div
= 4;
576 const unsigned y_div
= GEN_GEN
>= 8 ? 4 : 2;
577 assert(info
->x_offset_sa
% x_div
== 0);
578 assert(info
->y_offset_sa
% y_div
== 0);
579 s
.XOffset
= info
->x_offset_sa
/ x_div
;
580 s
.YOffset
= info
->y_offset_sa
/ y_div
;
582 assert(info
->x_offset_sa
== 0);
583 assert(info
->y_offset_sa
== 0);
587 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
588 /* Check valid aux usages per-gen */
590 assert(info
->aux_usage
== ISL_AUX_USAGE_MCS
||
591 info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
592 info
->aux_usage
== ISL_AUX_USAGE_HIZ_CCS_WT
||
593 info
->aux_usage
== ISL_AUX_USAGE_MCS_CCS
||
594 info
->aux_usage
== ISL_AUX_USAGE_STC_CCS
);
595 } else if (GEN_GEN
>= 9) {
596 assert(info
->aux_usage
== ISL_AUX_USAGE_HIZ
||
597 info
->aux_usage
== ISL_AUX_USAGE_MCS
||
598 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
||
599 info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
600 } else if (GEN_GEN
>= 8) {
601 assert(info
->aux_usage
== ISL_AUX_USAGE_HIZ
||
602 info
->aux_usage
== ISL_AUX_USAGE_MCS
||
603 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
604 } else if (GEN_GEN
>= 7) {
605 assert(info
->aux_usage
== ISL_AUX_USAGE_MCS
||
606 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
609 /* The docs don't appear to say anything whatsoever about compression
610 * and the data port. Testing seems to indicate that the data port
611 * completely ignores the AuxiliarySurfaceMode field.
613 * On gen12 HDC supports compression.
616 assert(!(info
->view
->usage
& ISL_SURF_USAGE_STORAGE_BIT
));
618 if (isl_surf_usage_is_depth(info
->surf
->usage
))
619 assert(isl_aux_usage_has_hiz(info
->aux_usage
));
621 if (isl_surf_usage_is_stencil(info
->surf
->usage
))
622 assert(info
->aux_usage
== ISL_AUX_USAGE_STC_CCS
);
624 if (isl_aux_usage_has_hiz(info
->aux_usage
)) {
625 /* For Gen8-10, there are some restrictions around sampling from HiZ.
626 * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
629 * "If this field is set to AUX_HIZ, Number of Multisamples must
630 * be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
632 * On Gen12, the docs are a bit less obvious but the restriction is
633 * the same. The limitation isn't called out explicitly but the docs
634 * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
637 * "If Number of multisamples > 1, programming this value means
638 * MSAA compression is enabled for that surface. Auxillary surface
639 * is MSC with tile y."
641 * Since this interpretation ignores whether the surface is
642 * depth/stencil or not and since multisampled depth buffers use
643 * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
644 * compression, this means that we can't even specify MSAA depth CCS
645 * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
647 assert(info
->surf
->samples
== 1);
649 /* The dimension must not be 3D */
650 assert(info
->surf
->dim
!= ISL_SURF_DIM_3D
);
652 /* The format must be one of the following: */
653 switch (info
->view
->format
) {
654 case ISL_FORMAT_R32_FLOAT
:
655 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
656 case ISL_FORMAT_R16_UNORM
:
659 assert(!"Incompatible HiZ Sampling format");
665 s
.AuxiliarySurfaceMode
= isl_to_gen_aux_mode
[info
->aux_usage
];
671 /* The auxiliary buffer info is filled when it's useable by the HW.
673 * Starting with Gen12, the only form of compression that can be used
674 * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
675 * HiZ still requires a surface but the HiZ surface can only be
676 * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
678 * On all earlier hardware, an aux surface is required for all forms
681 if ((GEN_GEN
< 12 && info
->aux_usage
!= ISL_AUX_USAGE_NONE
) ||
682 (GEN_GEN
>= 12 && isl_aux_usage_has_mcs(info
->aux_usage
))) {
684 assert(info
->aux_surf
!= NULL
);
686 struct isl_tile_info tile_info
;
687 isl_surf_get_tile_info(info
->aux_surf
, &tile_info
);
688 uint32_t pitch_in_tiles
=
689 info
->aux_surf
->row_pitch_B
/ tile_info
.phys_extent_B
.width
;
691 s
.AuxiliarySurfaceBaseAddress
= info
->aux_address
;
692 s
.AuxiliarySurfacePitch
= pitch_in_tiles
- 1;
695 /* Auxiliary surfaces in ISL have compressed formats but the hardware
696 * doesn't expect our definition of the compression, it expects qpitch
697 * in units of samples on the main surface.
699 s
.AuxiliarySurfaceQPitch
=
700 isl_surf_get_array_pitch_sa_rows(info
->aux_surf
) >> 2;
705 #if GEN_GEN >= 8 && GEN_GEN < 11
706 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
707 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
709 * This bit must be set for the following surface types: BC2_UNORM
710 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
712 if (GEN_GEN
>= 9 || dev
->info
->is_cherryview
) {
713 switch (info
->view
->format
) {
714 case ISL_FORMAT_BC2_UNORM
:
715 case ISL_FORMAT_BC3_UNORM
:
716 case ISL_FORMAT_BC5_UNORM
:
717 case ISL_FORMAT_BC5_SNORM
:
718 case ISL_FORMAT_BC7_UNORM
:
719 s
.SamplerL2BypassModeDisable
= true;
722 /* From the SKL PRM, Programming Note under Sampler Output Channel
725 * If a surface has an associated HiZ Auxilliary surface, the
726 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
729 if (GEN_GEN
>= 9 && info
->aux_usage
== ISL_AUX_USAGE_HIZ
)
730 s
.SamplerL2BypassModeDisable
= true;
736 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
737 if (info
->use_clear_address
) {
739 s
.ClearValueAddressEnable
= true;
740 s
.ClearValueAddress
= info
->clear_address
;
742 unreachable("Gen9 and earlier do not support indirect clear colors");
748 * From BXML > GT > Shared Functions > vol5c Shared Functions >
749 * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
753 * "Enables Pixel backend hw to convert clear values into native format
754 * and write back to clear address, so that display and sampler can use
755 * the converted value for resolving fast cleared RTs."
758 * Clear color conversion must be enabled if the clear color is stored
759 * indirectly and fast color clears are enabled.
761 if (info
->use_clear_address
) {
762 s
.ClearColorConversionEnable
= true;
767 assert(info
->use_clear_address
);
769 if (!info
->use_clear_address
) {
770 s
.RedClearColor
= info
->clear_color
.u32
[0];
771 s
.GreenClearColor
= info
->clear_color
.u32
[1];
772 s
.BlueClearColor
= info
->clear_color
.u32
[2];
773 s
.AlphaClearColor
= info
->clear_color
.u32
[3];
776 /* Prior to Sky Lake, we only have one bit for the clear color which
777 * gives us 0 or 1 in whatever the surface's format happens to be.
779 if (isl_format_has_int_channel(info
->view
->format
)) {
780 for (unsigned i
= 0; i
< 4; i
++) {
781 assert(info
->clear_color
.u32
[i
] == 0 ||
782 info
->clear_color
.u32
[i
] == 1);
784 s
.RedClearColor
= info
->clear_color
.u32
[0] != 0;
785 s
.GreenClearColor
= info
->clear_color
.u32
[1] != 0;
786 s
.BlueClearColor
= info
->clear_color
.u32
[2] != 0;
787 s
.AlphaClearColor
= info
->clear_color
.u32
[3] != 0;
789 for (unsigned i
= 0; i
< 4; i
++) {
790 assert(info
->clear_color
.f32
[i
] == 0.0f
||
791 info
->clear_color
.f32
[i
] == 1.0f
);
793 s
.RedClearColor
= info
->clear_color
.f32
[0] != 0.0f
;
794 s
.GreenClearColor
= info
->clear_color
.f32
[1] != 0.0f
;
795 s
.BlueClearColor
= info
->clear_color
.f32
[2] != 0.0f
;
796 s
.AlphaClearColor
= info
->clear_color
.f32
[3] != 0.0f
;
801 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
805 isl_genX(buffer_fill_state_s
)(const struct isl_device
*dev
, void *state
,
806 const struct isl_buffer_fill_state_info
*restrict info
)
808 uint64_t buffer_size
= info
->size_B
;
810 /* Uniform and Storage buffers need to have surface size not less that the
811 * aligned 32-bit size of the buffer. To calculate the array lenght on
812 * unsized arrays in StorageBuffer the last 2 bits store the padding size
813 * added to the surface, so we can calculate latter the original buffer
814 * size to know the number of elements.
816 * surface_size = isl_align(buffer_size, 4) +
817 * (isl_align(buffer_size) - buffer_size)
819 * buffer_size = (surface_size & ~3) - (surface_size & 3)
821 if (info
->format
== ISL_FORMAT_RAW
||
822 info
->stride_B
< isl_format_get_layout(info
->format
)->bpb
/ 8) {
823 assert(info
->stride_B
== 1);
824 uint64_t aligned_size
= isl_align(buffer_size
, 4);
825 buffer_size
= aligned_size
+ (aligned_size
- buffer_size
);
828 uint32_t num_elements
= buffer_size
/ info
->stride_B
;
831 /* From the IVB PRM, SURFACE_STATE::Height,
833 * For typed buffer and structured buffer surfaces, the number
834 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
835 * surfaces, the number of entries in the buffer is the number of bytes
836 * which can range from 1 to 2^30.
838 if (info
->format
== ISL_FORMAT_RAW
) {
839 assert(num_elements
<= (1ull << 30));
840 assert(num_elements
> 0);
842 assert(num_elements
<= (1ull << 27));
845 assert(num_elements
<= (1ull << 27));
848 struct GENX(RENDER_SURFACE_STATE
) s
= { 0, };
850 s
.SurfaceType
= SURFTYPE_BUFFER
;
851 s
.SurfaceFormat
= info
->format
;
854 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[4];
856 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[4];
857 s
.SurfaceArray
= false;
862 s
.Height
= ((num_elements
- 1) >> 7) & 0x3fff;
863 s
.Width
= (num_elements
- 1) & 0x7f;
864 s
.Depth
= ((num_elements
- 1) >> 21) & 0x3ff;
866 s
.Height
= ((num_elements
- 1) >> 7) & 0x1fff;
867 s
.Width
= (num_elements
- 1) & 0x7f;
868 s
.Depth
= ((num_elements
- 1) >> 20) & 0x7f;
871 if (GEN_GEN
== 12 && dev
->info
->revision
== 0) {
872 /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
873 * textures with very close base addresses (delta < 64B) to corrupt each
874 * other. We can sort-of work around this by making small buffer
875 * textures 1D textures instead. This doesn't fix the problem for large
876 * buffer textures but the liklihood of large, overlapping, and very
877 * close buffer textures is fairly low and the point is to hack around
878 * the bug so we can run apps and tests.
880 if (info
->format
!= ISL_FORMAT_RAW
&&
881 info
->stride_B
== isl_format_get_layout(info
->format
)->bpb
/ 8 &&
882 num_elements
<= (1 << 14)) {
883 s
.SurfaceType
= SURFTYPE_1D
;
884 s
.Width
= num_elements
- 1;
890 s
.SurfacePitch
= info
->stride_B
- 1;
893 s
.NumberofMultisamples
= MULTISAMPLECOUNT_1
;
899 s
.TiledSurface
= false;
903 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
905 s
.RenderCacheReadWriteMode
= 0;
908 s
.SurfaceBaseAddress
= info
->address
;
913 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
914 s
.ShaderChannelSelectRed
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.r
;
915 s
.ShaderChannelSelectGreen
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.g
;
916 s
.ShaderChannelSelectBlue
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.b
;
917 s
.ShaderChannelSelectAlpha
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.a
;
920 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
924 isl_genX(null_fill_state
)(void *state
, struct isl_extent3d size
)
926 struct GENX(RENDER_SURFACE_STATE
) s
= {
927 .SurfaceType
= SURFTYPE_NULL
,
928 /* We previously had this format set to B8G8R8A8_UNORM but ran into
929 * hangs on IVB. R32_UINT seems to work for everybody.
931 * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
933 .SurfaceFormat
= ISL_FORMAT_R32_UINT
,
935 .SurfaceArray
= size
.depth
> 1,
940 .TiledSurface
= true,
941 .TileWalk
= TILEWALK_YMAJOR
,
944 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
947 * RENDER_SURFACE_STATE::Surface Vertical Alignment
949 * "This field must be set to VALIGN_4 for all tiled Y Render Target
954 .SurfaceVerticalAlignment
= VALIGN_4
,
956 .Width
= size
.width
- 1,
957 .Height
= size
.height
- 1,
958 .Depth
= size
.depth
- 1,
959 .RenderTargetViewExtent
= size
.depth
- 1,
961 .ColorBufferComponentWriteDisables
= 0xf,
964 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);